| Mon, 20 Feb 2017 21:54:25 +0800 |
[C2] Remove unnecessary dsllv in mips_64.ad |
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| Mon, 20 Feb 2017 21:35:55 +0800 |
[Assembler] Redefine the srl instruction for MIPS. |
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| Mon, 20 Feb 2017 21:27:49 +0800 |
[Assembler] Redefine the sll instruction for MIPS. |
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| Sat, 18 Feb 2017 19:19:48 -0500 |
[C2] Add logical right-rotate instructions for long in mips_64.ad |
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| Sat, 18 Feb 2017 18:56:55 -0500 |
[C2] Add rolI_Reg_immI_0_31 and rorI_Reg_immI_0_31 in mips_64.ad |
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| Sun, 19 Feb 2017 17:42:22 +0800 |
[C2] Optimize zero-extend operations for MIPS following changeset 9baf2a6cb610. |
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| Sun, 19 Feb 2017 17:09:02 +0800 |
[C2] Optimize instruct salL_Reg_Reg in mips_64.ad |
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| Sun, 19 Feb 2017 16:34:38 +0800 |
[C2] Use dext to optimize zero-extend operations for MIPS. |
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| Thu, 16 Feb 2017 09:56:42 -0500 |
[C2] Add instruct convD2L_reg_fast in mips_64.ad |
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| Thu, 16 Feb 2017 08:59:10 -0500 |
[C2] Add instruct convD2I_reg_reg_fast in mips_64.ad |
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| Thu, 16 Feb 2017 07:55:00 -0500 |
[C2] Add instruct convF2L_reg_fast in mips_64.ad |
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| Thu, 16 Feb 2017 05:45:03 -0500 |
[C2] Optimize cmpF3_reg_reg, cmpD3_reg_reg and cmpL3_reg_reg in mips_64.ad |
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| Thu, 16 Feb 2017 03:58:02 -0500 |
[C2] Remove instruct loadConI_65536 in mips_64.ad |
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| Wed, 15 Feb 2017 15:56:09 -0500 |
[C2] Add instruct convF2I_reg_fast in mips_64.ad |
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| Wed, 15 Feb 2017 15:23:24 -0500 |
Delete an unused instruct in mips_64.ad |
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| Wed, 15 Feb 2017 13:43:16 -0500 |
[C2] Add instruct mulL_reg_regI2L in mips_64.ad |
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| Wed, 15 Feb 2017 12:58:01 -0500 |
[C2] Add instruct convL2I2L_reg_reg_zex in mips_64.ad |
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| Wed, 15 Feb 2017 12:37:43 -0500 |
[C2] Add instruct convL2I2L_reg in mips_64.ad |
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| Wed, 15 Feb 2017 10:22:07 -0500 |
[C2] Add instruct andL_Reg_immL_nonneg_mask in mips_64.ad |
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| Wed, 15 Feb 2017 09:29:03 -0500 |
[C2] Add instruct andI_Reg_immI_nonneg_mask in mips_64.ad |
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| Wed, 15 Feb 2017 07:56:12 -0500 |
[C2] gsandn & gsorn are not designed for long on Loongson CPUs. |
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| Tue, 14 Feb 2017 20:13:13 -0500 |
[C2] Import xori for MIPS. |
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| Tue, 14 Feb 2017 19:41:33 -0500 |
[C2] Enable gsorn for Loongson CPUs. |
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| Tue, 14 Feb 2017 19:21:53 -0500 |
[C2] Enable gsandn for Loongson CPUs. |
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| Tue, 14 Feb 2017 15:44:26 -0500 |
[C2] Enable instruct dins for MIPS CPUs. |
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| Tue, 14 Feb 2017 14:46:37 -0500 |
[C2] Add instruct shr_logical_Reg_imm_nonneg_mask in mips_64.add |
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| Mon, 13 Feb 2017 20:01:12 -0500 |
[C2] Add shr_logical_Reg_imm_mask63 in mips_64.ad |
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| Sat, 11 Feb 2017 22:40:29 +0800 |
[C2] Loading from memory seems slow, so remove loadConL_load & loadConP_load in mips_64.ad |
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| Fri, 10 Feb 2017 01:05:31 -0500 |
[C2] jr seems slow on Loongson CPUs, so remove instruct jumpXtnd in mips_64.ad |
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| Fri, 10 Feb 2017 00:40:22 -0500 |
For constant loading, li --> set64 in mips_64.ad |
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| Fri, 10 Feb 2017 00:24:55 -0500 |
[C2] Loading constant pointers from the constant table is OK for MIPS. |
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| Thu, 09 Feb 2017 06:04:22 -0500 |
[C2] set64 in loadConP_poll. |
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| Thu, 09 Feb 2017 05:25:35 -0500 |
[C2] Long offset for loading constants from the constant table is OK for MIPS. |
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| Thu, 09 Feb 2017 04:53:02 -0500 |
[C2] Adjust the loading of long constants for MIPS. |
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| Thu, 09 Feb 2017 00:19:58 -0500 |
[C2] Add instruct loadConL16 & loadConL0 in mips_64.ad |
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| Wed, 08 Feb 2017 11:51:48 -0500 |
[C2] li48 --> li when loading constants. |
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| Wed, 08 Feb 2017 10:08:25 -0500 |
[C2] Add instruct loadConP_poll in mips_64.ad |
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| Wed, 08 Feb 2017 05:52:20 -0500 |
[C2] Optimize store_B_reg_enc for Loongson CPUs. |
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| Wed, 08 Feb 2017 05:18:26 -0500 |
[C2] Optimize store_B_immI_enc for Loongson CPUs. |
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| Tue, 07 Feb 2017 11:30:19 -0500 |
[C2] Add instruct jumpXtnd in mips_64.ad |
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| Tue, 07 Feb 2017 10:01:57 -0500 |
[C2] For Loongson CPUs, gssq/gslq are enabled in prolog/epilog node. |
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| Mon, 06 Feb 2017 21:51:38 +0800 |
[C2] Optimize convP2B & convI2B for MIPS. |
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| Mon, 06 Feb 2017 16:22:13 +0800 |
[C2] Add orL_Reg_P2XReg in mips_64.ad |
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| Mon, 06 Feb 2017 16:11:45 +0800 |
[C2] Add slrL_P2XReg_immI_0_31 & slrL_P2XReg_immI_32_63 in mips_64.ad |
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| Sat, 04 Feb 2017 11:15:42 +0800 |
[C2] Remove sync in membar_release for MIPS CPUs. |
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| Sat, 04 Feb 2017 11:06:57 +0800 |
[C2] Optimize the loading of 0x1fa00000. |
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| Fri, 03 Feb 2017 22:13:43 +0800 |
[C2] Add instruct branchConL_reg_immL16_sub in mips_64.ad |
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| Fri, 03 Feb 2017 19:29:19 +0800 |
[C2] Optimize SubL operation for MIPS CPUs. |
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| Fri, 03 Feb 2017 18:15:07 +0800 |
[C2] Optimize SubI operation for MIPS CPUs. |
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| Fri, 03 Feb 2017 16:02:33 +0800 |
[C2] Remove divF_Reg_immF & storeF_imm for MIPS. |
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| Fri, 03 Feb 2017 09:24:36 +0800 |
[C2] Remove sync in membar_acquire. |
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| Fri, 03 Feb 2017 09:21:52 +0800 |
Sync in FastUnlock instead of membar_release_lock. |
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| Thu, 02 Feb 2017 17:46:04 +0800 |
Sync in membar_release_lock for 3A2000/3000 CPUs. |
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| Thu, 02 Feb 2017 13:01:19 +0800 |
[C2] Add load_fence and store_fence for MIPS CPUs. |
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| Thu, 02 Feb 2017 12:13:31 +0800 |
[C2] Remove sync in instruct membar_acquire_lock for MIPS CPUs. |
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| Thu, 02 Feb 2017 12:08:59 +0800 |
[C2] Remove sync in instruct membar_release_lock for MIPS CPUs. |
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| Thu, 02 Feb 2017 11:58:56 +0800 |
[C2] Remove sync in instruct unnecessary_membar_volatile for MIPS CPUs. |
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| Thu, 02 Feb 2017 11:50:25 +0800 |
[C2] Remove sync in instruct membar_storestore for MIPS CPUs. |
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| Wed, 01 Feb 2017 22:40:16 +0800 |
Optimize long to int conversion for MIPS CPUs. |
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| Wed, 01 Feb 2017 22:24:47 +0800 |
Add seb/seh instructions for MIPS CPUs. |
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