src/cpu/mips/vm/mips_64.ad

changeset 318
b7127982c97c
parent 317
001d396b2d46
child 319
2d7d048236e1
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Sat Feb 18 19:19:48 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Mon Feb 20 21:27:49 2017 +0800
     1.3 @@ -10754,19 +10754,7 @@
     1.4      Register dst = $dst$$Register;
     1.5      int    shamt = $shift$$constant;
     1.6  
     1.7 -/*
     1.8 -     094     SHL    S0, S0, #-7 #@salI_Reg_imm    
     1.9 -     static int insn_RRSO(int rt, int rd, int sa,   int op) { return (rt<<16) | (rd<<11) | (sa<<6)   | op; }
    1.10 -     void sll  (Register rd, Register rt ,  int sa) { 
    1.11 -         emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, sll_op));
    1.12 -     }
    1.13 -*/
    1.14 -
    1.15 -    if(0 <= shamt && shamt < 32) __ sll(dst, src, shamt);
    1.16 -    else {
    1.17 -       __ move(AT, shamt);
    1.18 -       __ sllv(dst, src, AT);
    1.19 -    }
    1.20 +    __ sll(dst, src, shamt);
    1.21    %}
    1.22    ins_pipe( ialu_regI_regI );
    1.23  %}
    1.24 @@ -10842,11 +10830,7 @@
    1.25      Register dst = $dst$$Register;
    1.26      int    shamt = $shift$$constant;
    1.27  
    1.28 -    if(0 <= shamt && shamt < 32) __ sll(dst, src, shamt);
    1.29 -    else {
    1.30 -       __ move(AT, shamt);
    1.31 -       __ sllv(dst, src, AT);
    1.32 -    }
    1.33 +    __ sll(dst, src, shamt);
    1.34    %}
    1.35    ins_pipe( ialu_regI_regI );
    1.36  %}

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