src/cpu/mips/vm/mips_64.ad

changeset 301
d585b6706dc2
parent 300
5c43ed10ee2f
child 302
f4ccb4aa25f1
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 09:29:03 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 10:22:07 2017 -0500
     1.3 @@ -3988,6 +3988,16 @@
     1.4    interface(CONST_INTER);
     1.5  %}
     1.6  
     1.7 +// Operand for non-negtive long mask
     1.8 +operand immL_nonneg_mask() %{
     1.9 +  predicate( (n->get_long() >= 0) && (Assembler::is_jlong_mask(n->get_long()) != -1) );
    1.10 +  match(ConL);
    1.11 +
    1.12 +  op_cost(0);
    1.13 +  format %{ %}
    1.14 +  interface(CONST_INTER);
    1.15 +%}
    1.16 +
    1.17  operand immL_0_65535() %{
    1.18    predicate( n->get_long() >= 0 && n->get_long() <= 65535 );
    1.19    match(ConL);
    1.20 @@ -10389,6 +10399,21 @@
    1.21    ins_pipe( ialu_regI_regI );
    1.22  %}
    1.23  
    1.24 +instruct andL_Reg_immL_nonneg_mask(mRegL dst, mRegL src1,  immL_nonneg_mask mask) %{
    1.25 +  match(Set dst (AndL src1 mask));
    1.26 +  ins_cost(60);
    1.27 +
    1.28 +  format %{ "and  $dst, $src1, $mask #@andL_Reg_immL_nonneg_mask" %}
    1.29 +  ins_encode %{
    1.30 +    Register dst = $dst$$Register;
    1.31 +    Register src = $src1$$Register;
    1.32 +    int     size = Assembler::is_jlong_mask($mask$$constant);
    1.33 +
    1.34 +    __ dext(dst, src, 0, size);
    1.35 +  %}
    1.36 +  ins_pipe( ialu_regI_regI );
    1.37 +%}
    1.38 +
    1.39  instruct xorI_Reg_imm_0_65535(mRegI dst, mRegI src1,  immI_0_65535 src2) %{
    1.40    match(Set dst (XorI src1 src2));
    1.41    ins_cost(60);

mercurial