Optimize long to int conversion for MIPS CPUs.

Wed, 01 Feb 2017 22:40:16 +0800

author
fujie
date
Wed, 01 Feb 2017 22:40:16 +0800
changeset 257
bba1c817d040
parent 256
f64feaeca32f
child 258
c92c4dee00a9

Optimize long to int conversion for MIPS CPUs.

src/cpu/mips/vm/mips_64.ad file | annotate | diff | comparison | revisions
src/cpu/mips/vm/templateTable_mips_64.cpp file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Wed Feb 01 22:24:47 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Feb 01 22:40:16 2017 +0800
     1.3 @@ -10525,8 +10525,7 @@
     1.4      Register dst = as_Register($dst$$reg);
     1.5      Register src = as_Register($src$$reg);
     1.6  
     1.7 -    __ dsll32(dst, src, 0);
     1.8 -    __ dsra32(dst, dst, 0);
     1.9 +    __ sll(dst, src, 0);
    1.10    %}
    1.11  
    1.12    ins_pipe( ialu_regI_regI );
     2.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Feb 01 22:24:47 2017 +0800
     2.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Feb 01 22:40:16 2017 +0800
     2.3 @@ -1605,8 +1605,9 @@
     2.4        __ seh(FSR, FSR);
     2.5        break;
     2.6      case Bytecodes::_l2i:
     2.7 -      __ dsll32(FSR, FSR, 0);
     2.8 -      __ dsra32(FSR, FSR, 0);
     2.9 +      __ sll(FSR, FSR, 0);
    2.10 +      //__ dsll32(FSR, FSR, 0);
    2.11 +      //__ dsra32(FSR, FSR, 0);
    2.12        break;
    2.13      case Bytecodes::_l2f:
    2.14        __ dmtc1(FSR, FSF);

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