1.1 --- a/src/cpu/mips/vm/mips_64.ad Sat Feb 18 18:56:55 2017 -0500 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Sat Feb 18 19:19:48 2017 -0500 1.3 @@ -11155,6 +11155,38 @@ 1.4 ins_pipe( ialu_regI_regI ); 1.5 %} 1.6 1.7 +instruct rolL_Reg_immI_0_31(mRegL dst, immI_32_63 lshift, immI_0_31 rshift) 1.8 +%{ 1.9 + predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 1.10 + match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); 1.11 + 1.12 + ins_cost(100); 1.13 + format %{ "rotr $dst, $dst, $rshift #@rolL_Reg_immI_0_31" %} 1.14 + ins_encode %{ 1.15 + Register dst = $dst$$Register; 1.16 + int sa = $rshift$$constant; 1.17 + 1.18 + __ drotr(dst, dst, sa); 1.19 + %} 1.20 + ins_pipe( ialu_regI_regI ); 1.21 +%} 1.22 + 1.23 +instruct rolL_Reg_immI_32_63(mRegL dst, immI_0_31 lshift, immI_32_63 rshift) 1.24 +%{ 1.25 + predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 1.26 + match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); 1.27 + 1.28 + ins_cost(100); 1.29 + format %{ "rotr $dst, $dst, $rshift #@rolL_Reg_immI_32_63" %} 1.30 + ins_encode %{ 1.31 + Register dst = $dst$$Register; 1.32 + int sa = $rshift$$constant; 1.33 + 1.34 + __ drotr32(dst, dst, sa - 32); 1.35 + %} 1.36 + ins_pipe( ialu_regI_regI ); 1.37 +%} 1.38 + 1.39 instruct rorI_Reg_immI_0_31(mRegI dst, immI_0_31 rshift, immI_0_31 lshift) 1.40 %{ 1.41 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 1.42 @@ -11171,6 +11203,38 @@ 1.43 ins_pipe( ialu_regI_regI ); 1.44 %} 1.45 1.46 +instruct rorL_Reg_immI_0_31(mRegL dst, immI_0_31 rshift, immI_32_63 lshift) 1.47 +%{ 1.48 + predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 1.49 + match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); 1.50 + 1.51 + ins_cost(100); 1.52 + format %{ "rotr $dst, $dst, $rshift #@rorL_Reg_immI_0_31" %} 1.53 + ins_encode %{ 1.54 + Register dst = $dst$$Register; 1.55 + int sa = $rshift$$constant; 1.56 + 1.57 + __ drotr(dst, dst, sa); 1.58 + %} 1.59 + ins_pipe( ialu_regI_regI ); 1.60 +%} 1.61 + 1.62 +instruct rorL_Reg_immI_32_63(mRegL dst, immI_32_63 rshift, immI_0_31 lshift) 1.63 +%{ 1.64 + predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 1.65 + match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); 1.66 + 1.67 + ins_cost(100); 1.68 + format %{ "rotr $dst, $dst, $rshift #@rorL_Reg_immI_32_63" %} 1.69 + ins_encode %{ 1.70 + Register dst = $dst$$Register; 1.71 + int sa = $rshift$$constant; 1.72 + 1.73 + __ drotr32(dst, dst, sa - 32); 1.74 + %} 1.75 + ins_pipe( ialu_regI_regI ); 1.76 +%} 1.77 + 1.78 // Logical Shift Right 1.79 instruct shr_logical_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{ 1.80 match(Set dst (URShiftI src shift));