src/cpu/mips/vm/mips_64.ad

changeset 305
d7cbb6e4dd66
parent 304
ba34e26ba021
child 306
fd79679fcbf8
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 13:43:16 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 15:23:24 2017 -0500
     1.3 @@ -11521,18 +11521,6 @@
     1.4    ins_pipe( fpu_regF_regF );
     1.5  %}
     1.6  
     1.7 -instruct convF2I_reg_reg(mRegI dst, regF src) %{
     1.8 -  match(Set dst (ConvF2I src));
     1.9 -  format %{ "convF2I  $dst, $src\t# @convF2D_reg_reg" %}
    1.10 -  ins_encode %{
    1.11 -    FloatRegister dst = $dst$$FloatRegister;
    1.12 -    FloatRegister src = $src$$FloatRegister;
    1.13 -
    1.14 -    __ cvt_d_s(dst, src);
    1.15 -  %}
    1.16 -  ins_pipe( fpu_regF_regF );
    1.17 -%}
    1.18 -
    1.19  instruct convF2D_reg_reg(regD dst, regF src) %{
    1.20    match(Set dst (ConvF2D src));
    1.21    format %{ "convF2D  $dst, $src\t# @convF2D_reg_reg" %}

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