Thu, 16 Feb 2017 09:56:42 -0500
[C2] Add instruct convD2L_reg_fast in mips_64.ad
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Thu Feb 16 08:59:10 2017 -0500 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Feb 16 09:56:42 2017 -0500 1.3 @@ -11266,9 +11266,45 @@ 1.4 ins_pipe( pipe_slow ); 1.5 %} 1.6 1.7 -instruct convD2L_reg( mRegL dst, regD src ) %{ 1.8 +instruct convD2L_reg_fast( mRegL dst, regD src ) %{ 1.9 match(Set dst (ConvD2L src)); 1.10 - format %{ "convD2L $dst, $src @ convD2L_reg" %} 1.11 + ins_cost(150); 1.12 + format %{ "convD2L $dst, $src @ convD2L_reg_fast" %} 1.13 + ins_encode %{ 1.14 + Register dst = as_Register($dst$$reg); 1.15 + FloatRegister src = as_FloatRegister($src$$reg); 1.16 + 1.17 + Label Done; 1.18 + 1.19 + __ trunc_l_d(F30, src); 1.20 + // max_long: 0x7fffffffffffffff 1.21 + // __ set64(AT, 0x7fffffffffffffff); 1.22 + __ daddiu(AT, R0, -1); 1.23 + __ dsrl(AT, AT, 1); 1.24 + __ dmfc1(dst, F30); 1.25 + 1.26 + __ bne(dst, AT, Done); 1.27 + __ delayed()->mtc1(R0, F30); 1.28 + 1.29 + __ cvt_d_w(F30, F30); 1.30 + __ c_ult_d(src, F30); 1.31 + __ bc1f(Done); 1.32 + __ delayed()->daddiu(T9, R0, -1); 1.33 + 1.34 + __ c_un_d(src, src); //NaN? 1.35 + __ subu(dst, T9, AT); 1.36 + __ movt(dst, R0); 1.37 + 1.38 + __ bind(Done); 1.39 + %} 1.40 + 1.41 + ins_pipe( pipe_slow ); 1.42 +%} 1.43 + 1.44 +instruct convD2L_reg_slow( mRegL dst, regD src ) %{ 1.45 + match(Set dst (ConvD2L src)); 1.46 + ins_cost(250); 1.47 + format %{ "convD2L $dst, $src @ convD2L_reg_slow" %} 1.48 ins_encode %{ 1.49 Register dst = as_Register($dst$$reg); 1.50 FloatRegister src = as_FloatRegister($src$$reg); 1.51 @@ -11546,7 +11582,7 @@ 1.52 __ delayed()->mtc1(R0, F30); 1.53 1.54 __ cvt_d_w(F30, F30); 1.55 - __ c_le_d(src, F30); 1.56 + __ c_ult_d(src, F30); 1.57 __ bc1f(Done); 1.58 __ delayed()->addiu(T9, R0, -1); 1.59