Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/assembler_mips.hpp	Sat Feb 18 19:19:48 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp	Mon Feb 20 21:27:49 2017 +0800
     1.3 @@ -1183,15 +1183,9 @@
     1.4    void mflo (Register rd)              { emit_long( ((int)rd->encoding()<<11) | mflo_op ); }
     1.5    void mthi (Register rs)              { emit_long( ((int)rs->encoding()<<21) | mthi_op ); }
     1.6    void mtlo (Register rs)              { emit_long( ((int)rs->encoding()<<21) | mtlo_op ); }
     1.7 -// Do mult and div need both 32-bit and 64-bit version? FIXME aoqi
     1.8 -//#ifndef _LP64
     1.9 -#if 1
    1.10 +
    1.11    void mult (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, mult_op)); }
    1.12    void multu(Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, multu_op)); }
    1.13 -#else
    1.14 -  void mult (Register rs, Register rt) { dmult  (rs, rt); }
    1.15 -  void multu(Register rs, Register rt) { dmultu (rs, rt); }
    1.16 -#endif
    1.17  
    1.18    void nor(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), nor_op)); }
    1.19  
    1.20 @@ -1205,30 +1199,17 @@
    1.21    void sdl  (Register rt, Register base, int off)     { emit_long(insn_ORRI(sdl_op,   (int)base->encoding(), (int)rt->encoding(), off)); }
    1.22    void sdr  (Register rt, Register base, int off)     { emit_long(insn_ORRI(sdr_op,   (int)base->encoding(), (int)rt->encoding(), off)); }
    1.23    void sh   (Register rt, Register base, int off)     { emit_long(insn_ORRI(sh_op,    (int)base->encoding(), (int)rt->encoding(), off)); }
    1.24 -//#ifndef _LP64
    1.25 -#if 1
    1.26 -  void sll  (Register rd, Register rt ,  int sa)      { emit_long(insn_RRSO((int)rt->encoding(),  (int)rd->encoding(),   sa,      sll_op)); }
    1.27 +  void sll  (Register rd, Register rt ,  int sa)      { emit_long(insn_RRSO((int)rt->encoding(),  (int)rd->encoding(),   low(sa, 5),      sll_op)); }
    1.28    void sllv (Register rd, Register rt,   Register rs) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), sllv_op)); }
    1.29 -#else
    1.30 -  void sll  (Register rd, Register rt ,  int sa)      { dsll  (rd, rt, sa);}
    1.31 -  void sllv (Register rd, Register rt,   Register rs) { dsllv (rd, rt, rs); }
    1.32 -#endif
    1.33    void slt  (Register rd, Register rs,   Register rt) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), slt_op)); }
    1.34    void slti (Register rt, Register rs,   int imm)     { emit_long(insn_ORRI(slti_op,  (int)rs->encoding(),   (int)rt->encoding(), imm)); }
    1.35    void sltiu(Register rt, Register rs,   int imm)     { emit_long(insn_ORRI(sltiu_op, (int)rs->encoding(),   (int)rt->encoding(), imm)); }
    1.36    void sltu (Register rd, Register rs,   Register rt) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), sltu_op)); }
    1.37 -//#ifndef _LP64
    1.38 -#if 1
    1.39    void sra  (Register rd, Register rt ,  int sa)      { emit_long(insn_RRSO((int)rt->encoding(),  (int)rd->encoding(),   sa,      sra_op)); }
    1.40    void srav (Register rd, Register rt,   Register rs) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), srav_op)); }
    1.41    void srl  (Register rd, Register rt ,  int sa)      { emit_long(insn_RRSO((int)rt->encoding(),  (int)rd->encoding(),   sa,      srl_op)); }
    1.42    void srlv (Register rd, Register rt,   Register rs) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), srlv_op)); }
    1.43 -#else
    1.44 -  void sra  (Register rd, Register rt ,  int sa)      { dsra  (rd, rt, sa); }
    1.45 -  void srav (Register rd, Register rt,   Register rs) { dsrav (rd, rt, rs); }
    1.46 -  void srl  (Register rd, Register rt ,  int sa)      { dsrl  (rd, rt, sa); }
    1.47 -  void srlv (Register rd, Register rt,   Register rs) { dsrlv (rd, rt, rs); }
    1.48 -#endif
    1.49 +
    1.50  #ifndef _LP64
    1.51    void sub  (Register rd, Register rs,   Register rt) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), sub_op)); }
    1.52    void subu (Register rd, Register rs,   Register rt) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), subu_op)); }

     2.1 --- a/src/cpu/mips/vm/mips_64.ad	Sat Feb 18 19:19:48 2017 -0500
     2.2 +++ b/src/cpu/mips/vm/mips_64.ad	Mon Feb 20 21:27:49 2017 +0800
     2.3 @@ -10754,19 +10754,7 @@
     2.4      Register dst = $dst$$Register;
     2.5      int    shamt = $shift$$constant;
     2.6  
     2.7 -/*
     2.8 -     094     SHL    S0, S0, #-7 #@salI_Reg_imm    
     2.9 -     static int insn_RRSO(int rt, int rd, int sa,   int op) { return (rt<<16) | (rd<<11) | (sa<<6)   | op; }
    2.10 -     void sll  (Register rd, Register rt ,  int sa) { 
    2.11 -         emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, sll_op));
    2.12 -     }
    2.13 -*/
    2.14 -
    2.15 -    if(0 <= shamt && shamt < 32) __ sll(dst, src, shamt);
    2.16 -    else {
    2.17 -       __ move(AT, shamt);
    2.18 -       __ sllv(dst, src, AT);
    2.19 -    }
    2.20 +    __ sll(dst, src, shamt);
    2.21    %}
    2.22    ins_pipe( ialu_regI_regI );
    2.23  %}
    2.24 @@ -10842,11 +10830,7 @@
    2.25      Register dst = $dst$$Register;
    2.26      int    shamt = $shift$$constant;
    2.27  
    2.28 -    if(0 <= shamt && shamt < 32) __ sll(dst, src, shamt);
    2.29 -    else {
    2.30 -       __ move(AT, shamt);
    2.31 -       __ sllv(dst, src, AT);
    2.32 -    }
    2.33 +    __ sll(dst, src, shamt);
    2.34    %}
    2.35    ins_pipe( ialu_regI_regI );
    2.36  %}