src/cpu/mips/vm/mips_64.ad

changeset 304
ba34e26ba021
parent 303
3c47814d2976
child 305
d7cbb6e4dd66
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 12:58:01 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 13:43:16 2017 -0500
     1.3 @@ -10140,6 +10140,24 @@
     1.4    ins_pipe( pipe_slow );
     1.5  %}
     1.6  
     1.7 +instruct mulL_reg_regI2L(mRegL dst, mRegL src1, mRegI src2) %{
     1.8 +  match(Set dst (MulL src1 (ConvI2L src2)));
     1.9 +  format %{ "mulL  $dst, $src1, $src2 @mulL_reg_regI2L" %}
    1.10 +  ins_encode %{
    1.11 +    Register dst = as_Register($dst$$reg);
    1.12 +    Register op1 = as_Register($src1$$reg);
    1.13 +    Register op2 = as_Register($src2$$reg);
    1.14 +
    1.15 +    if (UseLoongsonISA) {
    1.16 +      __ gsdmult(dst, op1, op2);
    1.17 +    } else {
    1.18 +      __ dmult(op1, op2);
    1.19 +      __ mflo(dst);
    1.20 +    }
    1.21 +  %}
    1.22 +  ins_pipe( pipe_slow );
    1.23 +%}
    1.24 +
    1.25  instruct divL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
    1.26    match(Set dst (DivL src1 src2));
    1.27    format %{ "divL  $dst, $src1, $src2 @divL_reg_reg" %}

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