Thu, 16 Feb 2017 08:59:10 -0500
[C2] Add instruct convD2I_reg_reg_fast in mips_64.ad
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Thu Feb 16 07:55:00 2017 -0500 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Feb 16 08:59:10 2017 -0500 1.3 @@ -11525,11 +11525,45 @@ 1.4 %} 1.5 1.6 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. 1.7 -instruct convD2I_reg_reg( mRegI dst, regD src ) %{ 1.8 +instruct convD2I_reg_reg_fast( mRegI dst, regD src ) %{ 1.9 match(Set dst (ConvD2I src)); 1.10 -// effect( KILL tmp, KILL cr );//after this instruction, it will release register tmp and cr 1.11 - 1.12 - format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg \n\t" %} 1.13 + 1.14 + ins_cost(150); 1.15 + format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_fast" %} 1.16 + 1.17 + ins_encode %{ 1.18 + FloatRegister src = $src$$FloatRegister; 1.19 + Register dst = $dst$$Register; 1.20 + 1.21 + Label Done; 1.22 + 1.23 + __ trunc_w_d(F30, src); 1.24 + // max_int: 2147483647 1.25 + __ move(AT, 0x7fffffff); 1.26 + __ mfc1(dst, F30); 1.27 + 1.28 + __ bne(dst, AT, Done); 1.29 + __ delayed()->mtc1(R0, F30); 1.30 + 1.31 + __ cvt_d_w(F30, F30); 1.32 + __ c_le_d(src, F30); 1.33 + __ bc1f(Done); 1.34 + __ delayed()->addiu(T9, R0, -1); 1.35 + 1.36 + __ c_un_d(src, src); //NaN? 1.37 + __ subu32(dst, T9, AT); 1.38 + __ movt(dst, R0); 1.39 + 1.40 + __ bind(Done); 1.41 + %} 1.42 + ins_pipe( pipe_slow ); 1.43 +%} 1.44 + 1.45 +instruct convD2I_reg_reg_slow( mRegI dst, regD src ) %{ 1.46 + match(Set dst (ConvD2I src)); 1.47 + 1.48 + ins_cost(250); 1.49 + format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_slow" %} 1.50 1.51 ins_encode %{ 1.52 FloatRegister src = $src$$FloatRegister;