[C2] Add rolI_Reg_immI_0_31 and rorI_Reg_immI_0_31 in mips_64.ad

Sat, 18 Feb 2017 18:56:55 -0500

author
fujie
date
Sat, 18 Feb 2017 18:56:55 -0500
changeset 316
28e6fbbe225f
parent 315
8ac5b6ff8466
child 317
001d396b2d46

[C2] Add rolI_Reg_immI_0_31 and rorI_Reg_immI_0_31 in mips_64.ad

src/cpu/mips/vm/mips_64.ad file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Sat Feb 18 18:25:01 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Sat Feb 18 18:56:55 2017 -0500
     1.3 @@ -11139,6 +11139,38 @@
     1.4    ins_pipe( ialu_regI_regI );
     1.5  %}
     1.6  
     1.7 +instruct rolI_Reg_immI_0_31(mRegI dst, immI_0_31 lshift, immI_0_31 rshift)
     1.8 +%{
     1.9 +  predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
    1.10 +  match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
    1.11 +
    1.12 +  ins_cost(100);
    1.13 +  format %{ "rotr    $dst, $dst, $rshift #@rolI_Reg_immI_0_31" %}
    1.14 +  ins_encode %{
    1.15 +    Register dst = $dst$$Register;
    1.16 +    int      sa  = $rshift$$constant;
    1.17 +
    1.18 +    __ rotr(dst, dst, sa);
    1.19 +  %}
    1.20 +  ins_pipe( ialu_regI_regI );
    1.21 +%}
    1.22 +
    1.23 +instruct rorI_Reg_immI_0_31(mRegI dst, immI_0_31 rshift, immI_0_31 lshift)
    1.24 +%{
    1.25 +  predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
    1.26 +  match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
    1.27 +
    1.28 +  ins_cost(100);
    1.29 +  format %{ "rotr    $dst, $dst, $rshift #@rorI_Reg_immI_0_31" %}
    1.30 +  ins_encode %{
    1.31 +    Register dst = $dst$$Register;
    1.32 +    int      sa  = $rshift$$constant;
    1.33 +
    1.34 +    __ rotr(dst, dst, sa);
    1.35 +  %}
    1.36 +  ins_pipe( ialu_regI_regI );
    1.37 +%}
    1.38 +
    1.39  // Logical Shift Right 
    1.40  instruct shr_logical_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
    1.41    match(Set dst (URShiftI src shift));

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