src/cpu/mips/vm/mips_64.ad

changeset 314
5682475ccb5d
parent 313
d2c593f7367a
child 316
28e6fbbe225f
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Sun Feb 19 17:09:02 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Sun Feb 19 17:42:22 2017 +0800
     1.3 @@ -12982,12 +12982,7 @@
     1.4      Register dst = $dst$$Register;
     1.5      Register src = $src$$Register;
     1.6  
     1.7 -    if (dst == src) {
     1.8 -       __ dext(dst, src, 0, 32);
     1.9 -    } else {
    1.10 -       __ dsll32(dst, src, 0);
    1.11 -       __ dsrl32(dst, dst, 0);
    1.12 -    }
    1.13 +    __ dext(dst, src, 0, 32);
    1.14    %}
    1.15    ins_pipe(ialu_regI_regI);
    1.16  %}
    1.17 @@ -13002,12 +12997,7 @@
    1.18      Register dst = $dst$$Register;
    1.19      Register src = $src$$Register;
    1.20  
    1.21 -    if (dst == src) {
    1.22 -       __ dext(dst, src, 0, 32);
    1.23 -    } else {
    1.24 -       __ dsll32(dst, src, 0);
    1.25 -       __ dsrl32(dst, dst, 0);
    1.26 -    }
    1.27 +    __ dext(dst, src, 0, 32);
    1.28    %}
    1.29    ins_pipe(ialu_regI_regI);
    1.30  %}
    1.31 @@ -13021,12 +13011,7 @@
    1.32      Register dst = $dst$$Register;
    1.33      Register src = $src$$Register;
    1.34  
    1.35 -    if (dst == src) {
    1.36 -       __ dext(dst, src, 0, 32);
    1.37 -    } else {
    1.38 -       __ dsll32(dst, src, 0);
    1.39 -       __ dsrl32(dst, dst, 0);
    1.40 -    }
    1.41 +    __ dext(dst, src, 0, 32);
    1.42    %}
    1.43    ins_pipe(ialu_regI_regI);
    1.44  %}

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