Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 15:56:09 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Thu Feb 16 03:58:02 2017 -0500
     1.3 @@ -6119,13 +6119,7 @@
     1.4  
     1.5     ins_cost(125); // XXX
     1.6     format %{ "lwu    $dst, $mem\t# compressed ptr @ loadN" %}
     1.7 -//TODO: Address should be implemented
     1.8 -/*
     1.9 -   ins_encode %{
    1.10 -     __ lwu($dst$$Register, $mem$$Address);
    1.11 -   %}
    1.12 -*/
    1.13 -  ins_encode (load_N_enc(dst, mem));
    1.14 +   ins_encode (load_N_enc(dst, mem));
    1.15     ins_pipe( ialu_loadI ); // XXX
    1.16  %}
    1.17  
    1.18 @@ -6157,11 +6151,6 @@
    1.19    ins_cost(125); // XXX
    1.20    format %{ "lwu    $dst, $mem\t# compressed klass ptr @ loadNKlass" %}
    1.21    ins_encode (load_N_enc(dst, mem));
    1.22 -/*
    1.23 -  ins_encode %{
    1.24 -    __ lwu($dst$$Register, $mem$$Address);
    1.25 -  %}
    1.26 -*/
    1.27    ins_pipe( ialu_loadI ); // XXX
    1.28  %}
    1.29  
    1.30 @@ -6179,19 +6168,6 @@
    1.31    ins_pipe( ialu_regI_regI );
    1.32  %}
    1.33  
    1.34 -// Load Constant 65536
    1.35 -instruct loadConI_65536(mRegI dst, immI_65536 src) %{
    1.36 -  match(Set dst src);
    1.37 -
    1.38 -  ins_cost(100);
    1.39 -  format %{ "mov    $dst, 65536 #@loadConI_65536" %}
    1.40 -  ins_encode %{
    1.41 -    Register dst = $dst$$Register;
    1.42 -
    1.43 -    __ lui(dst, 1);
    1.44 -  %}
    1.45 -  ins_pipe( ialu_regI_regI );
    1.46 -%}
    1.47  
    1.48  instruct loadConL_set64(mRegL dst, immL src) %{
    1.49    match(Set dst src);
    1.50 @@ -7767,21 +7743,6 @@
    1.51    ins_pipe( pipe_alu_branch );
    1.52  %}
    1.53  
    1.54 -/*
    1.55 -// Conditional Direct Branch
    1.56 -instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
    1.57 -  match(If cmp icc);
    1.58 -  effect(USE labl);
    1.59 -
    1.60 -  size(8);
    1.61 -  ins_cost(BRANCH_COST);
    1.62 -  format %{ "BP$cmp   $icc,$labl" %}
    1.63 -  // Prim = bits 24-22, Secnd = bits 31-30
    1.64 -  ins_encode( enc_bp( labl, cmp, icc ) );
    1.65 -  ins_pc_relative(1);
    1.66 -  ins_pipe(br_cc);
    1.67 -%}
    1.68 -*/
    1.69  
    1.70  //FIXME
    1.71  instruct branchConF_reg_reg(cmpOp cmp, regF src1, regF src2, label labl) %{
    1.72 @@ -9743,9 +9704,8 @@
    1.73    ins_pipe( ialu_regI_regI );
    1.74  %}
    1.75  
    1.76 -instruct addP_reg_imm(mRegP dst, mRegP src1,  immL32 src2) %{
    1.77 +instruct addP_reg_imm(mRegP dst, mRegP src1,  immL src2) %{
    1.78    match(Set dst (AddP src1 src2));
    1.79 -//  effect(KILL cr);
    1.80  
    1.81    format %{ "daddi   $dst, $src1, $src2 #@addP_reg_imm" %}
    1.82    ins_encode %{
    1.83 @@ -9756,7 +9716,7 @@
    1.84      if(Assembler::is_simm16(src2)) {
    1.85         __ daddiu(dst, src1, src2);
    1.86      } else {
    1.87 -       __ li(AT, src2);
    1.88 +       __ set64(AT, src2);
    1.89         __ daddu(dst, src1, AT);
    1.90      }
    1.91    %}
    1.92 @@ -10372,10 +10332,10 @@
    1.93  
    1.94  //And Instuctions
    1.95  // And Register with Immediate
    1.96 -instruct andI_Reg_imm(mRegI dst, mRegI src1,  immI src2) %{
    1.97 +instruct andI_Reg_immI(mRegI dst, mRegI src1,  immI src2) %{
    1.98    match(Set dst (AndI src1 src2));
    1.99  
   1.100 -  format %{ "and  $dst, $src1, $src2 #@andI_Reg_imm" %}
   1.101 +  format %{ "and  $dst, $src1, $src2 #@andI_Reg_immI" %}
   1.102    ins_encode %{
   1.103      Register dst = $dst$$Register;
   1.104      Register src = $src1$$Register;