1.1 --- a/src/cpu/mips/vm/mips_64.ad Wed Feb 15 12:37:43 2017 -0500
1.2 +++ b/src/cpu/mips/vm/mips_64.ad Wed Feb 15 12:58:01 2017 -0500
1.3 @@ -12952,6 +12952,20 @@
1.4 ins_pipe(ialu_regI_regI);
1.5 %}
1.6
1.7 +instruct convL2I2L_reg_reg_zex(mRegL dst, mRegL src, immL_32bits mask)
1.8 +%{
1.9 + match(Set dst (AndL (ConvI2L (ConvL2I src)) mask));
1.10 +
1.11 + format %{ "movl $dst, $src\t# i2l zero-extend @ convL2I2L_reg_reg_zex" %}
1.12 + ins_encode %{
1.13 + Register dst = $dst$$Register;
1.14 + Register src = $src$$Register;
1.15 +
1.16 + __ dsll32(dst, src, 0);
1.17 + __ dsrl32(dst, dst, 0);
1.18 + %}
1.19 + ins_pipe(ialu_regI_regI);
1.20 +%}
1.21
1.22 // Match loading integer and casting it to unsigned int in long register.
1.23 // LoadI + ConvI2L + AndL 0xffffffff.
