Sun, 19 Feb 2017 17:09:02 +0800
[C2] Optimize instruct salL_Reg_Reg in mips_64.ad
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Sun Feb 19 16:34:38 2017 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Sun Feb 19 17:09:02 2017 +0800 1.3 @@ -10916,13 +10916,10 @@ 1.4 ins_cost(100); 1.5 format %{ "salL $dst, $src, $shift @ salL_Reg_Reg" %} 1.6 ins_encode %{ 1.7 - Register creg = T9; 1.8 Register src_reg = as_Register($src$$reg); 1.9 Register dst_reg = as_Register($dst$$reg); 1.10 1.11 - __ move(creg, $shift$$Register); 1.12 - __ andi(creg, creg, 0x3f); 1.13 - __ dsllv(dst_reg, src_reg, creg); 1.14 + __ dsllv(dst_reg, src_reg, $shift$$Register); 1.15 %} 1.16 ins_pipe( ialu_regL_regL ); 1.17 %}