1.1 --- a/src/cpu/mips/vm/mips_64.ad Thu Feb 16 05:45:03 2017 -0500 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Feb 16 07:55:00 2017 -0500 1.3 @@ -11358,9 +11358,27 @@ 1.4 ins_pipe( pipe_slow ); 1.5 %} 1.6 1.7 -instruct convF2L_reg( mRegL dst, regF src ) %{ 1.8 +instruct convF2L_reg_fast( mRegL dst, regF src ) %{ 1.9 match(Set dst (ConvF2L src)); 1.10 - format %{ "convf2l $dst, $src @ convF2L_reg" %} 1.11 + ins_cost(150); 1.12 + format %{ "convf2l $dst, $src @ convF2L_reg_fast" %} 1.13 + ins_encode %{ 1.14 + Register dreg = $dst$$Register; 1.15 + FloatRegister fval = $src$$FloatRegister; 1.16 + 1.17 + __ trunc_l_s(F30, fval); 1.18 + __ dmfc1(dreg, F30); 1.19 + __ c_un_s(fval, fval); //NaN? 1.20 + __ movt(dreg, R0); 1.21 + %} 1.22 + 1.23 + ins_pipe( pipe_slow ); 1.24 +%} 1.25 + 1.26 +instruct convF2L_reg_slow( mRegL dst, regF src ) %{ 1.27 + match(Set dst (ConvF2L src)); 1.28 + ins_cost(250); 1.29 + format %{ "convf2l $dst, $src @ convF2L_reg_slow" %} 1.30 ins_encode %{ 1.31 Register dst = as_Register($dst$$reg); 1.32 FloatRegister fval = $src$$FloatRegister;