src/cpu/mips/vm/mips_64.ad

changeset 302
f4ccb4aa25f1
parent 301
d585b6706dc2
child 303
3c47814d2976
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 10:22:07 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 12:37:43 2017 -0500
     1.3 @@ -11277,6 +11277,20 @@
     1.4    ins_pipe( ialu_regI_regI );
     1.5  %}
     1.6  
     1.7 +instruct convL2I2L_reg( mRegL dst, mRegL src ) %{
     1.8 +  match(Set dst (ConvI2L (ConvL2I src)));
     1.9 +
    1.10 +  format %{ "sll    $dst, $src, 0 @ convL2I2L_reg" %}
    1.11 +  ins_encode %{
    1.12 +    Register dst = as_Register($dst$$reg);
    1.13 +    Register src = as_Register($src$$reg);
    1.14 +
    1.15 +    __ sll(dst, src, 0);
    1.16 +  %}
    1.17 +
    1.18 +  ins_pipe( ialu_regI_regI );
    1.19 +%}
    1.20 +
    1.21  instruct convL2D_reg( regD dst, mRegL src ) %{
    1.22    match(Set dst (ConvL2D src));
    1.23    format %{ "convL2D    $dst, $src @ convL2D_reg" %}

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