Sun, 19 Feb 2017 16:34:38 +0800
[C2] Use dext to optimize zero-extend operations for MIPS.
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Thu Feb 16 09:56:42 2017 -0500 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Sun Feb 19 16:34:38 2017 +0800 1.3 @@ -12985,8 +12985,12 @@ 1.4 Register dst = $dst$$Register; 1.5 Register src = $src$$Register; 1.6 1.7 - __ dsll32(dst, src, 0); 1.8 - __ dsrl32(dst, dst, 0); 1.9 + if (dst == src) { 1.10 + __ dext(dst, src, 0, 32); 1.11 + } else { 1.12 + __ dsll32(dst, src, 0); 1.13 + __ dsrl32(dst, dst, 0); 1.14 + } 1.15 %} 1.16 ins_pipe(ialu_regI_regI); 1.17 %} 1.18 @@ -13001,8 +13005,12 @@ 1.19 Register dst = $dst$$Register; 1.20 Register src = $src$$Register; 1.21 1.22 - __ dsll32(dst, src, 0); 1.23 - __ dsrl32(dst, dst, 0); 1.24 + if (dst == src) { 1.25 + __ dext(dst, src, 0, 32); 1.26 + } else { 1.27 + __ dsll32(dst, src, 0); 1.28 + __ dsrl32(dst, dst, 0); 1.29 + } 1.30 %} 1.31 ins_pipe(ialu_regI_regI); 1.32 %} 1.33 @@ -13016,8 +13024,12 @@ 1.34 Register dst = $dst$$Register; 1.35 Register src = $src$$Register; 1.36 1.37 - __ dsll32(dst, src, 0); 1.38 - __ dsrl32(dst, dst, 0); 1.39 + if (dst == src) { 1.40 + __ dext(dst, src, 0, 32); 1.41 + } else { 1.42 + __ dsll32(dst, src, 0); 1.43 + __ dsrl32(dst, dst, 0); 1.44 + } 1.45 %} 1.46 ins_pipe(ialu_regI_regI); 1.47 %}