1.1 --- a/src/cpu/mips/vm/mips_64.ad Mon Feb 20 21:27:49 2017 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Mon Feb 20 21:35:55 2017 +0800 1.3 @@ -11097,13 +11097,8 @@ 1.4 Register src = $src$$Register; 1.5 Register dst = $dst$$Register; 1.6 int shift = $shift$$constant; 1.7 - if (shift > 0) 1.8 - __ srl(dst, src, shift); 1.9 - else 1.10 - { 1.11 - __ move(AT, shift); 1.12 - __ srlv(dst, src, AT); 1.13 - } 1.14 + 1.15 + __ srl(dst, src, shift); 1.16 %} 1.17 ins_pipe( ialu_regI_regI ); 1.18 %}