src/cpu/mips/vm/mips_64.ad

changeset 300
5c43ed10ee2f
parent 299
9742e61a5f2d
child 301
d585b6706dc2
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 07:56:12 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Feb 15 09:29:03 2017 -0500
     1.3 @@ -10374,6 +10374,21 @@
     1.4    ins_pipe( ialu_regI_regI );
     1.5  %}
     1.6  
     1.7 +instruct andI_Reg_immI_nonneg_mask(mRegI dst, mRegI src1,  immI_nonneg_mask mask) %{
     1.8 +  match(Set dst (AndI src1 mask));
     1.9 +  ins_cost(60);
    1.10 +
    1.11 +  format %{ "and  $dst, $src1, $mask #@andI_Reg_immI_nonneg_mask" %}
    1.12 +  ins_encode %{
    1.13 +    Register dst = $dst$$Register;
    1.14 +    Register src = $src1$$Register;
    1.15 +    int     size = Assembler::is_int_mask($mask$$constant);
    1.16 +
    1.17 +    __ ext(dst, src, 0, size);
    1.18 +  %}
    1.19 +  ins_pipe( ialu_regI_regI );
    1.20 +%}
    1.21 +
    1.22  instruct xorI_Reg_imm_0_65535(mRegI dst, mRegI src1,  immI_0_65535 src2) %{
    1.23    match(Set dst (XorI src1 src2));
    1.24    ins_cost(60);

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