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src/cpu/mips/vm/mips_64.ad@f4ccb4aa25f1
src/cpu/mips/vm/mips_64.ad
Wed, 15 Feb 2017 12:37:43 -0500
- author
- fujie
- date
- Wed, 15 Feb 2017 12:37:43 -0500
- changeset 302
- f4ccb4aa25f1
- parent 301
- d585b6706dc2
- child 303
- 3c47814d2976
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- -rw-r--r--
[C2] Add instruct convL2I2L_reg in mips_64.ad
1 //
2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
26 // GodSon3 Architecture Description File
28 //----------REGISTER DEFINITION BLOCK------------------------------------------
29 // This information is used by the matcher and the register allocator to
30 // describe individual registers and classes of registers within the target
31 // archtecture.
33 // format:
34 // reg_def name (call convention, c-call convention, ideal type, encoding);
35 // call convention :
36 // NS = No-Save
37 // SOC = Save-On-Call
38 // SOE = Save-On-Entry
39 // AS = Always-Save
40 // ideal type :
41 // see opto/opcodes.hpp for more info
42 // reg_class name (reg, ...);
43 // alloc_class name (reg, ...);
44 register %{
46 // General Registers
47 // Integer Registers
48 reg_def R0 ( NS, NS, Op_RegI, 0, VMRegImpl::Bad());
49 reg_def AT ( NS, NS, Op_RegI, 1, AT->as_VMReg());
50 reg_def AT_H ( NS, NS, Op_RegI, 1, AT->as_VMReg()->next());
51 reg_def V0 (SOC, SOC, Op_RegI, 2, V0->as_VMReg());
52 reg_def V0_H (SOC, SOC, Op_RegI, 2, V0->as_VMReg()->next());
53 reg_def V1 (SOC, SOC, Op_RegI, 3, V1->as_VMReg());
54 reg_def V1_H (SOC, SOC, Op_RegI, 3, V1->as_VMReg()->next());
55 reg_def A0 (SOC, SOC, Op_RegI, 4, A0->as_VMReg());
56 reg_def A0_H (SOC, SOC, Op_RegI, 4, A0->as_VMReg()->next());
57 reg_def A1 (SOC, SOC, Op_RegI, 5, A1->as_VMReg());
58 reg_def A1_H (SOC, SOC, Op_RegI, 5, A1->as_VMReg()->next());
59 reg_def A2 (SOC, SOC, Op_RegI, 6, A2->as_VMReg());
60 reg_def A2_H (SOC, SOC, Op_RegI, 6, A2->as_VMReg()->next());
61 reg_def A3 (SOC, SOC, Op_RegI, 7, A3->as_VMReg());
62 reg_def A3_H (SOC, SOC, Op_RegI, 7, A3->as_VMReg()->next());
63 reg_def A4 (SOC, SOC, Op_RegI, 8, A4->as_VMReg());
64 reg_def A4_H (SOC, SOC, Op_RegI, 8, A4->as_VMReg()->next());
65 reg_def A5 (SOC, SOC, Op_RegI, 9, A5->as_VMReg());
66 reg_def A5_H (SOC, SOC, Op_RegI, 9, A5->as_VMReg()->next());
67 reg_def A6 (SOC, SOC, Op_RegI, 10, A6->as_VMReg());
68 reg_def A6_H (SOC, SOC, Op_RegI, 10, A6->as_VMReg()->next());
69 reg_def A7 (SOC, SOC, Op_RegI, 11, A7->as_VMReg());
70 reg_def A7_H (SOC, SOC, Op_RegI, 11, A7->as_VMReg()->next());
71 reg_def T0 (SOC, SOC, Op_RegI, 12, T0->as_VMReg());
72 reg_def T0_H (SOC, SOC, Op_RegI, 12, T0->as_VMReg()->next());
73 reg_def T1 (SOC, SOC, Op_RegI, 13, T1->as_VMReg());
74 reg_def T1_H (SOC, SOC, Op_RegI, 13, T1->as_VMReg()->next());
75 reg_def T2 (SOC, SOC, Op_RegI, 14, T2->as_VMReg());
76 reg_def T2_H (SOC, SOC, Op_RegI, 14, T2->as_VMReg()->next());
77 reg_def T3 (SOC, SOC, Op_RegI, 15, T3->as_VMReg());
78 reg_def T3_H (SOC, SOC, Op_RegI, 15, T3->as_VMReg()->next());
79 reg_def S0 (SOC, SOE, Op_RegI, 16, S0->as_VMReg());
80 reg_def S0_H (SOC, SOE, Op_RegI, 16, S0->as_VMReg()->next());
81 reg_def S1 (SOC, SOE, Op_RegI, 17, S1->as_VMReg());
82 reg_def S1_H (SOC, SOE, Op_RegI, 17, S1->as_VMReg()->next());
83 reg_def S2 (SOC, SOE, Op_RegI, 18, S2->as_VMReg());
84 reg_def S2_H (SOC, SOE, Op_RegI, 18, S2->as_VMReg()->next());
85 reg_def S3 (SOC, SOE, Op_RegI, 19, S3->as_VMReg());
86 reg_def S3_H (SOC, SOE, Op_RegI, 19, S3->as_VMReg()->next());
87 reg_def S4 (SOC, SOE, Op_RegI, 20, S4->as_VMReg());
88 reg_def S4_H (SOC, SOE, Op_RegI, 20, S4->as_VMReg()->next());
89 reg_def S5 (SOC, SOE, Op_RegI, 21, S5->as_VMReg());
90 reg_def S5_H (SOC, SOE, Op_RegI, 21, S5->as_VMReg()->next());
91 reg_def S6 (SOC, SOE, Op_RegI, 22, S6->as_VMReg());
92 reg_def S6_H (SOC, SOE, Op_RegI, 22, S6->as_VMReg()->next());
93 reg_def S7 (SOC, SOE, Op_RegI, 23, S7->as_VMReg());
94 reg_def S7_H (SOC, SOE, Op_RegI, 23, S7->as_VMReg()->next());
95 reg_def T8 (SOC, SOC, Op_RegI, 24, T8->as_VMReg());
96 reg_def T8_H (SOC, SOC, Op_RegI, 24, T8->as_VMReg()->next());
97 reg_def T9 (SOC, SOC, Op_RegI, 25, T9->as_VMReg());
98 reg_def T9_H (SOC, SOC, Op_RegI, 25, T9->as_VMReg()->next());
100 // Special Registers
101 reg_def K0 ( NS, NS, Op_RegI, 26, K0->as_VMReg());
102 reg_def K1 ( NS, NS, Op_RegI, 27, K1->as_VMReg());
103 reg_def GP ( NS, NS, Op_RegI, 28, GP->as_VMReg());
104 reg_def GP_H ( NS, NS, Op_RegI, 28, GP->as_VMReg()->next());
105 reg_def SP ( NS, NS, Op_RegI, 29, SP->as_VMReg());
106 reg_def SP_H ( NS, NS, Op_RegI, 29, SP->as_VMReg()->next());
107 reg_def FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
108 reg_def FP_H ( NS, NS, Op_RegI, 30, FP->as_VMReg()->next());
109 reg_def RA ( NS, NS, Op_RegI, 31, RA->as_VMReg());
110 reg_def RA_H ( NS, NS, Op_RegI, 31, RA->as_VMReg()->next());
112 // Floating registers.
113 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
114 reg_def F0_H ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()->next());
115 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
116 reg_def F1_H ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()->next());
117 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
118 reg_def F2_H ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()->next());
119 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
120 reg_def F3_H ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()->next());
121 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
122 reg_def F4_H ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()->next());
123 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
124 reg_def F5_H ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()->next());
125 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
126 reg_def F6_H ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()->next());
127 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
128 reg_def F7_H ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()->next());
129 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
130 reg_def F8_H ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()->next());
131 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
132 reg_def F9_H ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()->next());
133 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
134 reg_def F10_H ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()->next());
135 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
136 reg_def F11_H ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()->next());
137 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
138 reg_def F12_H ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()->next());
139 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
140 reg_def F13_H ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()->next());
141 reg_def F14 ( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
142 reg_def F14_H ( SOC, SOC, Op_RegF, 14, F14->as_VMReg()->next());
143 reg_def F15 ( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
144 reg_def F15_H ( SOC, SOC, Op_RegF, 15, F15->as_VMReg()->next());
145 reg_def F16 ( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
146 reg_def F16_H ( SOC, SOC, Op_RegF, 16, F16->as_VMReg()->next());
147 reg_def F17 ( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
148 reg_def F17_H ( SOC, SOC, Op_RegF, 17, F17->as_VMReg()->next());
149 reg_def F18 ( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
150 reg_def F18_H ( SOC, SOC, Op_RegF, 18, F18->as_VMReg()->next());
151 reg_def F19 ( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
152 reg_def F19_H ( SOC, SOC, Op_RegF, 19, F19->as_VMReg()->next());
153 reg_def F20 ( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
154 reg_def F20_H ( SOC, SOC, Op_RegF, 20, F20->as_VMReg()->next());
155 reg_def F21 ( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
156 reg_def F21_H ( SOC, SOC, Op_RegF, 21, F21->as_VMReg()->next());
157 reg_def F22 ( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
158 reg_def F22_H ( SOC, SOC, Op_RegF, 22, F22->as_VMReg()->next());
159 reg_def F23 ( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
160 reg_def F23_H ( SOC, SOC, Op_RegF, 23, F23->as_VMReg()->next());
161 reg_def F24 ( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
162 reg_def F24_H ( SOC, SOC, Op_RegF, 24, F24->as_VMReg()->next());
163 reg_def F25 ( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
164 reg_def F25_H ( SOC, SOC, Op_RegF, 25, F25->as_VMReg()->next());
165 reg_def F26 ( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
166 reg_def F26_H ( SOC, SOC, Op_RegF, 26, F26->as_VMReg()->next());
167 reg_def F27 ( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
168 reg_def F27_H ( SOC, SOC, Op_RegF, 27, F27->as_VMReg()->next());
169 reg_def F28 ( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
170 reg_def F28_H ( SOC, SOC, Op_RegF, 28, F28->as_VMReg()->next());
171 reg_def F29 ( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
172 reg_def F29_H ( SOC, SOC, Op_RegF, 29, F29->as_VMReg()->next());
173 reg_def F30 ( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
174 reg_def F30_H ( SOC, SOC, Op_RegF, 30, F30->as_VMReg()->next());
175 reg_def F31 ( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
176 reg_def F31_H ( SOC, SOC, Op_RegF, 31, F31->as_VMReg()->next());
179 // ----------------------------
180 // Special Registers
181 // Condition Codes Flag Registers
182 reg_def MIPS_FLAG (SOC, SOC, Op_RegFlags, 1, as_Register(1)->as_VMReg());
183 //S6 is used for get_thread(S6)
184 //S5 is uesd for heapbase of compressed oop
185 alloc_class chunk0(
186 S7, S7_H,
187 S0, S0_H,
188 S1, S1_H,
189 S2, S2_H,
190 S4, S4_H,
191 S5, S5_H,
192 S6, S6_H,
193 S3, S3_H,
194 T2, T2_H,
195 T3, T3_H,
196 T8, T8_H,
197 T9, T9_H,
198 T1, T1_H, // inline_cache_reg
199 V1, V1_H,
200 A7, A7_H,
201 A6, A6_H,
202 A5, A5_H,
203 A4, A4_H,
204 V0, V0_H,
205 A3, A3_H,
206 A2, A2_H,
207 A1, A1_H,
208 A0, A0_H,
209 T0, T0_H,
210 GP, GP_H
211 RA, RA_H,
212 SP, SP_H, // stack_pointer
213 FP, FP_H // frame_pointer
214 );
216 alloc_class chunk1( F0, F0_H,
217 F1, F1_H,
218 F2, F2_H,
219 F3, F3_H,
220 F4, F4_H,
221 F5, F5_H,
222 F6, F6_H,
223 F7, F7_H,
224 F8, F8_H,
225 F9, F9_H,
226 F10, F10_H,
227 F11, F11_H,
228 F20, F20_H,
229 F21, F21_H,
230 F22, F22_H,
231 F23, F23_H,
232 F24, F24_H,
233 F25, F25_H,
234 F26, F26_H,
235 F27, F27_H,
236 F28, F28_H,
237 F19, F19_H,
238 F18, F18_H,
239 F17, F17_H,
240 F16, F16_H,
241 F15, F15_H,
242 F14, F14_H,
243 F13, F13_H,
244 F12, F12_H,
245 F29, F29_H,
246 F30, F30_H,
247 F31, F31_H);
249 alloc_class chunk2(MIPS_FLAG);
251 reg_class s_reg( S0, S1, S2, S3, S4, S5, S6, S7 );
252 reg_class s0_reg( S0 );
253 reg_class s1_reg( S1 );
254 reg_class s2_reg( S2 );
255 reg_class s3_reg( S3 );
256 reg_class s4_reg( S4 );
257 reg_class s5_reg( S5 );
258 reg_class s6_reg( S6 );
259 reg_class s7_reg( S7 );
261 reg_class t_reg( T0, T1, T2, T3, T8, T9 );
262 reg_class t0_reg( T0 );
263 reg_class t1_reg( T1 );
264 reg_class t2_reg( T2 );
265 reg_class t3_reg( T3 );
266 reg_class t8_reg( T8 );
267 reg_class t9_reg( T9 );
269 reg_class a_reg( A0, A1, A2, A3, A4, A5, A6, A7 );
270 reg_class a0_reg( A0 );
271 reg_class a1_reg( A1 );
272 reg_class a2_reg( A2 );
273 reg_class a3_reg( A3 );
274 reg_class a4_reg( A4 );
275 reg_class a5_reg( A5 );
276 reg_class a6_reg( A6 );
277 reg_class a7_reg( A7 );
279 reg_class v0_reg( V0 );
280 reg_class v1_reg( V1 );
282 reg_class sp_reg( SP, SP_H );
283 reg_class fp_reg( FP, FP_H );
285 reg_class mips_flags(MIPS_FLAG);
287 reg_class v0_long_reg( V0, V0_H );
288 reg_class v1_long_reg( V1, V1_H );
289 reg_class a0_long_reg( A0, A0_H );
290 reg_class a1_long_reg( A1, A1_H );
291 reg_class a2_long_reg( A2, A2_H );
292 reg_class a3_long_reg( A3, A3_H );
293 reg_class a4_long_reg( A4, A4_H );
294 reg_class a5_long_reg( A5, A5_H );
295 reg_class a6_long_reg( A6, A6_H );
296 reg_class a7_long_reg( A7, A7_H );
297 reg_class t0_long_reg( T0, T0_H );
298 reg_class t1_long_reg( T1, T1_H );
299 reg_class t2_long_reg( T2, T2_H );
300 reg_class t3_long_reg( T3, T3_H );
301 reg_class t8_long_reg( T8, T8_H );
302 reg_class t9_long_reg( T9, T9_H );
303 reg_class s0_long_reg( S0, S0_H );
304 reg_class s1_long_reg( S1, S1_H );
305 reg_class s2_long_reg( S2, S2_H );
306 reg_class s3_long_reg( S3, S3_H );
307 reg_class s4_long_reg( S4, S4_H );
308 reg_class s5_long_reg( S5, S5_H );
309 reg_class s6_long_reg( S6, S6_H );
310 reg_class s7_long_reg( S7, S7_H );
312 reg_class int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, A7, A6, A5, A4, V0, A3, A2, A1, A0, T0 );
314 reg_class no_Ax_int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, V0, T0 );
316 reg_class p_reg(
317 S7, S7_H,
318 S0, S0_H,
319 S1, S1_H,
320 S2, S2_H,
321 S4, S4_H,
322 S3, S3_H,
323 T8, T8_H,
324 T2, T2_H,
325 T3, T3_H,
326 T1, T1_H,
327 A7, A7_H,
328 A6, A6_H,
329 A5, A5_H,
330 A4, A4_H,
331 A3, A3_H,
332 A2, A2_H,
333 A1, A1_H,
334 A0, A0_H,
335 T0, T0_H
336 );
338 reg_class no_T8_p_reg(
339 S7, S7_H,
340 S0, S0_H,
341 S1, S1_H,
342 S2, S2_H,
343 S4, S4_H,
344 S3, S3_H,
345 T2, T2_H,
346 T3, T3_H,
347 T1, T1_H,
348 A7, A7_H,
349 A6, A6_H,
350 A5, A5_H,
351 A4, A4_H,
352 A3, A3_H,
353 A2, A2_H,
354 A1, A1_H,
355 A0, A0_H,
356 T0, T0_H
357 );
359 reg_class long_reg(
360 S7, S7_H,
361 S0, S0_H,
362 S1, S1_H,
363 S2, S2_H,
364 S4, S4_H,
365 S3, S3_H,
366 T8, T8_H,
367 T2, T2_H,
368 T3, T3_H,
369 T1, T1_H,
370 A7, A7_H,
371 A6, A6_H,
372 A5, A5_H,
373 A4, A4_H,
374 A3, A3_H,
375 A2, A2_H,
376 A1, A1_H,
377 A0, A0_H,
378 T0, T0_H
379 );
382 // Floating point registers.
383 // 2012/8/23 Fu: F30/F31 are used as temporary registers in D2I
384 // 2016/12/1 aoqi: F31 are not used as temporary registers in D2I
385 reg_class flt_reg( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17 F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F31);
386 reg_class dbl_reg( F0, F0_H,
387 F1, F1_H,
388 F2, F2_H,
389 F3, F3_H,
390 F4, F4_H,
391 F5, F5_H,
392 F6, F6_H,
393 F7, F7_H,
394 F8, F8_H,
395 F9, F9_H,
396 F10, F10_H,
397 F11, F11_H,
398 F12, F12_H,
399 F13, F13_H,
400 F14, F14_H,
401 F15, F15_H,
402 F16, F16_H,
403 F17, F17_H,
404 F18, F18_H,
405 F19, F19_H,
406 F20, F20_H,
407 F21, F21_H,
408 F22, F22_H,
409 F23, F23_H,
410 F24, F24_H,
411 F25, F25_H,
412 F26, F26_H,
413 F27, F27_H,
414 F28, F28_H,
415 F29, F29_H,
416 F31, F31_H);
418 reg_class flt_arg0( F12 );
419 reg_class dbl_arg0( F12, F12_H );
420 reg_class dbl_arg1( F14, F14_H );
422 %}
424 //----------DEFINITION BLOCK---------------------------------------------------
425 // Define name --> value mappings to inform the ADLC of an integer valued name
426 // Current support includes integer values in the range [0, 0x7FFFFFFF]
427 // Format:
428 // int_def <name> ( <int_value>, <expression>);
429 // Generated Code in ad_<arch>.hpp
430 // #define <name> (<expression>)
431 // // value == <int_value>
432 // Generated code in ad_<arch>.cpp adlc_verification()
433 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
434 //
435 definitions %{
436 int_def DEFAULT_COST ( 100, 100);
437 int_def HUGE_COST (1000000, 1000000);
439 // Memory refs are twice as expensive as run-of-the-mill.
440 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
442 // Branches are even more expensive.
443 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
444 // we use jr instruction to construct call, so more expensive
445 // by yjl 2/28/2006
446 int_def CALL_COST ( 500, DEFAULT_COST * 5);
447 /*
448 int_def EQUAL ( 1, 1 );
449 int_def NOT_EQUAL ( 2, 2 );
450 int_def GREATER ( 3, 3 );
451 int_def GREATER_EQUAL ( 4, 4 );
452 int_def LESS ( 5, 5 );
453 int_def LESS_EQUAL ( 6, 6 );
454 */
455 %}
459 //----------SOURCE BLOCK-------------------------------------------------------
460 // This is a block of C++ code which provides values, functions, and
461 // definitions necessary in the rest of the architecture description
463 source_hpp %{
464 // Header information of the source block.
465 // Method declarations/definitions which are used outside
466 // the ad-scope can conveniently be defined here.
467 //
468 // To keep related declarations/definitions/uses close together,
469 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
471 class CallStubImpl {
473 //--------------------------------------------------------------
474 //---< Used for optimization in Compile::shorten_branches >---
475 //--------------------------------------------------------------
477 public:
478 // Size of call trampoline stub.
479 static uint size_call_trampoline() {
480 return 0; // no call trampolines on this platform
481 }
483 // number of relocations needed by a call trampoline stub
484 static uint reloc_call_trampoline() {
485 return 0; // no call trampolines on this platform
486 }
487 };
489 class HandlerImpl {
491 public:
493 static int emit_exception_handler(CodeBuffer &cbuf);
494 static int emit_deopt_handler(CodeBuffer& cbuf);
496 static uint size_exception_handler() {
497 // NativeCall instruction size is the same as NativeJump.
498 // exception handler starts out as jump and can be patched to
499 // a call be deoptimization. (4932387)
500 // Note that this value is also credited (in output.cpp) to
501 // the size of the code section.
502 // return NativeJump::instruction_size;
503 int size = NativeCall::instruction_size;
504 return round_to(size, 16);
505 }
507 #ifdef _LP64
508 static uint size_deopt_handler() {
509 int size = NativeCall::instruction_size;
510 return round_to(size, 16);
511 }
512 #else
513 static uint size_deopt_handler() {
514 // NativeCall instruction size is the same as NativeJump.
515 // exception handler starts out as jump and can be patched to
516 // a call be deoptimization. (4932387)
517 // Note that this value is also credited (in output.cpp) to
518 // the size of the code section.
519 return 5 + NativeJump::instruction_size; // pushl(); jmp;
520 }
521 #endif
522 };
524 %} // end source_hpp
526 source %{
528 #define NO_INDEX 0
529 #define RELOC_IMM64 Assembler::imm_operand
530 #define RELOC_DISP32 Assembler::disp32_operand
533 #define __ _masm.
536 // Emit exception handler code.
537 // Stuff framesize into a register and call a VM stub routine.
538 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
539 /*
540 // Note that the code buffer's insts_mark is always relative to insts.
541 // That's why we must use the macroassembler to generate a handler.
542 MacroAssembler _masm(&cbuf);
543 address base = __ start_a_stub(size_exception_handler());
544 if (base == NULL) return 0; // CodeBuffer::expand failed
545 int offset = __ offset();
546 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
547 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
548 __ end_a_stub();
549 return offset;
550 */
551 // Note that the code buffer's insts_mark is always relative to insts.
552 // That's why we must use the macroassembler to generate a handler.
553 MacroAssembler _masm(&cbuf);
554 address base =
555 __ start_a_stub(size_exception_handler());
556 if (base == NULL) return 0; // CodeBuffer::expand failed
557 int offset = __ offset();
559 __ block_comment("; emit_exception_handler");
561 /* 2012/9/25 FIXME Jin: According to X86, we should use direct jumpt.
562 * * However, this will trigger an assert after the 40th method:
563 * *
564 * * 39 b java.lang.Throwable::<init> (25 bytes)
565 * * --- ns java.lang.Throwable::fillInStackTrace
566 * * 40 !b java.net.URLClassLoader::findClass (29 bytes)
567 * * /vm/opto/runtime.cpp, 900 , assert(caller.is_compiled_frame(),"must be")
568 * * 40 made not entrant (2) java.net.URLClassLoader::findClass (29 bytes)
569 * *
570 * * If we change from JR to JALR, the assert will disappear, but WebClient will
571 * * fail after the 403th method with unknown reason.
572 * */
573 __ li48(T9, (long)OptoRuntime::exception_blob()->entry_point());
574 __ jr(T9);
575 __ delayed()->nop();
576 __ align(16);
577 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
578 __ end_a_stub();
579 return offset;
580 }
582 // Emit deopt handler code.
583 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
584 /*
585 // Note that the code buffer's insts_mark is always relative to insts.
586 // That's why we must use the macroassembler to generate a handler.
587 MacroAssembler _masm(&cbuf);
588 address base = __ start_a_stub(size_deopt_handler());
589 if (base == NULL) return 0; // CodeBuffer::expand failed
590 int offset = __ offset();
592 #ifdef _LP64
593 address the_pc = (address) __ pc();
594 Label next;
595 // push a "the_pc" on the stack without destroying any registers
596 // as they all may be live.
598 // push address of "next"
599 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
600 __ bind(next);
601 // adjust it so it matches "the_pc"
602 __ subptr(Address(rsp, 0), __ offset() - offset);
603 #else
604 InternalAddress here(__ pc());
605 __ pushptr(here.addr());
606 #endif
608 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
609 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
610 __ end_a_stub();
611 return offset;
612 */
613 // Note that the code buffer's insts_mark is always relative to insts.
614 // That's why we must use the macroassembler to generate a handler.
615 MacroAssembler _masm(&cbuf);
616 address base =
617 __ start_a_stub(size_deopt_handler());
619 // FIXME
620 if (base == NULL) return 0; // CodeBuffer::expand failed
621 int offset = __ offset();
623 __ block_comment("; emit_deopt_handler");
625 cbuf.set_insts_mark();
626 __ relocate(relocInfo::runtime_call_type);
628 __ li48(T9, (long)SharedRuntime::deopt_blob()->unpack());
629 __ jalr(T9);
630 __ delayed()->nop();
631 __ align(16);
632 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
633 __ end_a_stub();
634 return offset;
635 }
638 const bool Matcher::match_rule_supported(int opcode) {
639 if (!has_match_rule(opcode))
640 return false;
642 switch (opcode) {
643 //Op_CountLeadingZerosI Op_CountLeadingZerosL can be deleted, all MIPS CPUs support clz & dclz.
644 case Op_CountLeadingZerosI:
645 case Op_CountLeadingZerosL:
646 if (!UseCountLeadingZerosInstruction)
647 return false;
648 break;
649 case Op_CountTrailingZerosI:
650 case Op_CountTrailingZerosL:
651 if (!UseCountTrailingZerosInstruction)
652 return false;
653 break;
654 }
656 return true; // Per default match rules are supported.
657 }
659 //FIXME
660 // emit call stub, compiled java to interpreter
661 void emit_java_to_interp(CodeBuffer &cbuf ) {
662 // Stub is fixed up when the corresponding call is converted from calling
663 // compiled code to calling interpreted code.
664 // mov rbx,0
665 // jmp -1
667 address mark = cbuf.insts_mark(); // get mark within main instrs section
669 // Note that the code buffer's insts_mark is always relative to insts.
670 // That's why we must use the macroassembler to generate a stub.
671 MacroAssembler _masm(&cbuf);
673 address base =
674 __ start_a_stub(Compile::MAX_stubs_size);
675 if (base == NULL) return; // CodeBuffer::expand failed
676 // static stub relocation stores the instruction address of the call
678 __ relocate(static_stub_Relocation::spec(mark), 0);
680 /* 2012/10/29 Jin: Rmethod contains methodOop, it should be relocated for GC */
681 /*
682 int oop_index = __ oop_recorder()->allocate_index(NULL);
683 RelocationHolder rspec = oop_Relocation::spec(oop_index);
684 __ relocate(rspec);
685 */
687 // static stub relocation also tags the methodOop in the code-stream.
688 __ li48(S3, (long)0);
689 // This is recognized as unresolved by relocs/nativeInst/ic code
691 __ relocate(relocInfo::runtime_call_type);
693 cbuf.set_insts_mark();
694 address call_pc = (address)-1;
695 __ li48(AT, (long)call_pc);
696 __ jr(AT);
697 __ nop();
698 __ align(16);
699 __ end_a_stub();
700 // Update current stubs pointer and restore code_end.
701 }
703 // size of call stub, compiled java to interpretor
704 uint size_java_to_interp() {
705 int size = 4 * 4 + NativeCall::instruction_size; // sizeof(li48) + NativeCall::instruction_size
706 return round_to(size, 16);
707 }
709 // relocation entries for call stub, compiled java to interpreter
710 uint reloc_java_to_interp() {
711 return 16; // in emit_java_to_interp + in Java_Static_Call
712 }
714 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
715 if( Assembler::is_simm16(offset) ) return true;
716 else
717 {
718 assert(false, "Not implemented yet !" );
719 Unimplemented();
720 }
721 }
724 // No additional cost for CMOVL.
725 const int Matcher::long_cmove_cost() { return 0; }
727 // No CMOVF/CMOVD with SSE2
728 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
730 // Does the CPU require late expand (see block.cpp for description of late expand)?
731 const bool Matcher::require_postalloc_expand = false;
733 // Should the Matcher clone shifts on addressing modes, expecting them
734 // to be subsumed into complex addressing expressions or compute them
735 // into registers? True for Intel but false for most RISCs
736 const bool Matcher::clone_shift_expressions = false;
738 // Do we need to mask the count passed to shift instructions or does
739 // the cpu only look at the lower 5/6 bits anyway?
740 const bool Matcher::need_masked_shift_count = false;
742 bool Matcher::narrow_oop_use_complex_address() {
743 NOT_LP64(ShouldNotCallThis());
744 assert(UseCompressedOops, "only for compressed oops code");
745 return false;
746 }
748 bool Matcher::narrow_klass_use_complex_address() {
749 NOT_LP64(ShouldNotCallThis());
750 assert(UseCompressedClassPointers, "only for compressed klass code");
751 return false;
752 }
754 // This is UltraSparc specific, true just means we have fast l2f conversion
755 const bool Matcher::convL2FSupported(void) {
756 return true;
757 }
759 // Max vector size in bytes. 0 if not supported.
760 const int Matcher::vector_width_in_bytes(BasicType bt) {
761 assert(MaxVectorSize == 8, "");
762 return 8;
763 }
765 // Vector ideal reg
766 const int Matcher::vector_ideal_reg(int size) {
767 assert(MaxVectorSize == 8, "");
768 switch(size) {
769 case 8: return Op_VecD;
770 }
771 ShouldNotReachHere();
772 return 0;
773 }
775 // Only lowest bits of xmm reg are used for vector shift count.
776 const int Matcher::vector_shift_count_ideal_reg(int size) {
777 fatal("vector shift is not supported");
778 return Node::NotAMachineReg;
779 }
781 // Limits on vector size (number of elements) loaded into vector.
782 const int Matcher::max_vector_size(const BasicType bt) {
783 assert(is_java_primitive(bt), "only primitive type vectors");
784 return vector_width_in_bytes(bt)/type2aelembytes(bt);
785 }
787 const int Matcher::min_vector_size(const BasicType bt) {
788 return max_vector_size(bt); // Same as max.
789 }
791 // MIPS supports misaligned vectors store/load? FIXME
792 const bool Matcher::misaligned_vectors_ok() {
793 return false;
794 //return !AlignVector; // can be changed by flag
795 }
797 // Register for DIVI projection of divmodI
798 RegMask Matcher::divI_proj_mask() {
799 ShouldNotReachHere();
800 return RegMask();
801 }
803 // Register for MODI projection of divmodI
804 RegMask Matcher::modI_proj_mask() {
805 ShouldNotReachHere();
806 return RegMask();
807 }
809 // Register for DIVL projection of divmodL
810 RegMask Matcher::divL_proj_mask() {
811 ShouldNotReachHere();
812 return RegMask();
813 }
815 int Matcher::regnum_to_fpu_offset(int regnum) {
816 return regnum - 32; // The FP registers are in the second chunk
817 }
820 const bool Matcher::isSimpleConstant64(jlong value) {
821 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
822 return true;
823 }
826 // Return whether or not this register is ever used as an argument. This
827 // function is used on startup to build the trampoline stubs in generateOptoStub.
828 // Registers not mentioned will be killed by the VM call in the trampoline, and
829 // arguments in those registers not be available to the callee.
830 bool Matcher::can_be_java_arg( int reg ) {
831 /* Refer to: [sharedRuntime_mips_64.cpp] SharedRuntime::java_calling_convention() */
832 if ( reg == T0_num || reg == T0_H_num
833 || reg == A0_num || reg == A0_H_num
834 || reg == A1_num || reg == A1_H_num
835 || reg == A2_num || reg == A2_H_num
836 || reg == A3_num || reg == A3_H_num
837 || reg == A4_num || reg == A4_H_num
838 || reg == A5_num || reg == A5_H_num
839 || reg == A6_num || reg == A6_H_num
840 || reg == A7_num || reg == A7_H_num )
841 return true;
843 if ( reg == F12_num || reg == F12_H_num
844 || reg == F13_num || reg == F13_H_num
845 || reg == F14_num || reg == F14_H_num
846 || reg == F15_num || reg == F15_H_num
847 || reg == F16_num || reg == F16_H_num
848 || reg == F17_num || reg == F17_H_num
849 || reg == F18_num || reg == F18_H_num
850 || reg == F19_num || reg == F19_H_num )
851 return true;
853 return false;
854 }
856 bool Matcher::is_spillable_arg( int reg ) {
857 return can_be_java_arg(reg);
858 }
860 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
861 return false;
862 }
864 // Register for MODL projection of divmodL
865 RegMask Matcher::modL_proj_mask() {
866 ShouldNotReachHere();
867 return RegMask();
868 }
870 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
871 return FP_REG_mask();
872 }
874 // MIPS doesn't support AES intrinsics
875 const bool Matcher::pass_original_key_for_aes() {
876 return false;
877 }
879 // The address of the call instruction needs to be 16-byte aligned to
880 // ensure that it does not span a cache line so that it can be patched.
882 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
883 //lui
884 //ori
885 //dsll
886 //ori
888 //jalr
889 //nop
891 return round_to(current_offset, alignment_required()) - current_offset;
892 }
894 // The address of the call instruction needs to be 16-byte aligned to
895 // ensure that it does not span a cache line so that it can be patched.
896 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
897 //li64 <--- skip
899 //lui
900 //ori
901 //dsll
902 //ori
904 //jalr
905 //nop
907 current_offset += 4 * 6; // skip li64
908 return round_to(current_offset, alignment_required()) - current_offset;
909 }
911 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
912 //lui
913 //ori
914 //dsll
915 //ori
917 //jalr
918 //nop
920 return round_to(current_offset, alignment_required()) - current_offset;
921 }
923 int CallLeafDirectNode::compute_padding(int current_offset) const {
924 //lui
925 //ori
926 //dsll
927 //ori
929 //jalr
930 //nop
932 return round_to(current_offset, alignment_required()) - current_offset;
933 }
935 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
936 //lui
937 //ori
938 //dsll
939 //ori
941 //jalr
942 //nop
944 return round_to(current_offset, alignment_required()) - current_offset;
945 }
947 // If CPU can load and store mis-aligned doubles directly then no fixup is
948 // needed. Else we split the double into 2 integer pieces and move it
949 // piece-by-piece. Only happens when passing doubles into C code as the
950 // Java calling convention forces doubles to be aligned.
951 const bool Matcher::misaligned_doubles_ok = false;
952 // Do floats take an entire double register or just half?
953 //const bool Matcher::float_in_double = true;
954 bool Matcher::float_in_double() { return false; }
955 // Threshold size for cleararray.
956 const int Matcher::init_array_short_size = 8 * BytesPerLong;
957 // Do ints take an entire long register or just half?
958 const bool Matcher::int_in_long = true;
959 // Is it better to copy float constants, or load them directly from memory?
960 // Intel can load a float constant from a direct address, requiring no
961 // extra registers. Most RISCs will have to materialize an address into a
962 // register first, so they would do better to copy the constant from stack.
963 const bool Matcher::rematerialize_float_constants = false;
964 // Advertise here if the CPU requires explicit rounding operations
965 // to implement the UseStrictFP mode.
966 const bool Matcher::strict_fp_requires_explicit_rounding = false;
967 // The ecx parameter to rep stos for the ClearArray node is in dwords.
968 const bool Matcher::init_array_count_is_in_bytes = false;
971 // Indicate if the safepoint node needs the polling page as an input.
972 // Since MIPS doesn't have absolute addressing, it needs.
973 bool SafePointNode::needs_polling_address_input() {
974 return true;
975 }
977 // !!!!! Special hack to get all type of calls to specify the byte offset
978 // from the start of the call to the point where the return address
979 // will point.
980 int MachCallStaticJavaNode::ret_addr_offset() {
981 assert(NativeCall::instruction_size == 24, "in MachCallStaticJavaNode::ret_addr_offset");
982 //The value ought to be 16 bytes.
983 //lui
984 //ori
985 //dsll
986 //ori
987 //jalr
988 //nop
989 return NativeCall::instruction_size;
990 }
992 int MachCallDynamicJavaNode::ret_addr_offset() {
993 /* 2012/9/10 Jin: must be kept in sync with Java_Dynamic_Call */
995 // return NativeCall::instruction_size;
996 assert(NativeCall::instruction_size == 24, "in MachCallDynamicJavaNode::ret_addr_offset");
997 //The value ought to be 4 + 16 bytes.
998 //lui IC_Klass,
999 //ori IC_Klass,
1000 //dsll IC_Klass
1001 //ori IC_Klass
1002 //lui T9
1003 //ori T9
1004 //dsll T9
1005 //ori T9
1006 //jalr T9
1007 //nop
1008 return 6 * 4 + NativeCall::instruction_size;
1010 }
1012 /*
1013 // EMIT_OPCODE()
1014 void emit_opcode(CodeBuffer &cbuf, int code) {
1015 *(cbuf.code_end()) = (unsigned char)code;
1016 cbuf.set_code_end(cbuf.code_end() + 1);
1017 }
1018 */
1020 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
1021 int format) {
1022 cbuf.relocate(cbuf.insts_mark(), reloc, format);
1023 cbuf.insts()->emit_int32(d32);
1024 }
1026 //=============================================================================
1028 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1029 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1030 static enum RC rc_class( OptoReg::Name reg ) {
1031 if( !OptoReg::is_valid(reg) ) return rc_bad;
1032 if (OptoReg::is_stack(reg)) return rc_stack;
1033 VMReg r = OptoReg::as_VMReg(reg);
1034 if (r->is_Register()) return rc_int;
1035 assert(r->is_FloatRegister(), "must be");
1036 return rc_float;
1037 }
1039 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
1040 // Get registers to move
1041 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1042 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1043 OptoReg::Name dst_second = ra_->get_reg_second(this );
1044 OptoReg::Name dst_first = ra_->get_reg_first(this );
1046 enum RC src_second_rc = rc_class(src_second);
1047 enum RC src_first_rc = rc_class(src_first);
1048 enum RC dst_second_rc = rc_class(dst_second);
1049 enum RC dst_first_rc = rc_class(dst_first);
1051 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1053 // Generate spill code!
1054 int size = 0;
1056 if( src_first == dst_first && src_second == dst_second )
1057 return 0; // Self copy, no move
1059 if (src_first_rc == rc_stack) {
1060 // mem ->
1061 if (dst_first_rc == rc_stack) {
1062 // mem -> mem
1063 assert(src_second != dst_first, "overlap");
1064 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1065 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1066 // 64-bit
1067 int src_offset = ra_->reg2offset(src_first);
1068 int dst_offset = ra_->reg2offset(dst_first);
1069 if (cbuf) {
1070 MacroAssembler _masm(cbuf);
1071 __ ld(AT, Address(SP, src_offset));
1072 __ sd(AT, Address(SP, dst_offset));
1073 #ifndef PRODUCT
1074 } else {
1075 if(!do_size){
1076 if (size != 0) st->print("\n\t");
1077 st->print("ld AT, [SP + #%d]\t# 64-bit mem-mem spill 1\n\t"
1078 "sd AT, [SP + #%d]",
1079 src_offset, dst_offset);
1080 }
1081 #endif
1082 }
1083 size += 8;
1084 } else {
1085 // 32-bit
1086 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1087 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1088 // No pushl/popl, so:
1089 int src_offset = ra_->reg2offset(src_first);
1090 int dst_offset = ra_->reg2offset(dst_first);
1091 if (cbuf) {
1092 MacroAssembler _masm(cbuf);
1093 __ lw(AT, Address(SP, src_offset));
1094 __ sw(AT, Address(SP, dst_offset));
1095 #ifndef PRODUCT
1096 } else {
1097 if(!do_size){
1098 if (size != 0) st->print("\n\t");
1099 st->print("lw AT, [SP + #%d] spill 2\n\t"
1100 "sw AT, [SP + #%d]\n\t",
1101 src_offset, dst_offset);
1102 }
1103 #endif
1104 }
1105 size += 8;
1106 }
1107 return size;
1108 } else if (dst_first_rc == rc_int) {
1109 // mem -> gpr
1110 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1111 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1112 // 64-bit
1113 int offset = ra_->reg2offset(src_first);
1114 if (cbuf) {
1115 MacroAssembler _masm(cbuf);
1116 __ ld(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1117 #ifndef PRODUCT
1118 } else {
1119 if(!do_size){
1120 if (size != 0) st->print("\n\t");
1121 st->print("ld %s, [SP + #%d]\t# spill 3",
1122 Matcher::regName[dst_first],
1123 offset);
1124 }
1125 #endif
1126 }
1127 size += 4;
1128 } else {
1129 // 32-bit
1130 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1131 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1132 int offset = ra_->reg2offset(src_first);
1133 if (cbuf) {
1134 MacroAssembler _masm(cbuf);
1135 if (this->ideal_reg() == Op_RegI)
1136 __ lw(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1137 else
1138 __ lwu(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1139 #ifndef PRODUCT
1140 } else {
1141 if(!do_size){
1142 if (size != 0) st->print("\n\t");
1143 if (this->ideal_reg() == Op_RegI)
1144 st->print("lw %s, [SP + #%d]\t# spill 4",
1145 Matcher::regName[dst_first],
1146 offset);
1147 else
1148 st->print("lwu %s, [SP + #%d]\t# spill 5",
1149 Matcher::regName[dst_first],
1150 offset);
1151 }
1152 #endif
1153 }
1154 size += 4;
1155 }
1156 return size;
1157 } else if (dst_first_rc == rc_float) {
1158 // mem-> xmm
1159 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1160 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1161 // 64-bit
1162 int offset = ra_->reg2offset(src_first);
1163 if (cbuf) {
1164 MacroAssembler _masm(cbuf);
1165 __ ldc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1166 #ifndef PRODUCT
1167 } else {
1168 if(!do_size){
1169 if (size != 0) st->print("\n\t");
1170 st->print("ldc1 %s, [SP + #%d]\t# spill 6",
1171 Matcher::regName[dst_first],
1172 offset);
1173 }
1174 #endif
1175 }
1176 size += 4;
1177 } else {
1178 // 32-bit
1179 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1180 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1181 int offset = ra_->reg2offset(src_first);
1182 if (cbuf) {
1183 MacroAssembler _masm(cbuf);
1184 __ lwc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1185 #ifndef PRODUCT
1186 } else {
1187 if(!do_size){
1188 if (size != 0) st->print("\n\t");
1189 st->print("lwc1 %s, [SP + #%d]\t# spill 7",
1190 Matcher::regName[dst_first],
1191 offset);
1192 }
1193 #endif
1194 }
1195 size += 4;
1196 }
1197 return size;
1198 }
1199 } else if (src_first_rc == rc_int) {
1200 // gpr ->
1201 if (dst_first_rc == rc_stack) {
1202 // gpr -> mem
1203 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1204 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1205 // 64-bit
1206 int offset = ra_->reg2offset(dst_first);
1207 if (cbuf) {
1208 MacroAssembler _masm(cbuf);
1209 __ sd(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1210 #ifndef PRODUCT
1211 } else {
1212 if(!do_size){
1213 if (size != 0) st->print("\n\t");
1214 st->print("sd %s, [SP + #%d] # spill 8",
1215 Matcher::regName[src_first],
1216 offset);
1217 }
1218 #endif
1219 }
1220 size += 4;
1221 } else {
1222 // 32-bit
1223 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1224 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1225 int offset = ra_->reg2offset(dst_first);
1226 if (cbuf) {
1227 MacroAssembler _masm(cbuf);
1228 __ sw(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1229 #ifndef PRODUCT
1230 } else {
1231 if(!do_size){
1232 if (size != 0) st->print("\n\t");
1233 st->print("sw %s, [SP + #%d]\t# spill 9",
1234 Matcher::regName[src_first], offset);
1235 }
1236 #endif
1237 }
1238 size += 4;
1239 }
1240 return size;
1241 } else if (dst_first_rc == rc_int) {
1242 // gpr -> gpr
1243 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1244 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1245 // 64-bit
1246 if (cbuf) {
1247 MacroAssembler _masm(cbuf);
1248 __ move(as_Register(Matcher::_regEncode[dst_first]),
1249 as_Register(Matcher::_regEncode[src_first]));
1250 #ifndef PRODUCT
1251 } else {
1252 if(!do_size){
1253 if (size != 0) st->print("\n\t");
1254 st->print("move(64bit) %s <-- %s\t# spill 10",
1255 Matcher::regName[dst_first],
1256 Matcher::regName[src_first]);
1257 }
1258 #endif
1259 }
1260 size += 4;
1261 return size;
1262 } else {
1263 // 32-bit
1264 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1265 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1266 if (cbuf) {
1267 MacroAssembler _masm(cbuf);
1268 if (this->ideal_reg() == Op_RegI)
1269 __ move_u32(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1270 else
1271 __ daddu(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]), R0);
1273 #ifndef PRODUCT
1274 } else {
1275 if(!do_size){
1276 if (size != 0) st->print("\n\t");
1277 st->print("move(32-bit) %s <-- %s\t# spill 11",
1278 Matcher::regName[dst_first],
1279 Matcher::regName[src_first]);
1280 }
1281 #endif
1282 }
1283 size += 4;
1284 return size;
1285 }
1286 } else if (dst_first_rc == rc_float) {
1287 // gpr -> xmm
1288 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1289 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1290 // 64-bit
1291 if (cbuf) {
1292 MacroAssembler _masm(cbuf);
1293 __ dmtc1(as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]));
1294 #ifndef PRODUCT
1295 } else {
1296 if(!do_size){
1297 if (size != 0) st->print("\n\t");
1298 st->print("dmtc1 %s, %s\t# spill 12",
1299 Matcher::regName[dst_first],
1300 Matcher::regName[src_first]);
1301 }
1302 #endif
1303 }
1304 size += 4;
1305 } else {
1306 // 32-bit
1307 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1308 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1309 if (cbuf) {
1310 MacroAssembler _masm(cbuf);
1311 __ mtc1( as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]) );
1312 #ifndef PRODUCT
1313 } else {
1314 if(!do_size){
1315 if (size != 0) st->print("\n\t");
1316 st->print("mtc1 %s, %s\t# spill 13",
1317 Matcher::regName[dst_first],
1318 Matcher::regName[src_first]);
1319 }
1320 #endif
1321 }
1322 size += 4;
1323 }
1324 return size;
1325 }
1326 } else if (src_first_rc == rc_float) {
1327 // xmm ->
1328 if (dst_first_rc == rc_stack) {
1329 // xmm -> mem
1330 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1331 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1332 // 64-bit
1333 int offset = ra_->reg2offset(dst_first);
1334 if (cbuf) {
1335 MacroAssembler _masm(cbuf);
1336 __ sdc1( as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset) );
1337 #ifndef PRODUCT
1338 } else {
1339 if(!do_size){
1340 if (size != 0) st->print("\n\t");
1341 st->print("sdc1 %s, [SP + #%d]\t# spill 14",
1342 Matcher::regName[src_first],
1343 offset);
1344 }
1345 #endif
1346 }
1347 size += 4;
1348 } else {
1349 // 32-bit
1350 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1351 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1352 int offset = ra_->reg2offset(dst_first);
1353 if (cbuf) {
1354 MacroAssembler _masm(cbuf);
1355 __ swc1(as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset));
1356 #ifndef PRODUCT
1357 } else {
1358 if(!do_size){
1359 if (size != 0) st->print("\n\t");
1360 st->print("swc1 %s, [SP + #%d]\t# spill 15",
1361 Matcher::regName[src_first],
1362 offset);
1363 }
1364 #endif
1365 }
1366 size += 4;
1367 }
1368 return size;
1369 } else if (dst_first_rc == rc_int) {
1370 // xmm -> gpr
1371 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1372 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1373 // 64-bit
1374 if (cbuf) {
1375 MacroAssembler _masm(cbuf);
1376 __ dmfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1377 #ifndef PRODUCT
1378 } else {
1379 if(!do_size){
1380 if (size != 0) st->print("\n\t");
1381 st->print("dmfc1 %s, %s\t# spill 16",
1382 Matcher::regName[dst_first],
1383 Matcher::regName[src_first]);
1384 }
1385 #endif
1386 }
1387 size += 4;
1388 } else {
1389 // 32-bit
1390 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1391 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1392 if (cbuf) {
1393 MacroAssembler _masm(cbuf);
1394 __ mfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1395 #ifndef PRODUCT
1396 } else {
1397 if(!do_size){
1398 if (size != 0) st->print("\n\t");
1399 st->print("mfc1 %s, %s\t# spill 17",
1400 Matcher::regName[dst_first],
1401 Matcher::regName[src_first]);
1402 }
1403 #endif
1404 }
1405 size += 4;
1406 }
1407 return size;
1408 } else if (dst_first_rc == rc_float) {
1409 // xmm -> xmm
1410 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1411 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1412 // 64-bit
1413 if (cbuf) {
1414 MacroAssembler _masm(cbuf);
1415 __ mov_d( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1416 #ifndef PRODUCT
1417 } else {
1418 if(!do_size){
1419 if (size != 0) st->print("\n\t");
1420 st->print("mov_d %s <-- %s\t# spill 18",
1421 Matcher::regName[dst_first],
1422 Matcher::regName[src_first]);
1423 }
1424 #endif
1425 }
1426 size += 4;
1427 } else {
1428 // 32-bit
1429 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1430 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1431 if (cbuf) {
1432 MacroAssembler _masm(cbuf);
1433 __ mov_s( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1434 #ifndef PRODUCT
1435 } else {
1436 if(!do_size){
1437 if (size != 0) st->print("\n\t");
1438 st->print("mov_s %s <-- %s\t# spill 19",
1439 Matcher::regName[dst_first],
1440 Matcher::regName[src_first]);
1441 }
1442 #endif
1443 }
1444 size += 4;
1445 }
1446 return size;
1447 }
1448 }
1450 assert(0," foo ");
1451 Unimplemented();
1452 return size;
1454 }
1456 #ifndef PRODUCT
1457 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1458 implementation( NULL, ra_, false, st );
1459 }
1460 #endif
1462 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1463 implementation( &cbuf, ra_, false, NULL );
1464 }
1466 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1467 return implementation( NULL, ra_, true, NULL );
1468 }
1470 //=============================================================================
1471 #
1473 #ifndef PRODUCT
1474 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
1475 st->print("INT3");
1476 }
1477 #endif
1479 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
1480 MacroAssembler _masm(&cbuf);
1481 __ int3();
1482 }
1484 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
1485 return MachNode::size(ra_);
1486 }
1489 //=============================================================================
1490 #ifndef PRODUCT
1491 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1492 Compile *C = ra_->C;
1493 int framesize = C->frame_size_in_bytes();
1495 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1497 st->print("daddiu SP, SP, %d # Rlease stack @ MachEpilogNode",framesize);
1498 st->cr(); st->print("\t");
1499 if (UseLoongsonISA) {
1500 st->print("gslq RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
1501 } else {
1502 st->print("ld RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
1503 st->cr(); st->print("\t");
1504 st->print("ld FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
1505 }
1507 if( do_polling() && C->is_method_compilation() ) {
1508 st->print("Poll Safepoint # MachEpilogNode");
1509 }
1510 }
1511 #endif
1513 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1514 Compile *C = ra_->C;
1515 MacroAssembler _masm(&cbuf);
1516 int framesize = C->frame_size_in_bytes();
1518 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1520 __ daddiu(SP, SP, framesize);
1522 if (UseLoongsonISA) {
1523 __ gslq(RA, FP, SP, -wordSize*2);
1524 } else {
1525 __ ld(RA, SP, -wordSize );
1526 __ ld(FP, SP, -wordSize*2 );
1527 }
1529 /* 2012/11/19 Jin: The epilog in a RuntimeStub should not contain a safepoint */
1530 if( do_polling() && C->is_method_compilation() ) {
1531 #ifndef OPT_SAFEPOINT
1532 __ set64(AT, (long)os::get_polling_page());
1533 __ relocate(relocInfo::poll_return_type);
1534 __ lw(AT, AT, 0);
1535 #else
1536 __ lui(AT, Assembler::split_high((intptr_t)os::get_polling_page()));
1537 __ relocate(relocInfo::poll_return_type);
1538 __ lw(AT, AT, Assembler::split_low((intptr_t)os::get_polling_page()));
1539 #endif
1540 }
1541 }
1543 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1544 return MachNode::size(ra_); // too many variables; just compute it the hard way fujie debug
1545 }
1547 int MachEpilogNode::reloc() const {
1548 return 0; // a large enough number
1549 }
1551 const Pipeline * MachEpilogNode::pipeline() const {
1552 return MachNode::pipeline_class();
1553 }
1555 int MachEpilogNode::safepoint_offset() const { return 0; }
1557 //=============================================================================
1559 #ifndef PRODUCT
1560 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1561 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1562 int reg = ra_->get_reg_first(this);
1563 st->print("ADDI %s, SP, %d @BoxLockNode",Matcher::regName[reg],offset);
1564 }
1565 #endif
1568 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1569 return 4;
1570 }
1572 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1573 MacroAssembler _masm(&cbuf);
1574 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1575 int reg = ra_->get_encode(this);
1577 __ addi(as_Register(reg), SP, offset);
1578 /*
1579 if( offset >= 128 ) {
1580 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1581 emit_rm(cbuf, 0x2, reg, 0x04);
1582 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1583 emit_d32(cbuf, offset);
1584 }
1585 else {
1586 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1587 emit_rm(cbuf, 0x1, reg, 0x04);
1588 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1589 emit_d8(cbuf, offset);
1590 }
1591 */
1592 }
1595 //static int sizeof_FFree_Float_Stack_All = -1;
1597 int MachCallRuntimeNode::ret_addr_offset() {
1598 //lui
1599 //ori
1600 //dsll
1601 //ori
1602 //jalr
1603 //nop
1604 assert(NativeCall::instruction_size == 24, "in MachCallRuntimeNode::ret_addr_offset()");
1605 return NativeCall::instruction_size;
1606 // return 16;
1607 }
1613 //=============================================================================
1614 #ifndef PRODUCT
1615 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1616 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1617 }
1618 #endif
1620 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1621 MacroAssembler _masm(&cbuf);
1622 int i = 0;
1623 for(i = 0; i < _count; i++)
1624 __ nop();
1625 }
1627 uint MachNopNode::size(PhaseRegAlloc *) const {
1628 return 4 * _count;
1629 }
1630 const Pipeline* MachNopNode::pipeline() const {
1631 return MachNode::pipeline_class();
1632 }
1634 //=============================================================================
1636 //=============================================================================
1637 #ifndef PRODUCT
1638 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1639 st->print_cr("load_klass(AT, T0)");
1640 st->print_cr("\tbeq(AT, iCache, L)");
1641 st->print_cr("\tnop");
1642 st->print_cr("\tjmp(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type)");
1643 st->print_cr("\tnop");
1644 st->print_cr("\tnop");
1645 st->print_cr(" L:");
1646 }
1647 #endif
1650 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1651 MacroAssembler _masm(&cbuf);
1652 #ifdef ASSERT
1653 //uint code_size = cbuf.code_size();
1654 #endif
1655 int ic_reg = Matcher::inline_cache_reg_encode();
1656 Label L;
1657 Register receiver = T0;
1658 Register iCache = as_Register(ic_reg);
1659 __ load_klass(AT, receiver);
1660 __ beq(AT, iCache, L);
1661 __ nop();
1663 __ relocate(relocInfo::runtime_call_type);
1664 __ li48(T9, (long)SharedRuntime::get_ic_miss_stub());
1665 __ jr(T9);
1666 __ nop();
1668 /* WARNING these NOPs are critical so that verified entry point is properly
1669 * 8 bytes aligned for patching by NativeJump::patch_verified_entry() */
1670 __ align(CodeEntryAlignment);
1671 __ bind(L);
1672 }
1674 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1675 return MachNode::size(ra_);
1676 }
1680 //=============================================================================
1682 const RegMask& MachConstantBaseNode::_out_RegMask = P_REG_mask();
1684 int Compile::ConstantTable::calculate_table_base_offset() const {
1685 return 0; // absolute addressing, no offset
1686 }
1688 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1689 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1690 ShouldNotReachHere();
1691 }
1693 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1694 Compile* C = ra_->C;
1695 Compile::ConstantTable& constant_table = C->constant_table();
1696 MacroAssembler _masm(&cbuf);
1698 Register Rtoc = as_Register(ra_->get_encode(this));
1699 CodeSection* consts_section = __ code()->consts();
1700 int consts_size = consts_section->align_at_start(consts_section->size());
1701 assert(constant_table.size() == consts_size, "must be equal");
1703 if (consts_section->size()) {
1704 // Materialize the constant table base.
1705 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1706 // RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1707 __ relocate(relocInfo::internal_pc_type);
1708 __ li48(Rtoc, (long)baseaddr);
1709 }
1710 }
1712 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1713 // li48 (4 insts)
1714 return 4 * 4;
1715 }
1717 #ifndef PRODUCT
1718 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1719 Register r = as_Register(ra_->get_encode(this));
1720 st->print("li48 %s, &constanttable (constant table base) @ MachConstantBaseNode", r->name());
1721 }
1722 #endif
1725 //=============================================================================
1726 #ifndef PRODUCT
1727 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1728 Compile* C = ra_->C;
1730 int framesize = C->frame_size_in_bytes();
1731 int bangsize = C->bang_size_in_bytes();
1732 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1734 // Calls to C2R adapters often do not accept exceptional returns.
1735 // We require that their callers must bang for them. But be careful, because
1736 // some VM calls (such as call site linkage) can use several kilobytes of
1737 // stack. But the stack safety zone should account for that.
1738 // See bugs 4446381, 4468289, 4497237.
1739 if (C->need_stack_bang(bangsize)) {
1740 st->print_cr("# stack bang"); st->print("\t");
1741 }
1742 if (UseLoongsonISA) {
1743 st->print("gssq RA, FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1744 } else {
1745 st->print("sd RA, %d(SP) @ MachPrologNode\n\t", -wordSize);
1746 st->print("sd FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1747 }
1748 st->print("daddiu FP, SP, -%d \n\t", wordSize*2);
1749 st->print("daddiu SP, SP, -%d \t",framesize);
1750 }
1751 #endif
1754 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1755 Compile* C = ra_->C;
1756 MacroAssembler _masm(&cbuf);
1758 int framesize = C->frame_size_in_bytes();
1759 int bangsize = C->bang_size_in_bytes();
1761 // __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
1763 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1765 if (C->need_stack_bang(framesize)) {
1766 __ generate_stack_overflow_check(framesize);
1767 }
1769 if (UseLoongsonISA) {
1770 __ gssq(RA, FP, SP, -wordSize*2);
1771 } else {
1772 __ sd(RA, SP, -wordSize);
1773 __ sd(FP, SP, -wordSize*2);
1774 }
1775 __ daddiu(FP, SP, -wordSize*2);
1776 __ daddiu(SP, SP, -framesize);
1777 __ nop(); /* 2013.10.22 Jin: Make enough room for patch_verified_entry() */
1778 __ nop();
1780 C->set_frame_complete(cbuf.insts_size());
1781 if (C->has_mach_constant_base_node()) {
1782 // NOTE: We set the table base offset here because users might be
1783 // emitted before MachConstantBaseNode.
1784 Compile::ConstantTable& constant_table = C->constant_table();
1785 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1786 }
1788 }
1791 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1792 //fprintf(stderr, "\nPrologNode::size(ra_)= %d \n", MachNode::size(ra_));//fujie debug
1793 return MachNode::size(ra_); // too many variables; just compute it the hard way
1794 }
1796 int MachPrologNode::reloc() const {
1797 return 0; // a large enough number
1798 }
1800 %}
1802 //----------ENCODING BLOCK-----------------------------------------------------
1803 // This block specifies the encoding classes used by the compiler to output
1804 // byte streams. Encoding classes generate functions which are called by
1805 // Machine Instruction Nodes in order to generate the bit encoding of the
1806 // instruction. Operands specify their base encoding interface with the
1807 // interface keyword. There are currently supported four interfaces,
1808 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1809 // operand to generate a function which returns its register number when
1810 // queried. CONST_INTER causes an operand to generate a function which
1811 // returns the value of the constant when queried. MEMORY_INTER causes an
1812 // operand to generate four functions which return the Base Register, the
1813 // Index Register, the Scale Value, and the Offset Value of the operand when
1814 // queried. COND_INTER causes an operand to generate six functions which
1815 // return the encoding code (ie - encoding bits for the instruction)
1816 // associated with each basic boolean condition for a conditional instruction.
1817 // Instructions specify two basic values for encoding. They use the
1818 // ins_encode keyword to specify their encoding class (which must be one of
1819 // the class names specified in the encoding block), and they use the
1820 // opcode keyword to specify, in order, their primary, secondary, and
1821 // tertiary opcode. Only the opcode sections which a particular instruction
1822 // needs for encoding need to be specified.
1823 encode %{
1824 /*
1825 Alias:
1826 1044 b java.io.ObjectInputStream::readHandle (130 bytes)
1827 118 B14: # B19 B15 <- B13 Freq: 0.899955
1828 118 add S1, S2, V0 #@addP_reg_reg
1829 11c lb S0, [S1 + #-8257524] #@loadB
1830 120 BReq S0, #3, B19 #@branchConI_reg_imm P=0.100000 C=-1.000000
1831 */
1832 //Load byte signed
1833 enc_class load_B_enc (mRegI dst, memory mem) %{
1834 MacroAssembler _masm(&cbuf);
1835 int dst = $dst$$reg;
1836 int base = $mem$$base;
1837 int index = $mem$$index;
1838 int scale = $mem$$scale;
1839 int disp = $mem$$disp;
1841 if( index != 0 ) {
1842 if( Assembler::is_simm16(disp) ) {
1843 if( UseLoongsonISA ) {
1844 if (scale == 0) {
1845 __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1846 } else {
1847 __ dsll(AT, as_Register(index), scale);
1848 __ gslbx(as_Register(dst), as_Register(base), AT, disp);
1849 }
1850 } else {
1851 if (scale == 0) {
1852 __ addu(AT, as_Register(base), as_Register(index));
1853 } else {
1854 __ dsll(AT, as_Register(index), scale);
1855 __ addu(AT, as_Register(base), AT);
1856 }
1857 __ lb(as_Register(dst), AT, disp);
1858 }
1859 } else {
1860 if (scale == 0) {
1861 __ addu(AT, as_Register(base), as_Register(index));
1862 } else {
1863 __ dsll(AT, as_Register(index), scale);
1864 __ addu(AT, as_Register(base), AT);
1865 }
1866 __ move(T9, disp);
1867 if( UseLoongsonISA ) {
1868 __ gslbx(as_Register(dst), AT, T9, 0);
1869 } else {
1870 __ addu(AT, AT, T9);
1871 __ lb(as_Register(dst), AT, 0);
1872 }
1873 }
1874 } else {
1875 if( Assembler::is_simm16(disp) ) {
1876 __ lb(as_Register(dst), as_Register(base), disp);
1877 } else {
1878 __ move(T9, disp);
1879 if( UseLoongsonISA ) {
1880 __ gslbx(as_Register(dst), as_Register(base), T9, 0);
1881 } else {
1882 __ addu(AT, as_Register(base), T9);
1883 __ lb(as_Register(dst), AT, 0);
1884 }
1885 }
1886 }
1887 %}
1889 //Load byte unsigned
1890 enc_class load_UB_enc (mRegI dst, memory mem) %{
1891 MacroAssembler _masm(&cbuf);
1892 int dst = $dst$$reg;
1893 int base = $mem$$base;
1894 int index = $mem$$index;
1895 int scale = $mem$$scale;
1896 int disp = $mem$$disp;
1898 if( index != 0 ) {
1899 if (scale == 0) {
1900 __ daddu(AT, as_Register(base), as_Register(index));
1901 } else {
1902 __ dsll(AT, as_Register(index), scale);
1903 __ daddu(AT, as_Register(base), AT);
1904 }
1905 if( Assembler::is_simm16(disp) ) {
1906 __ lbu(as_Register(dst), AT, disp);
1907 } else {
1908 __ move(T9, disp);
1909 __ daddu(AT, AT, T9);
1910 __ lbu(as_Register(dst), AT, 0);
1911 }
1912 } else {
1913 if( Assembler::is_simm16(disp) ) {
1914 __ lbu(as_Register(dst), as_Register(base), disp);
1915 } else {
1916 __ move(T9, disp);
1917 __ daddu(AT, as_Register(base), T9);
1918 __ lbu(as_Register(dst), AT, 0);
1919 }
1920 }
1921 %}
1923 enc_class store_B_reg_enc (memory mem, mRegI src) %{
1924 MacroAssembler _masm(&cbuf);
1925 int src = $src$$reg;
1926 int base = $mem$$base;
1927 int index = $mem$$index;
1928 int scale = $mem$$scale;
1929 int disp = $mem$$disp;
1931 if( index != 0 ) {
1932 if (scale == 0) {
1933 if( Assembler::is_simm(disp, 8) ) {
1934 if (UseLoongsonISA) {
1935 __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
1936 } else {
1937 __ addu(AT, as_Register(base), as_Register(index));
1938 __ sb(as_Register(src), AT, disp);
1939 }
1940 } else if( Assembler::is_simm16(disp) ) {
1941 __ addu(AT, as_Register(base), as_Register(index));
1942 __ sb(as_Register(src), AT, disp);
1943 } else {
1944 __ addu(AT, as_Register(base), as_Register(index));
1945 __ move(T9, disp);
1946 if (UseLoongsonISA) {
1947 __ gssbx(as_Register(src), AT, T9, 0);
1948 } else {
1949 __ addu(AT, AT, T9);
1950 __ sb(as_Register(src), AT, 0);
1951 }
1952 }
1953 } else {
1954 __ dsll(AT, as_Register(index), scale);
1955 if( Assembler::is_simm(disp, 8) ) {
1956 if (UseLoongsonISA) {
1957 __ gssbx(as_Register(src), AT, as_Register(base), disp);
1958 } else {
1959 __ addu(AT, as_Register(base), AT);
1960 __ sb(as_Register(src), AT, disp);
1961 }
1962 } else if( Assembler::is_simm16(disp) ) {
1963 __ addu(AT, as_Register(base), AT);
1964 __ sb(as_Register(src), AT, disp);
1965 } else {
1966 __ addu(AT, as_Register(base), AT);
1967 __ move(T9, disp);
1968 if (UseLoongsonISA) {
1969 __ gssbx(as_Register(src), AT, T9, 0);
1970 } else {
1971 __ addu(AT, AT, T9);
1972 __ sb(as_Register(src), AT, 0);
1973 }
1974 }
1975 }
1976 } else {
1977 if( Assembler::is_simm16(disp) ) {
1978 __ sb(as_Register(src), as_Register(base), disp);
1979 } else {
1980 __ move(T9, disp);
1981 if (UseLoongsonISA) {
1982 __ gssbx(as_Register(src), as_Register(base), T9, 0);
1983 } else {
1984 __ addu(AT, as_Register(base), T9);
1985 __ sb(as_Register(src), AT, 0);
1986 }
1987 }
1988 }
1989 %}
1991 enc_class store_B_immI_enc (memory mem, immI8 src) %{
1992 MacroAssembler _masm(&cbuf);
1993 int base = $mem$$base;
1994 int index = $mem$$index;
1995 int scale = $mem$$scale;
1996 int disp = $mem$$disp;
1997 int value = $src$$constant;
1999 if( index != 0 ) {
2000 if (!UseLoongsonISA) {
2001 if (scale == 0) {
2002 __ daddu(AT, as_Register(base), as_Register(index));
2003 } else {
2004 __ dsll(AT, as_Register(index), scale);
2005 __ daddu(AT, as_Register(base), AT);
2006 }
2007 if( Assembler::is_simm16(disp) ) {
2008 if (value == 0) {
2009 __ sb(R0, AT, disp);
2010 } else {
2011 __ move(T9, value);
2012 __ sb(T9, AT, disp);
2013 }
2014 } else {
2015 if (value == 0) {
2016 __ move(T9, disp);
2017 __ daddu(AT, AT, T9);
2018 __ sb(R0, AT, 0);
2019 } else {
2020 __ move(T9, disp);
2021 __ daddu(AT, AT, T9);
2022 __ move(T9, value);
2023 __ sb(T9, AT, 0);
2024 }
2025 }
2026 } else {
2028 if (scale == 0) {
2029 if( Assembler::is_simm(disp, 8) ) {
2030 if (value == 0) {
2031 __ gssbx(R0, as_Register(base), as_Register(index), disp);
2032 } else {
2033 __ move(T9, value);
2034 __ gssbx(T9, as_Register(base), as_Register(index), disp);
2035 }
2036 } else if( Assembler::is_simm16(disp) ) {
2037 __ daddu(AT, as_Register(base), as_Register(index));
2038 if (value == 0) {
2039 __ sb(R0, AT, disp);
2040 } else {
2041 __ move(T9, value);
2042 __ sb(T9, AT, disp);
2043 }
2044 } else {
2045 if (value == 0) {
2046 __ daddu(AT, as_Register(base), as_Register(index));
2047 __ move(T9, disp);
2048 __ gssbx(R0, AT, T9, 0);
2049 } else {
2050 __ move(AT, disp);
2051 __ move(T9, value);
2052 __ daddu(AT, as_Register(base), AT);
2053 __ gssbx(T9, AT, as_Register(index), 0);
2054 }
2055 }
2057 } else {
2059 if( Assembler::is_simm(disp, 8) ) {
2060 __ dsll(AT, as_Register(index), scale);
2061 if (value == 0) {
2062 __ gssbx(R0, as_Register(base), AT, disp);
2063 } else {
2064 __ move(T9, value);
2065 __ gssbx(T9, as_Register(base), AT, disp);
2066 }
2067 } else if( Assembler::is_simm16(disp) ) {
2068 __ dsll(AT, as_Register(index), scale);
2069 __ daddu(AT, as_Register(base), AT);
2070 if (value == 0) {
2071 __ sb(R0, AT, disp);
2072 } else {
2073 __ move(T9, value);
2074 __ sb(T9, AT, disp);
2075 }
2076 } else {
2077 __ dsll(AT, as_Register(index), scale);
2078 if (value == 0) {
2079 __ daddu(AT, as_Register(base), AT);
2080 __ move(T9, disp);
2081 __ gssbx(R0, AT, T9, 0);
2082 } else {
2083 __ move(T9, disp);
2084 __ daddu(AT, AT, T9);
2085 __ move(T9, value);
2086 __ gssbx(T9, as_Register(base), AT, 0);
2087 }
2088 }
2089 }
2090 }
2091 } else {
2092 if( Assembler::is_simm16(disp) ) {
2093 if (value == 0) {
2094 __ sb(R0, as_Register(base), disp);
2095 } else {
2096 __ move(AT, value);
2097 __ sb(AT, as_Register(base), disp);
2098 }
2099 } else {
2100 if (value == 0) {
2101 __ move(T9, disp);
2102 if (UseLoongsonISA) {
2103 __ gssbx(R0, as_Register(base), T9, 0);
2104 } else {
2105 __ daddu(AT, as_Register(base), T9);
2106 __ sb(R0, AT, 0);
2107 }
2108 } else {
2109 __ move(T9, disp);
2110 if (UseLoongsonISA) {
2111 __ move(AT, value);
2112 __ gssbx(AT, as_Register(base), T9, 0);
2113 } else {
2114 __ daddu(AT, as_Register(base), T9);
2115 __ move(T9, value);
2116 __ sb(T9, AT, 0);
2117 }
2118 }
2119 }
2120 }
2121 %}
2124 enc_class store_B_immI_enc_sync (memory mem, immI8 src) %{
2125 MacroAssembler _masm(&cbuf);
2126 int base = $mem$$base;
2127 int index = $mem$$index;
2128 int scale = $mem$$scale;
2129 int disp = $mem$$disp;
2130 int value = $src$$constant;
2132 if( index != 0 ) {
2133 if (scale == 0) {
2134 __ daddu(AT, as_Register(base), as_Register(index));
2135 } else {
2136 __ dsll(AT, as_Register(index), scale);
2137 __ daddu(AT, as_Register(base), AT);
2138 }
2139 if( Assembler::is_simm16(disp) ) {
2140 if (value == 0) {
2141 __ sb(R0, AT, disp);
2142 } else {
2143 __ move(T9, value);
2144 __ sb(T9, AT, disp);
2145 }
2146 } else {
2147 if (value == 0) {
2148 __ move(T9, disp);
2149 __ daddu(AT, AT, T9);
2150 __ sb(R0, AT, 0);
2151 } else {
2152 __ move(T9, disp);
2153 __ daddu(AT, AT, T9);
2154 __ move(T9, value);
2155 __ sb(T9, AT, 0);
2156 }
2157 }
2158 } else {
2159 if( Assembler::is_simm16(disp) ) {
2160 if (value == 0) {
2161 __ sb(R0, as_Register(base), disp);
2162 } else {
2163 __ move(AT, value);
2164 __ sb(AT, as_Register(base), disp);
2165 }
2166 } else {
2167 if (value == 0) {
2168 __ move(T9, disp);
2169 __ daddu(AT, as_Register(base), T9);
2170 __ sb(R0, AT, 0);
2171 } else {
2172 __ move(T9, disp);
2173 __ daddu(AT, as_Register(base), T9);
2174 __ move(T9, value);
2175 __ sb(T9, AT, 0);
2176 }
2177 }
2178 }
2180 __ sync();
2181 %}
2183 // Load Short (16bit signed)
2184 enc_class load_S_enc (mRegI dst, memory mem) %{
2185 MacroAssembler _masm(&cbuf);
2186 int dst = $dst$$reg;
2187 int base = $mem$$base;
2188 int index = $mem$$index;
2189 int scale = $mem$$scale;
2190 int disp = $mem$$disp;
2192 if( index != 0 ) {
2193 if (scale == 0) {
2194 __ daddu(AT, as_Register(base), as_Register(index));
2195 } else {
2196 __ dsll(AT, as_Register(index), scale);
2197 __ daddu(AT, as_Register(base), AT);
2198 }
2199 if( Assembler::is_simm16(disp) ) {
2200 __ lh(as_Register(dst), AT, disp);
2201 } else {
2202 __ move(T9, disp);
2203 __ addu(AT, AT, T9);
2204 __ lh(as_Register(dst), AT, 0);
2205 }
2206 } else {
2207 if( Assembler::is_simm16(disp) ) {
2208 __ lh(as_Register(dst), as_Register(base), disp);
2209 } else {
2210 __ move(T9, disp);
2211 __ addu(AT, as_Register(base), T9);
2212 __ lh(as_Register(dst), AT, 0);
2213 }
2214 }
2215 %}
2217 // Load Char (16bit unsigned)
2218 enc_class load_C_enc (mRegI dst, memory mem) %{
2219 MacroAssembler _masm(&cbuf);
2220 int dst = $dst$$reg;
2221 int base = $mem$$base;
2222 int index = $mem$$index;
2223 int scale = $mem$$scale;
2224 int disp = $mem$$disp;
2226 if( index != 0 ) {
2227 if (scale == 0) {
2228 __ daddu(AT, as_Register(base), as_Register(index));
2229 } else {
2230 __ dsll(AT, as_Register(index), scale);
2231 __ daddu(AT, as_Register(base), AT);
2232 }
2233 if( Assembler::is_simm16(disp) ) {
2234 __ lhu(as_Register(dst), AT, disp);
2235 } else {
2236 __ move(T9, disp);
2237 __ addu(AT, AT, T9);
2238 __ lhu(as_Register(dst), AT, 0);
2239 }
2240 } else {
2241 if( Assembler::is_simm16(disp) ) {
2242 __ lhu(as_Register(dst), as_Register(base), disp);
2243 } else {
2244 __ move(T9, disp);
2245 __ daddu(AT, as_Register(base), T9);
2246 __ lhu(as_Register(dst), AT, 0);
2247 }
2248 }
2249 %}
2251 // Store Char (16bit unsigned)
2252 enc_class store_C_reg_enc (memory mem, mRegI src) %{
2253 MacroAssembler _masm(&cbuf);
2254 int src = $src$$reg;
2255 int base = $mem$$base;
2256 int index = $mem$$index;
2257 int scale = $mem$$scale;
2258 int disp = $mem$$disp;
2260 if( index != 0 ) {
2261 if( Assembler::is_simm16(disp) ) {
2262 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2263 if (scale == 0) {
2264 __ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
2265 } else {
2266 __ dsll(AT, as_Register(index), scale);
2267 __ gsshx(as_Register(src), as_Register(base), AT, disp);
2268 }
2269 } else {
2270 if (scale == 0) {
2271 __ addu(AT, as_Register(base), as_Register(index));
2272 } else {
2273 __ dsll(AT, as_Register(index), scale);
2274 __ addu(AT, as_Register(base), AT);
2275 }
2276 __ sh(as_Register(src), AT, disp);
2277 }
2278 } else {
2279 if (scale == 0) {
2280 __ addu(AT, as_Register(base), as_Register(index));
2281 } else {
2282 __ dsll(AT, as_Register(index), scale);
2283 __ addu(AT, as_Register(base), AT);
2284 }
2285 __ move(T9, disp);
2286 if( UseLoongsonISA ) {
2287 __ gsshx(as_Register(src), AT, T9, 0);
2288 } else {
2289 __ addu(AT, AT, T9);
2290 __ sh(as_Register(src), AT, 0);
2291 }
2292 }
2293 } else {
2294 if( Assembler::is_simm16(disp) ) {
2295 __ sh(as_Register(src), as_Register(base), disp);
2296 } else {
2297 __ move(T9, disp);
2298 if( UseLoongsonISA ) {
2299 __ gsshx(as_Register(src), as_Register(base), T9, 0);
2300 } else {
2301 __ addu(AT, as_Register(base), T9);
2302 __ sh(as_Register(src), AT, 0);
2303 }
2304 }
2305 }
2306 %}
2308 enc_class load_I_enc (mRegI dst, memory mem) %{
2309 MacroAssembler _masm(&cbuf);
2310 int dst = $dst$$reg;
2311 int base = $mem$$base;
2312 int index = $mem$$index;
2313 int scale = $mem$$scale;
2314 int disp = $mem$$disp;
2316 if( index != 0 ) {
2317 if( Assembler::is_simm16(disp) ) {
2318 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2319 if (scale == 0) {
2320 __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
2321 } else {
2322 __ dsll(AT, as_Register(index), scale);
2323 __ gslwx(as_Register(dst), as_Register(base), AT, disp);
2324 }
2325 } else {
2326 if (scale == 0) {
2327 __ addu(AT, as_Register(base), as_Register(index));
2328 } else {
2329 __ dsll(AT, as_Register(index), scale);
2330 __ addu(AT, as_Register(base), AT);
2331 }
2332 __ lw(as_Register(dst), AT, disp);
2333 }
2334 } else {
2335 if (scale == 0) {
2336 __ addu(AT, as_Register(base), as_Register(index));
2337 } else {
2338 __ dsll(AT, as_Register(index), scale);
2339 __ addu(AT, as_Register(base), AT);
2340 }
2341 __ move(T9, disp);
2342 if( UseLoongsonISA ) {
2343 __ gslwx(as_Register(dst), AT, T9, 0);
2344 } else {
2345 __ addu(AT, AT, T9);
2346 __ lw(as_Register(dst), AT, 0);
2347 }
2348 }
2349 } else {
2350 if( Assembler::is_simm16(disp) ) {
2351 __ lw(as_Register(dst), as_Register(base), disp);
2352 } else {
2353 __ move(T9, disp);
2354 if( UseLoongsonISA ) {
2355 __ gslwx(as_Register(dst), as_Register(base), T9, 0);
2356 } else {
2357 __ addu(AT, as_Register(base), T9);
2358 __ lw(as_Register(dst), AT, 0);
2359 }
2360 }
2361 }
2362 %}
2364 enc_class store_I_reg_enc (memory mem, mRegI src) %{
2365 MacroAssembler _masm(&cbuf);
2366 int src = $src$$reg;
2367 int base = $mem$$base;
2368 int index = $mem$$index;
2369 int scale = $mem$$scale;
2370 int disp = $mem$$disp;
2372 if( index != 0 ) {
2373 if( Assembler::is_simm16(disp) ) {
2374 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2375 if (scale == 0) {
2376 __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
2377 } else {
2378 __ dsll(AT, as_Register(index), scale);
2379 __ gsswx(as_Register(src), as_Register(base), AT, disp);
2380 }
2381 } else {
2382 if (scale == 0) {
2383 __ addu(AT, as_Register(base), as_Register(index));
2384 } else {
2385 __ dsll(AT, as_Register(index), scale);
2386 __ addu(AT, as_Register(base), AT);
2387 }
2388 __ sw(as_Register(src), AT, disp);
2389 }
2390 } else {
2391 if (scale == 0) {
2392 __ addu(AT, as_Register(base), as_Register(index));
2393 } else {
2394 __ dsll(AT, as_Register(index), scale);
2395 __ addu(AT, as_Register(base), AT);
2396 }
2397 __ move(T9, disp);
2398 if( UseLoongsonISA ) {
2399 __ gsswx(as_Register(src), AT, T9, 0);
2400 } else {
2401 __ addu(AT, AT, T9);
2402 __ sw(as_Register(src), AT, 0);
2403 }
2404 }
2405 } else {
2406 if( Assembler::is_simm16(disp) ) {
2407 __ sw(as_Register(src), as_Register(base), disp);
2408 } else {
2409 __ move(T9, disp);
2410 if( UseLoongsonISA ) {
2411 __ gsswx(as_Register(src), as_Register(base), T9, 0);
2412 } else {
2413 __ addu(AT, as_Register(base), T9);
2414 __ sw(as_Register(src), AT, 0);
2415 }
2416 }
2417 }
2418 %}
2420 enc_class store_I_immI_enc (memory mem, immI src) %{
2421 MacroAssembler _masm(&cbuf);
2422 int base = $mem$$base;
2423 int index = $mem$$index;
2424 int scale = $mem$$scale;
2425 int disp = $mem$$disp;
2426 int value = $src$$constant;
2428 if( index != 0 ) {
2429 if (scale == 0) {
2430 __ daddu(AT, as_Register(base), as_Register(index));
2431 } else {
2432 __ dsll(AT, as_Register(index), scale);
2433 __ daddu(AT, as_Register(base), AT);
2434 }
2435 if( Assembler::is_simm16(disp) ) {
2436 if (value == 0) {
2437 __ sw(R0, AT, disp);
2438 } else {
2439 __ move(T9, value);
2440 __ sw(T9, AT, disp);
2441 }
2442 } else {
2443 if (value == 0) {
2444 __ move(T9, disp);
2445 __ addu(AT, AT, T9);
2446 __ sw(R0, AT, 0);
2447 } else {
2448 __ move(T9, disp);
2449 __ addu(AT, AT, T9);
2450 __ move(T9, value);
2451 __ sw(T9, AT, 0);
2452 }
2453 }
2454 } else {
2455 if( Assembler::is_simm16(disp) ) {
2456 if (value == 0) {
2457 __ sw(R0, as_Register(base), disp);
2458 } else {
2459 __ move(AT, value);
2460 __ sw(AT, as_Register(base), disp);
2461 }
2462 } else {
2463 if (value == 0) {
2464 __ move(T9, disp);
2465 __ addu(AT, as_Register(base), T9);
2466 __ sw(R0, AT, 0);
2467 } else {
2468 __ move(T9, disp);
2469 __ addu(AT, as_Register(base), T9);
2470 __ move(T9, value);
2471 __ sw(T9, AT, 0);
2472 }
2473 }
2474 }
2475 %}
2477 enc_class load_N_enc (mRegN dst, memory mem) %{
2478 MacroAssembler _masm(&cbuf);
2479 int dst = $dst$$reg;
2480 int base = $mem$$base;
2481 int index = $mem$$index;
2482 int scale = $mem$$scale;
2483 int disp = $mem$$disp;
2484 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2485 assert(disp_reloc == relocInfo::none, "cannot have disp");
2487 if( index != 0 ) {
2488 if (scale == 0) {
2489 __ daddu(AT, as_Register(base), as_Register(index));
2490 } else {
2491 __ dsll(AT, as_Register(index), scale);
2492 __ daddu(AT, as_Register(base), AT);
2493 }
2494 if( Assembler::is_simm16(disp) ) {
2495 __ lwu(as_Register(dst), AT, disp);
2496 } else {
2497 __ li(T9, disp);
2498 __ daddu(AT, AT, T9);
2499 __ lwu(as_Register(dst), AT, 0);
2500 }
2501 } else {
2502 if( Assembler::is_simm16(disp) ) {
2503 __ lwu(as_Register(dst), as_Register(base), disp);
2504 } else {
2505 __ li(T9, disp);
2506 __ daddu(AT, as_Register(base), T9);
2507 __ lwu(as_Register(dst), AT, 0);
2508 }
2509 }
2511 %}
2514 enc_class load_P_enc (mRegP dst, memory mem) %{
2515 MacroAssembler _masm(&cbuf);
2516 int dst = $dst$$reg;
2517 int base = $mem$$base;
2518 int index = $mem$$index;
2519 int scale = $mem$$scale;
2520 int disp = $mem$$disp;
2521 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2522 assert(disp_reloc == relocInfo::none, "cannot have disp");
2524 if( index != 0 ) {
2525 if (scale == 0) {
2526 __ daddu(AT, as_Register(base), as_Register(index));
2527 } else {
2528 __ dsll(AT, as_Register(index), scale);
2529 __ daddu(AT, as_Register(base), AT);
2530 }
2531 if( Assembler::is_simm16(disp) ) {
2532 __ ld(as_Register(dst), AT, disp);
2533 } else {
2534 __ li(T9, disp);
2535 __ daddu(AT, AT, T9);
2536 __ ld(as_Register(dst), AT, 0);
2537 }
2538 } else {
2539 if( Assembler::is_simm16(disp) ) {
2540 __ ld(as_Register(dst), as_Register(base), disp);
2541 } else {
2542 __ li(T9, disp);
2543 __ daddu(AT, as_Register(base), T9);
2544 __ ld(as_Register(dst), AT, 0);
2545 }
2546 }
2547 // if( disp_reloc != relocInfo::none) __ ld(as_Register(dst), as_Register(dst), 0);
2548 %}
2550 enc_class store_P_reg_enc (memory mem, mRegP src) %{
2551 MacroAssembler _masm(&cbuf);
2552 int src = $src$$reg;
2553 int base = $mem$$base;
2554 int index = $mem$$index;
2555 int scale = $mem$$scale;
2556 int disp = $mem$$disp;
2558 if( index != 0 ) {
2559 if (scale == 0) {
2560 __ daddu(AT, as_Register(base), as_Register(index));
2561 } else {
2562 __ dsll(AT, as_Register(index), scale);
2563 __ daddu(AT, as_Register(base), AT);
2564 }
2565 if( Assembler::is_simm16(disp) ) {
2566 __ sd(as_Register(src), AT, disp);
2567 } else {
2568 __ move(T9, disp);
2569 __ daddu(AT, AT, T9);
2570 __ sd(as_Register(src), AT, 0);
2571 }
2572 } else {
2573 if( Assembler::is_simm16(disp) ) {
2574 __ sd(as_Register(src), as_Register(base), disp);
2575 } else {
2576 __ move(T9, disp);
2577 __ daddu(AT, as_Register(base), T9);
2578 __ sd(as_Register(src), AT, 0);
2579 }
2580 }
2581 %}
2583 enc_class store_N_reg_enc (memory mem, mRegN src) %{
2584 MacroAssembler _masm(&cbuf);
2585 int src = $src$$reg;
2586 int base = $mem$$base;
2587 int index = $mem$$index;
2588 int scale = $mem$$scale;
2589 int disp = $mem$$disp;
2591 if( index != 0 ) {
2592 if (scale == 0) {
2593 __ daddu(AT, as_Register(base), as_Register(index));
2594 } else {
2595 __ dsll(AT, as_Register(index), scale);
2596 __ daddu(AT, as_Register(base), AT);
2597 }
2598 if( Assembler::is_simm16(disp) ) {
2599 __ sw(as_Register(src), AT, disp);
2600 } else {
2601 __ move(T9, disp);
2602 __ addu(AT, AT, T9);
2603 __ sw(as_Register(src), AT, 0);
2604 }
2605 } else {
2606 if( Assembler::is_simm16(disp) ) {
2607 __ sw(as_Register(src), as_Register(base), disp);
2608 } else {
2609 __ move(T9, disp);
2610 __ addu(AT, as_Register(base), T9);
2611 __ sw(as_Register(src), AT, 0);
2612 }
2613 }
2614 %}
2616 enc_class store_P_immP_enc (memory mem, immP31 src) %{
2617 MacroAssembler _masm(&cbuf);
2618 int base = $mem$$base;
2619 int index = $mem$$index;
2620 int scale = $mem$$scale;
2621 int disp = $mem$$disp;
2622 long value = $src$$constant;
2624 if( index != 0 ) {
2625 if (scale == 0) {
2626 __ daddu(AT, as_Register(base), as_Register(index));
2627 } else {
2628 __ dsll(AT, as_Register(index), scale);
2629 __ daddu(AT, as_Register(base), AT);
2630 }
2631 if( Assembler::is_simm16(disp) ) {
2632 if (value == 0) {
2633 __ sd(R0, AT, disp);
2634 } else {
2635 __ move(T9, value);
2636 __ sd(T9, AT, disp);
2637 }
2638 } else {
2639 if (value == 0) {
2640 __ move(T9, disp);
2641 __ daddu(AT, AT, T9);
2642 __ sd(R0, AT, 0);
2643 } else {
2644 __ move(T9, disp);
2645 __ daddu(AT, AT, T9);
2646 __ move(T9, value);
2647 __ sd(T9, AT, 0);
2648 }
2649 }
2650 } else {
2651 if( Assembler::is_simm16(disp) ) {
2652 if (value == 0) {
2653 __ sd(R0, as_Register(base), disp);
2654 } else {
2655 __ move(AT, value);
2656 __ sd(AT, as_Register(base), disp);
2657 }
2658 } else {
2659 if (value == 0) {
2660 __ move(T9, disp);
2661 __ daddu(AT, as_Register(base), T9);
2662 __ sd(R0, AT, 0);
2663 } else {
2664 __ move(T9, disp);
2665 __ daddu(AT, as_Register(base), T9);
2666 __ move(T9, value);
2667 __ sd(T9, AT, 0);
2668 }
2669 }
2670 }
2671 %}
2673 /*
2674 * 1d4 storeImmN [S0 + #16 (8-bit)], narrowoop: spec/benchmarks/_213_javac/Identifier:exact *
2675 * # compressed ptr ! Field: spec/benchmarks/_213_javac/Identifier.value
2676 * 0x00000055648065d4: daddu at, s0, zero
2677 * 0x00000055648065d8: lui t9, 0x0 ; {oop(a 'spec/benchmarks/_213_javac/Identifier')}
2678 * 0x00000055648065dc: ori t9, t9, 0xfffff610
2679 * 0x00000055648065e0: dsll t9, t9, 16
2680 * 0x00000055648065e4: ori t9, t9, 0xffffc628
2681 * 0x00000055648065e8: sw t9, 0x10(at)
2682 */
2683 enc_class storeImmN_enc (memory mem, immN src) %{
2684 MacroAssembler _masm(&cbuf);
2685 int base = $mem$$base;
2686 int index = $mem$$index;
2687 int scale = $mem$$scale;
2688 int disp = $mem$$disp;
2689 long * value = (long *)$src$$constant;
2691 if (value == NULL) {
2692 guarantee(Assembler::is_simm16(disp), "FIXME: disp is not simm16!");
2693 if (index == 0) {
2694 __ sw(R0, as_Register(base), disp);
2695 } else {
2696 if (scale == 0) {
2697 __ daddu(AT, as_Register(base), as_Register(index));
2698 } else {
2699 __ dsll(AT, as_Register(index), scale);
2700 __ daddu(AT, as_Register(base), AT);
2701 }
2702 __ sw(R0, AT, disp);
2703 }
2705 return;
2706 }
2708 int oop_index = __ oop_recorder()->find_index((jobject)value);
2709 RelocationHolder rspec = oop_Relocation::spec(oop_index);
2711 guarantee(scale == 0, "FIXME: scale is not zero !");
2712 guarantee(value != 0, "FIXME: value is zero !");
2714 if (index != 0) {
2715 if (scale == 0) {
2716 __ daddu(AT, as_Register(base), as_Register(index));
2717 } else {
2718 __ dsll(AT, as_Register(index), scale);
2719 __ daddu(AT, as_Register(base), AT);
2720 }
2721 if( Assembler::is_simm16(disp) ) {
2722 if(rspec.type() != relocInfo::none) {
2723 __ relocate(rspec, Assembler::narrow_oop_operand);
2724 __ li48(T9, oop_index);
2725 } else {
2726 __ set64(T9, oop_index);
2727 }
2728 __ sw(T9, AT, disp);
2729 } else {
2730 __ move(T9, disp);
2731 __ addu(AT, AT, T9);
2733 if(rspec.type() != relocInfo::none) {
2734 __ relocate(rspec, Assembler::narrow_oop_operand);
2735 __ li48(T9, oop_index);
2736 } else {
2737 __ set64(T9, oop_index);
2738 }
2739 __ sw(T9, AT, 0);
2740 }
2741 }
2742 else {
2743 if( Assembler::is_simm16(disp) ) {
2744 if($src->constant_reloc() != relocInfo::none) {
2745 __ relocate(rspec, Assembler::narrow_oop_operand);
2746 __ li48(T9, oop_index);
2747 } else {
2748 __ set64(T9, oop_index);
2749 }
2750 __ sw(T9, as_Register(base), disp);
2751 } else {
2752 __ move(T9, disp);
2753 __ daddu(AT, as_Register(base), T9);
2755 if($src->constant_reloc() != relocInfo::none){
2756 __ relocate(rspec, Assembler::narrow_oop_operand);
2757 __ li48(T9, oop_index);
2758 } else {
2759 __ set64(T9, oop_index);
2760 }
2761 __ sw(T9, AT, 0);
2762 }
2763 }
2764 %}
2766 enc_class storeImmNKlass_enc (memory mem, immNKlass src) %{
2767 MacroAssembler _masm(&cbuf);
2769 assert (UseCompressedOops, "should only be used for compressed headers");
2770 assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
2772 int base = $mem$$base;
2773 int index = $mem$$index;
2774 int scale = $mem$$scale;
2775 int disp = $mem$$disp;
2776 long value = $src$$constant;
2778 int klass_index = __ oop_recorder()->find_index((Klass*)value);
2779 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
2780 long narrowp = Klass::encode_klass((Klass*)value);
2782 if(index!=0){
2783 if (scale == 0) {
2784 __ daddu(AT, as_Register(base), as_Register(index));
2785 } else {
2786 __ dsll(AT, as_Register(index), scale);
2787 __ daddu(AT, as_Register(base), AT);
2788 }
2790 if( Assembler::is_simm16(disp) ) {
2791 if(rspec.type() != relocInfo::none){
2792 __ relocate(rspec, Assembler::narrow_oop_operand);
2793 __ li48(T9, narrowp);
2794 } else {
2795 __ set64(T9, narrowp);
2796 }
2797 __ sw(T9, AT, disp);
2798 } else {
2799 __ move(T9, disp);
2800 __ daddu(AT, AT, T9);
2802 if(rspec.type() != relocInfo::none){
2803 __ relocate(rspec, Assembler::narrow_oop_operand);
2804 __ li48(T9, narrowp);
2805 } else {
2806 __ set64(T9, narrowp);
2807 }
2809 __ sw(T9, AT, 0);
2810 }
2811 } else {
2812 if( Assembler::is_simm16(disp) ) {
2813 if(rspec.type() != relocInfo::none){
2814 __ relocate(rspec, Assembler::narrow_oop_operand);
2815 __ li48(T9, narrowp);
2816 }
2817 else {
2818 __ set64(T9, narrowp);
2819 }
2820 __ sw(T9, as_Register(base), disp);
2821 } else {
2822 __ move(T9, disp);
2823 __ daddu(AT, as_Register(base), T9);
2825 if(rspec.type() != relocInfo::none){
2826 __ relocate(rspec, Assembler::narrow_oop_operand);
2827 __ li48(T9, narrowp);
2828 } else {
2829 __ set64(T9, narrowp);
2830 }
2831 __ sw(T9, AT, 0);
2832 }
2833 }
2834 %}
2836 enc_class storeImmN0_enc(memory mem, ImmN0 src) %{
2837 MacroAssembler _masm(&cbuf);
2838 int base = $mem$$base;
2839 int index = $mem$$index;
2840 int scale = $mem$$scale;
2841 int disp = $mem$$disp;
2843 if(index!=0){
2844 if (scale == 0) {
2845 __ daddu(AT, as_Register(base), as_Register(index));
2846 } else {
2847 __ dsll(AT, as_Register(index), scale);
2848 __ daddu(AT, as_Register(base), AT);
2849 }
2851 if( Assembler::is_simm16(disp) ) {
2852 __ sw(R0, AT, disp);
2853 } else {
2854 __ move(T9, disp);
2855 __ daddu(AT, AT, T9);
2856 __ sw(R0, AT, 0);
2857 }
2858 }
2859 else {
2860 if( Assembler::is_simm16(disp) ) {
2861 __ sw(R0, as_Register(base), disp);
2862 } else {
2863 __ move(T9, disp);
2864 __ daddu(AT, as_Register(base), T9);
2865 __ sw(R0, AT, 0);
2866 }
2867 }
2868 %}
2870 enc_class load_L_enc (mRegL dst, memory mem) %{
2871 MacroAssembler _masm(&cbuf);
2872 int base = $mem$$base;
2873 int index = $mem$$index;
2874 int scale = $mem$$scale;
2875 int disp = $mem$$disp;
2876 Register dst_reg = as_Register($dst$$reg);
2878 /*********************2013/03/27**************************
2879 * Jin: $base may contain a null object.
2880 * Server JIT force the exception_offset to be the pos of
2881 * the first instruction.
2882 * I insert such a 'null_check' at the beginning.
2883 *******************************************************/
2885 __ lw(AT, as_Register(base), 0);
2887 /*********************2012/10/04**************************
2888 * Error case found in SortTest
2889 * 337 b java.util.Arrays::sort1 (401 bytes)
2890 * B73:
2891 * d34 lw T4.lo, [T4 + #16] #@loadL-lo
2892 * lw T4.hi, [T4 + #16]+4 #@loadL-hi
2893 *
2894 * The original instructions generated here are :
2895 * __ lw(dst_lo, as_Register(base), disp);
2896 * __ lw(dst_hi, as_Register(base), disp + 4);
2897 *******************************************************/
2899 if( index != 0 ) {
2900 if (scale == 0) {
2901 __ daddu(AT, as_Register(base), as_Register(index));
2902 } else {
2903 __ dsll(AT, as_Register(index), scale);
2904 __ daddu(AT, as_Register(base), AT);
2905 }
2906 if( Assembler::is_simm16(disp) ) {
2907 __ ld(dst_reg, AT, disp);
2908 } else {
2909 __ move(T9, disp);
2910 __ daddu(AT, AT, T9);
2911 __ ld(dst_reg, AT, 0);
2912 }
2913 } else {
2914 if( Assembler::is_simm16(disp) ) {
2915 __ move(AT, as_Register(base));
2916 __ ld(dst_reg, AT, disp);
2917 } else {
2918 __ move(T9, disp);
2919 __ daddu(AT, as_Register(base), T9);
2920 __ ld(dst_reg, AT, 0);
2921 }
2922 }
2923 %}
2925 enc_class store_L_reg_enc (memory mem, mRegL src) %{
2926 MacroAssembler _masm(&cbuf);
2927 int base = $mem$$base;
2928 int index = $mem$$index;
2929 int scale = $mem$$scale;
2930 int disp = $mem$$disp;
2931 Register src_reg = as_Register($src$$reg);
2933 if( index != 0 ) {
2934 if (scale == 0) {
2935 __ daddu(AT, as_Register(base), as_Register(index));
2936 } else {
2937 __ dsll(AT, as_Register(index), scale);
2938 __ daddu(AT, as_Register(base), AT);
2939 }
2940 if( Assembler::is_simm16(disp) ) {
2941 __ sd(src_reg, AT, disp);
2942 } else {
2943 __ move(T9, disp);
2944 __ daddu(AT, AT, T9);
2945 __ sd(src_reg, AT, 0);
2946 }
2947 } else {
2948 if( Assembler::is_simm16(disp) ) {
2949 __ move(AT, as_Register(base));
2950 __ sd(src_reg, AT, disp);
2951 } else {
2952 __ move(T9, disp);
2953 __ daddu(AT, as_Register(base), T9);
2954 __ sd(src_reg, AT, 0);
2955 }
2956 }
2957 %}
2959 enc_class store_L_immL0_enc (memory mem, immL0 src) %{
2960 MacroAssembler _masm(&cbuf);
2961 int base = $mem$$base;
2962 int index = $mem$$index;
2963 int scale = $mem$$scale;
2964 int disp = $mem$$disp;
2966 if( index != 0 ) {
2967 if (scale == 0) {
2968 __ daddu(AT, as_Register(base), as_Register(index));
2969 } else {
2970 __ dsll(AT, as_Register(index), scale);
2971 __ daddu(AT, as_Register(base), AT);
2972 }
2973 if( Assembler::is_simm16(disp) ) {
2974 __ sd(R0, AT, disp);
2975 } else {
2976 __ move(T9, disp);
2977 __ addu(AT, AT, T9);
2978 __ sd(R0, AT, 0);
2979 }
2980 } else {
2981 if( Assembler::is_simm16(disp) ) {
2982 __ move(AT, as_Register(base));
2983 __ sd(R0, AT, disp);
2984 } else {
2985 __ move(T9, disp);
2986 __ addu(AT, as_Register(base), T9);
2987 __ sd(R0, AT, 0);
2988 }
2989 }
2990 %}
2992 enc_class store_L_immL_enc (memory mem, immL src) %{
2993 MacroAssembler _masm(&cbuf);
2994 int base = $mem$$base;
2995 int index = $mem$$index;
2996 int scale = $mem$$scale;
2997 int disp = $mem$$disp;
2998 long imm = $src$$constant;
3000 if( index != 0 ) {
3001 if (scale == 0) {
3002 __ daddu(AT, as_Register(base), as_Register(index));
3003 } else {
3004 __ dsll(AT, as_Register(index), scale);
3005 __ daddu(AT, as_Register(base), AT);
3006 }
3007 if( Assembler::is_simm16(disp) ) {
3008 __ li(T9, imm);
3009 __ sd(T9, AT, disp);
3010 } else {
3011 __ move(T9, disp);
3012 __ addu(AT, AT, T9);
3013 __ li(T9, imm);
3014 __ sd(T9, AT, 0);
3015 }
3016 } else {
3017 if( Assembler::is_simm16(disp) ) {
3018 __ move(AT, as_Register(base));
3019 __ li(T9, imm);
3020 __ sd(T9, AT, disp);
3021 } else {
3022 __ move(T9, disp);
3023 __ addu(AT, as_Register(base), T9);
3024 __ li(T9, imm);
3025 __ sd(T9, AT, 0);
3026 }
3027 }
3028 %}
3030 enc_class load_F_enc (regF dst, memory mem) %{
3031 MacroAssembler _masm(&cbuf);
3032 int base = $mem$$base;
3033 int index = $mem$$index;
3034 int scale = $mem$$scale;
3035 int disp = $mem$$disp;
3036 FloatRegister dst = $dst$$FloatRegister;
3038 if( index != 0 ) {
3039 if( Assembler::is_simm16(disp) ) {
3040 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3041 if (scale == 0) {
3042 __ gslwxc1(dst, as_Register(base), as_Register(index), disp);
3043 } else {
3044 __ dsll(AT, as_Register(index), scale);
3045 __ gslwxc1(dst, as_Register(base), AT, disp);
3046 }
3047 } else {
3048 if (scale == 0) {
3049 __ daddu(AT, as_Register(base), as_Register(index));
3050 } else {
3051 __ dsll(AT, as_Register(index), scale);
3052 __ daddu(AT, as_Register(base), AT);
3053 }
3054 __ lwc1(dst, AT, disp);
3055 }
3056 } else {
3057 if (scale == 0) {
3058 __ daddu(AT, as_Register(base), as_Register(index));
3059 } else {
3060 __ dsll(AT, as_Register(index), scale);
3061 __ daddu(AT, as_Register(base), AT);
3062 }
3063 __ move(T9, disp);
3064 if( UseLoongsonISA ) {
3065 __ gslwxc1(dst, AT, T9, 0);
3066 } else {
3067 __ daddu(AT, AT, T9);
3068 __ lwc1(dst, AT, 0);
3069 }
3070 }
3071 } else {
3072 if( Assembler::is_simm16(disp) ) {
3073 __ lwc1(dst, as_Register(base), disp);
3074 } else {
3075 __ move(T9, disp);
3076 if( UseLoongsonISA ) {
3077 __ gslwxc1(dst, as_Register(base), T9, 0);
3078 } else {
3079 __ daddu(AT, as_Register(base), T9);
3080 __ lwc1(dst, AT, 0);
3081 }
3082 }
3083 }
3084 %}
3086 enc_class store_F_reg_enc (memory mem, regF src) %{
3087 MacroAssembler _masm(&cbuf);
3088 int base = $mem$$base;
3089 int index = $mem$$index;
3090 int scale = $mem$$scale;
3091 int disp = $mem$$disp;
3092 FloatRegister src = $src$$FloatRegister;
3094 if( index != 0 ) {
3095 if( Assembler::is_simm16(disp) ) {
3096 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3097 if (scale == 0) {
3098 __ gsswxc1(src, as_Register(base), as_Register(index), disp);
3099 } else {
3100 __ dsll(AT, as_Register(index), scale);
3101 __ gsswxc1(src, as_Register(base), AT, disp);
3102 }
3103 } else {
3104 if (scale == 0) {
3105 __ daddu(AT, as_Register(base), as_Register(index));
3106 } else {
3107 __ dsll(AT, as_Register(index), scale);
3108 __ daddu(AT, as_Register(base), AT);
3109 }
3110 __ swc1(src, AT, disp);
3111 }
3112 } else {
3113 if (scale == 0) {
3114 __ daddu(AT, as_Register(base), as_Register(index));
3115 } else {
3116 __ dsll(AT, as_Register(index), scale);
3117 __ daddu(AT, as_Register(base), AT);
3118 }
3119 __ move(T9, disp);
3120 if( UseLoongsonISA ) {
3121 __ gsswxc1(src, AT, T9, 0);
3122 } else {
3123 __ daddu(AT, AT, T9);
3124 __ swc1(src, AT, 0);
3125 }
3126 }
3127 } else {
3128 if( Assembler::is_simm16(disp) ) {
3129 __ swc1(src, as_Register(base), disp);
3130 } else {
3131 __ move(T9, disp);
3132 if( UseLoongsonISA ) {
3133 __ gslwxc1(src, as_Register(base), T9, 0);
3134 } else {
3135 __ daddu(AT, as_Register(base), T9);
3136 __ swc1(src, AT, 0);
3137 }
3138 }
3139 }
3140 %}
3142 enc_class load_D_enc (regD dst, memory mem) %{
3143 MacroAssembler _masm(&cbuf);
3144 int base = $mem$$base;
3145 int index = $mem$$index;
3146 int scale = $mem$$scale;
3147 int disp = $mem$$disp;
3148 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3150 if( index != 0 ) {
3151 if( Assembler::is_simm16(disp) ) {
3152 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3153 if (scale == 0) {
3154 __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
3155 } else {
3156 __ dsll(AT, as_Register(index), scale);
3157 __ gsldxc1(dst_reg, as_Register(base), AT, disp);
3158 }
3159 } else {
3160 if (scale == 0) {
3161 __ daddu(AT, as_Register(base), as_Register(index));
3162 } else {
3163 __ dsll(AT, as_Register(index), scale);
3164 __ daddu(AT, as_Register(base), AT);
3165 }
3166 __ ldc1(dst_reg, AT, disp);
3167 }
3168 } else {
3169 if (scale == 0) {
3170 __ daddu(AT, as_Register(base), as_Register(index));
3171 } else {
3172 __ dsll(AT, as_Register(index), scale);
3173 __ daddu(AT, as_Register(base), AT);
3174 }
3175 __ move(T9, disp);
3176 if( UseLoongsonISA ) {
3177 __ gsldxc1(dst_reg, AT, T9, 0);
3178 } else {
3179 __ addu(AT, AT, T9);
3180 __ ldc1(dst_reg, AT, 0);
3181 }
3182 }
3183 } else {
3184 if( Assembler::is_simm16(disp) ) {
3185 __ ldc1(dst_reg, as_Register(base), disp);
3186 } else {
3187 __ move(T9, disp);
3188 if( UseLoongsonISA ) {
3189 __ gsldxc1(dst_reg, as_Register(base), T9, 0);
3190 } else {
3191 __ addu(AT, as_Register(base), T9);
3192 __ ldc1(dst_reg, AT, 0);
3193 }
3194 }
3195 }
3196 %}
3198 enc_class store_D_reg_enc (memory mem, regD src) %{
3199 MacroAssembler _masm(&cbuf);
3200 int base = $mem$$base;
3201 int index = $mem$$index;
3202 int scale = $mem$$scale;
3203 int disp = $mem$$disp;
3204 FloatRegister src_reg = as_FloatRegister($src$$reg);
3206 if( index != 0 ) {
3207 if( Assembler::is_simm16(disp) ) {
3208 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3209 if (scale == 0) {
3210 __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
3211 } else {
3212 __ dsll(AT, as_Register(index), scale);
3213 __ gssdxc1(src_reg, as_Register(base), AT, disp);
3214 }
3215 } else {
3216 if (scale == 0) {
3217 __ daddu(AT, as_Register(base), as_Register(index));
3218 } else {
3219 __ dsll(AT, as_Register(index), scale);
3220 __ daddu(AT, as_Register(base), AT);
3221 }
3222 __ sdc1(src_reg, AT, disp);
3223 }
3224 } else {
3225 if (scale == 0) {
3226 __ daddu(AT, as_Register(base), as_Register(index));
3227 } else {
3228 __ dsll(AT, as_Register(index), scale);
3229 __ daddu(AT, as_Register(base), AT);
3230 }
3231 __ move(T9, disp);
3232 if( UseLoongsonISA ) {
3233 __ gssdxc1(src_reg, AT, T9, 0);
3234 } else {
3235 __ addu(AT, AT, T9);
3236 __ sdc1(src_reg, AT, 0);
3237 }
3238 }
3239 } else {
3240 if( Assembler::is_simm16(disp) ) {
3241 __ sdc1(src_reg, as_Register(base), disp);
3242 } else {
3243 __ move(T9, disp);
3244 if( UseLoongsonISA ) {
3245 __ gssdxc1(src_reg, as_Register(base), T9, 0);
3246 } else {
3247 __ addu(AT, as_Register(base), T9);
3248 __ sdc1(src_reg, AT, 0);
3249 }
3250 }
3251 }
3252 %}
3254 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
3255 MacroAssembler _masm(&cbuf);
3256 // This is the instruction starting address for relocation info.
3257 __ block_comment("Java_To_Runtime");
3258 cbuf.set_insts_mark();
3259 __ relocate(relocInfo::runtime_call_type);
3261 __ li48(T9, (long)$meth$$method);
3262 __ jalr(T9);
3263 __ nop();
3264 %}
3266 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
3267 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
3268 // who we intended to call.
3269 MacroAssembler _masm(&cbuf);
3270 cbuf.set_insts_mark();
3272 if ( !_method ) {
3273 __ relocate(relocInfo::runtime_call_type);
3274 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
3275 // runtime_call_Relocation::spec(), RELOC_IMM32 );
3276 } else if(_optimized_virtual) {
3277 __ relocate(relocInfo::opt_virtual_call_type);
3278 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
3279 // opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
3280 } else {
3281 __ relocate(relocInfo::static_call_type);
3282 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
3283 // static_call_Relocation::spec(), RELOC_IMM32 );
3284 }
3286 __ li(T9, $meth$$method);
3287 __ jalr(T9);
3288 __ nop();
3289 if( _method ) { // Emit stub for static call
3290 emit_java_to_interp(cbuf);
3291 }
3292 %}
3295 /*
3296 * [Ref: LIR_Assembler::ic_call() ]
3297 */
3298 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
3299 MacroAssembler _masm(&cbuf);
3300 __ block_comment("Java_Dynamic_Call");
3301 __ ic_call((address)$meth$$method);
3302 %}
3305 enc_class Set_Flags_After_Fast_Lock_Unlock(FlagsReg cr) %{
3306 Register flags = $cr$$Register;
3307 Label L;
3309 MacroAssembler _masm(&cbuf);
3311 __ addu(flags, R0, R0);
3312 __ beq(AT, R0, L);
3313 __ delayed()->nop();
3314 __ move(flags, 0xFFFFFFFF);
3315 __ bind(L);
3316 %}
3318 enc_class enc_PartialSubtypeCheck(mRegP result, mRegP sub, mRegP super, mRegI tmp) %{
3319 Register result = $result$$Register;
3320 Register sub = $sub$$Register;
3321 Register super = $super$$Register;
3322 Register length = $tmp$$Register;
3323 Register tmp = T9;
3324 Label miss;
3326 /* 2012/9/28 Jin: result may be the same as sub
3327 * 47c B40: # B21 B41 <- B20 Freq: 0.155379
3328 * 47c partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
3329 * 4bc mov S2, NULL #@loadConP
3330 * 4c0 beq S1, S2, B21 #@branchConP P=0.999999 C=-1.000000
3331 */
3332 MacroAssembler _masm(&cbuf);
3333 Label done;
3334 __ check_klass_subtype_slow_path(sub, super, length, tmp,
3335 NULL, &miss,
3336 /*set_cond_codes:*/ true);
3337 /* 2013/7/22 Jin: Refer to X86_64's RDI */
3338 __ move(result, 0);
3339 __ b(done);
3340 __ nop();
3342 __ bind(miss);
3343 __ move(result, 1);
3344 __ bind(done);
3345 %}
3347 %}
3350 //---------MIPS FRAME--------------------------------------------------------------
3351 // Definition of frame structure and management information.
3352 //
3353 // S T A C K L A Y O U T Allocators stack-slot number
3354 // | (to get allocators register number
3355 // G Owned by | | v add SharedInfo::stack0)
3356 // r CALLER | |
3357 // o | +--------+ pad to even-align allocators stack-slot
3358 // w V | pad0 | numbers; owned by CALLER
3359 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3360 // h ^ | in | 5
3361 // | | args | 4 Holes in incoming args owned by SELF
3362 // | | old | | 3
3363 // | | SP-+--------+----> Matcher::_old_SP, even aligned
3364 // v | | ret | 3 return address
3365 // Owned by +--------+
3366 // Self | pad2 | 2 pad to align old SP
3367 // | +--------+ 1
3368 // | | locks | 0
3369 // | +--------+----> SharedInfo::stack0, even aligned
3370 // | | pad1 | 11 pad to align new SP
3371 // | +--------+
3372 // | | | 10
3373 // | | spills | 9 spills
3374 // V | | 8 (pad0 slot for callee)
3375 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3376 // ^ | out | 7
3377 // | | args | 6 Holes in outgoing args owned by CALLEE
3378 // Owned by new | |
3379 // Callee SP-+--------+----> Matcher::_new_SP, even aligned
3380 // | |
3381 //
3382 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3383 // known from SELF's arguments and the Java calling convention.
3384 // Region 6-7 is determined per call site.
3385 // Note 2: If the calling convention leaves holes in the incoming argument
3386 // area, those holes are owned by SELF. Holes in the outgoing area
3387 // are owned by the CALLEE. Holes should not be nessecary in the
3388 // incoming area, as the Java calling convention is completely under
3389 // the control of the AD file. Doubles can be sorted and packed to
3390 // avoid holes. Holes in the outgoing arguments may be nessecary for
3391 // varargs C calling conventions.
3392 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3393 // even aligned with pad0 as needed.
3394 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3395 // region 6-11 is even aligned; it may be padded out more so that
3396 // the region from SP to FP meets the minimum stack alignment.
3397 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
3398 // alignment. Region 11, pad1, may be dynamically extended so that
3399 // SP meets the minimum alignment.
3402 frame %{
3404 stack_direction(TOWARDS_LOW);
3406 // These two registers define part of the calling convention
3407 // between compiled code and the interpreter.
3408 // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention
3409 // for more information. by yjl 3/16/2006
3411 inline_cache_reg(T1); // Inline Cache Register
3412 interpreter_method_oop_reg(S3); // Method Oop Register when calling interpreter
3413 /*
3414 inline_cache_reg(T1); // Inline Cache Register or methodOop for I2C
3415 interpreter_arg_ptr_reg(A0); // Argument pointer for I2C adapters
3416 */
3418 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3419 cisc_spilling_operand_name(indOffset32);
3421 // Number of stack slots consumed by locking an object
3422 // generate Compile::sync_stack_slots
3423 #ifdef _LP64
3424 sync_stack_slots(2);
3425 #else
3426 sync_stack_slots(1);
3427 #endif
3429 frame_pointer(SP);
3431 // Interpreter stores its frame pointer in a register which is
3432 // stored to the stack by I2CAdaptors.
3433 // I2CAdaptors convert from interpreted java to compiled java.
3435 interpreter_frame_pointer(FP);
3437 // generate Matcher::stack_alignment
3438 stack_alignment(StackAlignmentInBytes); //wordSize = sizeof(char*);
3440 // Number of stack slots between incoming argument block and the start of
3441 // a new frame. The PROLOG must add this many slots to the stack. The
3442 // EPILOG must remove this many slots. Intel needs one slot for
3443 // return address.
3444 // generate Matcher::in_preserve_stack_slots
3445 //in_preserve_stack_slots(VerifyStackAtCalls + 2); //Now VerifyStackAtCalls is defined as false ! Leave one stack slot for ra and fp
3446 in_preserve_stack_slots(4); //Now VerifyStackAtCalls is defined as false ! Leave two stack slots for ra and fp
3448 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3449 // for calls to C. Supports the var-args backing area for register parms.
3450 varargs_C_out_slots_killed(0);
3452 // The after-PROLOG location of the return address. Location of
3453 // return address specifies a type (REG or STACK) and a number
3454 // representing the register number (i.e. - use a register name) or
3455 // stack slot.
3456 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3457 // Otherwise, it is above the locks and verification slot and alignment word
3458 //return_addr(STACK -1+ round_to(1+VerifyStackAtCalls+Compile::current()->sync()*Compile::current()->sync_stack_slots(),WordsPerLong));
3459 return_addr(REG RA);
3461 // Body of function which returns an integer array locating
3462 // arguments either in registers or in stack slots. Passed an array
3463 // of ideal registers called "sig" and a "length" count. Stack-slot
3464 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3465 // arguments for a CALLEE. Incoming stack arguments are
3466 // automatically biased by the preserve_stack_slots field above.
3469 // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing)
3470 // StartNode::calling_convention call this. by yjl 3/16/2006
3471 calling_convention %{
3472 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3473 %}
3478 // Body of function which returns an integer array locating
3479 // arguments either in registers or in stack slots. Passed an array
3480 // of ideal registers called "sig" and a "length" count. Stack-slot
3481 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3482 // arguments for a CALLEE. Incoming stack arguments are
3483 // automatically biased by the preserve_stack_slots field above.
3486 // SEE CallRuntimeNode::calling_convention for more information. by yjl 3/16/2006
3487 c_calling_convention %{
3488 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3489 %}
3492 // Location of C & interpreter return values
3493 // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR.
3494 // SEE Matcher::match. by yjl 3/16/2006
3495 c_return_value %{
3496 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3497 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3498 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3499 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num };
3500 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3501 %}
3503 // Location of return values
3504 // register(s) contain(s) return value for Op_StartC2I and Op_Start.
3505 // SEE Matcher::match. by yjl 3/16/2006
3507 return_value %{
3508 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3509 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3510 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3511 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num};
3512 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3513 %}
3515 %}
3517 //----------ATTRIBUTES---------------------------------------------------------
3518 //----------Operand Attributes-------------------------------------------------
3519 op_attrib op_cost(0); // Required cost attribute
3521 //----------Instruction Attributes---------------------------------------------
3522 ins_attrib ins_cost(100); // Required cost attribute
3523 ins_attrib ins_size(32); // Required size attribute (in bits)
3524 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3525 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3526 // non-matching short branch variant of some
3527 // long branch?
3528 ins_attrib ins_alignment(4); // Required alignment attribute (must be a power of 2)
3529 // specifies the alignment that some part of the instruction (not
3530 // necessarily the start) requires. If > 1, a compute_padding()
3531 // function must be provided for the instruction
3533 //----------OPERANDS-----------------------------------------------------------
3534 // Operand definitions must precede instruction definitions for correct parsing
3535 // in the ADLC because operands constitute user defined types which are used in
3536 // instruction definitions.
3538 // Vectors
3539 operand vecD() %{
3540 constraint(ALLOC_IN_RC(dbl_reg));
3541 match(VecD);
3543 format %{ %}
3544 interface(REG_INTER);
3545 %}
3547 // Flags register, used as output of compare instructions
3548 operand FlagsReg() %{
3549 constraint(ALLOC_IN_RC(mips_flags));
3550 match(RegFlags);
3552 format %{ "EFLAGS" %}
3553 interface(REG_INTER);
3554 %}
3556 //----------Simple Operands----------------------------------------------------
3557 //TODO: Should we need to define some more special immediate number ?
3558 // Immediate Operands
3559 // Integer Immediate
3560 operand immI() %{
3561 match(ConI);
3562 //TODO: should not match immI8 here LEE
3563 match(immI8);
3565 op_cost(20);
3566 format %{ %}
3567 interface(CONST_INTER);
3568 %}
3570 // Long Immediate 8-bit
3571 operand immL8()
3572 %{
3573 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3574 match(ConL);
3576 op_cost(5);
3577 format %{ %}
3578 interface(CONST_INTER);
3579 %}
3581 // Constant for test vs zero
3582 operand immI0() %{
3583 predicate(n->get_int() == 0);
3584 match(ConI);
3586 op_cost(0);
3587 format %{ %}
3588 interface(CONST_INTER);
3589 %}
3591 // Constant for increment
3592 operand immI1() %{
3593 predicate(n->get_int() == 1);
3594 match(ConI);
3596 op_cost(0);
3597 format %{ %}
3598 interface(CONST_INTER);
3599 %}
3601 // Constant for decrement
3602 operand immI_M1() %{
3603 predicate(n->get_int() == -1);
3604 match(ConI);
3606 op_cost(0);
3607 format %{ %}
3608 interface(CONST_INTER);
3609 %}
3611 // Valid scale values for addressing modes
3612 operand immI2() %{
3613 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3614 match(ConI);
3616 format %{ %}
3617 interface(CONST_INTER);
3618 %}
3620 operand immI8() %{
3621 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3622 match(ConI);
3624 op_cost(5);
3625 format %{ %}
3626 interface(CONST_INTER);
3627 %}
3629 operand immI16() %{
3630 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3631 match(ConI);
3633 op_cost(10);
3634 format %{ %}
3635 interface(CONST_INTER);
3636 %}
3638 // Constant for long shifts
3639 operand immI_32() %{
3640 predicate( n->get_int() == 32 );
3641 match(ConI);
3643 op_cost(0);
3644 format %{ %}
3645 interface(CONST_INTER);
3646 %}
3648 operand immI_63() %{
3649 predicate( n->get_int() == 63 );
3650 match(ConI);
3652 op_cost(0);
3653 format %{ %}
3654 interface(CONST_INTER);
3655 %}
3657 operand immI_0_31() %{
3658 predicate( n->get_int() >= 0 && n->get_int() <= 31 );
3659 match(ConI);
3661 op_cost(0);
3662 format %{ %}
3663 interface(CONST_INTER);
3664 %}
3666 // Operand for non-negtive integer mask
3667 operand immI_nonneg_mask() %{
3668 predicate( (n->get_int() >= 0) && (Assembler::is_int_mask(n->get_int()) != -1) );
3669 match(ConI);
3671 op_cost(0);
3672 format %{ %}
3673 interface(CONST_INTER);
3674 %}
3676 operand immI_32_63() %{
3677 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3678 match(ConI);
3679 op_cost(0);
3681 format %{ %}
3682 interface(CONST_INTER);
3683 %}
3685 operand immI16_sub() %{
3686 predicate((-32767 <= n->get_int()) && (n->get_int() <= 32768));
3687 match(ConI);
3689 op_cost(10);
3690 format %{ %}
3691 interface(CONST_INTER);
3692 %}
3694 operand immI_0_32767() %{
3695 predicate( n->get_int() >= 0 && n->get_int() <= 32767 );
3696 match(ConI);
3697 op_cost(0);
3699 format %{ %}
3700 interface(CONST_INTER);
3701 %}
3703 operand immI_0_65535() %{
3704 predicate( n->get_int() >= 0 && n->get_int() <= 65535 );
3705 match(ConI);
3706 op_cost(0);
3708 format %{ %}
3709 interface(CONST_INTER);
3710 %}
3712 operand immI_1() %{
3713 predicate( n->get_int() == 1 );
3714 match(ConI);
3716 op_cost(0);
3717 format %{ %}
3718 interface(CONST_INTER);
3719 %}
3721 operand immI_2() %{
3722 predicate( n->get_int() == 2 );
3723 match(ConI);
3725 op_cost(0);
3726 format %{ %}
3727 interface(CONST_INTER);
3728 %}
3730 operand immI_3() %{
3731 predicate( n->get_int() == 3 );
3732 match(ConI);
3734 op_cost(0);
3735 format %{ %}
3736 interface(CONST_INTER);
3737 %}
3739 operand immI_7() %{
3740 predicate( n->get_int() == 7 );
3741 match(ConI);
3743 format %{ %}
3744 interface(CONST_INTER);
3745 %}
3747 // Immediates for special shifts (sign extend)
3749 // Constants for increment
3750 operand immI_16() %{
3751 predicate( n->get_int() == 16 );
3752 match(ConI);
3754 format %{ %}
3755 interface(CONST_INTER);
3756 %}
3758 operand immI_24() %{
3759 predicate( n->get_int() == 24 );
3760 match(ConI);
3762 format %{ %}
3763 interface(CONST_INTER);
3764 %}
3766 // Constant for byte-wide masking
3767 operand immI_255() %{
3768 predicate( n->get_int() == 255 );
3769 match(ConI);
3771 op_cost(0);
3772 format %{ %}
3773 interface(CONST_INTER);
3774 %}
3776 operand immI_65535() %{
3777 predicate( n->get_int() == 65535 );
3778 match(ConI);
3780 op_cost(5);
3781 format %{ %}
3782 interface(CONST_INTER);
3783 %}
3785 operand immI_65536() %{
3786 predicate( n->get_int() == 65536 );
3787 match(ConI);
3789 op_cost(5);
3790 format %{ %}
3791 interface(CONST_INTER);
3792 %}
3794 // Pointer Immediate
3795 operand immP() %{
3796 match(ConP);
3798 op_cost(10);
3799 format %{ %}
3800 interface(CONST_INTER);
3801 %}
3803 operand immP31()
3804 %{
3805 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3806 && (n->get_ptr() >> 31) == 0);
3807 match(ConP);
3809 op_cost(5);
3810 format %{ %}
3811 interface(CONST_INTER);
3812 %}
3814 // NULL Pointer Immediate
3815 operand immP0() %{
3816 predicate( n->get_ptr() == 0 );
3817 match(ConP);
3818 op_cost(0);
3820 format %{ %}
3821 interface(CONST_INTER);
3822 %}
3824 // Pointer Immediate: 64-bit
3825 operand immP_set() %{
3826 match(ConP);
3828 op_cost(5);
3829 // formats are generated automatically for constants and base registers
3830 format %{ %}
3831 interface(CONST_INTER);
3832 %}
3834 // Pointer Immediate: 64-bit
3835 operand immP_load() %{
3836 predicate(n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set64(n->get_ptr()) > 3));
3837 match(ConP);
3839 op_cost(5);
3840 // formats are generated automatically for constants and base registers
3841 format %{ %}
3842 interface(CONST_INTER);
3843 %}
3845 // Pointer Immediate: 64-bit
3846 operand immP_no_oop_cheap() %{
3847 predicate(!n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set64(n->get_ptr()) <= 3));
3848 match(ConP);
3850 op_cost(5);
3851 // formats are generated automatically for constants and base registers
3852 format %{ %}
3853 interface(CONST_INTER);
3854 %}
3856 // Pointer for polling page
3857 operand immP_poll() %{
3858 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3859 match(ConP);
3860 op_cost(5);
3862 format %{ %}
3863 interface(CONST_INTER);
3864 %}
3866 // Pointer Immediate
3867 operand immN() %{
3868 match(ConN);
3870 op_cost(10);
3871 format %{ %}
3872 interface(CONST_INTER);
3873 %}
3875 operand immNKlass() %{
3876 match(ConNKlass);
3878 op_cost(10);
3879 format %{ %}
3880 interface(CONST_INTER);
3881 %}
3883 // NULL Pointer Immediate
3884 operand immN0() %{
3885 predicate(n->get_narrowcon() == 0);
3886 match(ConN);
3888 op_cost(5);
3889 format %{ %}
3890 interface(CONST_INTER);
3891 %}
3893 // Long Immediate
3894 operand immL() %{
3895 match(ConL);
3897 op_cost(20);
3898 format %{ %}
3899 interface(CONST_INTER);
3900 %}
3902 // Long Immediate zero
3903 operand immL0() %{
3904 predicate( n->get_long() == 0L );
3905 match(ConL);
3906 op_cost(0);
3908 format %{ %}
3909 interface(CONST_INTER);
3910 %}
3912 operand immL7() %{
3913 predicate( n->get_long() == 7L );
3914 match(ConL);
3915 op_cost(0);
3917 format %{ %}
3918 interface(CONST_INTER);
3919 %}
3921 operand immL_M1() %{
3922 predicate( n->get_long() == -1L );
3923 match(ConL);
3924 op_cost(0);
3926 format %{ %}
3927 interface(CONST_INTER);
3928 %}
3930 // bit 0..2 zero
3931 operand immL_M8() %{
3932 predicate( n->get_long() == -8L );
3933 match(ConL);
3934 op_cost(0);
3936 format %{ %}
3937 interface(CONST_INTER);
3938 %}
3940 // bit 2 zero
3941 operand immL_M5() %{
3942 predicate( n->get_long() == -5L );
3943 match(ConL);
3944 op_cost(0);
3946 format %{ %}
3947 interface(CONST_INTER);
3948 %}
3950 // bit 1..2 zero
3951 operand immL_M7() %{
3952 predicate( n->get_long() == -7L );
3953 match(ConL);
3954 op_cost(0);
3956 format %{ %}
3957 interface(CONST_INTER);
3958 %}
3960 // bit 0..1 zero
3961 operand immL_M4() %{
3962 predicate( n->get_long() == -4L );
3963 match(ConL);
3964 op_cost(0);
3966 format %{ %}
3967 interface(CONST_INTER);
3968 %}
3970 // bit 3..6 zero
3971 operand immL_M121() %{
3972 predicate( n->get_long() == -121L );
3973 match(ConL);
3974 op_cost(0);
3976 format %{ %}
3977 interface(CONST_INTER);
3978 %}
3980 // Long immediate from 0 to 127.
3981 // Used for a shorter form of long mul by 10.
3982 operand immL_127() %{
3983 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3984 match(ConL);
3985 op_cost(0);
3987 format %{ %}
3988 interface(CONST_INTER);
3989 %}
3991 // Operand for non-negtive long mask
3992 operand immL_nonneg_mask() %{
3993 predicate( (n->get_long() >= 0) && (Assembler::is_jlong_mask(n->get_long()) != -1) );
3994 match(ConL);
3996 op_cost(0);
3997 format %{ %}
3998 interface(CONST_INTER);
3999 %}
4001 operand immL_0_65535() %{
4002 predicate( n->get_long() >= 0 && n->get_long() <= 65535 );
4003 match(ConL);
4004 op_cost(0);
4006 format %{ %}
4007 interface(CONST_INTER);
4008 %}
4010 // Long Immediate: cheap (materialize in <= 3 instructions)
4011 operand immL_cheap() %{
4012 predicate(MacroAssembler::insts_for_set64(n->get_long()) <= 3);
4013 match(ConL);
4014 op_cost(0);
4016 format %{ %}
4017 interface(CONST_INTER);
4018 %}
4020 // Long Immediate: expensive (materialize in > 3 instructions)
4021 operand immL_expensive() %{
4022 predicate(MacroAssembler::insts_for_set64(n->get_long()) > 3);
4023 match(ConL);
4024 op_cost(0);
4026 format %{ %}
4027 interface(CONST_INTER);
4028 %}
4030 operand immL16() %{
4031 predicate((-32768 <= n->get_long()) && (n->get_long() <= 32767));
4032 match(ConL);
4034 op_cost(10);
4035 format %{ %}
4036 interface(CONST_INTER);
4037 %}
4039 operand immL16_sub() %{
4040 predicate((-32767 <= n->get_long()) && (n->get_long() <= 32768));
4041 match(ConL);
4043 op_cost(10);
4044 format %{ %}
4045 interface(CONST_INTER);
4046 %}
4048 // Long Immediate: low 32-bit mask
4049 operand immL_32bits() %{
4050 predicate(n->get_long() == 0xFFFFFFFFL);
4051 match(ConL);
4052 op_cost(20);
4054 format %{ %}
4055 interface(CONST_INTER);
4056 %}
4058 // Long Immediate 32-bit signed
4059 operand immL32()
4060 %{
4061 predicate(n->get_long() == (int) (n->get_long()));
4062 match(ConL);
4064 op_cost(15);
4065 format %{ %}
4066 interface(CONST_INTER);
4067 %}
4070 //single-precision floating-point zero
4071 operand immF0() %{
4072 predicate(jint_cast(n->getf()) == 0);
4073 match(ConF);
4075 op_cost(5);
4076 format %{ %}
4077 interface(CONST_INTER);
4078 %}
4080 //single-precision floating-point immediate
4081 operand immF() %{
4082 match(ConF);
4084 op_cost(20);
4085 format %{ %}
4086 interface(CONST_INTER);
4087 %}
4089 //double-precision floating-point zero
4090 operand immD0() %{
4091 predicate(jlong_cast(n->getd()) == 0);
4092 match(ConD);
4094 op_cost(5);
4095 format %{ %}
4096 interface(CONST_INTER);
4097 %}
4099 //double-precision floating-point immediate
4100 operand immD() %{
4101 match(ConD);
4103 op_cost(20);
4104 format %{ %}
4105 interface(CONST_INTER);
4106 %}
4108 // Register Operands
4109 // Integer Register
4110 operand mRegI() %{
4111 constraint(ALLOC_IN_RC(int_reg));
4112 match(RegI);
4114 format %{ %}
4115 interface(REG_INTER);
4116 %}
4118 operand no_Ax_mRegI() %{
4119 constraint(ALLOC_IN_RC(no_Ax_int_reg));
4120 match(RegI);
4121 match(mRegI);
4123 format %{ %}
4124 interface(REG_INTER);
4125 %}
4127 operand mS0RegI() %{
4128 constraint(ALLOC_IN_RC(s0_reg));
4129 match(RegI);
4130 match(mRegI);
4132 format %{ "S0" %}
4133 interface(REG_INTER);
4134 %}
4136 operand mS1RegI() %{
4137 constraint(ALLOC_IN_RC(s1_reg));
4138 match(RegI);
4139 match(mRegI);
4141 format %{ "S1" %}
4142 interface(REG_INTER);
4143 %}
4145 operand mS2RegI() %{
4146 constraint(ALLOC_IN_RC(s2_reg));
4147 match(RegI);
4148 match(mRegI);
4150 format %{ "S2" %}
4151 interface(REG_INTER);
4152 %}
4154 operand mS3RegI() %{
4155 constraint(ALLOC_IN_RC(s3_reg));
4156 match(RegI);
4157 match(mRegI);
4159 format %{ "S3" %}
4160 interface(REG_INTER);
4161 %}
4163 operand mS4RegI() %{
4164 constraint(ALLOC_IN_RC(s4_reg));
4165 match(RegI);
4166 match(mRegI);
4168 format %{ "S4" %}
4169 interface(REG_INTER);
4170 %}
4172 operand mS5RegI() %{
4173 constraint(ALLOC_IN_RC(s5_reg));
4174 match(RegI);
4175 match(mRegI);
4177 format %{ "S5" %}
4178 interface(REG_INTER);
4179 %}
4181 operand mS6RegI() %{
4182 constraint(ALLOC_IN_RC(s6_reg));
4183 match(RegI);
4184 match(mRegI);
4186 format %{ "S6" %}
4187 interface(REG_INTER);
4188 %}
4190 operand mS7RegI() %{
4191 constraint(ALLOC_IN_RC(s7_reg));
4192 match(RegI);
4193 match(mRegI);
4195 format %{ "S7" %}
4196 interface(REG_INTER);
4197 %}
4200 operand mT0RegI() %{
4201 constraint(ALLOC_IN_RC(t0_reg));
4202 match(RegI);
4203 match(mRegI);
4205 format %{ "T0" %}
4206 interface(REG_INTER);
4207 %}
4209 operand mT1RegI() %{
4210 constraint(ALLOC_IN_RC(t1_reg));
4211 match(RegI);
4212 match(mRegI);
4214 format %{ "T1" %}
4215 interface(REG_INTER);
4216 %}
4218 operand mT2RegI() %{
4219 constraint(ALLOC_IN_RC(t2_reg));
4220 match(RegI);
4221 match(mRegI);
4223 format %{ "T2" %}
4224 interface(REG_INTER);
4225 %}
4227 operand mT3RegI() %{
4228 constraint(ALLOC_IN_RC(t3_reg));
4229 match(RegI);
4230 match(mRegI);
4232 format %{ "T3" %}
4233 interface(REG_INTER);
4234 %}
4236 operand mT8RegI() %{
4237 constraint(ALLOC_IN_RC(t8_reg));
4238 match(RegI);
4239 match(mRegI);
4241 format %{ "T8" %}
4242 interface(REG_INTER);
4243 %}
4245 operand mT9RegI() %{
4246 constraint(ALLOC_IN_RC(t9_reg));
4247 match(RegI);
4248 match(mRegI);
4250 format %{ "T9" %}
4251 interface(REG_INTER);
4252 %}
4254 operand mA0RegI() %{
4255 constraint(ALLOC_IN_RC(a0_reg));
4256 match(RegI);
4257 match(mRegI);
4259 format %{ "A0" %}
4260 interface(REG_INTER);
4261 %}
4263 operand mA1RegI() %{
4264 constraint(ALLOC_IN_RC(a1_reg));
4265 match(RegI);
4266 match(mRegI);
4268 format %{ "A1" %}
4269 interface(REG_INTER);
4270 %}
4272 operand mA2RegI() %{
4273 constraint(ALLOC_IN_RC(a2_reg));
4274 match(RegI);
4275 match(mRegI);
4277 format %{ "A2" %}
4278 interface(REG_INTER);
4279 %}
4281 operand mA3RegI() %{
4282 constraint(ALLOC_IN_RC(a3_reg));
4283 match(RegI);
4284 match(mRegI);
4286 format %{ "A3" %}
4287 interface(REG_INTER);
4288 %}
4290 operand mA4RegI() %{
4291 constraint(ALLOC_IN_RC(a4_reg));
4292 match(RegI);
4293 match(mRegI);
4295 format %{ "A4" %}
4296 interface(REG_INTER);
4297 %}
4299 operand mA5RegI() %{
4300 constraint(ALLOC_IN_RC(a5_reg));
4301 match(RegI);
4302 match(mRegI);
4304 format %{ "A5" %}
4305 interface(REG_INTER);
4306 %}
4308 operand mA6RegI() %{
4309 constraint(ALLOC_IN_RC(a6_reg));
4310 match(RegI);
4311 match(mRegI);
4313 format %{ "A6" %}
4314 interface(REG_INTER);
4315 %}
4317 operand mA7RegI() %{
4318 constraint(ALLOC_IN_RC(a7_reg));
4319 match(RegI);
4320 match(mRegI);
4322 format %{ "A7" %}
4323 interface(REG_INTER);
4324 %}
4326 operand mV0RegI() %{
4327 constraint(ALLOC_IN_RC(v0_reg));
4328 match(RegI);
4329 match(mRegI);
4331 format %{ "V0" %}
4332 interface(REG_INTER);
4333 %}
4335 operand mV1RegI() %{
4336 constraint(ALLOC_IN_RC(v1_reg));
4337 match(RegI);
4338 match(mRegI);
4340 format %{ "V1" %}
4341 interface(REG_INTER);
4342 %}
4344 operand mRegN() %{
4345 constraint(ALLOC_IN_RC(int_reg));
4346 match(RegN);
4348 format %{ %}
4349 interface(REG_INTER);
4350 %}
4352 operand t0_RegN() %{
4353 constraint(ALLOC_IN_RC(t0_reg));
4354 match(RegN);
4355 match(mRegN);
4357 format %{ %}
4358 interface(REG_INTER);
4359 %}
4361 operand t1_RegN() %{
4362 constraint(ALLOC_IN_RC(t1_reg));
4363 match(RegN);
4364 match(mRegN);
4366 format %{ %}
4367 interface(REG_INTER);
4368 %}
4370 operand t2_RegN() %{
4371 constraint(ALLOC_IN_RC(t2_reg));
4372 match(RegN);
4373 match(mRegN);
4375 format %{ %}
4376 interface(REG_INTER);
4377 %}
4379 operand t3_RegN() %{
4380 constraint(ALLOC_IN_RC(t3_reg));
4381 match(RegN);
4382 match(mRegN);
4384 format %{ %}
4385 interface(REG_INTER);
4386 %}
4388 operand t8_RegN() %{
4389 constraint(ALLOC_IN_RC(t8_reg));
4390 match(RegN);
4391 match(mRegN);
4393 format %{ %}
4394 interface(REG_INTER);
4395 %}
4397 operand t9_RegN() %{
4398 constraint(ALLOC_IN_RC(t9_reg));
4399 match(RegN);
4400 match(mRegN);
4402 format %{ %}
4403 interface(REG_INTER);
4404 %}
4406 operand a0_RegN() %{
4407 constraint(ALLOC_IN_RC(a0_reg));
4408 match(RegN);
4409 match(mRegN);
4411 format %{ %}
4412 interface(REG_INTER);
4413 %}
4415 operand a1_RegN() %{
4416 constraint(ALLOC_IN_RC(a1_reg));
4417 match(RegN);
4418 match(mRegN);
4420 format %{ %}
4421 interface(REG_INTER);
4422 %}
4424 operand a2_RegN() %{
4425 constraint(ALLOC_IN_RC(a2_reg));
4426 match(RegN);
4427 match(mRegN);
4429 format %{ %}
4430 interface(REG_INTER);
4431 %}
4433 operand a3_RegN() %{
4434 constraint(ALLOC_IN_RC(a3_reg));
4435 match(RegN);
4436 match(mRegN);
4438 format %{ %}
4439 interface(REG_INTER);
4440 %}
4442 operand a4_RegN() %{
4443 constraint(ALLOC_IN_RC(a4_reg));
4444 match(RegN);
4445 match(mRegN);
4447 format %{ %}
4448 interface(REG_INTER);
4449 %}
4451 operand a5_RegN() %{
4452 constraint(ALLOC_IN_RC(a5_reg));
4453 match(RegN);
4454 match(mRegN);
4456 format %{ %}
4457 interface(REG_INTER);
4458 %}
4460 operand a6_RegN() %{
4461 constraint(ALLOC_IN_RC(a6_reg));
4462 match(RegN);
4463 match(mRegN);
4465 format %{ %}
4466 interface(REG_INTER);
4467 %}
4469 operand a7_RegN() %{
4470 constraint(ALLOC_IN_RC(a7_reg));
4471 match(RegN);
4472 match(mRegN);
4474 format %{ %}
4475 interface(REG_INTER);
4476 %}
4478 operand s0_RegN() %{
4479 constraint(ALLOC_IN_RC(s0_reg));
4480 match(RegN);
4481 match(mRegN);
4483 format %{ %}
4484 interface(REG_INTER);
4485 %}
4487 operand s1_RegN() %{
4488 constraint(ALLOC_IN_RC(s1_reg));
4489 match(RegN);
4490 match(mRegN);
4492 format %{ %}
4493 interface(REG_INTER);
4494 %}
4496 operand s2_RegN() %{
4497 constraint(ALLOC_IN_RC(s2_reg));
4498 match(RegN);
4499 match(mRegN);
4501 format %{ %}
4502 interface(REG_INTER);
4503 %}
4505 operand s3_RegN() %{
4506 constraint(ALLOC_IN_RC(s3_reg));
4507 match(RegN);
4508 match(mRegN);
4510 format %{ %}
4511 interface(REG_INTER);
4512 %}
4514 operand s4_RegN() %{
4515 constraint(ALLOC_IN_RC(s4_reg));
4516 match(RegN);
4517 match(mRegN);
4519 format %{ %}
4520 interface(REG_INTER);
4521 %}
4523 operand s5_RegN() %{
4524 constraint(ALLOC_IN_RC(s5_reg));
4525 match(RegN);
4526 match(mRegN);
4528 format %{ %}
4529 interface(REG_INTER);
4530 %}
4532 operand s6_RegN() %{
4533 constraint(ALLOC_IN_RC(s6_reg));
4534 match(RegN);
4535 match(mRegN);
4537 format %{ %}
4538 interface(REG_INTER);
4539 %}
4541 operand s7_RegN() %{
4542 constraint(ALLOC_IN_RC(s7_reg));
4543 match(RegN);
4544 match(mRegN);
4546 format %{ %}
4547 interface(REG_INTER);
4548 %}
4550 operand v0_RegN() %{
4551 constraint(ALLOC_IN_RC(v0_reg));
4552 match(RegN);
4553 match(mRegN);
4555 format %{ %}
4556 interface(REG_INTER);
4557 %}
4559 operand v1_RegN() %{
4560 constraint(ALLOC_IN_RC(v1_reg));
4561 match(RegN);
4562 match(mRegN);
4564 format %{ %}
4565 interface(REG_INTER);
4566 %}
4568 // Pointer Register
4569 operand mRegP() %{
4570 constraint(ALLOC_IN_RC(p_reg));
4571 match(RegP);
4573 format %{ %}
4574 interface(REG_INTER);
4575 %}
4577 operand no_T8_mRegP() %{
4578 constraint(ALLOC_IN_RC(no_T8_p_reg));
4579 match(RegP);
4580 match(mRegP);
4582 format %{ %}
4583 interface(REG_INTER);
4584 %}
4586 operand s0_RegP()
4587 %{
4588 constraint(ALLOC_IN_RC(s0_long_reg));
4589 match(RegP);
4590 match(mRegP);
4591 match(no_T8_mRegP);
4593 format %{ %}
4594 interface(REG_INTER);
4595 %}
4597 operand s1_RegP()
4598 %{
4599 constraint(ALLOC_IN_RC(s1_long_reg));
4600 match(RegP);
4601 match(mRegP);
4602 match(no_T8_mRegP);
4604 format %{ %}
4605 interface(REG_INTER);
4606 %}
4608 operand s2_RegP()
4609 %{
4610 constraint(ALLOC_IN_RC(s2_long_reg));
4611 match(RegP);
4612 match(mRegP);
4613 match(no_T8_mRegP);
4615 format %{ %}
4616 interface(REG_INTER);
4617 %}
4619 operand s3_RegP()
4620 %{
4621 constraint(ALLOC_IN_RC(s3_long_reg));
4622 match(RegP);
4623 match(mRegP);
4624 match(no_T8_mRegP);
4626 format %{ %}
4627 interface(REG_INTER);
4628 %}
4630 operand s4_RegP()
4631 %{
4632 constraint(ALLOC_IN_RC(s4_long_reg));
4633 match(RegP);
4634 match(mRegP);
4635 match(no_T8_mRegP);
4637 format %{ %}
4638 interface(REG_INTER);
4639 %}
4641 operand s5_RegP()
4642 %{
4643 constraint(ALLOC_IN_RC(s5_long_reg));
4644 match(RegP);
4645 match(mRegP);
4646 match(no_T8_mRegP);
4648 format %{ %}
4649 interface(REG_INTER);
4650 %}
4652 operand s6_RegP()
4653 %{
4654 constraint(ALLOC_IN_RC(s6_long_reg));
4655 match(RegP);
4656 match(mRegP);
4657 match(no_T8_mRegP);
4659 format %{ %}
4660 interface(REG_INTER);
4661 %}
4663 operand s7_RegP()
4664 %{
4665 constraint(ALLOC_IN_RC(s7_long_reg));
4666 match(RegP);
4667 match(mRegP);
4668 match(no_T8_mRegP);
4670 format %{ %}
4671 interface(REG_INTER);
4672 %}
4674 operand t0_RegP()
4675 %{
4676 constraint(ALLOC_IN_RC(t0_long_reg));
4677 match(RegP);
4678 match(mRegP);
4679 match(no_T8_mRegP);
4681 format %{ %}
4682 interface(REG_INTER);
4683 %}
4685 operand t1_RegP()
4686 %{
4687 constraint(ALLOC_IN_RC(t1_long_reg));
4688 match(RegP);
4689 match(mRegP);
4690 match(no_T8_mRegP);
4692 format %{ %}
4693 interface(REG_INTER);
4694 %}
4696 operand t2_RegP()
4697 %{
4698 constraint(ALLOC_IN_RC(t2_long_reg));
4699 match(RegP);
4700 match(mRegP);
4701 match(no_T8_mRegP);
4703 format %{ %}
4704 interface(REG_INTER);
4705 %}
4707 operand t3_RegP()
4708 %{
4709 constraint(ALLOC_IN_RC(t3_long_reg));
4710 match(RegP);
4711 match(mRegP);
4712 match(no_T8_mRegP);
4714 format %{ %}
4715 interface(REG_INTER);
4716 %}
4718 operand t8_RegP()
4719 %{
4720 constraint(ALLOC_IN_RC(t8_long_reg));
4721 match(RegP);
4722 match(mRegP);
4724 format %{ %}
4725 interface(REG_INTER);
4726 %}
4728 operand t9_RegP()
4729 %{
4730 constraint(ALLOC_IN_RC(t9_long_reg));
4731 match(RegP);
4732 match(mRegP);
4733 match(no_T8_mRegP);
4735 format %{ %}
4736 interface(REG_INTER);
4737 %}
4739 operand a0_RegP()
4740 %{
4741 constraint(ALLOC_IN_RC(a0_long_reg));
4742 match(RegP);
4743 match(mRegP);
4744 match(no_T8_mRegP);
4746 format %{ %}
4747 interface(REG_INTER);
4748 %}
4750 operand a1_RegP()
4751 %{
4752 constraint(ALLOC_IN_RC(a1_long_reg));
4753 match(RegP);
4754 match(mRegP);
4755 match(no_T8_mRegP);
4757 format %{ %}
4758 interface(REG_INTER);
4759 %}
4761 operand a2_RegP()
4762 %{
4763 constraint(ALLOC_IN_RC(a2_long_reg));
4764 match(RegP);
4765 match(mRegP);
4766 match(no_T8_mRegP);
4768 format %{ %}
4769 interface(REG_INTER);
4770 %}
4772 operand a3_RegP()
4773 %{
4774 constraint(ALLOC_IN_RC(a3_long_reg));
4775 match(RegP);
4776 match(mRegP);
4777 match(no_T8_mRegP);
4779 format %{ %}
4780 interface(REG_INTER);
4781 %}
4783 operand a4_RegP()
4784 %{
4785 constraint(ALLOC_IN_RC(a4_long_reg));
4786 match(RegP);
4787 match(mRegP);
4788 match(no_T8_mRegP);
4790 format %{ %}
4791 interface(REG_INTER);
4792 %}
4795 operand a5_RegP()
4796 %{
4797 constraint(ALLOC_IN_RC(a5_long_reg));
4798 match(RegP);
4799 match(mRegP);
4800 match(no_T8_mRegP);
4802 format %{ %}
4803 interface(REG_INTER);
4804 %}
4806 operand a6_RegP()
4807 %{
4808 constraint(ALLOC_IN_RC(a6_long_reg));
4809 match(RegP);
4810 match(mRegP);
4811 match(no_T8_mRegP);
4813 format %{ %}
4814 interface(REG_INTER);
4815 %}
4817 operand a7_RegP()
4818 %{
4819 constraint(ALLOC_IN_RC(a7_long_reg));
4820 match(RegP);
4821 match(mRegP);
4822 match(no_T8_mRegP);
4824 format %{ %}
4825 interface(REG_INTER);
4826 %}
4828 operand v0_RegP()
4829 %{
4830 constraint(ALLOC_IN_RC(v0_long_reg));
4831 match(RegP);
4832 match(mRegP);
4833 match(no_T8_mRegP);
4835 format %{ %}
4836 interface(REG_INTER);
4837 %}
4839 operand v1_RegP()
4840 %{
4841 constraint(ALLOC_IN_RC(v1_long_reg));
4842 match(RegP);
4843 match(mRegP);
4844 match(no_T8_mRegP);
4846 format %{ %}
4847 interface(REG_INTER);
4848 %}
4850 /*
4851 operand mSPRegP(mRegP reg) %{
4852 constraint(ALLOC_IN_RC(sp_reg));
4853 match(reg);
4855 format %{ "SP" %}
4856 interface(REG_INTER);
4857 %}
4859 operand mFPRegP(mRegP reg) %{
4860 constraint(ALLOC_IN_RC(fp_reg));
4861 match(reg);
4863 format %{ "FP" %}
4864 interface(REG_INTER);
4865 %}
4866 */
4868 operand mRegL() %{
4869 constraint(ALLOC_IN_RC(long_reg));
4870 match(RegL);
4872 format %{ %}
4873 interface(REG_INTER);
4874 %}
4876 operand v0RegL() %{
4877 constraint(ALLOC_IN_RC(v0_long_reg));
4878 match(RegL);
4879 match(mRegL);
4881 format %{ %}
4882 interface(REG_INTER);
4883 %}
4885 operand v1RegL() %{
4886 constraint(ALLOC_IN_RC(v1_long_reg));
4887 match(RegL);
4888 match(mRegL);
4890 format %{ %}
4891 interface(REG_INTER);
4892 %}
4894 operand a0RegL() %{
4895 constraint(ALLOC_IN_RC(a0_long_reg));
4896 match(RegL);
4897 match(mRegL);
4899 format %{ "A0" %}
4900 interface(REG_INTER);
4901 %}
4903 operand a1RegL() %{
4904 constraint(ALLOC_IN_RC(a1_long_reg));
4905 match(RegL);
4906 match(mRegL);
4908 format %{ %}
4909 interface(REG_INTER);
4910 %}
4912 operand a2RegL() %{
4913 constraint(ALLOC_IN_RC(a2_long_reg));
4914 match(RegL);
4915 match(mRegL);
4917 format %{ %}
4918 interface(REG_INTER);
4919 %}
4921 operand a3RegL() %{
4922 constraint(ALLOC_IN_RC(a3_long_reg));
4923 match(RegL);
4924 match(mRegL);
4926 format %{ %}
4927 interface(REG_INTER);
4928 %}
4930 operand t0RegL() %{
4931 constraint(ALLOC_IN_RC(t0_long_reg));
4932 match(RegL);
4933 match(mRegL);
4935 format %{ %}
4936 interface(REG_INTER);
4937 %}
4939 operand t1RegL() %{
4940 constraint(ALLOC_IN_RC(t1_long_reg));
4941 match(RegL);
4942 match(mRegL);
4944 format %{ %}
4945 interface(REG_INTER);
4946 %}
4948 operand t2RegL() %{
4949 constraint(ALLOC_IN_RC(t2_long_reg));
4950 match(RegL);
4951 match(mRegL);
4953 format %{ %}
4954 interface(REG_INTER);
4955 %}
4957 operand t3RegL() %{
4958 constraint(ALLOC_IN_RC(t3_long_reg));
4959 match(RegL);
4960 match(mRegL);
4962 format %{ %}
4963 interface(REG_INTER);
4964 %}
4966 operand t8RegL() %{
4967 constraint(ALLOC_IN_RC(t8_long_reg));
4968 match(RegL);
4969 match(mRegL);
4971 format %{ %}
4972 interface(REG_INTER);
4973 %}
4975 operand a4RegL() %{
4976 constraint(ALLOC_IN_RC(a4_long_reg));
4977 match(RegL);
4978 match(mRegL);
4980 format %{ %}
4981 interface(REG_INTER);
4982 %}
4984 operand a5RegL() %{
4985 constraint(ALLOC_IN_RC(a5_long_reg));
4986 match(RegL);
4987 match(mRegL);
4989 format %{ %}
4990 interface(REG_INTER);
4991 %}
4993 operand a6RegL() %{
4994 constraint(ALLOC_IN_RC(a6_long_reg));
4995 match(RegL);
4996 match(mRegL);
4998 format %{ %}
4999 interface(REG_INTER);
5000 %}
5002 operand a7RegL() %{
5003 constraint(ALLOC_IN_RC(a7_long_reg));
5004 match(RegL);
5005 match(mRegL);
5007 format %{ %}
5008 interface(REG_INTER);
5009 %}
5011 operand s0RegL() %{
5012 constraint(ALLOC_IN_RC(s0_long_reg));
5013 match(RegL);
5014 match(mRegL);
5016 format %{ %}
5017 interface(REG_INTER);
5018 %}
5020 operand s1RegL() %{
5021 constraint(ALLOC_IN_RC(s1_long_reg));
5022 match(RegL);
5023 match(mRegL);
5025 format %{ %}
5026 interface(REG_INTER);
5027 %}
5029 operand s2RegL() %{
5030 constraint(ALLOC_IN_RC(s2_long_reg));
5031 match(RegL);
5032 match(mRegL);
5034 format %{ %}
5035 interface(REG_INTER);
5036 %}
5038 operand s3RegL() %{
5039 constraint(ALLOC_IN_RC(s3_long_reg));
5040 match(RegL);
5041 match(mRegL);
5043 format %{ %}
5044 interface(REG_INTER);
5045 %}
5047 operand s4RegL() %{
5048 constraint(ALLOC_IN_RC(s4_long_reg));
5049 match(RegL);
5050 match(mRegL);
5052 format %{ %}
5053 interface(REG_INTER);
5054 %}
5056 operand s7RegL() %{
5057 constraint(ALLOC_IN_RC(s7_long_reg));
5058 match(RegL);
5059 match(mRegL);
5061 format %{ %}
5062 interface(REG_INTER);
5063 %}
5065 // Floating register operands
5066 operand regF() %{
5067 constraint(ALLOC_IN_RC(flt_reg));
5068 match(RegF);
5070 format %{ %}
5071 interface(REG_INTER);
5072 %}
5074 //Double Precision Floating register operands
5075 operand regD() %{
5076 constraint(ALLOC_IN_RC(dbl_reg));
5077 match(RegD);
5079 format %{ %}
5080 interface(REG_INTER);
5081 %}
5083 //----------Memory Operands----------------------------------------------------
5084 // Indirect Memory Operand
5085 operand indirect(mRegP reg) %{
5086 constraint(ALLOC_IN_RC(p_reg));
5087 match(reg);
5089 format %{ "[$reg] @ indirect" %}
5090 interface(MEMORY_INTER) %{
5091 base($reg);
5092 index(0x0); /* NO_INDEX */
5093 scale(0x0);
5094 disp(0x0);
5095 %}
5096 %}
5098 // Indirect Memory Plus Short Offset Operand
5099 operand indOffset8(mRegP reg, immL8 off)
5100 %{
5101 constraint(ALLOC_IN_RC(p_reg));
5102 match(AddP reg off);
5104 format %{ "[$reg + $off (8-bit)] @ indOffset8" %}
5105 interface(MEMORY_INTER) %{
5106 base($reg);
5107 index(0x0); /* NO_INDEX */
5108 scale(0x0);
5109 disp($off);
5110 %}
5111 %}
5113 // Indirect Memory Times Scale Plus Index Register
5114 operand indIndexScale(mRegP reg, mRegL lreg, immI2 scale)
5115 %{
5116 constraint(ALLOC_IN_RC(p_reg));
5117 match(AddP reg (LShiftL lreg scale));
5119 op_cost(10);
5120 format %{"[$reg + $lreg << $scale] @ indIndexScale" %}
5121 interface(MEMORY_INTER) %{
5122 base($reg);
5123 index($lreg);
5124 scale($scale);
5125 disp(0x0);
5126 %}
5127 %}
5130 // [base + index + offset]
5131 operand baseIndexOffset8(mRegP base, mRegL index, immL8 off)
5132 %{
5133 constraint(ALLOC_IN_RC(p_reg));
5134 op_cost(5);
5135 match(AddP (AddP base index) off);
5137 format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8" %}
5138 interface(MEMORY_INTER) %{
5139 base($base);
5140 index($index);
5141 scale(0x0);
5142 disp($off);
5143 %}
5144 %}
5146 // [base + index + offset]
5147 operand baseIndexOffset8_convI2L(mRegP base, mRegI index, immL8 off)
5148 %{
5149 constraint(ALLOC_IN_RC(p_reg));
5150 op_cost(5);
5151 match(AddP (AddP base (ConvI2L index)) off);
5153 format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8_convI2L" %}
5154 interface(MEMORY_INTER) %{
5155 base($base);
5156 index($index);
5157 scale(0x0);
5158 disp($off);
5159 %}
5160 %}
5162 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5163 operand indIndexScaleOffset8(mRegP reg, immL8 off, mRegL lreg, immI2 scale)
5164 %{
5165 constraint(ALLOC_IN_RC(p_reg));
5166 match(AddP (AddP reg (LShiftL lreg scale)) off);
5168 op_cost(10);
5169 format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffset8" %}
5170 interface(MEMORY_INTER) %{
5171 base($reg);
5172 index($lreg);
5173 scale($scale);
5174 disp($off);
5175 %}
5176 %}
5178 operand indIndexScaleOffset8_convI2L(mRegP reg, immL8 off, mRegI ireg, immI2 scale)
5179 %{
5180 constraint(ALLOC_IN_RC(p_reg));
5181 match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off);
5183 op_cost(10);
5184 format %{"[$reg + $off + $ireg << $scale] @ indIndexScaleOffset8_convI2L" %}
5185 interface(MEMORY_INTER) %{
5186 base($reg);
5187 index($ireg);
5188 scale($scale);
5189 disp($off);
5190 %}
5191 %}
5193 // [base + index<<scale + offset]
5194 operand basePosIndexScaleOffset8(mRegP base, mRegI index, immL8 off, immI_0_31 scale)
5195 %{
5196 constraint(ALLOC_IN_RC(p_reg));
5197 //predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5198 op_cost(10);
5199 match(AddP (AddP base (LShiftL (ConvI2L index) scale)) off);
5201 format %{ "[$base + $index << $scale + $off (8-bit)] @ basePosIndexScaleOffset8" %}
5202 interface(MEMORY_INTER) %{
5203 base($base);
5204 index($index);
5205 scale($scale);
5206 disp($off);
5207 %}
5208 %}
5210 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5211 operand indIndexScaleOffsetNarrow(mRegN reg, immL8 off, mRegL lreg, immI2 scale)
5212 %{
5213 predicate(Universe::narrow_oop_shift() == 0);
5214 constraint(ALLOC_IN_RC(p_reg));
5215 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
5217 op_cost(10);
5218 format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffsetNarrow" %}
5219 interface(MEMORY_INTER) %{
5220 base($reg);
5221 index($lreg);
5222 scale($scale);
5223 disp($off);
5224 %}
5225 %}
5227 // [base + index<<scale + offset] for compressd Oops
5228 operand indPosIndexI2LScaleOffset8Narrow(mRegN base, mRegI index, immL8 off, immI_0_31 scale)
5229 %{
5230 constraint(ALLOC_IN_RC(p_reg));
5231 //predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5232 predicate(Universe::narrow_oop_shift() == 0);
5233 op_cost(10);
5234 match(AddP (AddP (DecodeN base) (LShiftL (ConvI2L index) scale)) off);
5236 format %{ "[$base + $index << $scale + $off (8-bit)] @ indPosIndexI2LScaleOffset8Narrow" %}
5237 interface(MEMORY_INTER) %{
5238 base($base);
5239 index($index);
5240 scale($scale);
5241 disp($off);
5242 %}
5243 %}
5245 //FIXME: I think it's better to limit the immI to be 16-bit at most!
5246 // Indirect Memory Plus Long Offset Operand
5247 operand indOffset32(mRegP reg, immL32 off) %{
5248 constraint(ALLOC_IN_RC(p_reg));
5249 op_cost(20);
5250 match(AddP reg off);
5252 format %{ "[$reg + $off (32-bit)] @ indOffset32" %}
5253 interface(MEMORY_INTER) %{
5254 base($reg);
5255 index(0x0); /* NO_INDEX */
5256 scale(0x0);
5257 disp($off);
5258 %}
5259 %}
5261 // Indirect Memory Plus Index Register
5262 operand indIndex(mRegP addr, mRegL index) %{
5263 constraint(ALLOC_IN_RC(p_reg));
5264 match(AddP addr index);
5266 op_cost(20);
5267 format %{"[$addr + $index] @ indIndex" %}
5268 interface(MEMORY_INTER) %{
5269 base($addr);
5270 index($index);
5271 scale(0x0);
5272 disp(0x0);
5273 %}
5274 %}
5276 operand indirectNarrowKlass(mRegN reg)
5277 %{
5278 predicate(Universe::narrow_klass_shift() == 0);
5279 constraint(ALLOC_IN_RC(p_reg));
5280 op_cost(10);
5281 match(DecodeNKlass reg);
5283 format %{ "[$reg] @ indirectNarrowKlass" %}
5284 interface(MEMORY_INTER) %{
5285 base($reg);
5286 index(0x0);
5287 scale(0x0);
5288 disp(0x0);
5289 %}
5290 %}
5292 operand indOffset8NarrowKlass(mRegN reg, immL8 off)
5293 %{
5294 predicate(Universe::narrow_klass_shift() == 0);
5295 constraint(ALLOC_IN_RC(p_reg));
5296 op_cost(10);
5297 match(AddP (DecodeNKlass reg) off);
5299 format %{ "[$reg + $off (8-bit)] @ indOffset8NarrowKlass" %}
5300 interface(MEMORY_INTER) %{
5301 base($reg);
5302 index(0x0);
5303 scale(0x0);
5304 disp($off);
5305 %}
5306 %}
5308 operand indOffset32NarrowKlass(mRegN reg, immL32 off)
5309 %{
5310 predicate(Universe::narrow_klass_shift() == 0);
5311 constraint(ALLOC_IN_RC(p_reg));
5312 op_cost(10);
5313 match(AddP (DecodeNKlass reg) off);
5315 format %{ "[$reg + $off (32-bit)] @ indOffset32NarrowKlass" %}
5316 interface(MEMORY_INTER) %{
5317 base($reg);
5318 index(0x0);
5319 scale(0x0);
5320 disp($off);
5321 %}
5322 %}
5324 operand indIndexOffsetNarrowKlass(mRegN reg, mRegL lreg, immL32 off)
5325 %{
5326 predicate(Universe::narrow_klass_shift() == 0);
5327 constraint(ALLOC_IN_RC(p_reg));
5328 match(AddP (AddP (DecodeNKlass reg) lreg) off);
5330 op_cost(10);
5331 format %{"[$reg + $off + $lreg] @ indIndexOffsetNarrowKlass" %}
5332 interface(MEMORY_INTER) %{
5333 base($reg);
5334 index($lreg);
5335 scale(0x0);
5336 disp($off);
5337 %}
5338 %}
5340 operand indIndexNarrowKlass(mRegN reg, mRegL lreg)
5341 %{
5342 predicate(Universe::narrow_klass_shift() == 0);
5343 constraint(ALLOC_IN_RC(p_reg));
5344 match(AddP (DecodeNKlass reg) lreg);
5346 op_cost(10);
5347 format %{"[$reg + $lreg] @ indIndexNarrowKlass" %}
5348 interface(MEMORY_INTER) %{
5349 base($reg);
5350 index($lreg);
5351 scale(0x0);
5352 disp(0x0);
5353 %}
5354 %}
5356 // Indirect Memory Operand
5357 operand indirectNarrow(mRegN reg)
5358 %{
5359 predicate(Universe::narrow_oop_shift() == 0);
5360 constraint(ALLOC_IN_RC(p_reg));
5361 op_cost(10);
5362 match(DecodeN reg);
5364 format %{ "[$reg] @ indirectNarrow" %}
5365 interface(MEMORY_INTER) %{
5366 base($reg);
5367 index(0x0);
5368 scale(0x0);
5369 disp(0x0);
5370 %}
5371 %}
5373 // Indirect Memory Plus Short Offset Operand
5374 operand indOffset8Narrow(mRegN reg, immL8 off)
5375 %{
5376 predicate(Universe::narrow_oop_shift() == 0);
5377 constraint(ALLOC_IN_RC(p_reg));
5378 op_cost(10);
5379 match(AddP (DecodeN reg) off);
5381 format %{ "[$reg + $off (8-bit)] @ indOffset8Narrow" %}
5382 interface(MEMORY_INTER) %{
5383 base($reg);
5384 index(0x0);
5385 scale(0x0);
5386 disp($off);
5387 %}
5388 %}
5390 // Indirect Memory Plus Index Register Plus Offset Operand
5391 operand indIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off)
5392 %{
5393 predicate(Universe::narrow_oop_shift() == 0);
5394 constraint(ALLOC_IN_RC(p_reg));
5395 match(AddP (AddP (DecodeN reg) lreg) off);
5397 op_cost(10);
5398 format %{"[$reg + $off + $lreg] @ indIndexOffset8Narrow" %}
5399 interface(MEMORY_INTER) %{
5400 base($reg);
5401 index($lreg);
5402 scale(0x0);
5403 disp($off);
5404 %}
5405 %}
5407 //----------Load Long Memory Operands------------------------------------------
5408 // The load-long idiom will use it's address expression again after loading
5409 // the first word of the long. If the load-long destination overlaps with
5410 // registers used in the addressing expression, the 2nd half will be loaded
5411 // from a clobbered address. Fix this by requiring that load-long use
5412 // address registers that do not overlap with the load-long target.
5414 // load-long support
5415 operand load_long_RegP() %{
5416 constraint(ALLOC_IN_RC(p_reg));
5417 match(RegP);
5418 match(mRegP);
5419 op_cost(100);
5420 format %{ %}
5421 interface(REG_INTER);
5422 %}
5424 // Indirect Memory Operand Long
5425 operand load_long_indirect(load_long_RegP reg) %{
5426 constraint(ALLOC_IN_RC(p_reg));
5427 match(reg);
5429 format %{ "[$reg]" %}
5430 interface(MEMORY_INTER) %{
5431 base($reg);
5432 index(0x0);
5433 scale(0x0);
5434 disp(0x0);
5435 %}
5436 %}
5438 // Indirect Memory Plus Long Offset Operand
5439 operand load_long_indOffset32(load_long_RegP reg, immL32 off) %{
5440 match(AddP reg off);
5442 format %{ "[$reg + $off]" %}
5443 interface(MEMORY_INTER) %{
5444 base($reg);
5445 index(0x0);
5446 scale(0x0);
5447 disp($off);
5448 %}
5449 %}
5451 //----------Conditional Branch Operands----------------------------------------
5452 // Comparison Op - This is the operation of the comparison, and is limited to
5453 // the following set of codes:
5454 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5455 //
5456 // Other attributes of the comparison, such as unsignedness, are specified
5457 // by the comparison instruction that sets a condition code flags register.
5458 // That result is represented by a flags operand whose subtype is appropriate
5459 // to the unsignedness (etc.) of the comparison.
5460 //
5461 // Later, the instruction which matches both the Comparison Op (a Bool) and
5462 // the flags (produced by the Cmp) specifies the coding of the comparison op
5463 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5465 // Comparision Code
5466 operand cmpOp() %{
5467 match(Bool);
5469 format %{ "" %}
5470 interface(COND_INTER) %{
5471 equal(0x01);
5472 not_equal(0x02);
5473 greater(0x03);
5474 greater_equal(0x04);
5475 less(0x05);
5476 less_equal(0x06);
5477 overflow(0x7);
5478 no_overflow(0x8);
5479 %}
5480 %}
5483 // Comparision Code
5484 // Comparison Code, unsigned compare. Used by FP also, with
5485 // C2 (unordered) turned into GT or LT already. The other bits
5486 // C0 and C3 are turned into Carry & Zero flags.
5487 operand cmpOpU() %{
5488 match(Bool);
5490 format %{ "" %}
5491 interface(COND_INTER) %{
5492 equal(0x01);
5493 not_equal(0x02);
5494 greater(0x03);
5495 greater_equal(0x04);
5496 less(0x05);
5497 less_equal(0x06);
5498 overflow(0x7);
5499 no_overflow(0x8);
5500 %}
5501 %}
5503 /*
5504 // Comparison Code, unsigned compare. Used by FP also, with
5505 // C2 (unordered) turned into GT or LT already. The other bits
5506 // C0 and C3 are turned into Carry & Zero flags.
5507 operand cmpOpU() %{
5508 match(Bool);
5510 format %{ "" %}
5511 interface(COND_INTER) %{
5512 equal(0x4);
5513 not_equal(0x5);
5514 less(0x2);
5515 greater_equal(0x3);
5516 less_equal(0x6);
5517 greater(0x7);
5518 %}
5519 %}
5520 */
5521 /*
5522 // Comparison Code for FP conditional move
5523 operand cmpOp_fcmov() %{
5524 match(Bool);
5526 format %{ "" %}
5527 interface(COND_INTER) %{
5528 equal (0x01);
5529 not_equal (0x02);
5530 greater (0x03);
5531 greater_equal(0x04);
5532 less (0x05);
5533 less_equal (0x06);
5534 %}
5535 %}
5537 // Comparision Code used in long compares
5538 operand cmpOp_commute() %{
5539 match(Bool);
5541 format %{ "" %}
5542 interface(COND_INTER) %{
5543 equal(0x4);
5544 not_equal(0x5);
5545 less(0xF);
5546 greater_equal(0xE);
5547 less_equal(0xD);
5548 greater(0xC);
5549 %}
5550 %}
5551 */
5553 //----------Special Memory Operands--------------------------------------------
5554 // Stack Slot Operand - This operand is used for loading and storing temporary
5555 // values on the stack where a match requires a value to
5556 // flow through memory.
5557 operand stackSlotP(sRegP reg) %{
5558 constraint(ALLOC_IN_RC(stack_slots));
5559 // No match rule because this operand is only generated in matching
5560 op_cost(50);
5561 format %{ "[$reg]" %}
5562 interface(MEMORY_INTER) %{
5563 base(0x1d); // SP
5564 index(0x0); // No Index
5565 scale(0x0); // No Scale
5566 disp($reg); // Stack Offset
5567 %}
5568 %}
5570 operand stackSlotI(sRegI reg) %{
5571 constraint(ALLOC_IN_RC(stack_slots));
5572 // No match rule because this operand is only generated in matching
5573 op_cost(50);
5574 format %{ "[$reg]" %}
5575 interface(MEMORY_INTER) %{
5576 base(0x1d); // SP
5577 index(0x0); // No Index
5578 scale(0x0); // No Scale
5579 disp($reg); // Stack Offset
5580 %}
5581 %}
5583 operand stackSlotF(sRegF reg) %{
5584 constraint(ALLOC_IN_RC(stack_slots));
5585 // No match rule because this operand is only generated in matching
5586 op_cost(50);
5587 format %{ "[$reg]" %}
5588 interface(MEMORY_INTER) %{
5589 base(0x1d); // SP
5590 index(0x0); // No Index
5591 scale(0x0); // No Scale
5592 disp($reg); // Stack Offset
5593 %}
5594 %}
5596 operand stackSlotD(sRegD reg) %{
5597 constraint(ALLOC_IN_RC(stack_slots));
5598 // No match rule because this operand is only generated in matching
5599 op_cost(50);
5600 format %{ "[$reg]" %}
5601 interface(MEMORY_INTER) %{
5602 base(0x1d); // SP
5603 index(0x0); // No Index
5604 scale(0x0); // No Scale
5605 disp($reg); // Stack Offset
5606 %}
5607 %}
5609 operand stackSlotL(sRegL reg) %{
5610 constraint(ALLOC_IN_RC(stack_slots));
5611 // No match rule because this operand is only generated in matching
5612 op_cost(50);
5613 format %{ "[$reg]" %}
5614 interface(MEMORY_INTER) %{
5615 base(0x1d); // SP
5616 index(0x0); // No Index
5617 scale(0x0); // No Scale
5618 disp($reg); // Stack Offset
5619 %}
5620 %}
5623 //------------------------OPERAND CLASSES--------------------------------------
5624 //opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset );
5625 opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, indIndexScale, load_long_indirect, load_long_indOffset32, baseIndexOffset8, baseIndexOffset8_convI2L, indIndexScaleOffset8, indIndexScaleOffset8_convI2L, basePosIndexScaleOffset8, indIndexScaleOffsetNarrow, indPosIndexI2LScaleOffset8Narrow, indOffset8Narrow, indIndexOffset8Narrow);
5628 //----------PIPELINE-----------------------------------------------------------
5629 // Rules which define the behavior of the target architectures pipeline.
5631 pipeline %{
5633 //----------ATTRIBUTES---------------------------------------------------------
5634 attributes %{
5635 fixed_size_instructions; // Fixed size instructions
5636 branch_has_delay_slot; // branch have delay slot in gs2
5637 max_instructions_per_bundle = 1; // 1 instruction per bundle
5638 max_bundles_per_cycle = 4; // Up to 4 bundles per cycle
5639 bundle_unit_size=4;
5640 instruction_unit_size = 4; // An instruction is 4 bytes long
5641 instruction_fetch_unit_size = 16; // The processor fetches one line
5642 instruction_fetch_units = 1; // of 16 bytes
5644 // List of nop instructions
5645 nops( MachNop );
5646 %}
5648 //----------RESOURCES----------------------------------------------------------
5649 // Resources are the functional units available to the machine
5651 resources(D1, D2, D3, D4, DECODE = D1 | D2 | D3| D4, ALU1, ALU2, ALU = ALU1 | ALU2, FPU1, FPU2, FPU = FPU1 | FPU2, MEM, BR);
5653 //----------PIPELINE DESCRIPTION-----------------------------------------------
5654 // Pipeline Description specifies the stages in the machine's pipeline
5656 // IF: fetch
5657 // ID: decode
5658 // RD: read
5659 // CA: caculate
5660 // WB: write back
5661 // CM: commit
5663 pipe_desc(IF, ID, RD, CA, WB, CM);
5666 //----------PIPELINE CLASSES---------------------------------------------------
5667 // Pipeline Classes describe the stages in which input and output are
5668 // referenced by the hardware pipeline.
5670 //No.1 Integer ALU reg-reg operation : dst <-- reg1 op reg2
5671 pipe_class ialu_regI_regI(mRegI dst, mRegI src1, mRegI src2) %{
5672 single_instruction;
5673 src1 : RD(read);
5674 src2 : RD(read);
5675 dst : WB(write)+1;
5676 DECODE : ID;
5677 ALU : CA;
5678 %}
5680 //No.19 Integer mult operation : dst <-- reg1 mult reg2
5681 pipe_class ialu_mult(mRegI dst, mRegI src1, mRegI src2) %{
5682 src1 : RD(read);
5683 src2 : RD(read);
5684 dst : WB(write)+5;
5685 DECODE : ID;
5686 ALU2 : CA;
5687 %}
5689 pipe_class mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
5690 src1 : RD(read);
5691 src2 : RD(read);
5692 dst : WB(write)+10;
5693 DECODE : ID;
5694 ALU2 : CA;
5695 %}
5697 //No.19 Integer div operation : dst <-- reg1 div reg2
5698 pipe_class ialu_div(mRegI dst, mRegI src1, mRegI src2) %{
5699 src1 : RD(read);
5700 src2 : RD(read);
5701 dst : WB(write)+10;
5702 DECODE : ID;
5703 ALU2 : CA;
5704 %}
5706 //No.19 Integer mod operation : dst <-- reg1 mod reg2
5707 pipe_class ialu_mod(mRegI dst, mRegI src1, mRegI src2) %{
5708 instruction_count(2);
5709 src1 : RD(read);
5710 src2 : RD(read);
5711 dst : WB(write)+10;
5712 DECODE : ID;
5713 ALU2 : CA;
5714 %}
5716 //No.15 Long ALU reg-reg operation : dst <-- reg1 op reg2
5717 pipe_class ialu_regL_regL(mRegL dst, mRegL src1, mRegL src2) %{
5718 instruction_count(2);
5719 src1 : RD(read);
5720 src2 : RD(read);
5721 dst : WB(write);
5722 DECODE : ID;
5723 ALU : CA;
5724 %}
5726 //No.18 Long ALU reg-imm16 operation : dst <-- reg1 op imm16
5727 pipe_class ialu_regL_imm16(mRegL dst, mRegL src) %{
5728 instruction_count(2);
5729 src : RD(read);
5730 dst : WB(write);
5731 DECODE : ID;
5732 ALU : CA;
5733 %}
5735 //no.16 load Long from memory :
5736 pipe_class ialu_loadL(mRegL dst, memory mem) %{
5737 instruction_count(2);
5738 mem : RD(read);
5739 dst : WB(write)+5;
5740 DECODE : ID;
5741 MEM : RD;
5742 %}
5744 //No.17 Store Long to Memory :
5745 pipe_class ialu_storeL(mRegL src, memory mem) %{
5746 instruction_count(2);
5747 mem : RD(read);
5748 src : RD(read);
5749 DECODE : ID;
5750 MEM : RD;
5751 %}
5753 //No.2 Integer ALU reg-imm16 operation : dst <-- reg1 op imm16
5754 pipe_class ialu_regI_imm16(mRegI dst, mRegI src) %{
5755 single_instruction;
5756 src : RD(read);
5757 dst : WB(write);
5758 DECODE : ID;
5759 ALU : CA;
5760 %}
5762 //No.3 Integer move operation : dst <-- reg
5763 pipe_class ialu_regI_mov(mRegI dst, mRegI src) %{
5764 src : RD(read);
5765 dst : WB(write);
5766 DECODE : ID;
5767 ALU : CA;
5768 %}
5770 //No.4 No instructions : do nothing
5771 pipe_class empty( ) %{
5772 instruction_count(0);
5773 %}
5775 //No.5 UnConditional branch :
5776 pipe_class pipe_jump( label labl ) %{
5777 multiple_bundles;
5778 DECODE : ID;
5779 BR : RD;
5780 %}
5782 //No.6 ALU Conditional branch :
5783 pipe_class pipe_alu_branch(mRegI src1, mRegI src2, label labl ) %{
5784 multiple_bundles;
5785 src1 : RD(read);
5786 src2 : RD(read);
5787 DECODE : ID;
5788 BR : RD;
5789 %}
5791 //no.7 load integer from memory :
5792 pipe_class ialu_loadI(mRegI dst, memory mem) %{
5793 mem : RD(read);
5794 dst : WB(write)+3;
5795 DECODE : ID;
5796 MEM : RD;
5797 %}
5799 //No.8 Store Integer to Memory :
5800 pipe_class ialu_storeI(mRegI src, memory mem) %{
5801 mem : RD(read);
5802 src : RD(read);
5803 DECODE : ID;
5804 MEM : RD;
5805 %}
5808 //No.10 Floating FPU reg-reg operation : dst <-- reg1 op reg2
5809 pipe_class fpu_regF_regF(regF dst, regF src1, regF src2) %{
5810 src1 : RD(read);
5811 src2 : RD(read);
5812 dst : WB(write);
5813 DECODE : ID;
5814 FPU : CA;
5815 %}
5817 //No.22 Floating div operation : dst <-- reg1 div reg2
5818 pipe_class fpu_div(regF dst, regF src1, regF src2) %{
5819 src1 : RD(read);
5820 src2 : RD(read);
5821 dst : WB(write);
5822 DECODE : ID;
5823 FPU2 : CA;
5824 %}
5826 pipe_class fcvt_I2D(regD dst, mRegI src) %{
5827 src : RD(read);
5828 dst : WB(write);
5829 DECODE : ID;
5830 FPU1 : CA;
5831 %}
5833 pipe_class fcvt_D2I(mRegI dst, regD src) %{
5834 src : RD(read);
5835 dst : WB(write);
5836 DECODE : ID;
5837 FPU1 : CA;
5838 %}
5840 pipe_class pipe_mfc1(mRegI dst, regD src) %{
5841 src : RD(read);
5842 dst : WB(write);
5843 DECODE : ID;
5844 MEM : RD;
5845 %}
5847 pipe_class pipe_mtc1(regD dst, mRegI src) %{
5848 src : RD(read);
5849 dst : WB(write);
5850 DECODE : ID;
5851 MEM : RD(5);
5852 %}
5854 //No.23 Floating sqrt operation : dst <-- reg1 sqrt reg2
5855 pipe_class fpu_sqrt(regF dst, regF src1, regF src2) %{
5856 multiple_bundles;
5857 src1 : RD(read);
5858 src2 : RD(read);
5859 dst : WB(write);
5860 DECODE : ID;
5861 FPU2 : CA;
5862 %}
5864 //No.11 Load Floating from Memory :
5865 pipe_class fpu_loadF(regF dst, memory mem) %{
5866 instruction_count(1);
5867 mem : RD(read);
5868 dst : WB(write)+3;
5869 DECODE : ID;
5870 MEM : RD;
5871 %}
5873 //No.12 Store Floating to Memory :
5874 pipe_class fpu_storeF(regF src, memory mem) %{
5875 instruction_count(1);
5876 mem : RD(read);
5877 src : RD(read);
5878 DECODE : ID;
5879 MEM : RD;
5880 %}
5882 //No.13 FPU Conditional branch :
5883 pipe_class pipe_fpu_branch(regF src1, regF src2, label labl ) %{
5884 multiple_bundles;
5885 src1 : RD(read);
5886 src2 : RD(read);
5887 DECODE : ID;
5888 BR : RD;
5889 %}
5891 //No.14 Floating FPU reg operation : dst <-- op reg
5892 pipe_class fpu1_regF(regF dst, regF src) %{
5893 src : RD(read);
5894 dst : WB(write);
5895 DECODE : ID;
5896 FPU : CA;
5897 %}
5899 pipe_class long_memory_op() %{
5900 instruction_count(10); multiple_bundles; force_serialization;
5901 fixed_latency(30);
5902 %}
5904 pipe_class simple_call() %{
5905 instruction_count(10); multiple_bundles; force_serialization;
5906 fixed_latency(200);
5907 BR : RD;
5908 %}
5910 pipe_class call() %{
5911 instruction_count(10); multiple_bundles; force_serialization;
5912 fixed_latency(200);
5913 %}
5915 //FIXME:
5916 //No.9 Piple slow : for multi-instructions
5917 pipe_class pipe_slow( ) %{
5918 instruction_count(20);
5919 force_serialization;
5920 multiple_bundles;
5921 fixed_latency(50);
5922 %}
5924 %}
5928 //----------INSTRUCTIONS-------------------------------------------------------
5929 //
5930 // match -- States which machine-independent subtree may be replaced
5931 // by this instruction.
5932 // ins_cost -- The estimated cost of this instruction is used by instruction
5933 // selection to identify a minimum cost tree of machine
5934 // instructions that matches a tree of machine-independent
5935 // instructions.
5936 // format -- A string providing the disassembly for this instruction.
5937 // The value of an instruction's operand may be inserted
5938 // by referring to it with a '$' prefix.
5939 // opcode -- Three instruction opcodes may be provided. These are referred
5940 // to within an encode class as $primary, $secondary, and $tertiary
5941 // respectively. The primary opcode is commonly used to
5942 // indicate the type of machine instruction, while secondary
5943 // and tertiary are often used for prefix options or addressing
5944 // modes.
5945 // ins_encode -- A list of encode classes with parameters. The encode class
5946 // name must have been defined in an 'enc_class' specification
5947 // in the encode section of the architecture description.
5950 // Load Integer
5951 instruct loadI(mRegI dst, memory mem) %{
5952 match(Set dst (LoadI mem));
5954 ins_cost(125);
5955 format %{ "lw $dst, $mem #@loadI" %}
5956 ins_encode (load_I_enc(dst, mem));
5957 ins_pipe( ialu_loadI );
5958 %}
5960 instruct loadI_convI2L(mRegL dst, memory mem) %{
5961 match(Set dst (ConvI2L (LoadI mem)));
5963 ins_cost(125);
5964 format %{ "lw $dst, $mem #@loadI_convI2L" %}
5965 ins_encode (load_I_enc(dst, mem));
5966 ins_pipe( ialu_loadI );
5967 %}
5969 // Load Integer (32 bit signed) to Byte (8 bit signed)
5970 instruct loadI2B(mRegI dst, memory mem, immI_24 twentyfour) %{
5971 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5973 ins_cost(125);
5974 format %{ "lb $dst, $mem\t# int -> byte #@loadI2B" %}
5975 ins_encode(load_B_enc(dst, mem));
5976 ins_pipe(ialu_loadI);
5977 %}
5979 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5980 instruct loadI2UB(mRegI dst, memory mem, immI_255 mask) %{
5981 match(Set dst (AndI (LoadI mem) mask));
5983 ins_cost(125);
5984 format %{ "lbu $dst, $mem\t# int -> ubyte #@loadI2UB" %}
5985 ins_encode(load_UB_enc(dst, mem));
5986 ins_pipe(ialu_loadI);
5987 %}
5989 // Load Integer (32 bit signed) to Short (16 bit signed)
5990 instruct loadI2S(mRegI dst, memory mem, immI_16 sixteen) %{
5991 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5993 ins_cost(125);
5994 format %{ "lh $dst, $mem\t# int -> short #@loadI2S" %}
5995 ins_encode(load_S_enc(dst, mem));
5996 ins_pipe(ialu_loadI);
5997 %}
5999 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6000 instruct loadI2US(mRegI dst, memory mem, immI_65535 mask) %{
6001 match(Set dst (AndI (LoadI mem) mask));
6003 ins_cost(125);
6004 format %{ "lhu $dst, $mem\t# int -> ushort/char #@loadI2US" %}
6005 ins_encode(load_C_enc(dst, mem));
6006 ins_pipe(ialu_loadI);
6007 %}
6009 // Load Long.
6010 instruct loadL(mRegL dst, memory mem) %{
6011 // predicate(!((LoadLNode*)n)->require_atomic_access());
6012 match(Set dst (LoadL mem));
6014 ins_cost(250);
6015 format %{ "ld $dst, $mem #@loadL" %}
6016 ins_encode(load_L_enc(dst, mem));
6017 ins_pipe( ialu_loadL );
6018 %}
6020 // Load Long - UNaligned
6021 instruct loadL_unaligned(mRegL dst, memory mem) %{
6022 match(Set dst (LoadL_unaligned mem));
6024 // FIXME: Jin: Need more effective ldl/ldr
6025 ins_cost(450);
6026 format %{ "ld $dst, $mem #@loadL_unaligned\n\t" %}
6027 ins_encode(load_L_enc(dst, mem));
6028 ins_pipe( ialu_loadL );
6029 %}
6031 // Store Long
6032 instruct storeL_reg(memory mem, mRegL src) %{
6033 predicate(!((StoreLNode*)n)->require_atomic_access());
6034 match(Set mem (StoreL mem src));
6036 ins_cost(200);
6037 format %{ "sd $mem, $src #@storeL_reg\n" %}
6038 ins_encode(store_L_reg_enc(mem, src));
6039 ins_pipe( ialu_storeL );
6040 %}
6042 //FIXME:volatile! atomic!
6043 // Volatile Store Long. Must be atomic, so move it into
6044 // the FP TOS and then do a 64-bit FIST. Has to probe the
6045 // target address before the store (for null-ptr checks)
6046 // so the memory operand is used twice in the encoding.
6047 instruct storeL_reg_atomic(memory mem, mRegL src) %{
6048 predicate(((StoreLNode*)n)->require_atomic_access());
6049 match(Set mem (StoreL mem src));
6051 ins_cost(200);
6052 format %{ "sw $mem, $src #@storeL_reg_atomic\n" %}
6053 ins_encode %{
6054 Register src = as_Register($src$$reg);
6056 int base = $mem$$base;
6057 int index = $mem$$index;
6058 int scale = $mem$$scale;
6059 int disp = $mem$$disp;
6061 if( index != 0 ) {
6062 if( Assembler::is_simm16(disp) ) {
6063 if (scale == 0) {
6064 __ addu(AT, as_Register(base), as_Register(index));
6065 } else {
6066 __ dsll(AT, as_Register(index), scale);
6067 __ addu(AT, as_Register(base), AT);
6068 }
6069 __ sd(src, AT, disp);
6070 } else {
6071 if (scale == 0) {
6072 __ addu(AT, as_Register(base), as_Register(index));
6073 } else {
6074 __ dsll(AT, as_Register(index), scale);
6075 __ addu(AT, as_Register(base), AT);
6076 }
6077 __ move(T9, disp);
6078 __ addu(AT, AT, T9);
6079 __ sd(src, AT, 0);
6080 }
6081 } else {
6082 if( Assembler::is_simm16(disp) ) {
6083 __ move(AT, as_Register(base));
6084 __ sd(src, AT, disp);
6085 } else {
6086 __ move(AT, as_Register(base));
6087 __ move(T9, disp);
6088 __ addu(AT, AT, T9);
6089 __ sd(src, AT, 0);
6090 }
6091 }
6093 %}
6094 ins_pipe( ialu_storeL );
6095 %}
6097 instruct storeL_immL0(memory mem, immL0 zero) %{
6098 match(Set mem (StoreL mem zero));
6100 ins_cost(180);
6101 format %{ "sd $mem, zero #@storeL_immL0" %}
6102 ins_encode(store_L_immL0_enc(mem, zero));
6103 ins_pipe( ialu_storeL );
6104 %}
6106 instruct storeL_imm(memory mem, immL src) %{
6107 match(Set mem (StoreL mem src));
6109 ins_cost(200);
6110 format %{ "sw $mem, $src #@storeL_imm" %}
6111 ins_encode(store_L_immL_enc(mem, src));
6112 ins_pipe( ialu_storeL );
6113 %}
6115 // Load Compressed Pointer
6116 instruct loadN(mRegN dst, memory mem)
6117 %{
6118 match(Set dst (LoadN mem));
6120 ins_cost(125); // XXX
6121 format %{ "lwu $dst, $mem\t# compressed ptr @ loadN" %}
6122 //TODO: Address should be implemented
6123 /*
6124 ins_encode %{
6125 __ lwu($dst$$Register, $mem$$Address);
6126 %}
6127 */
6128 ins_encode (load_N_enc(dst, mem));
6129 ins_pipe( ialu_loadI ); // XXX
6130 %}
6132 // Load Pointer
6133 instruct loadP(mRegP dst, memory mem) %{
6134 match(Set dst (LoadP mem));
6136 ins_cost(125);
6137 format %{ "ld $dst, $mem #@loadP" %}
6138 ins_encode (load_P_enc(dst, mem));
6139 ins_pipe( ialu_loadI );
6140 %}
6142 // Load Klass Pointer
6143 instruct loadKlass(mRegP dst, memory mem) %{
6144 match(Set dst (LoadKlass mem));
6146 ins_cost(125);
6147 format %{ "MOV $dst,$mem @ loadKlass" %}
6148 ins_encode (load_P_enc(dst, mem));
6149 ins_pipe( ialu_loadI );
6150 %}
6152 // Load narrow Klass Pointer
6153 instruct loadNKlass(mRegN dst, memory mem)
6154 %{
6155 match(Set dst (LoadNKlass mem));
6157 ins_cost(125); // XXX
6158 format %{ "lwu $dst, $mem\t# compressed klass ptr @ loadNKlass" %}
6159 ins_encode (load_N_enc(dst, mem));
6160 /*
6161 ins_encode %{
6162 __ lwu($dst$$Register, $mem$$Address);
6163 %}
6164 */
6165 ins_pipe( ialu_loadI ); // XXX
6166 %}
6168 // Load Constant
6169 instruct loadConI(mRegI dst, immI src) %{
6170 match(Set dst src);
6172 ins_cost(150);
6173 format %{ "mov $dst, $src #@loadConI" %}
6174 ins_encode %{
6175 Register dst = $dst$$Register;
6176 int value = $src$$constant;
6177 __ move(dst, value);
6178 %}
6179 ins_pipe( ialu_regI_regI );
6180 %}
6182 // Load Constant 65536
6183 instruct loadConI_65536(mRegI dst, immI_65536 src) %{
6184 match(Set dst src);
6186 ins_cost(100);
6187 format %{ "mov $dst, 65536 #@loadConI_65536" %}
6188 ins_encode %{
6189 Register dst = $dst$$Register;
6191 __ lui(dst, 1);
6192 %}
6193 ins_pipe( ialu_regI_regI );
6194 %}
6196 instruct loadConL_set64(mRegL dst, immL src) %{
6197 match(Set dst src);
6198 ins_cost(120);
6199 format %{ "li $dst, $src @ loadConL_set64" %}
6200 ins_encode %{
6201 __ set64($dst$$Register, $src$$constant);
6202 %}
6203 ins_pipe(ialu_regL_regL);
6204 %}
6206 /*
6207 // Load long value from constant table (predicated by immL_expensive).
6208 instruct loadConL_load(mRegL dst, immL_expensive src) %{
6209 match(Set dst src);
6210 ins_cost(150);
6211 format %{ "ld $dst, $constantoffset[$constanttablebase] # load long $src from table @ loadConL_ldx" %}
6212 ins_encode %{
6213 int con_offset = $constantoffset($src);
6215 if (Assembler::is_simm16(con_offset)) {
6216 __ ld($dst$$Register, $constanttablebase, con_offset);
6217 } else {
6218 __ set64(AT, con_offset);
6219 if (UseLoongsonISA) {
6220 __ gsldx($dst$$Register, $constanttablebase, AT, 0);
6221 } else {
6222 __ daddu(AT, $constanttablebase, AT);
6223 __ ld($dst$$Register, AT, 0);
6224 }
6225 }
6226 %}
6227 ins_pipe(ialu_loadI);
6228 %}
6229 */
6231 instruct loadConL16(mRegL dst, immL16 src) %{
6232 match(Set dst src);
6233 ins_cost(105);
6234 format %{ "mov $dst, $src #@loadConL16" %}
6235 ins_encode %{
6236 Register dst_reg = as_Register($dst$$reg);
6237 int value = $src$$constant;
6238 __ daddiu(dst_reg, R0, value);
6239 %}
6240 ins_pipe( ialu_regL_regL );
6241 %}
6244 instruct loadConL0(mRegL dst, immL0 src) %{
6245 match(Set dst src);
6246 ins_cost(100);
6247 format %{ "mov $dst, zero #@loadConL0" %}
6248 ins_encode %{
6249 Register dst_reg = as_Register($dst$$reg);
6250 __ daddu(dst_reg, R0, R0);
6251 %}
6252 ins_pipe( ialu_regL_regL );
6253 %}
6255 // Load Range
6256 instruct loadRange(mRegI dst, memory mem) %{
6257 match(Set dst (LoadRange mem));
6259 ins_cost(125);
6260 format %{ "MOV $dst,$mem @ loadRange" %}
6261 ins_encode(load_I_enc(dst, mem));
6262 ins_pipe( ialu_loadI );
6263 %}
6266 instruct storeP(memory mem, mRegP src ) %{
6267 match(Set mem (StoreP mem src));
6269 ins_cost(125);
6270 format %{ "sd $src, $mem #@storeP" %}
6271 ins_encode(store_P_reg_enc(mem, src));
6272 ins_pipe( ialu_storeI );
6273 %}
6275 /*
6276 [Ref: loadConP]
6278 Error:
6279 0x2d4b6d40: lui t9, 0x4f <--- handle
6280 0x2d4b6d44: addiu t9, t9, 0xffff808c
6281 0x2d4b6d48: sw t9, 0x4(s2)
6283 OK:
6284 0x2cc5ed40: lui t9, 0x336a <--- klass
6285 0x2cc5ed44: addiu t9, t9, 0x5a10
6286 0x2cc5ed48: sw t9, 0x4(s2)
6287 */
6288 // Store Pointer Immediate; null pointers or constant oops that do not
6289 // need card-mark barriers.
6291 // Store NULL Pointer, mark word, or other simple pointer constant.
6292 instruct storeImmP(memory mem, immP31 src) %{
6293 match(Set mem (StoreP mem src));
6295 ins_cost(150);
6296 format %{ "mov $mem, $src #@storeImmP" %}
6297 ins_encode(store_P_immP_enc(mem, src));
6298 ins_pipe( ialu_storeI );
6299 %}
6301 // Store Byte Immediate
6302 instruct storeImmB(memory mem, immI8 src) %{
6303 match(Set mem (StoreB mem src));
6305 ins_cost(150);
6306 format %{ "movb $mem, $src #@storeImmB" %}
6307 ins_encode(store_B_immI_enc(mem, src));
6308 ins_pipe( ialu_storeI );
6309 %}
6311 // Store Compressed Pointer
6312 instruct storeN(memory mem, mRegN src)
6313 %{
6314 match(Set mem (StoreN mem src));
6316 ins_cost(125); // XXX
6317 format %{ "sw $mem, $src\t# compressed ptr @ storeN" %}
6318 ins_encode(store_N_reg_enc(mem, src));
6319 ins_pipe( ialu_storeI );
6320 %}
6322 instruct storeNKlass(memory mem, mRegN src)
6323 %{
6324 match(Set mem (StoreNKlass mem src));
6326 ins_cost(125); // XXX
6327 format %{ "sw $mem, $src\t# compressed klass ptr @ storeNKlass" %}
6328 ins_encode(store_N_reg_enc(mem, src));
6329 ins_pipe( ialu_storeI );
6330 %}
6332 instruct storeImmN0(memory mem, immN0 zero)
6333 %{
6334 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6335 match(Set mem (StoreN mem zero));
6337 ins_cost(125); // XXX
6338 format %{ "storeN0 $mem, R12\t# compressed ptr" %}
6339 ins_encode(storeImmN0_enc(mem, zero));
6340 ins_pipe( ialu_storeI );
6341 %}
6343 instruct storeImmN(memory mem, immN src)
6344 %{
6345 match(Set mem (StoreN mem src));
6347 ins_cost(150); // XXX
6348 format %{ "storeImmN $mem, $src\t# compressed ptr @ storeImmN" %}
6349 ins_encode(storeImmN_enc(mem, src));
6350 ins_pipe( ialu_storeI );
6351 %}
6353 instruct storeImmNKlass(memory mem, immNKlass src)
6354 %{
6355 match(Set mem (StoreNKlass mem src));
6357 ins_cost(150); // XXX
6358 format %{ "sw $mem, $src\t# compressed klass ptr @ storeImmNKlass" %}
6359 ins_encode(storeImmNKlass_enc(mem, src));
6360 ins_pipe( ialu_storeI );
6361 %}
6363 // Store Byte
6364 instruct storeB(memory mem, mRegI src) %{
6365 match(Set mem (StoreB mem src));
6367 ins_cost(125);
6368 format %{ "sb $src, $mem #@storeB" %}
6369 ins_encode(store_B_reg_enc(mem, src));
6370 ins_pipe( ialu_storeI );
6371 %}
6373 // Load Byte (8bit signed)
6374 instruct loadB(mRegI dst, memory mem) %{
6375 match(Set dst (LoadB mem));
6377 ins_cost(125);
6378 format %{ "lb $dst, $mem #@loadB" %}
6379 ins_encode(load_B_enc(dst, mem));
6380 ins_pipe( ialu_loadI );
6381 %}
6383 instruct loadB_convI2L(mRegL dst, memory mem) %{
6384 match(Set dst (ConvI2L (LoadB mem)));
6386 ins_cost(125);
6387 format %{ "lb $dst, $mem #@loadB_convI2L" %}
6388 ins_encode(load_B_enc(dst, mem));
6389 ins_pipe( ialu_loadI );
6390 %}
6392 // Load Byte (8bit UNsigned)
6393 instruct loadUB(mRegI dst, memory mem) %{
6394 match(Set dst (LoadUB mem));
6396 ins_cost(125);
6397 format %{ "lbu $dst, $mem #@loadUB" %}
6398 ins_encode(load_UB_enc(dst, mem));
6399 ins_pipe( ialu_loadI );
6400 %}
6402 instruct loadUB_convI2L(mRegL dst, memory mem) %{
6403 match(Set dst (ConvI2L (LoadUB mem)));
6405 ins_cost(125);
6406 format %{ "lbu $dst, $mem #@loadUB_convI2L" %}
6407 ins_encode(load_UB_enc(dst, mem));
6408 ins_pipe( ialu_loadI );
6409 %}
6411 // Load Short (16bit signed)
6412 instruct loadS(mRegI dst, memory mem) %{
6413 match(Set dst (LoadS mem));
6415 ins_cost(125);
6416 format %{ "lh $dst, $mem #@loadS" %}
6417 ins_encode(load_S_enc(dst, mem));
6418 ins_pipe( ialu_loadI );
6419 %}
6421 // Load Short (16 bit signed) to Byte (8 bit signed)
6422 instruct loadS2B(mRegI dst, memory mem, immI_24 twentyfour) %{
6423 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6425 ins_cost(125);
6426 format %{ "lb $dst, $mem\t# short -> byte #@loadS2B" %}
6427 ins_encode(load_B_enc(dst, mem));
6428 ins_pipe(ialu_loadI);
6429 %}
6431 instruct loadS_convI2L(mRegL dst, memory mem) %{
6432 match(Set dst (ConvI2L (LoadS mem)));
6434 ins_cost(125);
6435 format %{ "lh $dst, $mem #@loadS_convI2L" %}
6436 ins_encode(load_S_enc(dst, mem));
6437 ins_pipe( ialu_loadI );
6438 %}
6440 // Store Integer Immediate
6441 instruct storeImmI(memory mem, immI src) %{
6442 match(Set mem (StoreI mem src));
6444 ins_cost(150);
6445 format %{ "mov $mem, $src #@storeImmI" %}
6446 ins_encode(store_I_immI_enc(mem, src));
6447 ins_pipe( ialu_storeI );
6448 %}
6450 // Store Integer
6451 instruct storeI(memory mem, mRegI src) %{
6452 match(Set mem (StoreI mem src));
6454 ins_cost(125);
6455 format %{ "sw $mem, $src #@storeI" %}
6456 ins_encode(store_I_reg_enc(mem, src));
6457 ins_pipe( ialu_storeI );
6458 %}
6460 instruct storeI_convL2I(memory mem, mRegL src) %{
6461 match(Set mem (StoreI mem (ConvL2I src)));
6463 ins_cost(125);
6464 format %{ "sw $mem, $src #@storeI_convL2I" %}
6465 ins_encode(store_I_reg_enc(mem, src));
6466 ins_pipe( ialu_storeI );
6467 %}
6469 // Load Float
6470 instruct loadF(regF dst, memory mem) %{
6471 match(Set dst (LoadF mem));
6473 ins_cost(150);
6474 format %{ "loadF $dst, $mem #@loadF" %}
6475 ins_encode(load_F_enc(dst, mem));
6476 ins_pipe( ialu_loadI );
6477 %}
6479 instruct loadConP_general(mRegP dst, immP src) %{
6480 match(Set dst src);
6482 ins_cost(120);
6483 format %{ "li $dst, $src #@loadConP_general" %}
6485 ins_encode %{
6486 Register dst = $dst$$Register;
6487 long* value = (long*)$src$$constant;
6488 bool is_need_reloc = $src->constant_reloc() != relocInfo::none;
6490 /* During GC, klassOop may be moved to new position in the heap.
6491 * It must be relocated.
6492 * Refer: [c1_LIRAssembler_mips.cpp] jobject2reg()
6493 */
6494 if (is_need_reloc) {
6495 if($src->constant_reloc() == relocInfo::metadata_type){
6496 int klass_index = __ oop_recorder()->find_index((Klass*)value);
6497 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6499 __ relocate(rspec);
6500 __ li48(dst, (long)value);
6501 }
6503 if($src->constant_reloc() == relocInfo::oop_type){
6504 int oop_index = __ oop_recorder()->find_index((jobject)value);
6505 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6507 __ relocate(rspec);
6508 __ li48(dst, (long)value);
6509 }
6510 } else {
6511 __ set64(dst, (long)value);
6512 }
6513 %}
6515 ins_pipe( ialu_regI_regI );
6516 %}
6518 /*
6519 instruct loadConP_load(mRegP dst, immP_load src) %{
6520 match(Set dst src);
6522 ins_cost(100);
6523 format %{ "ld $dst, [$constanttablebase + $constantoffset] load from constant table: ptr=$src @ loadConP_load" %}
6525 ins_encode %{
6527 int con_offset = $constantoffset($src);
6529 if (Assembler::is_simm16(con_offset)) {
6530 __ ld($dst$$Register, $constanttablebase, con_offset);
6531 } else {
6532 __ set64(AT, con_offset);
6533 if (UseLoongsonISA) {
6534 __ gsldx($dst$$Register, $constanttablebase, AT, 0);
6535 } else {
6536 __ daddu(AT, $constanttablebase, AT);
6537 __ ld($dst$$Register, AT, 0);
6538 }
6539 }
6540 %}
6542 ins_pipe(ialu_loadI);
6543 %}
6544 */
6546 instruct loadConP_no_oop_cheap(mRegP dst, immP_no_oop_cheap src) %{
6547 match(Set dst src);
6549 ins_cost(80);
6550 format %{ "li $dst, $src @ loadConP_no_oop_cheap" %}
6552 ins_encode %{
6553 __ set64($dst$$Register, $src$$constant);
6554 %}
6556 ins_pipe(ialu_regI_regI);
6557 %}
6560 instruct loadConP_poll(mRegP dst, immP_poll src) %{
6561 match(Set dst src);
6563 ins_cost(50);
6564 format %{ "li $dst, $src #@loadConP_poll" %}
6566 ins_encode %{
6567 Register dst = $dst$$Register;
6568 intptr_t value = (intptr_t)$src$$constant;
6570 __ set64(dst, (jlong)value);
6571 %}
6573 ins_pipe( ialu_regI_regI );
6574 %}
6576 instruct loadConP0(mRegP dst, immP0 src)
6577 %{
6578 match(Set dst src);
6580 ins_cost(50);
6581 format %{ "mov $dst, R0\t# ptr" %}
6582 ins_encode %{
6583 Register dst_reg = $dst$$Register;
6584 __ daddu(dst_reg, R0, R0);
6585 %}
6586 ins_pipe( ialu_regI_regI );
6587 %}
6589 instruct loadConN0(mRegN dst, immN0 src) %{
6590 match(Set dst src);
6591 format %{ "move $dst, R0\t# compressed NULL ptr" %}
6592 ins_encode %{
6593 __ move($dst$$Register, R0);
6594 %}
6595 ins_pipe( ialu_regI_regI );
6596 %}
6598 instruct loadConN(mRegN dst, immN src) %{
6599 match(Set dst src);
6601 ins_cost(125);
6602 format %{ "li $dst, $src\t# compressed ptr @ loadConN" %}
6603 ins_encode %{
6604 address con = (address)$src$$constant;
6605 if (con == NULL) {
6606 ShouldNotReachHere();
6607 } else {
6608 assert (UseCompressedOops, "should only be used for compressed headers");
6609 assert (Universe::heap() != NULL, "java heap should be initialized");
6610 assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6612 Register dst = $dst$$Register;
6613 long* value = (long*)$src$$constant;
6614 int oop_index = __ oop_recorder()->find_index((jobject)value);
6615 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6616 if(rspec.type()!=relocInfo::none){
6617 __ relocate(rspec, Assembler::narrow_oop_operand);
6618 __ li48(dst, oop_index);
6619 } else {
6620 __ set64(dst, oop_index);
6621 }
6622 }
6623 %}
6624 ins_pipe( ialu_regI_regI ); // XXX
6625 %}
6627 instruct loadConNKlass(mRegN dst, immNKlass src) %{
6628 match(Set dst src);
6630 ins_cost(125);
6631 format %{ "li $dst, $src\t# compressed klass ptr @ loadConNKlass" %}
6632 ins_encode %{
6633 address con = (address)$src$$constant;
6634 if (con == NULL) {
6635 ShouldNotReachHere();
6636 } else {
6637 Register dst = $dst$$Register;
6638 long* value = (long*)$src$$constant;
6640 int klass_index = __ oop_recorder()->find_index((Klass*)value);
6641 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6642 long narrowp = (long)Klass::encode_klass((Klass*)value);
6644 if(rspec.type()!=relocInfo::none){
6645 __ relocate(rspec, Assembler::narrow_oop_operand);
6646 __ li48(dst, narrowp);
6647 } else {
6648 __ set64(dst, narrowp);
6649 }
6650 }
6651 %}
6652 ins_pipe( ialu_regI_regI ); // XXX
6653 %}
6655 //FIXME
6656 // Tail Call; Jump from runtime stub to Java code.
6657 // Also known as an 'interprocedural jump'.
6658 // Target of jump will eventually return to caller.
6659 // TailJump below removes the return address.
6660 instruct TailCalljmpInd(mRegP jump_target, mRegP method_oop) %{
6661 match(TailCall jump_target method_oop );
6662 ins_cost(300);
6663 format %{ "JMP $jump_target \t# @TailCalljmpInd" %}
6665 ins_encode %{
6666 Register target = $jump_target$$Register;
6667 Register oop = $method_oop$$Register;
6669 /* 2012/10/12 Jin: RA will be used in generate_forward_exception() */
6670 __ push(RA);
6672 __ move(S3, oop);
6673 __ jr(target);
6674 __ nop();
6675 %}
6677 ins_pipe( pipe_jump );
6678 %}
6680 // Create exception oop: created by stack-crawling runtime code.
6681 // Created exception is now available to this handler, and is setup
6682 // just prior to jumping to this handler. No code emitted.
6683 instruct CreateException( a0_RegP ex_oop )
6684 %{
6685 match(Set ex_oop (CreateEx));
6687 // use the following format syntax
6688 format %{ "# exception oop is in A0; no code emitted @CreateException" %}
6689 ins_encode %{
6690 /* Jin: X86 leaves this function empty */
6691 __ block_comment("CreateException is empty in X86/MIPS");
6692 %}
6693 ins_pipe( empty );
6694 // ins_pipe( pipe_jump );
6695 %}
6698 /* 2012/9/14 Jin: The mechanism of exception handling is clear now.
6700 - Common try/catch:
6701 2012/9/14 Jin: [stubGenerator_mips.cpp] generate_forward_exception()
6702 |- V0, V1 are created
6703 |- T9 <= SharedRuntime::exception_handler_for_return_address
6704 `- jr T9
6705 `- the caller's exception_handler
6706 `- jr OptoRuntime::exception_blob
6707 `- here
6708 - Rethrow(e.g. 'unwind'):
6709 * The callee:
6710 |- an exception is triggered during execution
6711 `- exits the callee method through RethrowException node
6712 |- The callee pushes exception_oop(T0) and exception_pc(RA)
6713 `- The callee jumps to OptoRuntime::rethrow_stub()
6714 * In OptoRuntime::rethrow_stub:
6715 |- The VM calls _rethrow_Java to determine the return address in the caller method
6716 `- exits the stub with tailjmpInd
6717 |- pops exception_oop(V0) and exception_pc(V1)
6718 `- jumps to the return address(usually an exception_handler)
6719 * The caller:
6720 `- continues processing the exception_blob with V0/V1
6721 */
6723 /*
6724 Disassembling OptoRuntime::rethrow_stub()
6726 ; locals
6727 0x2d3bf320: addiu sp, sp, 0xfffffff8
6728 0x2d3bf324: sw ra, 0x4(sp)
6729 0x2d3bf328: sw fp, 0x0(sp)
6730 0x2d3bf32c: addu fp, sp, zero
6731 0x2d3bf330: addiu sp, sp, 0xfffffff0
6732 0x2d3bf334: sw ra, 0x8(sp)
6733 0x2d3bf338: sw t0, 0x4(sp)
6734 0x2d3bf33c: sw sp, 0x0(sp)
6736 ; get_thread(S2)
6737 0x2d3bf340: addu s2, sp, zero
6738 0x2d3bf344: srl s2, s2, 12
6739 0x2d3bf348: sll s2, s2, 2
6740 0x2d3bf34c: lui at, 0x2c85
6741 0x2d3bf350: addu at, at, s2
6742 0x2d3bf354: lw s2, 0xffffcc80(at)
6744 0x2d3bf358: lw s0, 0x0(sp)
6745 0x2d3bf35c: sw s0, 0x118(s2) // last_sp -> threa
6746 0x2d3bf360: sw s2, 0xc(sp)
6748 ; OptoRuntime::rethrow_C(oopDesc* exception, JavaThread* thread, address ret_pc)
6749 0x2d3bf364: lw a0, 0x4(sp)
6750 0x2d3bf368: lw a1, 0xc(sp)
6751 0x2d3bf36c: lw a2, 0x8(sp)
6752 ;; Java_To_Runtime
6753 0x2d3bf370: lui t9, 0x2c34
6754 0x2d3bf374: addiu t9, t9, 0xffff8a48
6755 0x2d3bf378: jalr t9
6756 0x2d3bf37c: nop
6758 0x2d3bf380: addu s3, v0, zero ; S3: SharedRuntime::raw_exception_handler_for_return_address()
6760 0x2d3bf384: lw s0, 0xc(sp)
6761 0x2d3bf388: sw zero, 0x118(s0)
6762 0x2d3bf38c: sw zero, 0x11c(s0)
6763 0x2d3bf390: lw s1, 0x144(s0) ; ex_oop: S1
6764 0x2d3bf394: addu s2, s0, zero
6765 0x2d3bf398: sw zero, 0x144(s2)
6766 0x2d3bf39c: lw s0, 0x4(s2)
6767 0x2d3bf3a0: addiu s4, zero, 0x0
6768 0x2d3bf3a4: bne s0, s4, 0x2d3bf3d4
6769 0x2d3bf3a8: nop
6770 0x2d3bf3ac: addiu sp, sp, 0x10
6771 0x2d3bf3b0: addiu sp, sp, 0x8
6772 0x2d3bf3b4: lw ra, 0xfffffffc(sp)
6773 0x2d3bf3b8: lw fp, 0xfffffff8(sp)
6774 0x2d3bf3bc: lui at, 0x2b48
6775 0x2d3bf3c0: lw at, 0x100(at)
6777 ; tailjmpInd: Restores exception_oop & exception_pc
6778 0x2d3bf3c4: addu v1, ra, zero
6779 0x2d3bf3c8: addu v0, s1, zero
6780 0x2d3bf3cc: jr s3
6781 0x2d3bf3d0: nop
6782 ; Exception:
6783 0x2d3bf3d4: lui s1, 0x2cc8 ; generate_forward_exception()
6784 0x2d3bf3d8: addiu s1, s1, 0x40
6785 0x2d3bf3dc: addiu s2, zero, 0x0
6786 0x2d3bf3e0: addiu sp, sp, 0x10
6787 0x2d3bf3e4: addiu sp, sp, 0x8
6788 0x2d3bf3e8: lw ra, 0xfffffffc(sp)
6789 0x2d3bf3ec: lw fp, 0xfffffff8(sp)
6790 0x2d3bf3f0: lui at, 0x2b48
6791 0x2d3bf3f4: lw at, 0x100(at)
6792 ; TailCalljmpInd
6793 __ push(RA); ; to be used in generate_forward_exception()
6794 0x2d3bf3f8: addu t7, s2, zero
6795 0x2d3bf3fc: jr s1
6796 0x2d3bf400: nop
6797 */
6798 // Rethrow exception:
6799 // The exception oop will come in the first argument position.
6800 // Then JUMP (not call) to the rethrow stub code.
6801 instruct RethrowException()
6802 %{
6803 match(Rethrow);
6805 // use the following format syntax
6806 format %{ "JMP rethrow_stub #@RethrowException" %}
6807 ins_encode %{
6808 __ block_comment("@ RethrowException");
6810 cbuf.set_insts_mark();
6811 cbuf.relocate(cbuf.insts_mark(), runtime_call_Relocation::spec());
6813 // call OptoRuntime::rethrow_stub to get the exception handler in parent method
6814 __ li(T9, OptoRuntime::rethrow_stub());
6815 __ jr(T9);
6816 __ nop();
6817 %}
6818 ins_pipe( pipe_jump );
6819 %}
6821 instruct branchConP_zero(cmpOpU cmp, mRegP op1, immP0 zero, label labl) %{
6822 match(If cmp (CmpP op1 zero));
6823 effect(USE labl);
6825 ins_cost(180);
6826 format %{ "b$cmp $op1, R0, $labl #@branchConP_zero" %}
6828 ins_encode %{
6829 Register op1 = $op1$$Register;
6830 Register op2 = R0;
6831 Label &L = *($labl$$label);
6832 int flag = $cmp$$cmpcode;
6834 switch(flag)
6835 {
6836 case 0x01: //equal
6837 if (&L)
6838 __ beq(op1, op2, L);
6839 else
6840 __ beq(op1, op2, (int)0);
6841 break;
6842 case 0x02: //not_equal
6843 if (&L)
6844 __ bne(op1, op2, L);
6845 else
6846 __ bne(op1, op2, (int)0);
6847 break;
6848 /*
6849 case 0x03: //above
6850 __ sltu(AT, op2, op1);
6851 if(&L)
6852 __ bne(R0, AT, L);
6853 else
6854 __ bne(R0, AT, (int)0);
6855 break;
6856 case 0x04: //above_equal
6857 __ sltu(AT, op1, op2);
6858 if(&L)
6859 __ beq(AT, R0, L);
6860 else
6861 __ beq(AT, R0, (int)0);
6862 break;
6863 case 0x05: //below
6864 __ sltu(AT, op1, op2);
6865 if(&L)
6866 __ bne(R0, AT, L);
6867 else
6868 __ bne(R0, AT, (int)0);
6869 break;
6870 case 0x06: //below_equal
6871 __ sltu(AT, op2, op1);
6872 if(&L)
6873 __ beq(AT, R0, L);
6874 else
6875 __ beq(AT, R0, (int)0);
6876 break;
6877 */
6878 default:
6879 Unimplemented();
6880 }
6881 __ nop();
6882 %}
6884 ins_pc_relative(1);
6885 ins_pipe( pipe_alu_branch );
6886 %}
6889 instruct branchConP(cmpOpU cmp, mRegP op1, mRegP op2, label labl) %{
6890 match(If cmp (CmpP op1 op2));
6891 // predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
6892 effect(USE labl);
6894 ins_cost(200);
6895 format %{ "b$cmp $op1, $op2, $labl #@branchConP" %}
6897 ins_encode %{
6898 Register op1 = $op1$$Register;
6899 Register op2 = $op2$$Register;
6900 Label &L = *($labl$$label);
6901 int flag = $cmp$$cmpcode;
6903 switch(flag)
6904 {
6905 case 0x01: //equal
6906 if (&L)
6907 __ beq(op1, op2, L);
6908 else
6909 __ beq(op1, op2, (int)0);
6910 break;
6911 case 0x02: //not_equal
6912 if (&L)
6913 __ bne(op1, op2, L);
6914 else
6915 __ bne(op1, op2, (int)0);
6916 break;
6917 case 0x03: //above
6918 __ sltu(AT, op2, op1);
6919 if(&L)
6920 __ bne(R0, AT, L);
6921 else
6922 __ bne(R0, AT, (int)0);
6923 break;
6924 case 0x04: //above_equal
6925 __ sltu(AT, op1, op2);
6926 if(&L)
6927 __ beq(AT, R0, L);
6928 else
6929 __ beq(AT, R0, (int)0);
6930 break;
6931 case 0x05: //below
6932 __ sltu(AT, op1, op2);
6933 if(&L)
6934 __ bne(R0, AT, L);
6935 else
6936 __ bne(R0, AT, (int)0);
6937 break;
6938 case 0x06: //below_equal
6939 __ sltu(AT, op2, op1);
6940 if(&L)
6941 __ beq(AT, R0, L);
6942 else
6943 __ beq(AT, R0, (int)0);
6944 break;
6945 default:
6946 Unimplemented();
6947 }
6948 __ nop();
6949 %}
6951 ins_pc_relative(1);
6952 ins_pipe( pipe_alu_branch );
6953 %}
6955 instruct cmpN_null_branch(cmpOp cmp, mRegN op1, immN0 null, label labl) %{
6956 match(If cmp (CmpN op1 null));
6957 effect(USE labl);
6959 ins_cost(180);
6960 format %{ "CMP $op1,0\t! compressed ptr\n\t"
6961 "BP$cmp $labl @ cmpN_null_branch" %}
6962 ins_encode %{
6963 Register op1 = $op1$$Register;
6964 Register op2 = R0;
6965 Label &L = *($labl$$label);
6966 int flag = $cmp$$cmpcode;
6968 switch(flag)
6969 {
6970 case 0x01: //equal
6971 if (&L)
6972 __ beq(op1, op2, L);
6973 else
6974 __ beq(op1, op2, (int)0);
6975 break;
6976 case 0x02: //not_equal
6977 if (&L)
6978 __ bne(op1, op2, L);
6979 else
6980 __ bne(op1, op2, (int)0);
6981 break;
6982 default:
6983 Unimplemented();
6984 }
6985 __ nop();
6986 %}
6987 //TODO: pipe_branchP or create pipe_branchN LEE
6988 ins_pc_relative(1);
6989 ins_pipe( pipe_alu_branch );
6990 %}
6992 instruct cmpN_reg_branch(cmpOp cmp, mRegN op1, mRegN op2, label labl) %{
6993 match(If cmp (CmpN op1 op2));
6994 effect(USE labl);
6996 ins_cost(180);
6997 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
6998 "BP$cmp $labl" %}
6999 ins_encode %{
7000 Register op1_reg = $op1$$Register;
7001 Register op2_reg = $op2$$Register;
7002 Label &L = *($labl$$label);
7003 int flag = $cmp$$cmpcode;
7005 switch(flag)
7006 {
7007 case 0x01: //equal
7008 if (&L)
7009 __ beq(op1_reg, op2_reg, L);
7010 else
7011 __ beq(op1_reg, op2_reg, (int)0);
7012 break;
7013 case 0x02: //not_equal
7014 if (&L)
7015 __ bne(op1_reg, op2_reg, L);
7016 else
7017 __ bne(op1_reg, op2_reg, (int)0);
7018 break;
7019 case 0x03: //above
7020 __ sltu(AT, op2_reg, op1_reg);
7021 if(&L)
7022 __ bne(R0, AT, L);
7023 else
7024 __ bne(R0, AT, (int)0);
7025 break;
7026 case 0x04: //above_equal
7027 __ sltu(AT, op1_reg, op2_reg);
7028 if(&L)
7029 __ beq(AT, R0, L);
7030 else
7031 __ beq(AT, R0, (int)0);
7032 break;
7033 case 0x05: //below
7034 __ sltu(AT, op1_reg, op2_reg);
7035 if(&L)
7036 __ bne(R0, AT, L);
7037 else
7038 __ bne(R0, AT, (int)0);
7039 break;
7040 case 0x06: //below_equal
7041 __ sltu(AT, op2_reg, op1_reg);
7042 if(&L)
7043 __ beq(AT, R0, L);
7044 else
7045 __ beq(AT, R0, (int)0);
7046 break;
7047 default:
7048 Unimplemented();
7049 }
7050 __ nop();
7051 %}
7052 ins_pc_relative(1);
7053 ins_pipe( pipe_alu_branch );
7054 %}
7056 instruct branchConIU_reg_reg(cmpOpU cmp, mRegI src1, mRegI src2, label labl) %{
7057 match( If cmp (CmpU src1 src2) );
7058 effect(USE labl);
7059 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_reg" %}
7061 ins_encode %{
7062 Register op1 = $src1$$Register;
7063 Register op2 = $src2$$Register;
7064 Label &L = *($labl$$label);
7065 int flag = $cmp$$cmpcode;
7067 switch(flag)
7068 {
7069 case 0x01: //equal
7070 if (&L)
7071 __ beq(op1, op2, L);
7072 else
7073 __ beq(op1, op2, (int)0);
7074 break;
7075 case 0x02: //not_equal
7076 if (&L)
7077 __ bne(op1, op2, L);
7078 else
7079 __ bne(op1, op2, (int)0);
7080 break;
7081 case 0x03: //above
7082 __ sltu(AT, op2, op1);
7083 if(&L)
7084 __ bne(AT, R0, L);
7085 else
7086 __ bne(AT, R0, (int)0);
7087 break;
7088 case 0x04: //above_equal
7089 __ sltu(AT, op1, op2);
7090 if(&L)
7091 __ beq(AT, R0, L);
7092 else
7093 __ beq(AT, R0, (int)0);
7094 break;
7095 case 0x05: //below
7096 __ sltu(AT, op1, op2);
7097 if(&L)
7098 __ bne(AT, R0, L);
7099 else
7100 __ bne(AT, R0, (int)0);
7101 break;
7102 case 0x06: //below_equal
7103 __ sltu(AT, op2, op1);
7104 if(&L)
7105 __ beq(AT, R0, L);
7106 else
7107 __ beq(AT, R0, (int)0);
7108 break;
7109 default:
7110 Unimplemented();
7111 }
7112 __ nop();
7113 %}
7115 ins_pc_relative(1);
7116 ins_pipe( pipe_alu_branch );
7117 %}
7120 instruct branchConIU_reg_imm(cmpOpU cmp, mRegI src1, immI src2, label labl) %{
7121 match( If cmp (CmpU src1 src2) );
7122 effect(USE labl);
7123 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_imm" %}
7125 ins_encode %{
7126 Register op1 = $src1$$Register;
7127 int val = $src2$$constant;
7128 Label &L = *($labl$$label);
7129 int flag = $cmp$$cmpcode;
7131 __ move(AT, val);
7132 switch(flag)
7133 {
7134 case 0x01: //equal
7135 if (&L)
7136 __ beq(op1, AT, L);
7137 else
7138 __ beq(op1, AT, (int)0);
7139 break;
7140 case 0x02: //not_equal
7141 if (&L)
7142 __ bne(op1, AT, L);
7143 else
7144 __ bne(op1, AT, (int)0);
7145 break;
7146 case 0x03: //above
7147 __ sltu(AT, AT, op1);
7148 if(&L)
7149 __ bne(R0, AT, L);
7150 else
7151 __ bne(R0, AT, (int)0);
7152 break;
7153 case 0x04: //above_equal
7154 __ sltu(AT, op1, AT);
7155 if(&L)
7156 __ beq(AT, R0, L);
7157 else
7158 __ beq(AT, R0, (int)0);
7159 break;
7160 case 0x05: //below
7161 __ sltu(AT, op1, AT);
7162 if(&L)
7163 __ bne(R0, AT, L);
7164 else
7165 __ bne(R0, AT, (int)0);
7166 break;
7167 case 0x06: //below_equal
7168 __ sltu(AT, AT, op1);
7169 if(&L)
7170 __ beq(AT, R0, L);
7171 else
7172 __ beq(AT, R0, (int)0);
7173 break;
7174 default:
7175 Unimplemented();
7176 }
7177 __ nop();
7178 %}
7180 ins_pc_relative(1);
7181 ins_pipe( pipe_alu_branch );
7182 %}
7184 instruct branchConI_reg_reg(cmpOp cmp, mRegI src1, mRegI src2, label labl) %{
7185 match( If cmp (CmpI src1 src2) );
7186 effect(USE labl);
7187 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_reg" %}
7189 ins_encode %{
7190 Register op1 = $src1$$Register;
7191 Register op2 = $src2$$Register;
7192 Label &L = *($labl$$label);
7193 int flag = $cmp$$cmpcode;
7195 switch(flag)
7196 {
7197 case 0x01: //equal
7198 if (&L)
7199 __ beq(op1, op2, L);
7200 else
7201 __ beq(op1, op2, (int)0);
7202 break;
7203 case 0x02: //not_equal
7204 if (&L)
7205 __ bne(op1, op2, L);
7206 else
7207 __ bne(op1, op2, (int)0);
7208 break;
7209 case 0x03: //above
7210 __ slt(AT, op2, op1);
7211 if(&L)
7212 __ bne(R0, AT, L);
7213 else
7214 __ bne(R0, AT, (int)0);
7215 break;
7216 case 0x04: //above_equal
7217 __ slt(AT, op1, op2);
7218 if(&L)
7219 __ beq(AT, R0, L);
7220 else
7221 __ beq(AT, R0, (int)0);
7222 break;
7223 case 0x05: //below
7224 __ slt(AT, op1, op2);
7225 if(&L)
7226 __ bne(R0, AT, L);
7227 else
7228 __ bne(R0, AT, (int)0);
7229 break;
7230 case 0x06: //below_equal
7231 __ slt(AT, op2, op1);
7232 if(&L)
7233 __ beq(AT, R0, L);
7234 else
7235 __ beq(AT, R0, (int)0);
7236 break;
7237 default:
7238 Unimplemented();
7239 }
7240 __ nop();
7241 %}
7243 ins_pc_relative(1);
7244 ins_pipe( pipe_alu_branch );
7245 %}
7247 instruct branchConI_reg_imm0(cmpOp cmp, mRegI src1, immI0 src2, label labl) %{
7248 match( If cmp (CmpI src1 src2) );
7249 effect(USE labl);
7250 ins_cost(170);
7251 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm0" %}
7253 ins_encode %{
7254 Register op1 = $src1$$Register;
7255 // int val = $src2$$constant;
7256 Label &L = *($labl$$label);
7257 int flag = $cmp$$cmpcode;
7259 //__ move(AT, val);
7260 switch(flag)
7261 {
7262 case 0x01: //equal
7263 if (&L)
7264 __ beq(op1, R0, L);
7265 else
7266 __ beq(op1, R0, (int)0);
7267 break;
7268 case 0x02: //not_equal
7269 if (&L)
7270 __ bne(op1, R0, L);
7271 else
7272 __ bne(op1, R0, (int)0);
7273 break;
7274 case 0x03: //greater
7275 if(&L)
7276 __ bgtz(op1, L);
7277 else
7278 __ bgtz(op1, (int)0);
7279 break;
7280 case 0x04: //greater_equal
7281 if(&L)
7282 __ bgez(op1, L);
7283 else
7284 __ bgez(op1, (int)0);
7285 break;
7286 case 0x05: //less
7287 if(&L)
7288 __ bltz(op1, L);
7289 else
7290 __ bltz(op1, (int)0);
7291 break;
7292 case 0x06: //less_equal
7293 if(&L)
7294 __ blez(op1, L);
7295 else
7296 __ blez(op1, (int)0);
7297 break;
7298 default:
7299 Unimplemented();
7300 }
7301 __ nop();
7302 %}
7304 ins_pc_relative(1);
7305 ins_pipe( pipe_alu_branch );
7306 %}
7309 instruct branchConI_reg_imm(cmpOp cmp, mRegI src1, immI src2, label labl) %{
7310 match( If cmp (CmpI src1 src2) );
7311 effect(USE labl);
7312 ins_cost(200);
7313 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm" %}
7315 ins_encode %{
7316 Register op1 = $src1$$Register;
7317 int val = $src2$$constant;
7318 Label &L = *($labl$$label);
7319 int flag = $cmp$$cmpcode;
7321 __ move(AT, val);
7322 switch(flag)
7323 {
7324 case 0x01: //equal
7325 if (&L)
7326 __ beq(op1, AT, L);
7327 else
7328 __ beq(op1, AT, (int)0);
7329 break;
7330 case 0x02: //not_equal
7331 if (&L)
7332 __ bne(op1, AT, L);
7333 else
7334 __ bne(op1, AT, (int)0);
7335 break;
7336 case 0x03: //greater
7337 __ slt(AT, AT, op1);
7338 if(&L)
7339 __ bne(R0, AT, L);
7340 else
7341 __ bne(R0, AT, (int)0);
7342 break;
7343 case 0x04: //greater_equal
7344 __ slt(AT, op1, AT);
7345 if(&L)
7346 __ beq(AT, R0, L);
7347 else
7348 __ beq(AT, R0, (int)0);
7349 break;
7350 case 0x05: //less
7351 __ slt(AT, op1, AT);
7352 if(&L)
7353 __ bne(R0, AT, L);
7354 else
7355 __ bne(R0, AT, (int)0);
7356 break;
7357 case 0x06: //less_equal
7358 __ slt(AT, AT, op1);
7359 if(&L)
7360 __ beq(AT, R0, L);
7361 else
7362 __ beq(AT, R0, (int)0);
7363 break;
7364 default:
7365 Unimplemented();
7366 }
7367 __ nop();
7368 %}
7370 ins_pc_relative(1);
7371 ins_pipe( pipe_alu_branch );
7372 %}
7374 instruct branchConIU_reg_imm0(cmpOpU cmp, mRegI src1, immI0 zero, label labl) %{
7375 match( If cmp (CmpU src1 zero) );
7376 effect(USE labl);
7377 format %{ "BR$cmp $src1, zero, $labl #@branchConIU_reg_imm0" %}
7379 ins_encode %{
7380 Register op1 = $src1$$Register;
7381 Label &L = *($labl$$label);
7382 int flag = $cmp$$cmpcode;
7384 switch(flag)
7385 {
7386 case 0x01: //equal
7387 if (&L)
7388 __ beq(op1, R0, L);
7389 else
7390 __ beq(op1, R0, (int)0);
7391 break;
7392 case 0x02: //not_equal
7393 if (&L)
7394 __ bne(op1, R0, L);
7395 else
7396 __ bne(op1, R0, (int)0);
7397 break;
7398 case 0x03: //above
7399 if(&L)
7400 __ bne(R0, op1, L);
7401 else
7402 __ bne(R0, op1, (int)0);
7403 break;
7404 case 0x04: //above_equal
7405 if(&L)
7406 __ beq(R0, R0, L);
7407 else
7408 __ beq(R0, R0, (int)0);
7409 break;
7410 case 0x05: //below
7411 return;
7412 break;
7413 case 0x06: //below_equal
7414 if(&L)
7415 __ beq(op1, R0, L);
7416 else
7417 __ beq(op1, R0, (int)0);
7418 break;
7419 default:
7420 Unimplemented();
7421 }
7422 __ nop();
7423 %}
7425 ins_pc_relative(1);
7426 ins_pipe( pipe_alu_branch );
7427 %}
7430 instruct branchConIU_reg_immI16(cmpOpU cmp, mRegI src1, immI16 src2, label labl) %{
7431 match( If cmp (CmpU src1 src2) );
7432 effect(USE labl);
7433 ins_cost(180);
7434 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_immI16" %}
7436 ins_encode %{
7437 Register op1 = $src1$$Register;
7438 int val = $src2$$constant;
7439 Label &L = *($labl$$label);
7440 int flag = $cmp$$cmpcode;
7442 switch(flag)
7443 {
7444 case 0x01: //equal
7445 __ move(AT, val);
7446 if (&L)
7447 __ beq(op1, AT, L);
7448 else
7449 __ beq(op1, AT, (int)0);
7450 break;
7451 case 0x02: //not_equal
7452 __ move(AT, val);
7453 if (&L)
7454 __ bne(op1, AT, L);
7455 else
7456 __ bne(op1, AT, (int)0);
7457 break;
7458 case 0x03: //above
7459 __ move(AT, val);
7460 __ sltu(AT, AT, op1);
7461 if(&L)
7462 __ bne(R0, AT, L);
7463 else
7464 __ bne(R0, AT, (int)0);
7465 break;
7466 case 0x04: //above_equal
7467 __ sltiu(AT, op1, val);
7468 if(&L)
7469 __ beq(AT, R0, L);
7470 else
7471 __ beq(AT, R0, (int)0);
7472 break;
7473 case 0x05: //below
7474 __ sltiu(AT, op1, val);
7475 if(&L)
7476 __ bne(R0, AT, L);
7477 else
7478 __ bne(R0, AT, (int)0);
7479 break;
7480 case 0x06: //below_equal
7481 __ move(AT, val);
7482 __ sltu(AT, AT, op1);
7483 if(&L)
7484 __ beq(AT, R0, L);
7485 else
7486 __ beq(AT, R0, (int)0);
7487 break;
7488 default:
7489 Unimplemented();
7490 }
7491 __ nop();
7492 %}
7494 ins_pc_relative(1);
7495 ins_pipe( pipe_alu_branch );
7496 %}
7499 instruct branchConL_regL_regL(cmpOp cmp, mRegL src1, mRegL src2, label labl) %{
7500 match( If cmp (CmpL src1 src2) );
7501 effect(USE labl);
7502 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_regL_regL" %}
7503 ins_cost(250);
7505 ins_encode %{
7506 Register opr1_reg = as_Register($src1$$reg);
7507 Register opr2_reg = as_Register($src2$$reg);
7509 Label &target = *($labl$$label);
7510 int flag = $cmp$$cmpcode;
7512 switch(flag)
7513 {
7514 case 0x01: //equal
7515 if (&target)
7516 __ beq(opr1_reg, opr2_reg, target);
7517 else
7518 __ beq(opr1_reg, opr2_reg, (int)0);
7519 __ delayed()->nop();
7520 break;
7522 case 0x02: //not_equal
7523 if(&target)
7524 __ bne(opr1_reg, opr2_reg, target);
7525 else
7526 __ bne(opr1_reg, opr2_reg, (int)0);
7527 __ delayed()->nop();
7528 break;
7530 case 0x03: //greater
7531 __ slt(AT, opr2_reg, opr1_reg);
7532 if(&target)
7533 __ bne(AT, R0, target);
7534 else
7535 __ bne(AT, R0, (int)0);
7536 __ delayed()->nop();
7537 break;
7539 case 0x04: //greater_equal
7540 __ slt(AT, opr1_reg, opr2_reg);
7541 if(&target)
7542 __ beq(AT, R0, target);
7543 else
7544 __ beq(AT, R0, (int)0);
7545 __ delayed()->nop();
7547 break;
7549 case 0x05: //less
7550 __ slt(AT, opr1_reg, opr2_reg);
7551 if(&target)
7552 __ bne(AT, R0, target);
7553 else
7554 __ bne(AT, R0, (int)0);
7555 __ delayed()->nop();
7557 break;
7559 case 0x06: //less_equal
7560 __ slt(AT, opr2_reg, opr1_reg);
7562 if(&target)
7563 __ beq(AT, R0, target);
7564 else
7565 __ beq(AT, R0, (int)0);
7566 __ delayed()->nop();
7568 break;
7570 default:
7571 Unimplemented();
7572 }
7573 %}
7576 ins_pc_relative(1);
7577 ins_pipe( pipe_alu_branch );
7578 %}
7580 instruct branchConL_reg_immL16_sub(cmpOp cmp, mRegL src1, immL16_sub src2, label labl) %{
7581 match( If cmp (CmpL src1 src2) );
7582 effect(USE labl);
7583 ins_cost(180);
7584 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_reg_immL16_sub" %}
7586 ins_encode %{
7587 Register op1 = $src1$$Register;
7588 int val = $src2$$constant;
7589 Label &L = *($labl$$label);
7590 int flag = $cmp$$cmpcode;
7592 __ daddiu(AT, op1, -1 * val);
7593 switch(flag)
7594 {
7595 case 0x01: //equal
7596 if (&L)
7597 __ beq(R0, AT, L);
7598 else
7599 __ beq(R0, AT, (int)0);
7600 break;
7601 case 0x02: //not_equal
7602 if (&L)
7603 __ bne(R0, AT, L);
7604 else
7605 __ bne(R0, AT, (int)0);
7606 break;
7607 case 0x03: //greater
7608 if(&L)
7609 __ bgtz(AT, L);
7610 else
7611 __ bgtz(AT, (int)0);
7612 break;
7613 case 0x04: //greater_equal
7614 if(&L)
7615 __ bgez(AT, L);
7616 else
7617 __ bgez(AT, (int)0);
7618 break;
7619 case 0x05: //less
7620 if(&L)
7621 __ bltz(AT, L);
7622 else
7623 __ bltz(AT, (int)0);
7624 break;
7625 case 0x06: //less_equal
7626 if(&L)
7627 __ blez(AT, L);
7628 else
7629 __ blez(AT, (int)0);
7630 break;
7631 default:
7632 Unimplemented();
7633 }
7634 __ nop();
7635 %}
7637 ins_pc_relative(1);
7638 ins_pipe( pipe_alu_branch );
7639 %}
7642 instruct branchConI_reg_imm16_sub(cmpOp cmp, mRegI src1, immI16_sub src2, label labl) %{
7643 match( If cmp (CmpI src1 src2) );
7644 effect(USE labl);
7645 ins_cost(180);
7646 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm16_sub" %}
7648 ins_encode %{
7649 Register op1 = $src1$$Register;
7650 int val = $src2$$constant;
7651 Label &L = *($labl$$label);
7652 int flag = $cmp$$cmpcode;
7654 __ addiu32(AT, op1, -1 * val);
7655 switch(flag)
7656 {
7657 case 0x01: //equal
7658 if (&L)
7659 __ beq(R0, AT, L);
7660 else
7661 __ beq(R0, AT, (int)0);
7662 break;
7663 case 0x02: //not_equal
7664 if (&L)
7665 __ bne(R0, AT, L);
7666 else
7667 __ bne(R0, AT, (int)0);
7668 break;
7669 case 0x03: //greater
7670 if(&L)
7671 __ bgtz(AT, L);
7672 else
7673 __ bgtz(AT, (int)0);
7674 break;
7675 case 0x04: //greater_equal
7676 if(&L)
7677 __ bgez(AT, L);
7678 else
7679 __ bgez(AT, (int)0);
7680 break;
7681 case 0x05: //less
7682 if(&L)
7683 __ bltz(AT, L);
7684 else
7685 __ bltz(AT, (int)0);
7686 break;
7687 case 0x06: //less_equal
7688 if(&L)
7689 __ blez(AT, L);
7690 else
7691 __ blez(AT, (int)0);
7692 break;
7693 default:
7694 Unimplemented();
7695 }
7696 __ nop();
7697 %}
7699 ins_pc_relative(1);
7700 ins_pipe( pipe_alu_branch );
7701 %}
7703 instruct branchConL_regL_immL0(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{
7704 match( If cmp (CmpL src1 zero) );
7705 effect(USE labl);
7706 format %{ "BR$cmp $src1, zero, $labl #@branchConL_regL_immL0" %}
7707 ins_cost(150);
7709 ins_encode %{
7710 Register opr1_reg = as_Register($src1$$reg);
7711 Label &target = *($labl$$label);
7712 int flag = $cmp$$cmpcode;
7714 switch(flag)
7715 {
7716 case 0x01: //equal
7717 if (&target)
7718 __ beq(opr1_reg, R0, target);
7719 else
7720 __ beq(opr1_reg, R0, int(0));
7721 break;
7723 case 0x02: //not_equal
7724 if(&target)
7725 __ bne(opr1_reg, R0, target);
7726 else
7727 __ bne(opr1_reg, R0, (int)0);
7728 break;
7730 case 0x03: //greater
7731 if(&target)
7732 __ bgtz(opr1_reg, target);
7733 else
7734 __ bgtz(opr1_reg, (int)0);
7735 break;
7737 case 0x04: //greater_equal
7738 if(&target)
7739 __ bgez(opr1_reg, target);
7740 else
7741 __ bgez(opr1_reg, (int)0);
7742 break;
7744 case 0x05: //less
7745 __ slt(AT, opr1_reg, R0);
7746 if(&target)
7747 __ bne(AT, R0, target);
7748 else
7749 __ bne(AT, R0, (int)0);
7750 break;
7752 case 0x06: //less_equal
7753 if (&target)
7754 __ blez(opr1_reg, target);
7755 else
7756 __ blez(opr1_reg, int(0));
7757 break;
7759 default:
7760 Unimplemented();
7761 }
7762 __ delayed()->nop();
7763 %}
7766 ins_pc_relative(1);
7767 ins_pipe( pipe_alu_branch );
7768 %}
7770 /*
7771 // Conditional Direct Branch
7772 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
7773 match(If cmp icc);
7774 effect(USE labl);
7776 size(8);
7777 ins_cost(BRANCH_COST);
7778 format %{ "BP$cmp $icc,$labl" %}
7779 // Prim = bits 24-22, Secnd = bits 31-30
7780 ins_encode( enc_bp( labl, cmp, icc ) );
7781 ins_pc_relative(1);
7782 ins_pipe(br_cc);
7783 %}
7784 */
7786 //FIXME
7787 instruct branchConF_reg_reg(cmpOp cmp, regF src1, regF src2, label labl) %{
7788 match( If cmp (CmpF src1 src2) );
7789 effect(USE labl);
7790 format %{ "BR$cmp $src1, $src2, $labl #@branchConF_reg_reg" %}
7792 ins_encode %{
7793 FloatRegister reg_op1 = $src1$$FloatRegister;
7794 FloatRegister reg_op2 = $src2$$FloatRegister;
7795 Label &L = *($labl$$label);
7796 int flag = $cmp$$cmpcode;
7798 switch(flag)
7799 {
7800 case 0x01: //equal
7801 __ c_eq_s(reg_op1, reg_op2);
7802 if (&L)
7803 __ bc1t(L);
7804 else
7805 __ bc1t((int)0);
7806 break;
7807 case 0x02: //not_equal
7808 __ c_eq_s(reg_op1, reg_op2);
7809 if (&L)
7810 __ bc1f(L);
7811 else
7812 __ bc1f((int)0);
7813 break;
7814 case 0x03: //greater
7815 __ c_ule_s(reg_op1, reg_op2);
7816 if(&L)
7817 __ bc1f(L);
7818 else
7819 __ bc1f((int)0);
7820 break;
7821 case 0x04: //greater_equal
7822 __ c_ult_s(reg_op1, reg_op2);
7823 if(&L)
7824 __ bc1f(L);
7825 else
7826 __ bc1f((int)0);
7827 break;
7828 case 0x05: //less
7829 __ c_ult_s(reg_op1, reg_op2);
7830 if(&L)
7831 __ bc1t(L);
7832 else
7833 __ bc1t((int)0);
7834 break;
7835 case 0x06: //less_equal
7836 __ c_ule_s(reg_op1, reg_op2);
7837 if(&L)
7838 __ bc1t(L);
7839 else
7840 __ bc1t((int)0);
7841 break;
7842 default:
7843 Unimplemented();
7844 }
7845 __ nop();
7846 %}
7848 ins_pc_relative(1);
7849 ins_pipe(pipe_slow);
7850 %}
7852 instruct branchConD_reg_reg(cmpOp cmp, regD src1, regD src2, label labl) %{
7853 match( If cmp (CmpD src1 src2) );
7854 effect(USE labl);
7855 format %{ "BR$cmp $src1, $src2, $labl #@branchConD_reg_reg" %}
7857 ins_encode %{
7858 FloatRegister reg_op1 = $src1$$FloatRegister;
7859 FloatRegister reg_op2 = $src2$$FloatRegister;
7860 Label &L = *($labl$$label);
7861 int flag = $cmp$$cmpcode;
7863 switch(flag)
7864 {
7865 case 0x01: //equal
7866 __ c_eq_d(reg_op1, reg_op2);
7867 if (&L)
7868 __ bc1t(L);
7869 else
7870 __ bc1t((int)0);
7871 break;
7872 case 0x02: //not_equal
7873 //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
7874 __ c_eq_d(reg_op1, reg_op2);
7875 if (&L)
7876 __ bc1f(L);
7877 else
7878 __ bc1f((int)0);
7879 break;
7880 case 0x03: //greater
7881 __ c_ule_d(reg_op1, reg_op2);
7882 if(&L)
7883 __ bc1f(L);
7884 else
7885 __ bc1f((int)0);
7886 break;
7887 case 0x04: //greater_equal
7888 __ c_ult_d(reg_op1, reg_op2);
7889 if(&L)
7890 __ bc1f(L);
7891 else
7892 __ bc1f((int)0);
7893 break;
7894 case 0x05: //less
7895 __ c_ult_d(reg_op1, reg_op2);
7896 if(&L)
7897 __ bc1t(L);
7898 else
7899 __ bc1t((int)0);
7900 break;
7901 case 0x06: //less_equal
7902 __ c_ule_d(reg_op1, reg_op2);
7903 if(&L)
7904 __ bc1t(L);
7905 else
7906 __ bc1t((int)0);
7907 break;
7908 default:
7909 Unimplemented();
7910 }
7911 __ nop();
7912 %}
7914 ins_pc_relative(1);
7915 ins_pipe(pipe_slow);
7916 %}
7919 // Call Runtime Instruction
7920 instruct CallRuntimeDirect(method meth) %{
7921 match(CallRuntime );
7922 effect(USE meth);
7924 ins_cost(300);
7925 format %{ "CALL,runtime #@CallRuntimeDirect" %}
7926 ins_encode( Java_To_Runtime( meth ) );
7927 ins_pipe( pipe_slow );
7928 ins_alignment(16);
7929 %}
7933 //------------------------MemBar Instructions-------------------------------
7934 //Memory barrier flavors
7936 instruct membar_acquire() %{
7937 match(MemBarAcquire);
7938 ins_cost(0);
7940 size(0);
7941 format %{ "MEMBAR-acquire (empty) @ membar_acquire" %}
7942 ins_encode();
7943 ins_pipe(empty);
7944 %}
7946 instruct load_fence() %{
7947 match(LoadFence);
7948 ins_cost(400);
7950 format %{ "MEMBAR @ load_fence" %}
7951 ins_encode %{
7952 __ sync();
7953 %}
7954 ins_pipe(pipe_slow);
7955 %}
7957 instruct membar_acquire_lock()
7958 %{
7959 match(MemBarAcquireLock);
7960 ins_cost(0);
7962 size(0);
7963 format %{ "MEMBAR-acquire (acquire as part of CAS in prior FastLock so empty encoding) @ membar_acquire_lock" %}
7964 ins_encode();
7965 ins_pipe(empty);
7966 %}
7968 instruct membar_release() %{
7969 match(MemBarRelease);
7970 ins_cost(0);
7972 size(0);
7973 format %{ "MEMBAR-release (empty) @ membar_release" %}
7974 ins_encode();
7975 ins_pipe(empty);
7976 %}
7978 instruct store_fence() %{
7979 match(StoreFence);
7980 ins_cost(400);
7982 format %{ "MEMBAR @ store_fence" %}
7984 ins_encode %{
7985 __ sync();
7986 %}
7988 ins_pipe(pipe_slow);
7989 %}
7991 instruct membar_release_lock()
7992 %{
7993 match(MemBarReleaseLock);
7994 ins_cost(0);
7996 size(0);
7997 format %{ "MEMBAR-release-lock (release in FastUnlock so empty) @ membar_release_lock" %}
7998 ins_encode();
7999 ins_pipe(empty);
8000 %}
8003 instruct membar_volatile() %{
8004 match(MemBarVolatile);
8005 ins_cost(400);
8007 format %{ "MEMBAR-volatile" %}
8008 ins_encode %{
8009 if( !os::is_MP() ) return; // Not needed on single CPU
8010 __ sync();
8012 %}
8013 ins_pipe(pipe_slow);
8014 %}
8016 instruct unnecessary_membar_volatile() %{
8017 match(MemBarVolatile);
8018 predicate(Matcher::post_store_load_barrier(n));
8019 ins_cost(0);
8021 size(0);
8022 format %{ "MEMBAR-volatile (unnecessary so empty encoding) @ unnecessary_membar_volatile" %}
8023 ins_encode( );
8024 ins_pipe(empty);
8025 %}
8027 instruct membar_storestore() %{
8028 match(MemBarStoreStore);
8030 ins_cost(0);
8031 size(0);
8032 format %{ "MEMBAR-storestore (empty encoding) @ membar_storestore" %}
8033 ins_encode( );
8034 ins_pipe(empty);
8035 %}
8037 //----------Move Instructions--------------------------------------------------
8038 instruct castX2P(mRegP dst, mRegL src) %{
8039 match(Set dst (CastX2P src));
8040 format %{ "castX2P $dst, $src @ castX2P" %}
8041 ins_encode %{
8042 Register src = $src$$Register;
8043 Register dst = $dst$$Register;
8045 if(src != dst)
8046 __ move(dst, src);
8047 %}
8048 ins_cost(10);
8049 ins_pipe( ialu_regI_mov );
8050 %}
8052 instruct castP2X(mRegL dst, mRegP src ) %{
8053 match(Set dst (CastP2X src));
8055 format %{ "mov $dst, $src\t #@castP2X" %}
8056 ins_encode %{
8057 Register src = $src$$Register;
8058 Register dst = $dst$$Register;
8060 if(src != dst)
8061 __ move(dst, src);
8062 %}
8063 ins_pipe( ialu_regI_mov );
8064 %}
8066 instruct MoveF2I_reg_reg(mRegI dst, regF src) %{
8067 match(Set dst (MoveF2I src));
8068 effect(DEF dst, USE src);
8069 ins_cost(85);
8070 format %{ "MoveF2I $dst, $src @ MoveF2I_reg_reg" %}
8071 ins_encode %{
8072 Register dst = as_Register($dst$$reg);
8073 FloatRegister src = as_FloatRegister($src$$reg);
8075 __ mfc1(dst, src);
8076 %}
8077 ins_pipe( pipe_slow );
8078 %}
8080 instruct MoveI2F_reg_reg(regF dst, mRegI src) %{
8081 match(Set dst (MoveI2F src));
8082 effect(DEF dst, USE src);
8083 ins_cost(85);
8084 format %{ "MoveI2F $dst, $src @ MoveI2F_reg_reg" %}
8085 ins_encode %{
8086 Register src = as_Register($src$$reg);
8087 FloatRegister dst = as_FloatRegister($dst$$reg);
8089 __ mtc1(src, dst);
8090 %}
8091 ins_pipe( pipe_slow );
8092 %}
8094 instruct MoveD2L_reg_reg(mRegL dst, regD src) %{
8095 match(Set dst (MoveD2L src));
8096 effect(DEF dst, USE src);
8097 ins_cost(85);
8098 format %{ "MoveD2L $dst, $src @ MoveD2L_reg_reg" %}
8099 ins_encode %{
8100 Register dst = as_Register($dst$$reg);
8101 FloatRegister src = as_FloatRegister($src$$reg);
8103 __ dmfc1(dst, src);
8104 %}
8105 ins_pipe( pipe_slow );
8106 %}
8108 instruct MoveL2D_reg_reg(regD dst, mRegL src) %{
8109 match(Set dst (MoveL2D src));
8110 effect(DEF dst, USE src);
8111 ins_cost(85);
8112 format %{ "MoveL2D $dst, $src @ MoveL2D_reg_reg" %}
8113 ins_encode %{
8114 FloatRegister dst = as_FloatRegister($dst$$reg);
8115 Register src = as_Register($src$$reg);
8117 __ dmtc1(src, dst);
8118 %}
8119 ins_pipe( pipe_slow );
8120 %}
8122 //----------Conditional Move---------------------------------------------------
8123 // Conditional move
8124 instruct cmovI_cmpI_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8125 match(Set dst (CMoveI (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8126 ins_cost(80);
8127 format %{
8128 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpI_reg_reg\n"
8129 "\tCMOV $dst,$src \t @cmovI_cmpI_reg_reg"
8130 %}
8132 ins_encode %{
8133 Register op1 = $tmp1$$Register;
8134 Register op2 = $tmp2$$Register;
8135 Register dst = $dst$$Register;
8136 Register src = $src$$Register;
8137 int flag = $cop$$cmpcode;
8139 switch(flag)
8140 {
8141 case 0x01: //equal
8142 __ subu32(AT, op1, op2);
8143 __ movz(dst, src, AT);
8144 break;
8146 case 0x02: //not_equal
8147 __ subu32(AT, op1, op2);
8148 __ movn(dst, src, AT);
8149 break;
8151 case 0x03: //great
8152 __ slt(AT, op2, op1);
8153 __ movn(dst, src, AT);
8154 break;
8156 case 0x04: //great_equal
8157 __ slt(AT, op1, op2);
8158 __ movz(dst, src, AT);
8159 break;
8161 case 0x05: //less
8162 __ slt(AT, op1, op2);
8163 __ movn(dst, src, AT);
8164 break;
8166 case 0x06: //less_equal
8167 __ slt(AT, op2, op1);
8168 __ movz(dst, src, AT);
8169 break;
8171 default:
8172 Unimplemented();
8173 }
8174 %}
8176 ins_pipe( pipe_slow );
8177 %}
8179 instruct cmovI_cmpP_reg_reg(mRegI dst, mRegI src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8180 match(Set dst (CMoveI (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8181 ins_cost(80);
8182 format %{
8183 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpP_reg_reg\n\t"
8184 "CMOV $dst,$src\t @cmovI_cmpP_reg_reg"
8185 %}
8186 ins_encode %{
8187 Register op1 = $tmp1$$Register;
8188 Register op2 = $tmp2$$Register;
8189 Register dst = $dst$$Register;
8190 Register src = $src$$Register;
8191 int flag = $cop$$cmpcode;
8193 switch(flag)
8194 {
8195 case 0x01: //equal
8196 __ subu(AT, op1, op2);
8197 __ movz(dst, src, AT);
8198 break;
8200 case 0x02: //not_equal
8201 __ subu(AT, op1, op2);
8202 __ movn(dst, src, AT);
8203 break;
8205 case 0x03: //above
8206 __ sltu(AT, op2, op1);
8207 __ movn(dst, src, AT);
8208 break;
8210 case 0x04: //above_equal
8211 __ sltu(AT, op1, op2);
8212 __ movz(dst, src, AT);
8213 break;
8215 case 0x05: //below
8216 __ sltu(AT, op1, op2);
8217 __ movn(dst, src, AT);
8218 break;
8220 case 0x06: //below_equal
8221 __ sltu(AT, op2, op1);
8222 __ movz(dst, src, AT);
8223 break;
8225 default:
8226 Unimplemented();
8227 }
8228 %}
8230 ins_pipe( pipe_slow );
8231 %}
8233 instruct cmovI_cmpN_reg_reg(mRegI dst, mRegI src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8234 match(Set dst (CMoveI (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8235 ins_cost(80);
8236 format %{
8237 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpN_reg_reg\n\t"
8238 "CMOV $dst,$src\t @cmovI_cmpN_reg_reg"
8239 %}
8240 ins_encode %{
8241 Register op1 = $tmp1$$Register;
8242 Register op2 = $tmp2$$Register;
8243 Register dst = $dst$$Register;
8244 Register src = $src$$Register;
8245 int flag = $cop$$cmpcode;
8247 switch(flag)
8248 {
8249 case 0x01: //equal
8250 __ subu32(AT, op1, op2);
8251 __ movz(dst, src, AT);
8252 break;
8254 case 0x02: //not_equal
8255 __ subu32(AT, op1, op2);
8256 __ movn(dst, src, AT);
8257 break;
8259 case 0x03: //above
8260 __ sltu(AT, op2, op1);
8261 __ movn(dst, src, AT);
8262 break;
8264 case 0x04: //above_equal
8265 __ sltu(AT, op1, op2);
8266 __ movz(dst, src, AT);
8267 break;
8269 case 0x05: //below
8270 __ sltu(AT, op1, op2);
8271 __ movn(dst, src, AT);
8272 break;
8274 case 0x06: //below_equal
8275 __ sltu(AT, op2, op1);
8276 __ movz(dst, src, AT);
8277 break;
8279 default:
8280 Unimplemented();
8281 }
8282 %}
8284 ins_pipe( pipe_slow );
8285 %}
8287 instruct cmovP_cmpN_reg_reg(mRegP dst, mRegP src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8288 match(Set dst (CMoveP (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8289 ins_cost(80);
8290 format %{
8291 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpN_reg_reg\n\t"
8292 "CMOV $dst,$src\t @cmovP_cmpN_reg_reg"
8293 %}
8294 ins_encode %{
8295 Register op1 = $tmp1$$Register;
8296 Register op2 = $tmp2$$Register;
8297 Register dst = $dst$$Register;
8298 Register src = $src$$Register;
8299 int flag = $cop$$cmpcode;
8301 switch(flag)
8302 {
8303 case 0x01: //equal
8304 __ subu32(AT, op1, op2);
8305 __ movz(dst, src, AT);
8306 break;
8308 case 0x02: //not_equal
8309 __ subu32(AT, op1, op2);
8310 __ movn(dst, src, AT);
8311 break;
8313 case 0x03: //above
8314 __ sltu(AT, op2, op1);
8315 __ movn(dst, src, AT);
8316 break;
8318 case 0x04: //above_equal
8319 __ sltu(AT, op1, op2);
8320 __ movz(dst, src, AT);
8321 break;
8323 case 0x05: //below
8324 __ sltu(AT, op1, op2);
8325 __ movn(dst, src, AT);
8326 break;
8328 case 0x06: //below_equal
8329 __ sltu(AT, op2, op1);
8330 __ movz(dst, src, AT);
8331 break;
8333 default:
8334 Unimplemented();
8335 }
8336 %}
8338 ins_pipe( pipe_slow );
8339 %}
8341 instruct cmovN_cmpP_reg_reg(mRegN dst, mRegN src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8342 match(Set dst (CMoveN (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8343 ins_cost(80);
8344 format %{
8345 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpP_reg_reg\n\t"
8346 "CMOV $dst,$src\t @cmovN_cmpP_reg_reg"
8347 %}
8348 ins_encode %{
8349 Register op1 = $tmp1$$Register;
8350 Register op2 = $tmp2$$Register;
8351 Register dst = $dst$$Register;
8352 Register src = $src$$Register;
8353 int flag = $cop$$cmpcode;
8355 switch(flag)
8356 {
8357 case 0x01: //equal
8358 __ subu(AT, op1, op2);
8359 __ movz(dst, src, AT);
8360 break;
8362 case 0x02: //not_equal
8363 __ subu(AT, op1, op2);
8364 __ movn(dst, src, AT);
8365 break;
8367 case 0x03: //above
8368 __ sltu(AT, op2, op1);
8369 __ movn(dst, src, AT);
8370 break;
8372 case 0x04: //above_equal
8373 __ sltu(AT, op1, op2);
8374 __ movz(dst, src, AT);
8375 break;
8377 case 0x05: //below
8378 __ sltu(AT, op1, op2);
8379 __ movn(dst, src, AT);
8380 break;
8382 case 0x06: //below_equal
8383 __ sltu(AT, op2, op1);
8384 __ movz(dst, src, AT);
8385 break;
8387 default:
8388 Unimplemented();
8389 }
8390 %}
8392 ins_pipe( pipe_slow );
8393 %}
8395 instruct cmovP_cmpD_reg_reg(mRegP dst, mRegP src, regD tmp1, regD tmp2, cmpOp cop ) %{
8396 match(Set dst (CMoveP (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8397 ins_cost(80);
8398 format %{
8399 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpD_reg_reg\n"
8400 "\tCMOV $dst,$src \t @cmovP_cmpD_reg_reg"
8401 %}
8402 ins_encode %{
8403 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8404 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8405 Register dst = as_Register($dst$$reg);
8406 Register src = as_Register($src$$reg);
8408 int flag = $cop$$cmpcode;
8410 switch(flag)
8411 {
8412 case 0x01: //equal
8413 __ c_eq_d(reg_op1, reg_op2);
8414 __ movt(dst, src);
8415 break;
8416 case 0x02: //not_equal
8417 __ c_eq_d(reg_op1, reg_op2);
8418 __ movf(dst, src);
8419 break;
8420 case 0x03: //greater
8421 __ c_ole_d(reg_op1, reg_op2);
8422 __ movf(dst, src);
8423 break;
8424 case 0x04: //greater_equal
8425 __ c_olt_d(reg_op1, reg_op2);
8426 __ movf(dst, src);
8427 break;
8428 case 0x05: //less
8429 __ c_ult_d(reg_op1, reg_op2);
8430 __ movt(dst, src);
8431 break;
8432 case 0x06: //less_equal
8433 __ c_ule_d(reg_op1, reg_op2);
8434 __ movt(dst, src);
8435 break;
8436 default:
8437 Unimplemented();
8438 }
8439 %}
8441 ins_pipe( pipe_slow );
8442 %}
8445 instruct cmovN_cmpN_reg_reg(mRegN dst, mRegN src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8446 match(Set dst (CMoveN (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8447 ins_cost(80);
8448 format %{
8449 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpN_reg_reg\n\t"
8450 "CMOV $dst,$src\t @cmovN_cmpN_reg_reg"
8451 %}
8452 ins_encode %{
8453 Register op1 = $tmp1$$Register;
8454 Register op2 = $tmp2$$Register;
8455 Register dst = $dst$$Register;
8456 Register src = $src$$Register;
8457 int flag = $cop$$cmpcode;
8459 switch(flag)
8460 {
8461 case 0x01: //equal
8462 __ subu32(AT, op1, op2);
8463 __ movz(dst, src, AT);
8464 break;
8466 case 0x02: //not_equal
8467 __ subu32(AT, op1, op2);
8468 __ movn(dst, src, AT);
8469 break;
8471 case 0x03: //above
8472 __ sltu(AT, op2, op1);
8473 __ movn(dst, src, AT);
8474 break;
8476 case 0x04: //above_equal
8477 __ sltu(AT, op1, op2);
8478 __ movz(dst, src, AT);
8479 break;
8481 case 0x05: //below
8482 __ sltu(AT, op1, op2);
8483 __ movn(dst, src, AT);
8484 break;
8486 case 0x06: //below_equal
8487 __ sltu(AT, op2, op1);
8488 __ movz(dst, src, AT);
8489 break;
8491 default:
8492 Unimplemented();
8493 }
8494 %}
8496 ins_pipe( pipe_slow );
8497 %}
8500 instruct cmovI_cmpU_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{
8501 match(Set dst (CMoveI (Binary cop (CmpU tmp1 tmp2)) (Binary dst src)));
8502 ins_cost(80);
8503 format %{
8504 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpU_reg_reg\n\t"
8505 "CMOV $dst,$src\t @cmovI_cmpU_reg_reg"
8506 %}
8507 ins_encode %{
8508 Register op1 = $tmp1$$Register;
8509 Register op2 = $tmp2$$Register;
8510 Register dst = $dst$$Register;
8511 Register src = $src$$Register;
8512 int flag = $cop$$cmpcode;
8514 switch(flag)
8515 {
8516 case 0x01: //equal
8517 __ subu(AT, op1, op2);
8518 __ movz(dst, src, AT);
8519 break;
8521 case 0x02: //not_equal
8522 __ subu(AT, op1, op2);
8523 __ movn(dst, src, AT);
8524 break;
8526 case 0x03: //above
8527 __ sltu(AT, op2, op1);
8528 __ movn(dst, src, AT);
8529 break;
8531 case 0x04: //above_equal
8532 __ sltu(AT, op1, op2);
8533 __ movz(dst, src, AT);
8534 break;
8536 case 0x05: //below
8537 __ sltu(AT, op1, op2);
8538 __ movn(dst, src, AT);
8539 break;
8541 case 0x06: //below_equal
8542 __ sltu(AT, op2, op1);
8543 __ movz(dst, src, AT);
8544 break;
8546 default:
8547 Unimplemented();
8548 }
8549 %}
8551 ins_pipe( pipe_slow );
8552 %}
8554 instruct cmovI_cmpL_reg_reg(mRegI dst, mRegI src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8555 match(Set dst (CMoveI (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8556 ins_cost(80);
8557 format %{
8558 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpL_reg_reg\n"
8559 "\tCMOV $dst,$src \t @cmovI_cmpL_reg_reg"
8560 %}
8561 ins_encode %{
8562 Register opr1 = as_Register($tmp1$$reg);
8563 Register opr2 = as_Register($tmp2$$reg);
8564 Register dst = $dst$$Register;
8565 Register src = $src$$Register;
8566 int flag = $cop$$cmpcode;
8568 switch(flag)
8569 {
8570 case 0x01: //equal
8571 __ subu(AT, opr1, opr2);
8572 __ movz(dst, src, AT);
8573 break;
8575 case 0x02: //not_equal
8576 __ subu(AT, opr1, opr2);
8577 __ movn(dst, src, AT);
8578 break;
8580 case 0x03: //greater
8581 __ slt(AT, opr2, opr1);
8582 __ movn(dst, src, AT);
8583 break;
8585 case 0x04: //greater_equal
8586 __ slt(AT, opr1, opr2);
8587 __ movz(dst, src, AT);
8588 break;
8590 case 0x05: //less
8591 __ slt(AT, opr1, opr2);
8592 __ movn(dst, src, AT);
8593 break;
8595 case 0x06: //less_equal
8596 __ slt(AT, opr2, opr1);
8597 __ movz(dst, src, AT);
8598 break;
8600 default:
8601 Unimplemented();
8602 }
8603 %}
8605 ins_pipe( pipe_slow );
8606 %}
8608 instruct cmovP_cmpL_reg_reg(mRegP dst, mRegP src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8609 match(Set dst (CMoveP (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8610 ins_cost(80);
8611 format %{
8612 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpL_reg_reg\n"
8613 "\tCMOV $dst,$src \t @cmovP_cmpL_reg_reg"
8614 %}
8615 ins_encode %{
8616 Register opr1 = as_Register($tmp1$$reg);
8617 Register opr2 = as_Register($tmp2$$reg);
8618 Register dst = $dst$$Register;
8619 Register src = $src$$Register;
8620 int flag = $cop$$cmpcode;
8622 switch(flag)
8623 {
8624 case 0x01: //equal
8625 __ subu(AT, opr1, opr2);
8626 __ movz(dst, src, AT);
8627 break;
8629 case 0x02: //not_equal
8630 __ subu(AT, opr1, opr2);
8631 __ movn(dst, src, AT);
8632 break;
8634 case 0x03: //greater
8635 __ slt(AT, opr2, opr1);
8636 __ movn(dst, src, AT);
8637 break;
8639 case 0x04: //greater_equal
8640 __ slt(AT, opr1, opr2);
8641 __ movz(dst, src, AT);
8642 break;
8644 case 0x05: //less
8645 __ slt(AT, opr1, opr2);
8646 __ movn(dst, src, AT);
8647 break;
8649 case 0x06: //less_equal
8650 __ slt(AT, opr2, opr1);
8651 __ movz(dst, src, AT);
8652 break;
8654 default:
8655 Unimplemented();
8656 }
8657 %}
8659 ins_pipe( pipe_slow );
8660 %}
8662 instruct cmovI_cmpD_reg_reg(mRegI dst, mRegI src, regD tmp1, regD tmp2, cmpOp cop ) %{
8663 match(Set dst (CMoveI (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8664 ins_cost(80);
8665 format %{
8666 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpD_reg_reg\n"
8667 "\tCMOV $dst,$src \t @cmovI_cmpD_reg_reg"
8668 %}
8669 ins_encode %{
8670 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8671 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8672 Register dst = as_Register($dst$$reg);
8673 Register src = as_Register($src$$reg);
8675 int flag = $cop$$cmpcode;
8677 switch(flag)
8678 {
8679 case 0x01: //equal
8680 __ c_eq_d(reg_op1, reg_op2);
8681 __ movt(dst, src);
8682 break;
8683 case 0x02: //not_equal
8684 //2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
8685 __ c_eq_d(reg_op1, reg_op2);
8686 __ movf(dst, src);
8687 break;
8688 case 0x03: //greater
8689 __ c_ole_d(reg_op1, reg_op2);
8690 __ movf(dst, src);
8691 break;
8692 case 0x04: //greater_equal
8693 __ c_olt_d(reg_op1, reg_op2);
8694 __ movf(dst, src);
8695 break;
8696 case 0x05: //less
8697 __ c_ult_d(reg_op1, reg_op2);
8698 __ movt(dst, src);
8699 break;
8700 case 0x06: //less_equal
8701 __ c_ule_d(reg_op1, reg_op2);
8702 __ movt(dst, src);
8703 break;
8704 default:
8705 Unimplemented();
8706 }
8707 %}
8709 ins_pipe( pipe_slow );
8710 %}
8713 instruct cmovP_cmpP_reg_reg(mRegP dst, mRegP src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8714 match(Set dst (CMoveP (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8715 ins_cost(80);
8716 format %{
8717 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpP_reg_reg\n\t"
8718 "CMOV $dst,$src\t @cmovP_cmpP_reg_reg"
8719 %}
8720 ins_encode %{
8721 Register op1 = $tmp1$$Register;
8722 Register op2 = $tmp2$$Register;
8723 Register dst = $dst$$Register;
8724 Register src = $src$$Register;
8725 int flag = $cop$$cmpcode;
8727 switch(flag)
8728 {
8729 case 0x01: //equal
8730 __ subu(AT, op1, op2);
8731 __ movz(dst, src, AT);
8732 break;
8734 case 0x02: //not_equal
8735 __ subu(AT, op1, op2);
8736 __ movn(dst, src, AT);
8737 break;
8739 case 0x03: //above
8740 __ sltu(AT, op2, op1);
8741 __ movn(dst, src, AT);
8742 break;
8744 case 0x04: //above_equal
8745 __ sltu(AT, op1, op2);
8746 __ movz(dst, src, AT);
8747 break;
8749 case 0x05: //below
8750 __ sltu(AT, op1, op2);
8751 __ movn(dst, src, AT);
8752 break;
8754 case 0x06: //below_equal
8755 __ sltu(AT, op2, op1);
8756 __ movz(dst, src, AT);
8757 break;
8759 default:
8760 Unimplemented();
8761 }
8762 %}
8764 ins_pipe( pipe_slow );
8765 %}
8767 instruct cmovP_cmpI_reg_reg(mRegP dst, mRegP src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8768 match(Set dst (CMoveP (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8769 ins_cost(80);
8770 format %{
8771 "CMP$cop $tmp1,$tmp2\t @cmovP_cmpI_reg_reg\n\t"
8772 "CMOV $dst,$src\t @cmovP_cmpI_reg_reg"
8773 %}
8774 ins_encode %{
8775 Register op1 = $tmp1$$Register;
8776 Register op2 = $tmp2$$Register;
8777 Register dst = $dst$$Register;
8778 Register src = $src$$Register;
8779 int flag = $cop$$cmpcode;
8781 switch(flag)
8782 {
8783 case 0x01: //equal
8784 __ subu32(AT, op1, op2);
8785 __ movz(dst, src, AT);
8786 break;
8788 case 0x02: //not_equal
8789 __ subu32(AT, op1, op2);
8790 __ movn(dst, src, AT);
8791 break;
8793 case 0x03: //above
8794 __ slt(AT, op2, op1);
8795 __ movn(dst, src, AT);
8796 break;
8798 case 0x04: //above_equal
8799 __ slt(AT, op1, op2);
8800 __ movz(dst, src, AT);
8801 break;
8803 case 0x05: //below
8804 __ slt(AT, op1, op2);
8805 __ movn(dst, src, AT);
8806 break;
8808 case 0x06: //below_equal
8809 __ slt(AT, op2, op1);
8810 __ movz(dst, src, AT);
8811 break;
8813 default:
8814 Unimplemented();
8815 }
8816 %}
8818 ins_pipe( pipe_slow );
8819 %}
8821 instruct cmovN_cmpI_reg_reg(mRegN dst, mRegN src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8822 match(Set dst (CMoveN (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8823 ins_cost(80);
8824 format %{
8825 "CMP$cop $tmp1,$tmp2\t @cmovN_cmpI_reg_reg\n\t"
8826 "CMOV $dst,$src\t @cmovN_cmpI_reg_reg"
8827 %}
8828 ins_encode %{
8829 Register op1 = $tmp1$$Register;
8830 Register op2 = $tmp2$$Register;
8831 Register dst = $dst$$Register;
8832 Register src = $src$$Register;
8833 int flag = $cop$$cmpcode;
8835 switch(flag)
8836 {
8837 case 0x01: //equal
8838 __ subu32(AT, op1, op2);
8839 __ movz(dst, src, AT);
8840 break;
8842 case 0x02: //not_equal
8843 __ subu32(AT, op1, op2);
8844 __ movn(dst, src, AT);
8845 break;
8847 case 0x03: //above
8848 __ slt(AT, op2, op1);
8849 __ movn(dst, src, AT);
8850 break;
8852 case 0x04: //above_equal
8853 __ slt(AT, op1, op2);
8854 __ movz(dst, src, AT);
8855 break;
8857 case 0x05: //below
8858 __ slt(AT, op1, op2);
8859 __ movn(dst, src, AT);
8860 break;
8862 case 0x06: //below_equal
8863 __ slt(AT, op2, op1);
8864 __ movz(dst, src, AT);
8865 break;
8867 default:
8868 Unimplemented();
8869 }
8870 %}
8872 ins_pipe( pipe_slow );
8873 %}
8876 instruct cmovL_cmpI_reg_reg(mRegL dst, mRegL src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8877 match(Set dst (CMoveL (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8878 ins_cost(80);
8879 format %{
8880 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpI_reg_reg\n"
8881 "\tCMOV $dst,$src \t @cmovL_cmpI_reg_reg"
8882 %}
8884 ins_encode %{
8885 Register op1 = $tmp1$$Register;
8886 Register op2 = $tmp2$$Register;
8887 Register dst = as_Register($dst$$reg);
8888 Register src = as_Register($src$$reg);
8889 int flag = $cop$$cmpcode;
8891 switch(flag)
8892 {
8893 case 0x01: //equal
8894 __ subu32(AT, op1, op2);
8895 __ movz(dst, src, AT);
8896 break;
8898 case 0x02: //not_equal
8899 __ subu32(AT, op1, op2);
8900 __ movn(dst, src, AT);
8901 break;
8903 case 0x03: //great
8904 __ slt(AT, op2, op1);
8905 __ movn(dst, src, AT);
8906 break;
8908 case 0x04: //great_equal
8909 __ slt(AT, op1, op2);
8910 __ movz(dst, src, AT);
8911 break;
8913 case 0x05: //less
8914 __ slt(AT, op1, op2);
8915 __ movn(dst, src, AT);
8916 break;
8918 case 0x06: //less_equal
8919 __ slt(AT, op2, op1);
8920 __ movz(dst, src, AT);
8921 break;
8923 default:
8924 Unimplemented();
8925 }
8926 %}
8928 ins_pipe( pipe_slow );
8929 %}
8931 instruct cmovL_cmpL_reg_reg(mRegL dst, mRegL src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8932 match(Set dst (CMoveL (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8933 ins_cost(80);
8934 format %{
8935 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpL_reg_reg\n"
8936 "\tCMOV $dst,$src \t @cmovL_cmpL_reg_reg"
8937 %}
8938 ins_encode %{
8939 Register opr1 = as_Register($tmp1$$reg);
8940 Register opr2 = as_Register($tmp2$$reg);
8941 Register dst = as_Register($dst$$reg);
8942 Register src = as_Register($src$$reg);
8943 int flag = $cop$$cmpcode;
8945 switch(flag)
8946 {
8947 case 0x01: //equal
8948 __ subu(AT, opr1, opr2);
8949 __ movz(dst, src, AT);
8950 break;
8952 case 0x02: //not_equal
8953 __ subu(AT, opr1, opr2);
8954 __ movn(dst, src, AT);
8955 break;
8957 case 0x03: //greater
8958 __ slt(AT, opr2, opr1);
8959 __ movn(dst, src, AT);
8960 break;
8962 case 0x04: //greater_equal
8963 __ slt(AT, opr1, opr2);
8964 __ movz(dst, src, AT);
8965 break;
8967 case 0x05: //less
8968 __ slt(AT, opr1, opr2);
8969 __ movn(dst, src, AT);
8970 break;
8972 case 0x06: //less_equal
8973 __ slt(AT, opr2, opr1);
8974 __ movz(dst, src, AT);
8975 break;
8977 default:
8978 Unimplemented();
8979 }
8980 %}
8982 ins_pipe( pipe_slow );
8983 %}
8985 instruct cmovL_cmpN_reg_reg(mRegL dst, mRegL src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8986 match(Set dst (CMoveL (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8987 ins_cost(80);
8988 format %{
8989 "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpN_reg_reg\n\t"
8990 "CMOV $dst,$src\t @cmovL_cmpN_reg_reg"
8991 %}
8992 ins_encode %{
8993 Register op1 = $tmp1$$Register;
8994 Register op2 = $tmp2$$Register;
8995 Register dst = $dst$$Register;
8996 Register src = $src$$Register;
8997 int flag = $cop$$cmpcode;
8999 switch(flag)
9000 {
9001 case 0x01: //equal
9002 __ subu32(AT, op1, op2);
9003 __ movz(dst, src, AT);
9004 break;
9006 case 0x02: //not_equal
9007 __ subu32(AT, op1, op2);
9008 __ movn(dst, src, AT);
9009 break;
9011 case 0x03: //above
9012 __ sltu(AT, op2, op1);
9013 __ movn(dst, src, AT);
9014 break;
9016 case 0x04: //above_equal
9017 __ sltu(AT, op1, op2);
9018 __ movz(dst, src, AT);
9019 break;
9021 case 0x05: //below
9022 __ sltu(AT, op1, op2);
9023 __ movn(dst, src, AT);
9024 break;
9026 case 0x06: //below_equal
9027 __ sltu(AT, op2, op1);
9028 __ movz(dst, src, AT);
9029 break;
9031 default:
9032 Unimplemented();
9033 }
9034 %}
9036 ins_pipe( pipe_slow );
9037 %}
9040 instruct cmovL_cmpD_reg_reg(mRegL dst, mRegL src, regD tmp1, regD tmp2, cmpOp cop ) %{
9041 match(Set dst (CMoveL (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
9042 ins_cost(80);
9043 format %{
9044 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpD_reg_reg\n"
9045 "\tCMOV $dst,$src \t @cmovL_cmpD_reg_reg"
9046 %}
9047 ins_encode %{
9048 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
9049 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
9050 Register dst = as_Register($dst$$reg);
9051 Register src = as_Register($src$$reg);
9053 int flag = $cop$$cmpcode;
9055 switch(flag)
9056 {
9057 case 0x01: //equal
9058 __ c_eq_d(reg_op1, reg_op2);
9059 __ movt(dst, src);
9060 break;
9061 case 0x02: //not_equal
9062 __ c_eq_d(reg_op1, reg_op2);
9063 __ movf(dst, src);
9064 break;
9065 case 0x03: //greater
9066 __ c_ole_d(reg_op1, reg_op2);
9067 __ movf(dst, src);
9068 break;
9069 case 0x04: //greater_equal
9070 __ c_olt_d(reg_op1, reg_op2);
9071 __ movf(dst, src);
9072 break;
9073 case 0x05: //less
9074 __ c_ult_d(reg_op1, reg_op2);
9075 __ movt(dst, src);
9076 break;
9077 case 0x06: //less_equal
9078 __ c_ule_d(reg_op1, reg_op2);
9079 __ movt(dst, src);
9080 break;
9081 default:
9082 Unimplemented();
9083 }
9084 %}
9086 ins_pipe( pipe_slow );
9087 %}
9089 instruct cmovD_cmpD_reg_reg(regD dst, regD src, regD tmp1, regD tmp2, cmpOp cop ) %{
9090 match(Set dst (CMoveD (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
9091 ins_cost(200);
9092 format %{
9093 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpD_reg_reg\n"
9094 "\tCMOV $dst,$src \t @cmovD_cmpD_reg_reg"
9095 %}
9096 ins_encode %{
9097 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
9098 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
9099 FloatRegister dst = as_FloatRegister($dst$$reg);
9100 FloatRegister src = as_FloatRegister($src$$reg);
9102 int flag = $cop$$cmpcode;
9104 Label L;
9106 switch(flag)
9107 {
9108 case 0x01: //equal
9109 __ c_eq_d(reg_op1, reg_op2);
9110 __ bc1f(L);
9111 __ nop();
9112 __ mov_d(dst, src);
9113 __ bind(L);
9114 break;
9115 case 0x02: //not_equal
9116 //2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
9117 __ c_eq_d(reg_op1, reg_op2);
9118 __ bc1t(L);
9119 __ nop();
9120 __ mov_d(dst, src);
9121 __ bind(L);
9122 break;
9123 case 0x03: //greater
9124 __ c_ole_d(reg_op1, reg_op2);
9125 __ bc1t(L);
9126 __ nop();
9127 __ mov_d(dst, src);
9128 __ bind(L);
9129 break;
9130 case 0x04: //greater_equal
9131 __ c_olt_d(reg_op1, reg_op2);
9132 __ bc1t(L);
9133 __ nop();
9134 __ mov_d(dst, src);
9135 __ bind(L);
9136 break;
9137 case 0x05: //less
9138 __ c_ult_d(reg_op1, reg_op2);
9139 __ bc1f(L);
9140 __ nop();
9141 __ mov_d(dst, src);
9142 __ bind(L);
9143 break;
9144 case 0x06: //less_equal
9145 __ c_ule_d(reg_op1, reg_op2);
9146 __ bc1f(L);
9147 __ nop();
9148 __ mov_d(dst, src);
9149 __ bind(L);
9150 break;
9151 default:
9152 Unimplemented();
9153 }
9154 %}
9156 ins_pipe( pipe_slow );
9157 %}
9159 instruct cmovF_cmpI_reg_reg(regF dst, regF src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
9160 match(Set dst (CMoveF (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
9161 ins_cost(200);
9162 format %{
9163 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpI_reg_reg\n"
9164 "\tCMOV $dst, $src \t @cmovF_cmpI_reg_reg"
9165 %}
9167 ins_encode %{
9168 Register op1 = $tmp1$$Register;
9169 Register op2 = $tmp2$$Register;
9170 FloatRegister dst = as_FloatRegister($dst$$reg);
9171 FloatRegister src = as_FloatRegister($src$$reg);
9172 int flag = $cop$$cmpcode;
9173 Label L;
9175 switch(flag)
9176 {
9177 case 0x01: //equal
9178 __ bne(op1, op2, L);
9179 __ nop();
9180 __ mov_s(dst, src);
9181 __ bind(L);
9182 break;
9183 case 0x02: //not_equal
9184 __ beq(op1, op2, L);
9185 __ nop();
9186 __ mov_s(dst, src);
9187 __ bind(L);
9188 break;
9189 case 0x03: //great
9190 __ slt(AT, op2, op1);
9191 __ beq(AT, R0, L);
9192 __ nop();
9193 __ mov_s(dst, src);
9194 __ bind(L);
9195 break;
9196 case 0x04: //great_equal
9197 __ slt(AT, op1, op2);
9198 __ bne(AT, R0, L);
9199 __ nop();
9200 __ mov_s(dst, src);
9201 __ bind(L);
9202 break;
9203 case 0x05: //less
9204 __ slt(AT, op1, op2);
9205 __ beq(AT, R0, L);
9206 __ nop();
9207 __ mov_s(dst, src);
9208 __ bind(L);
9209 break;
9210 case 0x06: //less_equal
9211 __ slt(AT, op2, op1);
9212 __ bne(AT, R0, L);
9213 __ nop();
9214 __ mov_s(dst, src);
9215 __ bind(L);
9216 break;
9217 default:
9218 Unimplemented();
9219 }
9220 %}
9222 ins_pipe( pipe_slow );
9223 %}
9225 instruct cmovD_cmpI_reg_reg(regD dst, regD src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
9226 match(Set dst (CMoveD (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
9227 ins_cost(200);
9228 format %{
9229 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpI_reg_reg\n"
9230 "\tCMOV $dst, $src \t @cmovD_cmpI_reg_reg"
9231 %}
9233 ins_encode %{
9234 Register op1 = $tmp1$$Register;
9235 Register op2 = $tmp2$$Register;
9236 FloatRegister dst = as_FloatRegister($dst$$reg);
9237 FloatRegister src = as_FloatRegister($src$$reg);
9238 int flag = $cop$$cmpcode;
9239 Label L;
9241 switch(flag)
9242 {
9243 case 0x01: //equal
9244 __ bne(op1, op2, L);
9245 __ nop();
9246 __ mov_d(dst, src);
9247 __ bind(L);
9248 break;
9249 case 0x02: //not_equal
9250 __ beq(op1, op2, L);
9251 __ nop();
9252 __ mov_d(dst, src);
9253 __ bind(L);
9254 break;
9255 case 0x03: //great
9256 __ slt(AT, op2, op1);
9257 __ beq(AT, R0, L);
9258 __ nop();
9259 __ mov_d(dst, src);
9260 __ bind(L);
9261 break;
9262 case 0x04: //great_equal
9263 __ slt(AT, op1, op2);
9264 __ bne(AT, R0, L);
9265 __ nop();
9266 __ mov_d(dst, src);
9267 __ bind(L);
9268 break;
9269 case 0x05: //less
9270 __ slt(AT, op1, op2);
9271 __ beq(AT, R0, L);
9272 __ nop();
9273 __ mov_d(dst, src);
9274 __ bind(L);
9275 break;
9276 case 0x06: //less_equal
9277 __ slt(AT, op2, op1);
9278 __ bne(AT, R0, L);
9279 __ nop();
9280 __ mov_d(dst, src);
9281 __ bind(L);
9282 break;
9283 default:
9284 Unimplemented();
9285 }
9286 %}
9288 ins_pipe( pipe_slow );
9289 %}
9291 instruct cmovD_cmpP_reg_reg(regD dst, regD src, mRegP tmp1, mRegP tmp2, cmpOp cop ) %{
9292 match(Set dst (CMoveD (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
9293 ins_cost(200);
9294 format %{
9295 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpP_reg_reg\n"
9296 "\tCMOV $dst, $src \t @cmovD_cmpP_reg_reg"
9297 %}
9299 ins_encode %{
9300 Register op1 = $tmp1$$Register;
9301 Register op2 = $tmp2$$Register;
9302 FloatRegister dst = as_FloatRegister($dst$$reg);
9303 FloatRegister src = as_FloatRegister($src$$reg);
9304 int flag = $cop$$cmpcode;
9305 Label L;
9307 switch(flag)
9308 {
9309 case 0x01: //equal
9310 __ bne(op1, op2, L);
9311 __ nop();
9312 __ mov_d(dst, src);
9313 __ bind(L);
9314 break;
9315 case 0x02: //not_equal
9316 __ beq(op1, op2, L);
9317 __ nop();
9318 __ mov_d(dst, src);
9319 __ bind(L);
9320 break;
9321 case 0x03: //great
9322 __ slt(AT, op2, op1);
9323 __ beq(AT, R0, L);
9324 __ nop();
9325 __ mov_d(dst, src);
9326 __ bind(L);
9327 break;
9328 case 0x04: //great_equal
9329 __ slt(AT, op1, op2);
9330 __ bne(AT, R0, L);
9331 __ nop();
9332 __ mov_d(dst, src);
9333 __ bind(L);
9334 break;
9335 case 0x05: //less
9336 __ slt(AT, op1, op2);
9337 __ beq(AT, R0, L);
9338 __ nop();
9339 __ mov_d(dst, src);
9340 __ bind(L);
9341 break;
9342 case 0x06: //less_equal
9343 __ slt(AT, op2, op1);
9344 __ bne(AT, R0, L);
9345 __ nop();
9346 __ mov_d(dst, src);
9347 __ bind(L);
9348 break;
9349 default:
9350 Unimplemented();
9351 }
9352 %}
9354 ins_pipe( pipe_slow );
9355 %}
9357 //FIXME
9358 instruct cmovI_cmpF_reg_reg(mRegI dst, mRegI src, regF tmp1, regF tmp2, cmpOp cop ) %{
9359 match(Set dst (CMoveI (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
9360 ins_cost(80);
9361 format %{
9362 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpF_reg_reg\n"
9363 "\tCMOV $dst,$src \t @cmovI_cmpF_reg_reg"
9364 %}
9366 ins_encode %{
9367 FloatRegister reg_op1 = $tmp1$$FloatRegister;
9368 FloatRegister reg_op2 = $tmp2$$FloatRegister;
9369 Register dst = $dst$$Register;
9370 Register src = $src$$Register;
9371 int flag = $cop$$cmpcode;
9373 switch(flag)
9374 {
9375 case 0x01: //equal
9376 __ c_eq_s(reg_op1, reg_op2);
9377 __ movt(dst, src);
9378 break;
9379 case 0x02: //not_equal
9380 __ c_eq_s(reg_op1, reg_op2);
9381 __ movf(dst, src);
9382 break;
9383 case 0x03: //greater
9384 __ c_ole_s(reg_op1, reg_op2);
9385 __ movf(dst, src);
9386 break;
9387 case 0x04: //greater_equal
9388 __ c_olt_s(reg_op1, reg_op2);
9389 __ movf(dst, src);
9390 break;
9391 case 0x05: //less
9392 __ c_ult_s(reg_op1, reg_op2);
9393 __ movt(dst, src);
9394 break;
9395 case 0x06: //less_equal
9396 __ c_ule_s(reg_op1, reg_op2);
9397 __ movt(dst, src);
9398 break;
9399 default:
9400 Unimplemented();
9401 }
9402 %}
9403 ins_pipe( pipe_slow );
9404 %}
9406 instruct cmovF_cmpF_reg_reg(regF dst, regF src, regF tmp1, regF tmp2, cmpOp cop ) %{
9407 match(Set dst (CMoveF (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
9408 ins_cost(200);
9409 format %{
9410 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpF_reg_reg\n"
9411 "\tCMOV $dst,$src \t @cmovF_cmpF_reg_reg"
9412 %}
9414 ins_encode %{
9415 FloatRegister reg_op1 = $tmp1$$FloatRegister;
9416 FloatRegister reg_op2 = $tmp2$$FloatRegister;
9417 FloatRegister dst = $dst$$FloatRegister;
9418 FloatRegister src = $src$$FloatRegister;
9419 Label L;
9420 int flag = $cop$$cmpcode;
9422 switch(flag)
9423 {
9424 case 0x01: //equal
9425 __ c_eq_s(reg_op1, reg_op2);
9426 __ bc1f(L);
9427 __ nop();
9428 __ mov_s(dst, src);
9429 __ bind(L);
9430 break;
9431 case 0x02: //not_equal
9432 __ c_eq_s(reg_op1, reg_op2);
9433 __ bc1t(L);
9434 __ nop();
9435 __ mov_s(dst, src);
9436 __ bind(L);
9437 break;
9438 case 0x03: //greater
9439 __ c_ole_s(reg_op1, reg_op2);
9440 __ bc1t(L);
9441 __ nop();
9442 __ mov_s(dst, src);
9443 __ bind(L);
9444 break;
9445 case 0x04: //greater_equal
9446 __ c_olt_s(reg_op1, reg_op2);
9447 __ bc1t(L);
9448 __ nop();
9449 __ mov_s(dst, src);
9450 __ bind(L);
9451 break;
9452 case 0x05: //less
9453 __ c_ult_s(reg_op1, reg_op2);
9454 __ bc1f(L);
9455 __ nop();
9456 __ mov_s(dst, src);
9457 __ bind(L);
9458 break;
9459 case 0x06: //less_equal
9460 __ c_ule_s(reg_op1, reg_op2);
9461 __ bc1f(L);
9462 __ nop();
9463 __ mov_s(dst, src);
9464 __ bind(L);
9465 break;
9466 default:
9467 Unimplemented();
9468 }
9469 %}
9470 ins_pipe( pipe_slow );
9471 %}
9473 // Manifest a CmpL result in an integer register. Very painful.
9474 // This is the test to avoid.
9475 instruct cmpL3_reg_reg(mRegI dst, mRegL src1, mRegL src2) %{
9476 match(Set dst (CmpL3 src1 src2));
9477 ins_cost(1000);
9478 format %{ "cmpL3 $dst, $src1, $src2 @ cmpL3_reg_reg" %}
9479 ins_encode %{
9480 Register opr1 = as_Register($src1$$reg);
9481 Register opr2 = as_Register($src2$$reg);
9482 Register dst = as_Register($dst$$reg);
9484 Label p_one, done;
9486 __ subu(dst, opr1, opr2);
9488 __ beq(dst, R0, done);
9489 __ nop();
9491 __ bgtz(dst, done);
9492 __ delayed()->addiu32(dst, R0, 1);
9494 __ addiu32(dst, R0, -1);
9496 __ bind(done);
9497 %}
9498 ins_pipe( pipe_slow );
9499 %}
9501 //
9502 // less_rsult = -1
9503 // greater_result = 1
9504 // equal_result = 0
9505 // nan_result = -1
9506 //
9507 instruct cmpF3_reg_reg(mRegI dst, regF src1, regF src2) %{
9508 match(Set dst (CmpF3 src1 src2));
9509 ins_cost(1000);
9510 format %{ "cmpF3 $dst, $src1, $src2 @ cmpF3_reg_reg" %}
9511 ins_encode %{
9512 FloatRegister src1 = as_FloatRegister($src1$$reg);
9513 FloatRegister src2 = as_FloatRegister($src2$$reg);
9514 Register dst = as_Register($dst$$reg);
9516 Label EQU, LESS, DONE;
9518 __ move(dst, 1);
9519 __ c_eq_s(src1, src2);
9520 __ bc1t(EQU);
9521 __ nop();
9522 __ c_ult_s(src1, src2);
9523 __ bc1t(LESS);
9524 __ nop();
9525 __ beq(R0, R0, DONE);
9526 __ nop();
9527 __ bind(EQU);
9528 __ move(dst, 0);
9529 __ beq(R0, R0, DONE);
9530 __ nop();
9531 __ bind(LESS);
9532 __ move(dst, -1);
9533 __ bind(DONE);
9534 %}
9535 ins_pipe( pipe_slow );
9536 %}
9538 instruct cmpD3_reg_reg(mRegI dst, regD src1, regD src2) %{
9539 match(Set dst (CmpD3 src1 src2));
9540 ins_cost(1000);
9541 format %{ "cmpD3 $dst, $src1, $src2 @ cmpD3_reg_reg" %}
9542 ins_encode %{
9543 FloatRegister src1 = as_FloatRegister($src1$$reg);
9544 FloatRegister src2 = as_FloatRegister($src2$$reg);
9545 Register dst = as_Register($dst$$reg);
9547 Label EQU, LESS, DONE;
9549 __ move(dst, 1);
9550 __ c_eq_d(src1, src2);
9551 __ bc1t(EQU);
9552 __ nop();
9553 __ c_ult_d(src1, src2);
9554 __ bc1t(LESS);
9555 __ nop();
9556 __ beq(R0, R0, DONE);
9557 __ nop();
9558 __ bind(EQU);
9559 __ move(dst, 0);
9560 __ beq(R0, R0, DONE);
9561 __ nop();
9562 __ bind(LESS);
9563 __ move(dst, -1);
9564 __ bind(DONE);
9565 %}
9566 ins_pipe( pipe_slow );
9567 %}
9569 instruct clear_array(mRegL cnt, mRegP base, Universe dummy) %{
9570 match(Set dummy (ClearArray cnt base));
9571 format %{ "CLEAR_ARRAY base = $base, cnt = $cnt # Clear doublewords" %}
9572 ins_encode %{
9573 //Assume cnt is the number of bytes in an array to be cleared,
9574 //and base points to the starting address of the array.
9575 Register base = $base$$Register;
9576 Register num = $cnt$$Register;
9577 Label Loop, done;
9579 /* 2012/9/21 Jin: according to X86, $cnt is caculated by doublewords(8 bytes) */
9580 __ move(T9, num); /* T9 = words */
9581 __ beq(T9, R0, done);
9582 __ nop();
9583 __ move(AT, base);
9585 __ bind(Loop);
9586 __ sd(R0, Address(AT, 0));
9587 __ daddi(AT, AT, wordSize);
9588 __ daddi(T9, T9, -1);
9589 __ bne(T9, R0, Loop);
9590 __ delayed()->nop();
9591 __ bind(done);
9592 %}
9593 ins_pipe( pipe_slow );
9594 %}
9596 instruct string_compare(a4_RegP str1, mA5RegI cnt1, a6_RegP str2, mA7RegI cnt2, no_Ax_mRegI result) %{
9597 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9598 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);
9600 format %{ "String Compare $str1[len: $cnt1], $str2[len: $cnt2] -> $result @ string_compare" %}
9601 ins_encode %{
9602 // Get the first character position in both strings
9603 // [8] char array, [12] offset, [16] count
9604 Register str1 = $str1$$Register;
9605 Register str2 = $str2$$Register;
9606 Register cnt1 = $cnt1$$Register;
9607 Register cnt2 = $cnt2$$Register;
9608 Register result = $result$$Register;
9610 Label L, Loop, haveResult, done;
9612 // compute the and difference of lengths (in result)
9613 __ subu(result, cnt1, cnt2); // result holds the difference of two lengths
9615 // compute the shorter length (in cnt1)
9616 __ slt(AT, cnt2, cnt1);
9617 __ movn(cnt1, cnt2, AT);
9619 // Now the shorter length is in cnt1 and cnt2 can be used as a tmp register
9620 __ bind(Loop); // Loop begin
9621 __ beq(cnt1, R0, done);
9622 __ delayed()->lhu(AT, str1, 0);;
9624 // compare current character
9625 __ lhu(cnt2, str2, 0);
9626 __ bne(AT, cnt2, haveResult);
9627 __ delayed()->addi(str1, str1, 2);
9628 __ addi(str2, str2, 2);
9629 __ b(Loop);
9630 __ delayed()->addi(cnt1, cnt1, -1); // Loop end
9632 __ bind(haveResult);
9633 __ subu(result, AT, cnt2);
9635 __ bind(done);
9636 %}
9638 ins_pipe( pipe_slow );
9639 %}
9641 // intrinsic optimization
9642 instruct string_equals(a4_RegP str1, a5_RegP str2, mA6RegI cnt, mA7RegI temp, no_Ax_mRegI result) %{
9643 match(Set result (StrEquals (Binary str1 str2) cnt));
9644 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL temp);
9646 format %{ "String Equal $str1, $str2, len:$cnt tmp:$temp -> $result @ string_equals" %}
9647 ins_encode %{
9648 // Get the first character position in both strings
9649 // [8] char array, [12] offset, [16] count
9650 Register str1 = $str1$$Register;
9651 Register str2 = $str2$$Register;
9652 Register cnt = $cnt$$Register;
9653 Register tmp = $temp$$Register;
9654 Register result = $result$$Register;
9656 Label Loop, done;
9659 __ beq(str1, str2, done); // same char[] ?
9660 __ daddiu(result, R0, 1);
9662 __ bind(Loop); // Loop begin
9663 __ beq(cnt, R0, done);
9664 __ daddiu(result, R0, 1); // count == 0
9666 // compare current character
9667 __ lhu(AT, str1, 0);;
9668 __ lhu(tmp, str2, 0);
9669 __ bne(AT, tmp, done);
9670 __ delayed()->daddi(result, R0, 0);
9671 __ addi(str1, str1, 2);
9672 __ addi(str2, str2, 2);
9673 __ b(Loop);
9674 __ delayed()->addi(cnt, cnt, -1); // Loop end
9676 __ bind(done);
9677 %}
9679 ins_pipe( pipe_slow );
9680 %}
9682 //----------Arithmetic Instructions-------------------------------------------
9683 //----------Addition Instructions---------------------------------------------
9684 instruct addI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9685 match(Set dst (AddI src1 src2));
9687 format %{ "add $dst, $src1, $src2 #@addI_Reg_Reg" %}
9688 ins_encode %{
9689 Register dst = $dst$$Register;
9690 Register src1 = $src1$$Register;
9691 Register src2 = $src2$$Register;
9692 __ addu32(dst, src1, src2);
9693 %}
9694 ins_pipe( ialu_regI_regI );
9695 %}
9697 instruct addI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{
9698 match(Set dst (AddI src1 src2));
9700 format %{ "add $dst, $src1, $src2 #@addI_Reg_imm" %}
9701 ins_encode %{
9702 Register dst = $dst$$Register;
9703 Register src1 = $src1$$Register;
9704 int imm = $src2$$constant;
9706 if(Assembler::is_simm16(imm)) {
9707 __ addiu32(dst, src1, imm);
9708 } else {
9709 __ move(AT, imm);
9710 __ addu32(dst, src1, AT);
9711 }
9712 %}
9713 ins_pipe( ialu_regI_regI );
9714 %}
9716 instruct addP_reg_reg(mRegP dst, mRegP src1, mRegL src2) %{
9717 match(Set dst (AddP src1 src2));
9719 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg" %}
9721 ins_encode %{
9722 Register dst = $dst$$Register;
9723 Register src1 = $src1$$Register;
9724 Register src2 = $src2$$Register;
9725 __ daddu(dst, src1, src2);
9726 %}
9728 ins_pipe( ialu_regI_regI );
9729 %}
9731 instruct addP_reg_reg_convI2L(mRegP dst, mRegP src1, mRegI src2) %{
9732 match(Set dst (AddP src1 (ConvI2L src2)));
9734 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg_convI2L" %}
9736 ins_encode %{
9737 Register dst = $dst$$Register;
9738 Register src1 = $src1$$Register;
9739 Register src2 = $src2$$Register;
9740 __ daddu(dst, src1, src2);
9741 %}
9743 ins_pipe( ialu_regI_regI );
9744 %}
9746 instruct addP_reg_imm(mRegP dst, mRegP src1, immL32 src2) %{
9747 match(Set dst (AddP src1 src2));
9748 // effect(KILL cr);
9750 format %{ "daddi $dst, $src1, $src2 #@addP_reg_imm" %}
9751 ins_encode %{
9752 Register src1 = $src1$$Register;
9753 long src2 = $src2$$constant;
9754 Register dst = $dst$$Register;
9756 if(Assembler::is_simm16(src2)) {
9757 __ daddiu(dst, src1, src2);
9758 } else {
9759 __ li(AT, src2);
9760 __ daddu(dst, src1, AT);
9761 }
9762 %}
9763 ins_pipe( ialu_regI_imm16 );
9764 %}
9766 // Add Long Register with Register
9767 instruct addL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
9768 match(Set dst (AddL src1 src2));
9769 ins_cost(200);
9770 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_Reg\t" %}
9772 ins_encode %{
9773 Register dst_reg = as_Register($dst$$reg);
9774 Register src1_reg = as_Register($src1$$reg);
9775 Register src2_reg = as_Register($src2$$reg);
9777 __ daddu(dst_reg, src1_reg, src2_reg);
9778 %}
9780 ins_pipe( ialu_regL_regL );
9781 %}
9783 instruct addL_Reg_imm(mRegL dst, mRegL src1, immL16 src2)
9784 %{
9785 match(Set dst (AddL src1 src2));
9787 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_imm " %}
9788 ins_encode %{
9789 Register dst_reg = as_Register($dst$$reg);
9790 Register src1_reg = as_Register($src1$$reg);
9791 int src2_imm = $src2$$constant;
9793 __ daddiu(dst_reg, src1_reg, src2_imm);
9794 %}
9796 ins_pipe( ialu_regL_regL );
9797 %}
9799 instruct addL_RegI2L_imm(mRegL dst, mRegI src1, immL16 src2)
9800 %{
9801 match(Set dst (AddL (ConvI2L src1) src2));
9803 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_imm " %}
9804 ins_encode %{
9805 Register dst_reg = as_Register($dst$$reg);
9806 Register src1_reg = as_Register($src1$$reg);
9807 int src2_imm = $src2$$constant;
9809 __ daddiu(dst_reg, src1_reg, src2_imm);
9810 %}
9812 ins_pipe( ialu_regL_regL );
9813 %}
9815 instruct addL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{
9816 match(Set dst (AddL (ConvI2L src1) src2));
9817 ins_cost(200);
9818 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_Reg\t" %}
9820 ins_encode %{
9821 Register dst_reg = as_Register($dst$$reg);
9822 Register src1_reg = as_Register($src1$$reg);
9823 Register src2_reg = as_Register($src2$$reg);
9825 __ daddu(dst_reg, src1_reg, src2_reg);
9826 %}
9828 ins_pipe( ialu_regL_regL );
9829 %}
9831 instruct addL_RegI2L_RegI2L(mRegL dst, mRegI src1, mRegI src2) %{
9832 match(Set dst (AddL (ConvI2L src1) (ConvI2L src2)));
9833 ins_cost(200);
9834 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_RegI2L\t" %}
9836 ins_encode %{
9837 Register dst_reg = as_Register($dst$$reg);
9838 Register src1_reg = as_Register($src1$$reg);
9839 Register src2_reg = as_Register($src2$$reg);
9841 __ daddu(dst_reg, src1_reg, src2_reg);
9842 %}
9844 ins_pipe( ialu_regL_regL );
9845 %}
9847 instruct addL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{
9848 match(Set dst (AddL src1 (ConvI2L src2)));
9849 ins_cost(200);
9850 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_RegI2L\t" %}
9852 ins_encode %{
9853 Register dst_reg = as_Register($dst$$reg);
9854 Register src1_reg = as_Register($src1$$reg);
9855 Register src2_reg = as_Register($src2$$reg);
9857 __ daddu(dst_reg, src1_reg, src2_reg);
9858 %}
9860 ins_pipe( ialu_regL_regL );
9861 %}
9863 //----------Subtraction Instructions-------------------------------------------
9864 // Integer Subtraction Instructions
9865 instruct subI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9866 match(Set dst (SubI src1 src2));
9867 ins_cost(100);
9869 format %{ "sub $dst, $src1, $src2 #@subI_Reg_Reg" %}
9870 ins_encode %{
9871 Register dst = $dst$$Register;
9872 Register src1 = $src1$$Register;
9873 Register src2 = $src2$$Register;
9874 __ subu32(dst, src1, src2);
9875 %}
9876 ins_pipe( ialu_regI_regI );
9877 %}
9879 instruct subI_Reg_immI16_sub(mRegI dst, mRegI src1, immI16_sub src2) %{
9880 match(Set dst (SubI src1 src2));
9881 ins_cost(80);
9883 format %{ "sub $dst, $src1, $src2 #@subI_Reg_immI16_sub" %}
9884 ins_encode %{
9885 Register dst = $dst$$Register;
9886 Register src1 = $src1$$Register;
9887 __ addiu32(dst, src1, -1 * $src2$$constant);
9888 %}
9889 ins_pipe( ialu_regI_regI );
9890 %}
9892 instruct negI_Reg(mRegI dst, immI0 zero, mRegI src) %{
9893 match(Set dst (SubI zero src));
9894 ins_cost(80);
9896 format %{ "neg $dst, $src #@negI_Reg" %}
9897 ins_encode %{
9898 Register dst = $dst$$Register;
9899 Register src = $src$$Register;
9900 __ subu32(dst, R0, src);
9901 %}
9902 ins_pipe( ialu_regI_regI );
9903 %}
9905 instruct negL_Reg(mRegL dst, immL0 zero, mRegL src) %{
9906 match(Set dst (SubL zero src));
9907 ins_cost(80);
9909 format %{ "neg $dst, $src #@negL_Reg" %}
9910 ins_encode %{
9911 Register dst = $dst$$Register;
9912 Register src = $src$$Register;
9913 __ subu(dst, R0, src);
9914 %}
9915 ins_pipe( ialu_regI_regI );
9916 %}
9918 instruct subL_Reg_immL16_sub(mRegL dst, mRegL src1, immL16_sub src2) %{
9919 match(Set dst (SubL src1 src2));
9920 ins_cost(80);
9922 format %{ "sub $dst, $src1, $src2 #@subL_Reg_immL16_sub" %}
9923 ins_encode %{
9924 Register dst = $dst$$Register;
9925 Register src1 = $src1$$Register;
9926 __ daddiu(dst, src1, -1 * $src2$$constant);
9927 %}
9928 ins_pipe( ialu_regI_regI );
9929 %}
9931 // Subtract Long Register with Register.
9932 instruct subL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
9933 match(Set dst (SubL src1 src2));
9934 ins_cost(100);
9935 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_Reg" %}
9936 ins_encode %{
9937 Register dst = as_Register($dst$$reg);
9938 Register src1 = as_Register($src1$$reg);
9939 Register src2 = as_Register($src2$$reg);
9941 __ subu(dst, src1, src2);
9942 %}
9943 ins_pipe( ialu_regL_regL );
9944 %}
9946 instruct subL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{
9947 match(Set dst (SubL src1 (ConvI2L src2)));
9948 ins_cost(100);
9949 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_RegI2L" %}
9950 ins_encode %{
9951 Register dst = as_Register($dst$$reg);
9952 Register src1 = as_Register($src1$$reg);
9953 Register src2 = as_Register($src2$$reg);
9955 __ subu(dst, src1, src2);
9956 %}
9957 ins_pipe( ialu_regL_regL );
9958 %}
9960 instruct subL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{
9961 match(Set dst (SubL (ConvI2L src1) src2));
9962 ins_cost(200);
9963 format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_Reg" %}
9964 ins_encode %{
9965 Register dst = as_Register($dst$$reg);
9966 Register src1 = as_Register($src1$$reg);
9967 Register src2 = as_Register($src2$$reg);
9969 __ subu(dst, src1, src2);
9970 %}
9971 ins_pipe( ialu_regL_regL );
9972 %}
9974 instruct subL_RegI2L_RegI2L(mRegL dst, mRegI src1, mRegI src2) %{
9975 match(Set dst (SubL (ConvI2L src1) (ConvI2L src2)));
9976 ins_cost(200);
9977 format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_RegI2L" %}
9978 ins_encode %{
9979 Register dst = as_Register($dst$$reg);
9980 Register src1 = as_Register($src1$$reg);
9981 Register src2 = as_Register($src2$$reg);
9983 __ subu(dst, src1, src2);
9984 %}
9985 ins_pipe( ialu_regL_regL );
9986 %}
9988 // Integer MOD with Register
9989 instruct modI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9990 match(Set dst (ModI src1 src2));
9991 ins_cost(300);
9992 format %{ "modi $dst, $src1, $src2 @ modI_Reg_Reg" %}
9993 ins_encode %{
9994 Register dst = $dst$$Register;
9995 Register src1 = $src1$$Register;
9996 Register src2 = $src2$$Register;
9998 //if (UseLoongsonISA) {
9999 if (0) {
10000 // 2016.08.10
10001 // Experiments show that gsmod is slower that div+mfhi.
10002 // So I just disable it here.
10003 __ gsmod(dst, src1, src2);
10004 } else {
10005 __ div(src1, src2);
10006 __ mfhi(dst);
10007 }
10008 %}
10010 //ins_pipe( ialu_mod );
10011 ins_pipe( ialu_regI_regI );
10012 %}
10014 instruct modL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
10015 match(Set dst (ModL src1 src2));
10016 format %{ "modL $dst, $src1, $src2 @modL_reg_reg" %}
10018 ins_encode %{
10019 Register dst = as_Register($dst$$reg);
10020 Register op1 = as_Register($src1$$reg);
10021 Register op2 = as_Register($src2$$reg);
10023 if (UseLoongsonISA) {
10024 __ gsdmod(dst, op1, op2);
10025 } else {
10026 __ ddiv(op1, op2);
10027 __ mfhi(dst);
10028 }
10029 %}
10030 ins_pipe( pipe_slow );
10031 %}
10033 instruct mulI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
10034 match(Set dst (MulI src1 src2));
10036 ins_cost(300);
10037 format %{ "mul $dst, $src1, $src2 @ mulI_Reg_Reg" %}
10038 ins_encode %{
10039 Register src1 = $src1$$Register;
10040 Register src2 = $src2$$Register;
10041 Register dst = $dst$$Register;
10043 __ mul(dst, src1, src2);
10044 %}
10045 ins_pipe( ialu_mult );
10046 %}
10048 instruct maddI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mRegI src3) %{
10049 match(Set dst (AddI (MulI src1 src2) src3));
10051 ins_cost(999);
10052 format %{ "madd $dst, $src1 * $src2 + $src3 #@maddI_Reg_Reg" %}
10053 ins_encode %{
10054 Register src1 = $src1$$Register;
10055 Register src2 = $src2$$Register;
10056 Register src3 = $src3$$Register;
10057 Register dst = $dst$$Register;
10059 __ mtlo(src3);
10060 __ madd(src1, src2);
10061 __ mflo(dst);
10062 %}
10063 ins_pipe( ialu_mult );
10064 %}
10066 instruct divI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
10067 match(Set dst (DivI src1 src2));
10069 ins_cost(300);
10070 format %{ "div $dst, $src1, $src2 @ divI_Reg_Reg" %}
10071 ins_encode %{
10072 Register src1 = $src1$$Register;
10073 Register src2 = $src2$$Register;
10074 Register dst = $dst$$Register;
10076 /* 2012/4/21 Jin: In MIPS, div does not cause exception.
10077 We must trap an exception manually. */
10078 __ teq(R0, src2, 0x7);
10080 if (UseLoongsonISA) {
10081 __ gsdiv(dst, src1, src2);
10082 } else {
10083 __ div(src1, src2);
10085 __ nop();
10086 __ nop();
10087 __ mflo(dst);
10088 }
10089 %}
10090 ins_pipe( ialu_mod );
10091 %}
10093 instruct divF_Reg_Reg(regF dst, regF src1, regF src2) %{
10094 match(Set dst (DivF src1 src2));
10096 ins_cost(300);
10097 format %{ "divF $dst, $src1, $src2 @ divF_Reg_Reg" %}
10098 ins_encode %{
10099 FloatRegister src1 = $src1$$FloatRegister;
10100 FloatRegister src2 = $src2$$FloatRegister;
10101 FloatRegister dst = $dst$$FloatRegister;
10103 /* Here do we need to trap an exception manually ? */
10104 __ div_s(dst, src1, src2);
10105 %}
10106 ins_pipe( pipe_slow );
10107 %}
10109 instruct divD_Reg_Reg(regD dst, regD src1, regD src2) %{
10110 match(Set dst (DivD src1 src2));
10112 ins_cost(300);
10113 format %{ "divD $dst, $src1, $src2 @ divD_Reg_Reg" %}
10114 ins_encode %{
10115 FloatRegister src1 = $src1$$FloatRegister;
10116 FloatRegister src2 = $src2$$FloatRegister;
10117 FloatRegister dst = $dst$$FloatRegister;
10119 /* Here do we need to trap an exception manually ? */
10120 __ div_d(dst, src1, src2);
10121 %}
10122 ins_pipe( pipe_slow );
10123 %}
10125 instruct mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
10126 match(Set dst (MulL src1 src2));
10127 format %{ "mulL $dst, $src1, $src2 @mulL_reg_reg" %}
10128 ins_encode %{
10129 Register dst = as_Register($dst$$reg);
10130 Register op1 = as_Register($src1$$reg);
10131 Register op2 = as_Register($src2$$reg);
10133 if (UseLoongsonISA) {
10134 __ gsdmult(dst, op1, op2);
10135 } else {
10136 __ dmult(op1, op2);
10137 __ mflo(dst);
10138 }
10139 %}
10140 ins_pipe( pipe_slow );
10141 %}
10143 instruct divL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
10144 match(Set dst (DivL src1 src2));
10145 format %{ "divL $dst, $src1, $src2 @divL_reg_reg" %}
10147 ins_encode %{
10148 Register dst = as_Register($dst$$reg);
10149 Register op1 = as_Register($src1$$reg);
10150 Register op2 = as_Register($src2$$reg);
10152 if (UseLoongsonISA) {
10153 __ gsddiv(dst, op1, op2);
10154 } else {
10155 __ ddiv(op1, op2);
10156 __ mflo(dst);
10157 }
10158 %}
10159 ins_pipe( pipe_slow );
10160 %}
10162 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
10163 match(Set dst (AddF src1 src2));
10164 format %{ "AddF $dst, $src1, $src2 @addF_reg_reg" %}
10165 ins_encode %{
10166 FloatRegister src1 = as_FloatRegister($src1$$reg);
10167 FloatRegister src2 = as_FloatRegister($src2$$reg);
10168 FloatRegister dst = as_FloatRegister($dst$$reg);
10170 __ add_s(dst, src1, src2);
10171 %}
10172 ins_pipe( fpu_regF_regF );
10173 %}
10175 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
10176 match(Set dst (SubF src1 src2));
10177 format %{ "SubF $dst, $src1, $src2 @subF_reg_reg" %}
10178 ins_encode %{
10179 FloatRegister src1 = as_FloatRegister($src1$$reg);
10180 FloatRegister src2 = as_FloatRegister($src2$$reg);
10181 FloatRegister dst = as_FloatRegister($dst$$reg);
10183 __ sub_s(dst, src1, src2);
10184 %}
10185 ins_pipe( fpu_regF_regF );
10186 %}
10187 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
10188 match(Set dst (AddD src1 src2));
10189 format %{ "AddD $dst, $src1, $src2 @addD_reg_reg" %}
10190 ins_encode %{
10191 FloatRegister src1 = as_FloatRegister($src1$$reg);
10192 FloatRegister src2 = as_FloatRegister($src2$$reg);
10193 FloatRegister dst = as_FloatRegister($dst$$reg);
10195 __ add_d(dst, src1, src2);
10196 %}
10197 ins_pipe( fpu_regF_regF );
10198 %}
10200 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
10201 match(Set dst (SubD src1 src2));
10202 format %{ "SubD $dst, $src1, $src2 @subD_reg_reg" %}
10203 ins_encode %{
10204 FloatRegister src1 = as_FloatRegister($src1$$reg);
10205 FloatRegister src2 = as_FloatRegister($src2$$reg);
10206 FloatRegister dst = as_FloatRegister($dst$$reg);
10208 __ sub_d(dst, src1, src2);
10209 %}
10210 ins_pipe( fpu_regF_regF );
10211 %}
10213 instruct negF_reg(regF dst, regF src) %{
10214 match(Set dst (NegF src));
10215 format %{ "negF $dst, $src @negF_reg" %}
10216 ins_encode %{
10217 FloatRegister src = as_FloatRegister($src$$reg);
10218 FloatRegister dst = as_FloatRegister($dst$$reg);
10220 __ neg_s(dst, src);
10221 %}
10222 ins_pipe( fpu_regF_regF );
10223 %}
10225 instruct negD_reg(regD dst, regD src) %{
10226 match(Set dst (NegD src));
10227 format %{ "negD $dst, $src @negD_reg" %}
10228 ins_encode %{
10229 FloatRegister src = as_FloatRegister($src$$reg);
10230 FloatRegister dst = as_FloatRegister($dst$$reg);
10232 __ neg_d(dst, src);
10233 %}
10234 ins_pipe( fpu_regF_regF );
10235 %}
10238 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
10239 match(Set dst (MulF src1 src2));
10240 format %{ "MULF $dst, $src1, $src2 @mulF_reg_reg" %}
10241 ins_encode %{
10242 FloatRegister src1 = $src1$$FloatRegister;
10243 FloatRegister src2 = $src2$$FloatRegister;
10244 FloatRegister dst = $dst$$FloatRegister;
10246 __ mul_s(dst, src1, src2);
10247 %}
10248 ins_pipe( fpu_regF_regF );
10249 %}
10251 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
10252 match(Set dst (AddF (MulF src1 src2) src3));
10253 // For compatibility reason (e.g. on the Loongson platform), disable this guy.
10254 ins_cost(44444);
10255 format %{ "maddF $dst, $src1, $src2, $src3 @maddF_reg_reg" %}
10256 ins_encode %{
10257 FloatRegister src1 = $src1$$FloatRegister;
10258 FloatRegister src2 = $src2$$FloatRegister;
10259 FloatRegister src3 = $src3$$FloatRegister;
10260 FloatRegister dst = $dst$$FloatRegister;
10262 __ madd_s(dst, src1, src2, src3);
10263 %}
10264 ins_pipe( fpu_regF_regF );
10265 %}
10267 // Mul two double precision floating piont number
10268 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
10269 match(Set dst (MulD src1 src2));
10270 format %{ "MULD $dst, $src1, $src2 @mulD_reg_reg" %}
10271 ins_encode %{
10272 FloatRegister src1 = $src1$$FloatRegister;
10273 FloatRegister src2 = $src2$$FloatRegister;
10274 FloatRegister dst = $dst$$FloatRegister;
10276 __ mul_d(dst, src1, src2);
10277 %}
10278 ins_pipe( fpu_regF_regF );
10279 %}
10281 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
10282 match(Set dst (AddD (MulD src1 src2) src3));
10283 // For compatibility reason (e.g. on the Loongson platform), disable this guy.
10284 ins_cost(44444);
10285 format %{ "maddD $dst, $src1, $src2, $src3 @maddD_reg_reg" %}
10286 ins_encode %{
10287 FloatRegister src1 = $src1$$FloatRegister;
10288 FloatRegister src2 = $src2$$FloatRegister;
10289 FloatRegister src3 = $src3$$FloatRegister;
10290 FloatRegister dst = $dst$$FloatRegister;
10292 __ madd_d(dst, src1, src2, src3);
10293 %}
10294 ins_pipe( fpu_regF_regF );
10295 %}
10297 instruct absF_reg(regF dst, regF src) %{
10298 match(Set dst (AbsF src));
10299 ins_cost(100);
10300 format %{ "absF $dst, $src @absF_reg" %}
10301 ins_encode %{
10302 FloatRegister src = as_FloatRegister($src$$reg);
10303 FloatRegister dst = as_FloatRegister($dst$$reg);
10305 __ abs_s(dst, src);
10306 %}
10307 ins_pipe( fpu_regF_regF );
10308 %}
10311 // intrinsics for math_native.
10312 // AbsD SqrtD CosD SinD TanD LogD Log10D
10314 instruct absD_reg(regD dst, regD src) %{
10315 match(Set dst (AbsD src));
10316 ins_cost(100);
10317 format %{ "absD $dst, $src @absD_reg" %}
10318 ins_encode %{
10319 FloatRegister src = as_FloatRegister($src$$reg);
10320 FloatRegister dst = as_FloatRegister($dst$$reg);
10322 __ abs_d(dst, src);
10323 %}
10324 ins_pipe( fpu_regF_regF );
10325 %}
10327 instruct sqrtD_reg(regD dst, regD src) %{
10328 match(Set dst (SqrtD src));
10329 ins_cost(100);
10330 format %{ "SqrtD $dst, $src @sqrtD_reg" %}
10331 ins_encode %{
10332 FloatRegister src = as_FloatRegister($src$$reg);
10333 FloatRegister dst = as_FloatRegister($dst$$reg);
10335 __ sqrt_d(dst, src);
10336 %}
10337 ins_pipe( fpu_regF_regF );
10338 %}
10340 instruct sqrtF_reg(regF dst, regF src) %{
10341 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10342 ins_cost(100);
10343 format %{ "SqrtF $dst, $src @sqrtF_reg" %}
10344 ins_encode %{
10345 FloatRegister src = as_FloatRegister($src$$reg);
10346 FloatRegister dst = as_FloatRegister($dst$$reg);
10348 __ sqrt_s(dst, src);
10349 %}
10350 ins_pipe( fpu_regF_regF );
10351 %}
10352 //----------------------------------Logical Instructions----------------------
10353 //__________________________________Integer Logical Instructions-------------
10355 //And Instuctions
10356 // And Register with Immediate
10357 instruct andI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{
10358 match(Set dst (AndI src1 src2));
10360 format %{ "and $dst, $src1, $src2 #@andI_Reg_imm" %}
10361 ins_encode %{
10362 Register dst = $dst$$Register;
10363 Register src = $src1$$Register;
10364 int val = $src2$$constant;
10366 __ move(AT, val);
10367 __ andr(dst, src, AT);
10368 %}
10369 ins_pipe( ialu_regI_regI );
10370 %}
10372 instruct andI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
10373 match(Set dst (AndI src1 src2));
10374 ins_cost(60);
10376 format %{ "and $dst, $src1, $src2 #@andI_Reg_imm_0_65535" %}
10377 ins_encode %{
10378 Register dst = $dst$$Register;
10379 Register src = $src1$$Register;
10380 int val = $src2$$constant;
10382 __ andi(dst, src, val);
10383 %}
10384 ins_pipe( ialu_regI_regI );
10385 %}
10387 instruct andI_Reg_immI_nonneg_mask(mRegI dst, mRegI src1, immI_nonneg_mask mask) %{
10388 match(Set dst (AndI src1 mask));
10389 ins_cost(60);
10391 format %{ "and $dst, $src1, $mask #@andI_Reg_immI_nonneg_mask" %}
10392 ins_encode %{
10393 Register dst = $dst$$Register;
10394 Register src = $src1$$Register;
10395 int size = Assembler::is_int_mask($mask$$constant);
10397 __ ext(dst, src, 0, size);
10398 %}
10399 ins_pipe( ialu_regI_regI );
10400 %}
10402 instruct andL_Reg_immL_nonneg_mask(mRegL dst, mRegL src1, immL_nonneg_mask mask) %{
10403 match(Set dst (AndL src1 mask));
10404 ins_cost(60);
10406 format %{ "and $dst, $src1, $mask #@andL_Reg_immL_nonneg_mask" %}
10407 ins_encode %{
10408 Register dst = $dst$$Register;
10409 Register src = $src1$$Register;
10410 int size = Assembler::is_jlong_mask($mask$$constant);
10412 __ dext(dst, src, 0, size);
10413 %}
10414 ins_pipe( ialu_regI_regI );
10415 %}
10417 instruct xorI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
10418 match(Set dst (XorI src1 src2));
10419 ins_cost(60);
10421 format %{ "xori $dst, $src1, $src2 #@xorI_Reg_imm_0_65535" %}
10422 ins_encode %{
10423 Register dst = $dst$$Register;
10424 Register src = $src1$$Register;
10425 int val = $src2$$constant;
10427 __ xori(dst, src, val);
10428 %}
10429 ins_pipe( ialu_regI_regI );
10430 %}
10432 instruct xorI_Reg_immI_M1(mRegI dst, mRegI src1, immI_M1 M1) %{
10433 match(Set dst (XorI src1 M1));
10434 predicate(UseLoongsonISA);
10435 ins_cost(60);
10437 format %{ "xor $dst, $src1, $M1 #@xorI_Reg_immI_M1" %}
10438 ins_encode %{
10439 Register dst = $dst$$Register;
10440 Register src = $src1$$Register;
10442 __ gsorn(dst, R0, src);
10443 %}
10444 ins_pipe( ialu_regI_regI );
10445 %}
10447 instruct xorL_Reg_imm_0_65535(mRegL dst, mRegL src1, immL_0_65535 src2) %{
10448 match(Set dst (XorL src1 src2));
10449 ins_cost(60);
10451 format %{ "xori $dst, $src1, $src2 #@xorL_Reg_imm_0_65535" %}
10452 ins_encode %{
10453 Register dst = $dst$$Register;
10454 Register src = $src1$$Register;
10455 int val = $src2$$constant;
10457 __ xori(dst, src, val);
10458 %}
10459 ins_pipe( ialu_regI_regI );
10460 %}
10462 /*
10463 instruct xorL_Reg_immL_M1(mRegL dst, mRegL src1, immL_M1 M1) %{
10464 match(Set dst (XorL src1 M1));
10465 predicate(UseLoongsonISA);
10466 ins_cost(60);
10468 format %{ "xor $dst, $src1, $M1 #@xorL_Reg_immL_M1" %}
10469 ins_encode %{
10470 Register dst = $dst$$Register;
10471 Register src = $src1$$Register;
10473 __ gsorn(dst, R0, src);
10474 %}
10475 ins_pipe( ialu_regI_regI );
10476 %}
10477 */
10479 instruct lbu_and_lmask(mRegI dst, memory mem, immI_255 mask) %{
10480 match(Set dst (AndI mask (LoadB mem)));
10481 ins_cost(60);
10483 format %{ "lhu $dst, $mem #@lbu_and_lmask" %}
10484 ins_encode(load_UB_enc(dst, mem));
10485 ins_pipe( ialu_loadI );
10486 %}
10488 instruct lbu_and_rmask(mRegI dst, memory mem, immI_255 mask) %{
10489 match(Set dst (AndI (LoadB mem) mask));
10490 ins_cost(60);
10492 format %{ "lhu $dst, $mem #@lbu_and_rmask" %}
10493 ins_encode(load_UB_enc(dst, mem));
10494 ins_pipe( ialu_loadI );
10495 %}
10497 instruct andI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
10498 match(Set dst (AndI src1 src2));
10500 format %{ "and $dst, $src1, $src2 #@andI_Reg_Reg" %}
10501 ins_encode %{
10502 Register dst = $dst$$Register;
10503 Register src1 = $src1$$Register;
10504 Register src2 = $src2$$Register;
10505 __ andr(dst, src1, src2);
10506 %}
10507 ins_pipe( ialu_regI_regI );
10508 %}
10510 instruct andnI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10511 match(Set dst (AndI src1 (XorI src2 M1)));
10512 predicate(UseLoongsonISA);
10514 format %{ "andn $dst, $src1, $src2 #@andnI_Reg_nReg" %}
10515 ins_encode %{
10516 Register dst = $dst$$Register;
10517 Register src1 = $src1$$Register;
10518 Register src2 = $src2$$Register;
10520 __ gsandn(dst, src1, src2);
10521 %}
10522 ins_pipe( ialu_regI_regI );
10523 %}
10525 instruct ornI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10526 match(Set dst (OrI src1 (XorI src2 M1)));
10527 predicate(UseLoongsonISA);
10529 format %{ "orn $dst, $src1, $src2 #@ornI_Reg_nReg" %}
10530 ins_encode %{
10531 Register dst = $dst$$Register;
10532 Register src1 = $src1$$Register;
10533 Register src2 = $src2$$Register;
10535 __ gsorn(dst, src1, src2);
10536 %}
10537 ins_pipe( ialu_regI_regI );
10538 %}
10540 instruct andnI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10541 match(Set dst (AndI (XorI src1 M1) src2));
10542 predicate(UseLoongsonISA);
10544 format %{ "andn $dst, $src2, $src1 #@andnI_nReg_Reg" %}
10545 ins_encode %{
10546 Register dst = $dst$$Register;
10547 Register src1 = $src1$$Register;
10548 Register src2 = $src2$$Register;
10550 __ gsandn(dst, src2, src1);
10551 %}
10552 ins_pipe( ialu_regI_regI );
10553 %}
10555 instruct ornI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10556 match(Set dst (OrI (XorI src1 M1) src2));
10557 predicate(UseLoongsonISA);
10559 format %{ "orn $dst, $src2, $src1 #@ornI_nReg_Reg" %}
10560 ins_encode %{
10561 Register dst = $dst$$Register;
10562 Register src1 = $src1$$Register;
10563 Register src2 = $src2$$Register;
10565 __ gsorn(dst, src2, src1);
10566 %}
10567 ins_pipe( ialu_regI_regI );
10568 %}
10570 // And Long Register with Register
10571 instruct andL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10572 match(Set dst (AndL src1 src2));
10573 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg\n\t" %}
10574 ins_encode %{
10575 Register dst_reg = as_Register($dst$$reg);
10576 Register src1_reg = as_Register($src1$$reg);
10577 Register src2_reg = as_Register($src2$$reg);
10579 __ andr(dst_reg, src1_reg, src2_reg);
10580 %}
10581 ins_pipe( ialu_regL_regL );
10582 %}
10584 instruct andL_Reg_Reg_convI2L(mRegL dst, mRegL src1, mRegI src2) %{
10585 match(Set dst (AndL src1 (ConvI2L src2)));
10586 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg_convI2L\n\t" %}
10587 ins_encode %{
10588 Register dst_reg = as_Register($dst$$reg);
10589 Register src1_reg = as_Register($src1$$reg);
10590 Register src2_reg = as_Register($src2$$reg);
10592 __ andr(dst_reg, src1_reg, src2_reg);
10593 %}
10594 ins_pipe( ialu_regL_regL );
10595 %}
10597 instruct andL_Reg_imm_0_65535(mRegL dst, mRegL src1, immL_0_65535 src2) %{
10598 match(Set dst (AndL src1 src2));
10599 ins_cost(60);
10601 format %{ "and $dst, $src1, $src2 #@andL_Reg_imm_0_65535" %}
10602 ins_encode %{
10603 Register dst = $dst$$Register;
10604 Register src = $src1$$Register;
10605 long val = $src2$$constant;
10607 __ andi(dst, src, val);
10608 %}
10609 ins_pipe( ialu_regI_regI );
10610 %}
10612 /*
10613 instruct andnL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10614 match(Set dst (AndL src1 (XorL src2 M1)));
10615 predicate(UseLoongsonISA);
10617 format %{ "andn $dst, $src1, $src2 #@andnL_Reg_nReg" %}
10618 ins_encode %{
10619 Register dst = $dst$$Register;
10620 Register src1 = $src1$$Register;
10621 Register src2 = $src2$$Register;
10623 __ gsandn(dst, src1, src2);
10624 %}
10625 ins_pipe( ialu_regI_regI );
10626 %}
10627 */
10629 /*
10630 instruct ornL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10631 match(Set dst (OrL src1 (XorL src2 M1)));
10632 predicate(UseLoongsonISA);
10634 format %{ "orn $dst, $src1, $src2 #@ornL_Reg_nReg" %}
10635 ins_encode %{
10636 Register dst = $dst$$Register;
10637 Register src1 = $src1$$Register;
10638 Register src2 = $src2$$Register;
10640 __ gsorn(dst, src1, src2);
10641 %}
10642 ins_pipe( ialu_regI_regI );
10643 %}
10644 */
10646 /*
10647 instruct andnL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10648 match(Set dst (AndL (XorL src1 M1) src2));
10649 predicate(UseLoongsonISA);
10651 format %{ "andn $dst, $src2, $src1 #@andnL_nReg_Reg" %}
10652 ins_encode %{
10653 Register dst = $dst$$Register;
10654 Register src1 = $src1$$Register;
10655 Register src2 = $src2$$Register;
10657 __ gsandn(dst, src2, src1);
10658 %}
10659 ins_pipe( ialu_regI_regI );
10660 %}
10661 */
10663 /*
10664 instruct ornL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10665 match(Set dst (OrL (XorL src1 M1) src2));
10666 predicate(UseLoongsonISA);
10668 format %{ "orn $dst, $src2, $src1 #@ornL_nReg_Reg" %}
10669 ins_encode %{
10670 Register dst = $dst$$Register;
10671 Register src1 = $src1$$Register;
10672 Register src2 = $src2$$Register;
10674 __ gsorn(dst, src2, src1);
10675 %}
10676 ins_pipe( ialu_regI_regI );
10677 %}
10678 */
10680 instruct andL_Reg_immL_M8(mRegL dst, immL_M8 M8) %{
10681 match(Set dst (AndL dst M8));
10682 ins_cost(60);
10684 format %{ "and $dst, $dst, $M8 #@andL_Reg_immL_M8" %}
10685 ins_encode %{
10686 Register dst = $dst$$Register;
10688 __ dins(dst, R0, 0, 3);
10689 %}
10690 ins_pipe( ialu_regI_regI );
10691 %}
10693 instruct andL_Reg_immL_M5(mRegL dst, immL_M5 M5) %{
10694 match(Set dst (AndL dst M5));
10695 ins_cost(60);
10697 format %{ "and $dst, $dst, $M5 #@andL_Reg_immL_M5" %}
10698 ins_encode %{
10699 Register dst = $dst$$Register;
10701 __ dins(dst, R0, 2, 1);
10702 %}
10703 ins_pipe( ialu_regI_regI );
10704 %}
10706 instruct andL_Reg_immL_M7(mRegL dst, immL_M7 M7) %{
10707 match(Set dst (AndL dst M7));
10708 ins_cost(60);
10710 format %{ "and $dst, $dst, $M7 #@andL_Reg_immL_M7" %}
10711 ins_encode %{
10712 Register dst = $dst$$Register;
10714 __ dins(dst, R0, 1, 2);
10715 %}
10716 ins_pipe( ialu_regI_regI );
10717 %}
10719 instruct andL_Reg_immL_M4(mRegL dst, immL_M4 M4) %{
10720 match(Set dst (AndL dst M4));
10721 ins_cost(60);
10723 format %{ "and $dst, $dst, $M4 #@andL_Reg_immL_M4" %}
10724 ins_encode %{
10725 Register dst = $dst$$Register;
10727 __ dins(dst, R0, 0, 2);
10728 %}
10729 ins_pipe( ialu_regI_regI );
10730 %}
10732 instruct andL_Reg_immL_M121(mRegL dst, immL_M121 M121) %{
10733 match(Set dst (AndL dst M121));
10734 ins_cost(60);
10736 format %{ "and $dst, $dst, $M121 #@andL_Reg_immL_M121" %}
10737 ins_encode %{
10738 Register dst = $dst$$Register;
10740 __ dins(dst, R0, 3, 4);
10741 %}
10742 ins_pipe( ialu_regI_regI );
10743 %}
10745 // Or Long Register with Register
10746 instruct orL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10747 match(Set dst (OrL src1 src2));
10748 format %{ "OR $dst, $src1, $src2 @ orL_Reg_Reg\t" %}
10749 ins_encode %{
10750 Register dst_reg = $dst$$Register;
10751 Register src1_reg = $src1$$Register;
10752 Register src2_reg = $src2$$Register;
10754 __ orr(dst_reg, src1_reg, src2_reg);
10755 %}
10756 ins_pipe( ialu_regL_regL );
10757 %}
10759 instruct orL_Reg_P2XReg(mRegL dst, mRegP src1, mRegL src2) %{
10760 match(Set dst (OrL (CastP2X src1) src2));
10761 format %{ "OR $dst, $src1, $src2 @ orL_Reg_P2XReg\t" %}
10762 ins_encode %{
10763 Register dst_reg = $dst$$Register;
10764 Register src1_reg = $src1$$Register;
10765 Register src2_reg = $src2$$Register;
10767 __ orr(dst_reg, src1_reg, src2_reg);
10768 %}
10769 ins_pipe( ialu_regL_regL );
10770 %}
10772 // Xor Long Register with Register
10773 instruct xorL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10774 match(Set dst (XorL src1 src2));
10775 format %{ "XOR $dst, $src1, $src2 @ xorL_Reg_Reg\t" %}
10776 ins_encode %{
10777 Register dst_reg = as_Register($dst$$reg);
10778 Register src1_reg = as_Register($src1$$reg);
10779 Register src2_reg = as_Register($src2$$reg);
10781 __ xorr(dst_reg, src1_reg, src2_reg);
10782 %}
10783 ins_pipe( ialu_regL_regL );
10784 %}
10786 // Shift Left by 8-bit immediate
10787 instruct salI_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
10788 match(Set dst (LShiftI src shift));
10790 format %{ "SHL $dst, $src, $shift #@salI_Reg_imm" %}
10791 ins_encode %{
10792 Register src = $src$$Register;
10793 Register dst = $dst$$Register;
10794 int shamt = $shift$$constant;
10796 /*
10797 094 SHL S0, S0, #-7 #@salI_Reg_imm
10798 static int insn_RRSO(int rt, int rd, int sa, int op) { return (rt<<16) | (rd<<11) | (sa<<6) | op; }
10799 void sll (Register rd, Register rt , int sa) {
10800 emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, sll_op));
10801 }
10802 */
10804 if(0 <= shamt && shamt < 32) __ sll(dst, src, shamt);
10805 else {
10806 __ move(AT, shamt);
10807 __ sllv(dst, src, AT);
10808 }
10809 %}
10810 ins_pipe( ialu_regI_regI );
10811 %}
10813 instruct land7_2_s(mRegI dst, mRegL src, immL7 seven, immI_16 sixteen)
10814 %{
10815 match(Set dst (RShiftI (LShiftI (ConvL2I (AndL src seven)) sixteen) sixteen));
10817 format %{ "andi $dst, $src, 7\t# @land7_2_s" %}
10818 ins_encode %{
10819 Register src = $src$$Register;
10820 Register dst = $dst$$Register;
10822 __ andi(dst, src, 7);
10823 %}
10824 ins_pipe(ialu_regI_regI);
10825 %}
10827 instruct ori2s(mRegI dst, mRegI src1, immI_0_32767 src2, immI_16 sixteen)
10828 %{
10829 match(Set dst (RShiftI (LShiftI (OrI src1 src2) sixteen) sixteen));
10831 format %{ "ori $dst, $src1, $src2\t# @ori2s" %}
10832 ins_encode %{
10833 Register src = $src1$$Register;
10834 int val = $src2$$constant;
10835 Register dst = $dst$$Register;
10837 __ ori(dst, src, val);
10838 %}
10839 ins_pipe(ialu_regI_regI);
10840 %}
10842 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
10843 // This idiom is used by the compiler the i2s bytecode.
10844 instruct i2s(mRegI dst, mRegI src, immI_16 sixteen)
10845 %{
10846 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
10848 format %{ "i2s $dst, $src\t# @i2s" %}
10849 ins_encode %{
10850 Register src = $src$$Register;
10851 Register dst = $dst$$Register;
10853 __ seh(dst, src);
10854 %}
10855 ins_pipe(ialu_regI_regI);
10856 %}
10858 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
10859 // This idiom is used by the compiler for the i2b bytecode.
10860 instruct i2b(mRegI dst, mRegI src, immI_24 twentyfour)
10861 %{
10862 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
10864 format %{ "i2b $dst, $src\t# @i2b" %}
10865 ins_encode %{
10866 Register src = $src$$Register;
10867 Register dst = $dst$$Register;
10869 __ seb(dst, src);
10870 %}
10871 ins_pipe(ialu_regI_regI);
10872 %}
10875 instruct salI_RegL2I_imm(mRegI dst, mRegL src, immI8 shift) %{
10876 match(Set dst (LShiftI (ConvL2I src) shift));
10878 format %{ "SHL $dst, $src, $shift #@salI_RegL2I_imm" %}
10879 ins_encode %{
10880 Register src = $src$$Register;
10881 Register dst = $dst$$Register;
10882 int shamt = $shift$$constant;
10884 if(0 <= shamt && shamt < 32) __ sll(dst, src, shamt);
10885 else {
10886 __ move(AT, shamt);
10887 __ sllv(dst, src, AT);
10888 }
10889 %}
10890 ins_pipe( ialu_regI_regI );
10891 %}
10893 // Shift Left by 8-bit immediate
10894 instruct salI_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
10895 match(Set dst (LShiftI src shift));
10897 format %{ "SHL $dst, $src, $shift #@salI_Reg_Reg" %}
10898 ins_encode %{
10899 Register src = $src$$Register;
10900 Register dst = $dst$$Register;
10901 Register shamt = $shift$$Register;
10902 __ sllv(dst, src, shamt);
10903 %}
10904 ins_pipe( ialu_regI_regI );
10905 %}
10908 // Shift Left Long
10909 instruct salL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
10910 //predicate(UseNewLongLShift);
10911 match(Set dst (LShiftL src shift));
10912 ins_cost(100);
10913 format %{ "salL $dst, $src, $shift @ salL_Reg_imm" %}
10914 ins_encode %{
10915 Register src_reg = as_Register($src$$reg);
10916 Register dst_reg = as_Register($dst$$reg);
10917 int shamt = $shift$$constant;
10919 if (__ is_simm(shamt, 5))
10920 __ dsll(dst_reg, src_reg, shamt);
10921 else
10922 {
10923 __ move(AT, shamt);
10924 __ dsllv(dst_reg, src_reg, AT);
10925 }
10926 %}
10927 ins_pipe( ialu_regL_regL );
10928 %}
10930 instruct salL_RegI2L_imm(mRegL dst, mRegI src, immI8 shift) %{
10931 //predicate(UseNewLongLShift);
10932 match(Set dst (LShiftL (ConvI2L src) shift));
10933 ins_cost(100);
10934 format %{ "salL $dst, $src, $shift @ salL_RegI2L_imm" %}
10935 ins_encode %{
10936 Register src_reg = as_Register($src$$reg);
10937 Register dst_reg = as_Register($dst$$reg);
10938 int shamt = $shift$$constant;
10940 if (__ is_simm(shamt, 5))
10941 __ dsll(dst_reg, src_reg, shamt);
10942 else
10943 {
10944 __ move(AT, shamt);
10945 __ dsllv(dst_reg, src_reg, AT);
10946 }
10947 %}
10948 ins_pipe( ialu_regL_regL );
10949 %}
10951 // Shift Left Long
10952 instruct salL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
10953 //predicate(UseNewLongLShift);
10954 match(Set dst (LShiftL src shift));
10955 ins_cost(100);
10956 format %{ "salL $dst, $src, $shift @ salL_Reg_Reg" %}
10957 ins_encode %{
10958 Register creg = T9;
10959 Register src_reg = as_Register($src$$reg);
10960 Register dst_reg = as_Register($dst$$reg);
10962 __ move(creg, $shift$$Register);
10963 __ andi(creg, creg, 0x3f);
10964 __ dsllv(dst_reg, src_reg, creg);
10965 %}
10966 ins_pipe( ialu_regL_regL );
10967 %}
10969 instruct salL_convI2L_Reg_imm(mRegL dst, mRegI src, immI8 shift) %{
10970 match(Set dst (LShiftL (ConvI2L src) shift));
10971 ins_cost(100);
10972 format %{ "salL $dst, $src, $shift @ salL_convI2L_Reg_imm" %}
10973 ins_encode %{
10974 Register src_reg = as_Register($src$$reg);
10975 Register dst_reg = as_Register($dst$$reg);
10976 int shamt = $shift$$constant;
10978 if (__ is_simm(shamt, 5)) {
10979 __ dsll(dst_reg, src_reg, shamt);
10980 } else {
10981 __ move(AT, shamt);
10982 __ dsllv(dst_reg, src_reg, AT);
10983 }
10984 %}
10985 ins_pipe( ialu_regL_regL );
10986 %}
10988 // Shift Right Long
10989 instruct sarL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
10990 //predicate(UseNewLongLShift);
10991 match(Set dst (RShiftL src shift));
10992 ins_cost(100);
10993 format %{ "sarL $dst, $src, $shift @ sarL_Reg_imm" %}
10994 ins_encode %{
10995 Register src_reg = as_Register($src$$reg);
10996 Register dst_reg = as_Register($dst$$reg);
10997 int shamt = ($shift$$constant & 0x3f);
10998 if (__ is_simm(shamt, 5))
10999 __ dsra(dst_reg, src_reg, shamt);
11000 else
11001 {
11002 __ move(AT, shamt);
11003 __ dsrav(dst_reg, src_reg, AT);
11004 }
11005 %}
11006 ins_pipe( ialu_regL_regL );
11007 %}
11009 // Shift Right Long arithmetically
11010 instruct sarL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
11011 //predicate(UseNewLongLShift);
11012 match(Set dst (RShiftL src shift));
11013 ins_cost(100);
11014 format %{ "sarL $dst, $src, $shift @ sarL_Reg_Reg" %}
11015 ins_encode %{
11016 Register creg = T9;
11017 Register src_reg = as_Register($src$$reg);
11018 Register dst_reg = as_Register($dst$$reg);
11020 __ move(creg, $shift$$Register);
11021 __ andi(creg, creg, 0x3f);
11022 __ dsrav(dst_reg, src_reg, creg);
11023 %}
11024 ins_pipe( ialu_regL_regL );
11025 %}
11027 // Shift Right Long logically
11028 instruct slrL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
11029 match(Set dst (URShiftL src shift));
11030 ins_cost(100);
11031 format %{ "slrL $dst, $src, $shift @ slrL_Reg_Reg" %}
11032 ins_encode %{
11033 Register creg = T9;
11034 Register src_reg = as_Register($src$$reg);
11035 Register dst_reg = as_Register($dst$$reg);
11037 __ move(creg, $shift$$Register);
11038 __ andi(creg, creg, 0x3f);
11039 __ dsrlv(dst_reg, src_reg, creg);
11040 %}
11041 ins_pipe( ialu_regL_regL );
11042 %}
11044 instruct slrL_Reg_immI_0_31(mRegL dst, mRegL src, immI_0_31 shift) %{
11045 match(Set dst (URShiftL src shift));
11046 ins_cost(80);
11047 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_0_31" %}
11048 ins_encode %{
11049 Register src_reg = as_Register($src$$reg);
11050 Register dst_reg = as_Register($dst$$reg);
11051 int shamt = $shift$$constant;
11053 __ dsrl(dst_reg, src_reg, shamt);
11054 %}
11055 ins_pipe( ialu_regL_regL );
11056 %}
11058 instruct slrL_P2XReg_immI_0_31(mRegL dst, mRegP src, immI_0_31 shift) %{
11059 match(Set dst (URShiftL (CastP2X src) shift));
11060 ins_cost(80);
11061 format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_0_31" %}
11062 ins_encode %{
11063 Register src_reg = as_Register($src$$reg);
11064 Register dst_reg = as_Register($dst$$reg);
11065 int shamt = $shift$$constant;
11067 __ dsrl(dst_reg, src_reg, shamt);
11068 %}
11069 ins_pipe( ialu_regL_regL );
11070 %}
11072 instruct slrL_Reg_immI_32_63(mRegL dst, mRegL src, immI_32_63 shift) %{
11073 match(Set dst (URShiftL src shift));
11074 ins_cost(80);
11075 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_32_63" %}
11076 ins_encode %{
11077 Register src_reg = as_Register($src$$reg);
11078 Register dst_reg = as_Register($dst$$reg);
11079 int shamt = $shift$$constant;
11081 __ dsrl32(dst_reg, src_reg, shamt - 32);
11082 %}
11083 ins_pipe( ialu_regL_regL );
11084 %}
11086 instruct slrL_P2XReg_immI_32_63(mRegL dst, mRegP src, immI_32_63 shift) %{
11087 match(Set dst (URShiftL (CastP2X src) shift));
11088 ins_cost(80);
11089 format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_32_63" %}
11090 ins_encode %{
11091 Register src_reg = as_Register($src$$reg);
11092 Register dst_reg = as_Register($dst$$reg);
11093 int shamt = $shift$$constant;
11095 __ dsrl32(dst_reg, src_reg, shamt - 32);
11096 %}
11097 ins_pipe( ialu_regL_regL );
11098 %}
11100 // Xor Instructions
11101 // Xor Register with Register
11102 instruct xorI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
11103 match(Set dst (XorI src1 src2));
11105 format %{ "XOR $dst, $src1, $src2 #@xorI_Reg_Reg" %}
11107 ins_encode %{
11108 Register dst = $dst$$Register;
11109 Register src1 = $src1$$Register;
11110 Register src2 = $src2$$Register;
11111 __ xorr(dst, src1, src2);
11112 __ sll(dst, dst, 0); /* long -> int */
11113 %}
11115 ins_pipe( ialu_regI_regI );
11116 %}
11118 // Or Instructions
11119 // Or Register with Register
11120 instruct orI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
11121 match(Set dst (OrI src1 src2));
11123 format %{ "OR $dst, $src1, $src2 #@orI_Reg_Reg" %}
11124 ins_encode %{
11125 Register dst = $dst$$Register;
11126 Register src1 = $src1$$Register;
11127 Register src2 = $src2$$Register;
11128 __ orr(dst, src1, src2);
11129 %}
11131 ins_pipe( ialu_regI_regI );
11132 %}
11134 instruct orI_Reg_castP2X(mRegL dst, mRegL src1, mRegP src2) %{
11135 match(Set dst (OrI src1 (CastP2X src2)));
11137 format %{ "OR $dst, $src1, $src2 #@orI_Reg_castP2X" %}
11138 ins_encode %{
11139 Register dst = $dst$$Register;
11140 Register src1 = $src1$$Register;
11141 Register src2 = $src2$$Register;
11142 __ orr(dst, src1, src2);
11143 %}
11145 ins_pipe( ialu_regI_regI );
11146 %}
11148 // Logical Shift Right by 8-bit immediate
11149 instruct shr_logical_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
11150 match(Set dst (URShiftI src shift));
11151 // effect(KILL cr);
11153 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_imm" %}
11154 ins_encode %{
11155 Register src = $src$$Register;
11156 Register dst = $dst$$Register;
11157 int shift = $shift$$constant;
11158 if (shift > 0)
11159 __ srl(dst, src, shift);
11160 else
11161 {
11162 __ move(AT, shift);
11163 __ srlv(dst, src, AT);
11164 }
11165 %}
11166 ins_pipe( ialu_regI_regI );
11167 %}
11169 instruct shr_logical_Reg_imm_nonneg_mask(mRegI dst, mRegI src, immI_0_31 shift, immI_nonneg_mask mask) %{
11170 match(Set dst (AndI (URShiftI src shift) mask));
11172 format %{ "ext $dst, $src, $shift, one-bits($mask) #@shr_logical_Reg_imm_nonneg_mask" %}
11173 ins_encode %{
11174 Register src = $src$$Register;
11175 Register dst = $dst$$Register;
11176 int pos = $shift$$constant;
11177 int size = Assembler::is_int_mask($mask$$constant);
11179 __ ext(dst, src, pos, size);
11180 %}
11181 ins_pipe( ialu_regI_regI );
11182 %}
11184 // Logical Shift Right
11185 instruct shr_logical_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
11186 match(Set dst (URShiftI src shift));
11188 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_Reg" %}
11189 ins_encode %{
11190 Register src = $src$$Register;
11191 Register dst = $dst$$Register;
11192 Register shift = $shift$$Register;
11193 __ srlv(dst, src, shift);
11194 %}
11195 ins_pipe( ialu_regI_regI );
11196 %}
11199 instruct shr_arith_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
11200 match(Set dst (RShiftI src shift));
11201 // effect(KILL cr);
11203 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_imm" %}
11204 ins_encode %{
11205 Register src = $src$$Register;
11206 Register dst = $dst$$Register;
11207 int shift = $shift$$constant;
11208 __ sra(dst, src, shift);
11209 %}
11210 ins_pipe( ialu_regI_regI );
11211 %}
11213 instruct shr_arith_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
11214 match(Set dst (RShiftI src shift));
11215 // effect(KILL cr);
11217 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_Reg" %}
11218 ins_encode %{
11219 Register src = $src$$Register;
11220 Register dst = $dst$$Register;
11221 Register shift = $shift$$Register;
11222 __ srav(dst, src, shift);
11223 %}
11224 ins_pipe( ialu_regI_regI );
11225 %}
11227 //----------Convert Int to Boolean---------------------------------------------
11229 instruct convI2B(mRegI dst, mRegI src) %{
11230 match(Set dst (Conv2B src));
11232 ins_cost(100);
11233 format %{ "convI2B $dst, $src @ convI2B" %}
11234 ins_encode %{
11235 Register dst = as_Register($dst$$reg);
11236 Register src = as_Register($src$$reg);
11238 if (dst != src) {
11239 __ daddiu(dst, R0, 1);
11240 __ movz(dst, R0, src);
11241 } else {
11242 __ move(AT, src);
11243 __ daddiu(dst, R0, 1);
11244 __ movz(dst, R0, AT);
11245 }
11246 %}
11248 ins_pipe( ialu_regL_regL );
11249 %}
11251 instruct convI2L_reg( mRegL dst, mRegI src) %{
11252 match(Set dst (ConvI2L src));
11254 ins_cost(100);
11255 format %{ "SLL $dst, $src @ convI2L_reg\t" %}
11256 ins_encode %{
11257 Register dst = as_Register($dst$$reg);
11258 Register src = as_Register($src$$reg);
11260 if(dst != src) __ sll(dst, src, 0);
11261 %}
11262 ins_pipe( ialu_regL_regL );
11263 %}
11266 instruct convL2I_reg( mRegI dst, mRegL src ) %{
11267 match(Set dst (ConvL2I src));
11269 format %{ "MOV $dst, $src @ convL2I_reg" %}
11270 ins_encode %{
11271 Register dst = as_Register($dst$$reg);
11272 Register src = as_Register($src$$reg);
11274 __ sll(dst, src, 0);
11275 %}
11277 ins_pipe( ialu_regI_regI );
11278 %}
11280 instruct convL2I2L_reg( mRegL dst, mRegL src ) %{
11281 match(Set dst (ConvI2L (ConvL2I src)));
11283 format %{ "sll $dst, $src, 0 @ convL2I2L_reg" %}
11284 ins_encode %{
11285 Register dst = as_Register($dst$$reg);
11286 Register src = as_Register($src$$reg);
11288 __ sll(dst, src, 0);
11289 %}
11291 ins_pipe( ialu_regI_regI );
11292 %}
11294 instruct convL2D_reg( regD dst, mRegL src ) %{
11295 match(Set dst (ConvL2D src));
11296 format %{ "convL2D $dst, $src @ convL2D_reg" %}
11297 ins_encode %{
11298 Register src = as_Register($src$$reg);
11299 FloatRegister dst = as_FloatRegister($dst$$reg);
11301 __ dmtc1(src, dst);
11302 __ cvt_d_l(dst, dst);
11303 %}
11305 ins_pipe( pipe_slow );
11306 %}
11308 instruct convD2L_reg( mRegL dst, regD src ) %{
11309 match(Set dst (ConvD2L src));
11310 format %{ "convD2L $dst, $src @ convD2L_reg" %}
11311 ins_encode %{
11312 Register dst = as_Register($dst$$reg);
11313 FloatRegister src = as_FloatRegister($src$$reg);
11315 Label L;
11317 __ c_un_d(src, src); //NaN?
11318 __ bc1t(L);
11319 __ delayed();
11320 __ move(dst, R0);
11322 __ trunc_l_d(F30, src);
11323 __ cfc1(AT, 31);
11324 __ li(T9, 0x10000);
11325 __ andr(AT, AT, T9);
11326 __ beq(AT, R0, L);
11327 __ delayed()->dmfc1(dst, F30);
11329 __ mov_d(F12, src);
11330 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l), 1);
11331 __ move(dst, V0);
11332 __ bind(L);
11333 %}
11335 ins_pipe( pipe_slow );
11336 %}
11338 instruct convF2I_reg( mRegI dst, regF src ) %{
11339 match(Set dst (ConvF2I src));
11340 format %{ "convf2i $dst, $src @ convF2I_reg" %}
11341 ins_encode %{
11342 Register dreg = $dst$$Register;
11343 FloatRegister fval = $src$$FloatRegister;
11344 Label L;
11346 __ c_un_s(fval, fval); //NaN?
11347 __ bc1t(L);
11348 __ delayed();
11349 __ move(dreg, R0);
11351 __ trunc_w_s(F30, fval);
11353 /* Call SharedRuntime:f2i() to do valid convention */
11354 __ cfc1(AT, 31);
11355 __ li(T9, 0x10000);
11356 __ andr(AT, AT, T9);
11357 __ beq(AT, R0, L);
11358 __ delayed()->mfc1(dreg, F30);
11360 __ mov_s(F12, fval);
11362 /* 2014/01/08 Fu : This bug was found when running ezDS's control-panel.
11363 * J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
11364 *
11365 * An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
11366 * V0 is corrupted during call_VM_leaf(), and should be preserved.
11367 */
11368 if(dreg != V0) {
11369 __ push(V0);
11370 }
11371 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), 1);
11372 if(dreg != V0) {
11373 __ move(dreg, V0);
11374 __ pop(V0);
11375 }
11376 __ bind(L);
11377 %}
11379 ins_pipe( pipe_slow );
11380 %}
11382 instruct convF2L_reg( mRegL dst, regF src ) %{
11383 match(Set dst (ConvF2L src));
11384 format %{ "convf2l $dst, $src @ convF2L_reg" %}
11385 ins_encode %{
11386 Register dst = as_Register($dst$$reg);
11387 FloatRegister fval = $src$$FloatRegister;
11388 Label L;
11390 __ c_un_s(fval, fval); //NaN?
11391 __ bc1t(L);
11392 __ delayed();
11393 __ move(dst, R0);
11395 __ trunc_l_s(F30, fval);
11396 __ cfc1(AT, 31);
11397 __ li(T9, 0x10000);
11398 __ andr(AT, AT, T9);
11399 __ beq(AT, R0, L);
11400 __ delayed()->dmfc1(dst, F30);
11402 __ mov_s(F12, fval);
11403 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l), 1);
11404 __ move(dst, V0);
11405 __ bind(L);
11406 %}
11408 ins_pipe( pipe_slow );
11409 %}
11411 instruct convL2F_reg( regF dst, mRegL src ) %{
11412 match(Set dst (ConvL2F src));
11413 format %{ "convl2f $dst, $src @ convL2F_reg" %}
11414 ins_encode %{
11415 FloatRegister dst = $dst$$FloatRegister;
11416 Register src = as_Register($src$$reg);
11417 Label L;
11419 __ dmtc1(src, dst);
11420 __ cvt_s_l(dst, dst);
11421 %}
11423 ins_pipe( pipe_slow );
11424 %}
11426 instruct convI2F_reg( regF dst, mRegI src ) %{
11427 match(Set dst (ConvI2F src));
11428 format %{ "convi2f $dst, $src @ convI2F_reg" %}
11429 ins_encode %{
11430 Register src = $src$$Register;
11431 FloatRegister dst = $dst$$FloatRegister;
11433 __ mtc1(src, dst);
11434 __ cvt_s_w(dst, dst);
11435 %}
11437 ins_pipe( fpu_regF_regF );
11438 %}
11440 instruct cmpLTMask_immI0( mRegI dst, mRegI p, immI0 zero ) %{
11441 match(Set dst (CmpLTMask p zero));
11442 ins_cost(100);
11444 format %{ "sra $dst, $p, 31 @ cmpLTMask_immI0" %}
11445 ins_encode %{
11446 Register src = $p$$Register;
11447 Register dst = $dst$$Register;
11449 __ sra(dst, src, 31);
11450 %}
11451 ins_pipe( pipe_slow );
11452 %}
11455 instruct cmpLTMask( mRegI dst, mRegI p, mRegI q ) %{
11456 match(Set dst (CmpLTMask p q));
11457 ins_cost(400);
11459 format %{ "cmpLTMask $dst, $p, $q @ cmpLTMask" %}
11460 ins_encode %{
11461 Register p = $p$$Register;
11462 Register q = $q$$Register;
11463 Register dst = $dst$$Register;
11465 __ slt(dst, p, q);
11466 __ subu(dst, R0, dst);
11467 %}
11468 ins_pipe( pipe_slow );
11469 %}
11471 instruct convP2B(mRegI dst, mRegP src) %{
11472 match(Set dst (Conv2B src));
11474 ins_cost(100);
11475 format %{ "convP2B $dst, $src @ convP2B" %}
11476 ins_encode %{
11477 Register dst = as_Register($dst$$reg);
11478 Register src = as_Register($src$$reg);
11480 if (dst != src) {
11481 __ daddiu(dst, R0, 1);
11482 __ movz(dst, R0, src);
11483 } else {
11484 __ move(AT, src);
11485 __ daddiu(dst, R0, 1);
11486 __ movz(dst, R0, AT);
11487 }
11488 %}
11490 ins_pipe( ialu_regL_regL );
11491 %}
11494 instruct convI2D_reg_reg(regD dst, mRegI src) %{
11495 match(Set dst (ConvI2D src));
11496 format %{ "conI2D $dst, $src @convI2D_reg" %}
11497 ins_encode %{
11498 Register src = $src$$Register;
11499 FloatRegister dst = $dst$$FloatRegister;
11500 __ mtc1(src, dst);
11501 __ cvt_d_w(dst, dst);
11502 %}
11503 ins_pipe( fpu_regF_regF );
11504 %}
11506 instruct convF2I_reg_reg(mRegI dst, regF src) %{
11507 match(Set dst (ConvF2I src));
11508 format %{ "convF2I $dst, $src\t# @convF2D_reg_reg" %}
11509 ins_encode %{
11510 FloatRegister dst = $dst$$FloatRegister;
11511 FloatRegister src = $src$$FloatRegister;
11513 __ cvt_d_s(dst, src);
11514 %}
11515 ins_pipe( fpu_regF_regF );
11516 %}
11518 instruct convF2D_reg_reg(regD dst, regF src) %{
11519 match(Set dst (ConvF2D src));
11520 format %{ "convF2D $dst, $src\t# @convF2D_reg_reg" %}
11521 ins_encode %{
11522 FloatRegister dst = $dst$$FloatRegister;
11523 FloatRegister src = $src$$FloatRegister;
11525 __ cvt_d_s(dst, src);
11526 %}
11527 ins_pipe( fpu_regF_regF );
11528 %}
11530 instruct convD2F_reg_reg(regF dst, regD src) %{
11531 match(Set dst (ConvD2F src));
11532 format %{ "convD2F $dst, $src\t# @convD2F_reg_reg" %}
11533 ins_encode %{
11534 FloatRegister dst = $dst$$FloatRegister;
11535 FloatRegister src = $src$$FloatRegister;
11537 __ cvt_s_d(dst, src);
11538 %}
11539 ins_pipe( fpu_regF_regF );
11540 %}
11542 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11543 instruct convD2I_reg_reg( mRegI dst, regD src ) %{
11544 match(Set dst (ConvD2I src));
11545 // effect( KILL tmp, KILL cr );//after this instruction, it will release register tmp and cr
11547 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg \n\t" %}
11549 ins_encode %{
11550 FloatRegister src = $src$$FloatRegister;
11551 Register dst = $dst$$Register;
11552 Label L;
11554 __ trunc_w_d(F30, src);
11555 __ cfc1(AT, 31);
11556 __ li(T9, 0x10000);
11557 __ andr(AT, AT, T9);
11558 __ beq(AT, R0, L);
11559 __ delayed()->mfc1(dst, F30);
11561 __ mov_d(F12, src);
11562 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 1);
11563 __ move(dst, V0);
11564 __ bind(L);
11566 %}
11567 ins_pipe( pipe_slow );
11568 %}
11570 // Convert oop pointer into compressed form
11571 instruct encodeHeapOop(mRegN dst, mRegP src) %{
11572 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
11573 match(Set dst (EncodeP src));
11574 format %{ "encode_heap_oop $dst,$src" %}
11575 ins_encode %{
11576 Register src = $src$$Register;
11577 Register dst = $dst$$Register;
11578 if (src != dst) {
11579 __ move(dst, src);
11580 }
11581 __ encode_heap_oop(dst);
11582 %}
11583 ins_pipe( ialu_regL_regL );
11584 %}
11586 instruct encodeHeapOop_not_null(mRegN dst, mRegP src) %{
11587 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
11588 match(Set dst (EncodeP src));
11589 format %{ "encode_heap_oop_not_null $dst,$src @ encodeHeapOop_not_null" %}
11590 ins_encode %{
11591 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
11592 %}
11593 ins_pipe( ialu_regL_regL );
11594 %}
11596 instruct decodeHeapOop(mRegP dst, mRegN src) %{
11597 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
11598 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
11599 match(Set dst (DecodeN src));
11600 format %{ "decode_heap_oop $dst,$src @ decodeHeapOop" %}
11601 ins_encode %{
11602 Register s = $src$$Register;
11603 Register d = $dst$$Register;
11604 if (s != d) {
11605 __ move(d, s);
11606 }
11607 __ decode_heap_oop(d);
11608 %}
11609 ins_pipe( ialu_regL_regL );
11610 %}
11612 instruct decodeHeapOop_not_null(mRegP dst, mRegN src) %{
11613 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
11614 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
11615 match(Set dst (DecodeN src));
11616 format %{ "decode_heap_oop_not_null $dst,$src @ decodeHeapOop_not_null" %}
11617 ins_encode %{
11618 Register s = $src$$Register;
11619 Register d = $dst$$Register;
11620 if (s != d) {
11621 __ decode_heap_oop_not_null(d, s);
11622 } else {
11623 __ decode_heap_oop_not_null(d);
11624 }
11625 %}
11626 ins_pipe( ialu_regL_regL );
11627 %}
11629 instruct encodeKlass_not_null(mRegN dst, mRegP src) %{
11630 match(Set dst (EncodePKlass src));
11631 format %{ "encode_heap_oop_not_null $dst,$src @ encodeKlass_not_null" %}
11632 ins_encode %{
11633 __ encode_klass_not_null($dst$$Register, $src$$Register);
11634 %}
11635 ins_pipe( ialu_regL_regL );
11636 %}
11638 instruct decodeKlass_not_null(mRegP dst, mRegN src) %{
11639 match(Set dst (DecodeNKlass src));
11640 format %{ "decode_heap_klass_not_null $dst,$src" %}
11641 ins_encode %{
11642 Register s = $src$$Register;
11643 Register d = $dst$$Register;
11644 if (s != d) {
11645 __ decode_klass_not_null(d, s);
11646 } else {
11647 __ decode_klass_not_null(d);
11648 }
11649 %}
11650 ins_pipe( ialu_regL_regL );
11651 %}
11653 //FIXME
11654 instruct tlsLoadP(mRegP dst) %{
11655 match(Set dst (ThreadLocal));
11657 ins_cost(0);
11658 format %{ " get_thread in $dst #@tlsLoadP" %}
11659 ins_encode %{
11660 Register dst = $dst$$Register;
11661 #ifdef OPT_THREAD
11662 __ move(dst, TREG);
11663 #else
11664 __ get_thread(dst);
11665 #endif
11666 %}
11668 ins_pipe( ialu_loadI );
11669 %}
11672 instruct checkCastPP( mRegP dst ) %{
11673 match(Set dst (CheckCastPP dst));
11675 format %{ "#checkcastPP of $dst (empty encoding) #@chekCastPP" %}
11676 ins_encode( /*empty encoding*/ );
11677 ins_pipe( empty );
11678 %}
11680 instruct castPP(mRegP dst)
11681 %{
11682 match(Set dst (CastPP dst));
11684 size(0);
11685 format %{ "# castPP of $dst" %}
11686 ins_encode(/* empty encoding */);
11687 ins_pipe(empty);
11688 %}
11690 instruct castII( mRegI dst ) %{
11691 match(Set dst (CastII dst));
11692 format %{ "#castII of $dst empty encoding" %}
11693 ins_encode( /*empty encoding*/ );
11694 ins_cost(0);
11695 ins_pipe( empty );
11696 %}
11698 // Return Instruction
11699 // Remove the return address & jump to it.
11700 instruct Ret() %{
11701 match(Return);
11702 format %{ "RET #@Ret" %}
11704 ins_encode %{
11705 __ jr(RA);
11706 __ nop();
11707 %}
11709 ins_pipe( pipe_jump );
11710 %}
11712 /*
11713 // For Loongson CPUs, jr seems too slow, so this rule shouldn't be imported.
11714 instruct jumpXtnd(mRegL switch_val) %{
11715 match(Jump switch_val);
11717 ins_cost(350);
11719 format %{ "load T9 <-- [$constanttablebase, $switch_val, $constantoffset] @ jumpXtnd\n\t"
11720 "jr T9\n\t"
11721 "nop" %}
11722 ins_encode %{
11723 Register table_base = $constanttablebase;
11724 int con_offset = $constantoffset;
11725 Register switch_reg = $switch_val$$Register;
11727 if (UseLoongsonISA) {
11728 if (Assembler::is_simm(con_offset, 8)) {
11729 __ gsldx(T9, table_base, switch_reg, con_offset);
11730 } else if (Assembler::is_simm16(con_offset)) {
11731 __ daddu(T9, table_base, switch_reg);
11732 __ ld(T9, T9, con_offset);
11733 } else {
11734 __ move(T9, con_offset);
11735 __ daddu(AT, table_base, switch_reg);
11736 __ gsldx(T9, AT, T9, 0);
11737 }
11738 } else {
11739 if (Assembler::is_simm16(con_offset)) {
11740 __ daddu(T9, table_base, switch_reg);
11741 __ ld(T9, T9, con_offset);
11742 } else {
11743 __ move(T9, con_offset);
11744 __ daddu(AT, table_base, switch_reg);
11745 __ daddu(AT, T9, AT);
11746 __ ld(T9, AT, 0);
11747 }
11748 }
11750 __ jr(T9);
11751 __ nop();
11753 %}
11754 ins_pipe(pipe_jump);
11755 %}
11756 */
11758 // Jump Direct - Label defines a relative address from JMP
11759 instruct jmpDir(label labl) %{
11760 match(Goto);
11761 effect(USE labl);
11763 ins_cost(300);
11764 format %{ "JMP $labl #@jmpDir" %}
11766 ins_encode %{
11767 Label &L = *($labl$$label);
11768 if(&L)
11769 __ b(L);
11770 else
11771 __ b(int(0));
11772 __ nop();
11773 %}
11775 ins_pipe( pipe_jump );
11776 ins_pc_relative(1);
11777 %}
11781 // Tail Jump; remove the return address; jump to target.
11782 // TailCall above leaves the return address around.
11783 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11784 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11785 // "restore" before this instruction (in Epilogue), we need to materialize it
11786 // in %i0.
11787 //FIXME
11788 instruct tailjmpInd(mRegP jump_target,mRegP ex_oop) %{
11789 match( TailJump jump_target ex_oop );
11790 ins_cost(200);
11791 format %{ "Jmp $jump_target ; ex_oop = $ex_oop #@tailjmpInd" %}
11792 ins_encode %{
11793 Register target = $jump_target$$Register;
11795 /* 2012/9/14 Jin: V0, V1 are indicated in:
11796 * [stubGenerator_mips.cpp] generate_forward_exception()
11797 * [runtime_mips.cpp] OptoRuntime::generate_exception_blob()
11798 */
11799 Register oop = $ex_oop$$Register;
11800 Register exception_oop = V0;
11801 Register exception_pc = V1;
11803 __ move(exception_pc, RA);
11804 __ move(exception_oop, oop);
11806 __ jr(target);
11807 __ nop();
11808 %}
11809 ins_pipe( pipe_jump );
11810 %}
11812 // ============================================================================
11813 // Procedure Call/Return Instructions
11814 // Call Java Static Instruction
11815 // Note: If this code changes, the corresponding ret_addr_offset() and
11816 // compute_padding() functions will have to be adjusted.
11817 instruct CallStaticJavaDirect(method meth) %{
11818 match(CallStaticJava);
11819 effect(USE meth);
11821 ins_cost(300);
11822 format %{ "CALL,static #@CallStaticJavaDirect " %}
11823 ins_encode( Java_Static_Call( meth ) );
11824 ins_pipe( pipe_slow );
11825 ins_pc_relative(1);
11826 ins_alignment(16);
11827 %}
11829 // Call Java Dynamic Instruction
11830 // Note: If this code changes, the corresponding ret_addr_offset() and
11831 // compute_padding() functions will have to be adjusted.
11832 instruct CallDynamicJavaDirect(method meth) %{
11833 match(CallDynamicJava);
11834 effect(USE meth);
11836 ins_cost(300);
11837 format %{"MOV IC_Klass, (oop)-1 @ CallDynamicJavaDirect\n\t"
11838 "CallDynamic @ CallDynamicJavaDirect" %}
11839 ins_encode( Java_Dynamic_Call( meth ) );
11840 ins_pipe( pipe_slow );
11841 ins_pc_relative(1);
11842 ins_alignment(16);
11843 %}
11845 instruct CallLeafNoFPDirect(method meth) %{
11846 match(CallLeafNoFP);
11847 effect(USE meth);
11849 ins_cost(300);
11850 format %{ "CALL_LEAF_NOFP,runtime " %}
11851 ins_encode(Java_To_Runtime(meth));
11852 ins_pipe( pipe_slow );
11853 ins_pc_relative(1);
11854 ins_alignment(16);
11855 %}
11857 // Prefetch instructions.
11859 instruct prefetchrNTA( memory mem ) %{
11860 match(PrefetchRead mem);
11861 ins_cost(125);
11863 format %{ "pref $mem\t# Prefetch into non-temporal cache for read @ prefetchrNTA" %}
11864 ins_encode %{
11865 int base = $mem$$base;
11866 int index = $mem$$index;
11867 int scale = $mem$$scale;
11868 int disp = $mem$$disp;
11870 if( index != 0 ) {
11871 if (scale == 0) {
11872 __ daddu(AT, as_Register(base), as_Register(index));
11873 } else {
11874 __ dsll(AT, as_Register(index), scale);
11875 __ daddu(AT, as_Register(base), AT);
11876 }
11877 } else {
11878 __ move(AT, as_Register(base));
11879 }
11880 if( Assembler::is_simm16(disp) ) {
11881 __ daddiu(AT, as_Register(base), disp);
11882 __ daddiu(AT, AT, disp);
11883 } else {
11884 __ move(T9, disp);
11885 __ daddu(AT, as_Register(base), T9);
11886 }
11887 __ pref(0, AT, 0); //hint: 0:load
11888 %}
11889 ins_pipe(pipe_slow);
11890 %}
11892 instruct prefetchwNTA( memory mem ) %{
11893 match(PrefetchWrite mem);
11894 ins_cost(125);
11895 format %{ "pref $mem\t# Prefetch to non-temporal cache for write @ prefetchwNTA" %}
11896 ins_encode %{
11897 int base = $mem$$base;
11898 int index = $mem$$index;
11899 int scale = $mem$$scale;
11900 int disp = $mem$$disp;
11902 if( index != 0 ) {
11903 if (scale == 0) {
11904 __ daddu(AT, as_Register(base), as_Register(index));
11905 } else {
11906 __ dsll(AT, as_Register(index), scale);
11907 __ daddu(AT, as_Register(base), AT);
11908 }
11909 } else {
11910 __ move(AT, as_Register(base));
11911 }
11912 if( Assembler::is_simm16(disp) ) {
11913 __ daddiu(AT, as_Register(base), disp);
11914 __ daddiu(AT, AT, disp);
11915 } else {
11916 __ move(T9, disp);
11917 __ daddu(AT, as_Register(base), T9);
11918 }
11919 __ pref(1, AT, 0); //hint: 1:store
11920 %}
11921 ins_pipe(pipe_slow);
11922 %}
11924 // Prefetch instructions for allocation.
11926 instruct prefetchAllocNTA( memory mem ) %{
11927 match(PrefetchAllocation mem);
11928 ins_cost(125);
11929 format %{ "pref $mem\t# Prefetch allocation @ prefetchAllocNTA" %}
11930 ins_encode %{
11931 int base = $mem$$base;
11932 int index = $mem$$index;
11933 int scale = $mem$$scale;
11934 int disp = $mem$$disp;
11936 Register dst = R0;
11938 if( index != 0 ) {
11939 if( Assembler::is_simm16(disp) ) {
11940 if( UseLoongsonISA ) {
11941 if (scale == 0) {
11942 __ gslbx(dst, as_Register(base), as_Register(index), disp);
11943 } else {
11944 __ dsll(AT, as_Register(index), scale);
11945 __ gslbx(dst, as_Register(base), AT, disp);
11946 }
11947 } else {
11948 if (scale == 0) {
11949 __ addu(AT, as_Register(base), as_Register(index));
11950 } else {
11951 __ dsll(AT, as_Register(index), scale);
11952 __ addu(AT, as_Register(base), AT);
11953 }
11954 __ lb(dst, AT, disp);
11955 }
11956 } else {
11957 if (scale == 0) {
11958 __ addu(AT, as_Register(base), as_Register(index));
11959 } else {
11960 __ dsll(AT, as_Register(index), scale);
11961 __ addu(AT, as_Register(base), AT);
11962 }
11963 __ move(T9, disp);
11964 if( UseLoongsonISA ) {
11965 __ gslbx(dst, AT, T9, 0);
11966 } else {
11967 __ addu(AT, AT, T9);
11968 __ lb(dst, AT, 0);
11969 }
11970 }
11971 } else {
11972 if( Assembler::is_simm16(disp) ) {
11973 __ lb(dst, as_Register(base), disp);
11974 } else {
11975 __ move(T9, disp);
11976 if( UseLoongsonISA ) {
11977 __ gslbx(dst, as_Register(base), T9, 0);
11978 } else {
11979 __ addu(AT, as_Register(base), T9);
11980 __ lb(dst, AT, 0);
11981 }
11982 }
11983 }
11984 %}
11985 ins_pipe(pipe_slow);
11986 %}
11989 // Call runtime without safepoint
11990 instruct CallLeafDirect(method meth) %{
11991 match(CallLeaf);
11992 effect(USE meth);
11994 ins_cost(300);
11995 format %{ "CALL_LEAF,runtime #@CallLeafDirect " %}
11996 ins_encode(Java_To_Runtime(meth));
11997 ins_pipe( pipe_slow );
11998 ins_pc_relative(1);
11999 ins_alignment(16);
12000 %}
12002 // Load Char (16bit unsigned)
12003 instruct loadUS(mRegI dst, memory mem) %{
12004 match(Set dst (LoadUS mem));
12006 ins_cost(125);
12007 format %{ "loadUS $dst,$mem @ loadC" %}
12008 ins_encode(load_C_enc(dst, mem));
12009 ins_pipe( ialu_loadI );
12010 %}
12012 instruct loadUS_convI2L(mRegL dst, memory mem) %{
12013 match(Set dst (ConvI2L (LoadUS mem)));
12015 ins_cost(125);
12016 format %{ "loadUS $dst,$mem @ loadUS_convI2L" %}
12017 ins_encode(load_C_enc(dst, mem));
12018 ins_pipe( ialu_loadI );
12019 %}
12021 // Store Char (16bit unsigned)
12022 instruct storeC(memory mem, mRegI src) %{
12023 match(Set mem (StoreC mem src));
12025 ins_cost(125);
12026 format %{ "storeC $src,$mem @ storeC" %}
12027 ins_encode(store_C_reg_enc(mem, src));
12028 ins_pipe( ialu_loadI );
12029 %}
12032 instruct loadConF0(regF dst, immF0 zero) %{
12033 match(Set dst zero);
12034 ins_cost(100);
12036 format %{ "mov $dst, zero @ loadConF0\n"%}
12037 ins_encode %{
12038 FloatRegister dst = $dst$$FloatRegister;
12040 __ mtc1(R0, dst);
12041 %}
12042 ins_pipe( fpu_loadF );
12043 %}
12046 instruct loadConF(regF dst, immF src) %{
12047 match(Set dst src);
12048 ins_cost(125);
12050 format %{ "lwc1 $dst, $constantoffset[$constanttablebase] # load FLOAT $src from table @ loadConF" %}
12051 ins_encode %{
12052 int con_offset = $constantoffset($src);
12054 if (Assembler::is_simm16(con_offset)) {
12055 __ lwc1($dst$$FloatRegister, $constanttablebase, con_offset);
12056 } else {
12057 __ set64(AT, con_offset);
12058 if (UseLoongsonISA) {
12059 __ gslwxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
12060 } else {
12061 __ daddu(AT, $constanttablebase, AT);
12062 __ lwc1($dst$$FloatRegister, AT, 0);
12063 }
12064 }
12065 %}
12066 ins_pipe( fpu_loadF );
12067 %}
12070 instruct loadConD0(regD dst, immD0 zero) %{
12071 match(Set dst zero);
12072 ins_cost(100);
12074 format %{ "mov $dst, zero @ loadConD0"%}
12075 ins_encode %{
12076 FloatRegister dst = as_FloatRegister($dst$$reg);
12078 __ dmtc1(R0, dst);
12079 %}
12080 ins_pipe( fpu_loadF );
12081 %}
12083 instruct loadConD(regD dst, immD src) %{
12084 match(Set dst src);
12085 ins_cost(125);
12087 format %{ "ldc1 $dst, $constantoffset[$constanttablebase] # load DOUBLE $src from table @ loadConD" %}
12088 ins_encode %{
12089 int con_offset = $constantoffset($src);
12091 if (Assembler::is_simm16(con_offset)) {
12092 __ ldc1($dst$$FloatRegister, $constanttablebase, con_offset);
12093 } else {
12094 __ set64(AT, con_offset);
12095 if (UseLoongsonISA) {
12096 __ gsldxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
12097 } else {
12098 __ daddu(AT, $constanttablebase, AT);
12099 __ ldc1($dst$$FloatRegister, AT, 0);
12100 }
12101 }
12102 %}
12103 ins_pipe( fpu_loadF );
12104 %}
12106 // Store register Float value (it is faster than store from FPU register)
12107 instruct storeF_reg( memory mem, regF src) %{
12108 match(Set mem (StoreF mem src));
12110 ins_cost(50);
12111 format %{ "store $mem, $src\t# store float @ storeF_reg" %}
12112 ins_encode(store_F_reg_enc(mem, src));
12113 ins_pipe( fpu_storeF );
12114 %}
12116 instruct storeF_imm0( memory mem, immF0 zero) %{
12117 match(Set mem (StoreF mem zero));
12119 ins_cost(40);
12120 format %{ "store $mem, zero\t# store float @ storeF_imm0" %}
12121 ins_encode %{
12122 int base = $mem$$base;
12123 int index = $mem$$index;
12124 int scale = $mem$$scale;
12125 int disp = $mem$$disp;
12127 if( index != 0 ) {
12128 if(scale != 0) {
12129 __ dsll(T9, as_Register(index), scale);
12130 __ addu(AT, as_Register(base), T9);
12131 } else {
12132 __ daddu(AT, as_Register(base), as_Register(index));
12133 }
12134 if( Assembler::is_simm16(disp) ) {
12135 __ sw(R0, AT, disp);
12136 } else {
12137 __ move(T9, disp);
12138 __ addu(AT, AT, T9);
12139 __ sw(R0, AT, 0);
12140 }
12142 } else {
12143 if( Assembler::is_simm16(disp) ) {
12144 __ sw(R0, as_Register(base), disp);
12145 } else {
12146 __ move(T9, disp);
12147 __ addu(AT, as_Register(base), T9);
12148 __ sw(R0, AT, 0);
12149 }
12150 }
12151 %}
12152 ins_pipe( ialu_storeI );
12153 %}
12155 // Load Double
12156 instruct loadD(regD dst, memory mem) %{
12157 match(Set dst (LoadD mem));
12159 ins_cost(150);
12160 format %{ "loadD $dst, $mem #@loadD" %}
12161 ins_encode(load_D_enc(dst, mem));
12162 ins_pipe( ialu_loadI );
12163 %}
12165 // Load Double - UNaligned
12166 instruct loadD_unaligned(regD dst, memory mem ) %{
12167 match(Set dst (LoadD_unaligned mem));
12168 ins_cost(250);
12169 // FIXME: Jin: Need more effective ldl/ldr
12170 format %{ "loadD_unaligned $dst, $mem #@loadD_unaligned" %}
12171 ins_encode(load_D_enc(dst, mem));
12172 ins_pipe( ialu_loadI );
12173 %}
12175 instruct storeD_reg( memory mem, regD src) %{
12176 match(Set mem (StoreD mem src));
12178 ins_cost(50);
12179 format %{ "store $mem, $src\t# store float @ storeD_reg" %}
12180 ins_encode(store_D_reg_enc(mem, src));
12181 ins_pipe( fpu_storeF );
12182 %}
12184 instruct storeD_imm0( memory mem, immD0 zero) %{
12185 match(Set mem (StoreD mem zero));
12187 ins_cost(40);
12188 format %{ "store $mem, zero\t# store float @ storeD_imm0" %}
12189 ins_encode %{
12190 int base = $mem$$base;
12191 int index = $mem$$index;
12192 int scale = $mem$$scale;
12193 int disp = $mem$$disp;
12195 __ mtc1(R0, F30);
12196 __ cvt_d_w(F30, F30);
12198 if( index != 0 ) {
12199 if(scale != 0) {
12200 __ dsll(T9, as_Register(index), scale);
12201 __ addu(AT, as_Register(base), T9);
12202 } else {
12203 __ daddu(AT, as_Register(base), as_Register(index));
12204 }
12205 if( Assembler::is_simm16(disp) ) {
12206 __ sdc1(F30, AT, disp);
12207 } else {
12208 __ move(T9, disp);
12209 __ addu(AT, AT, T9);
12210 __ sdc1(F30, AT, 0);
12211 }
12213 } else {
12214 if( Assembler::is_simm16(disp) ) {
12215 __ sdc1(F30, as_Register(base), disp);
12216 } else {
12217 __ move(T9, disp);
12218 __ addu(AT, as_Register(base), T9);
12219 __ sdc1(F30, AT, 0);
12220 }
12221 }
12222 %}
12223 ins_pipe( ialu_storeI );
12224 %}
12226 instruct loadSSI(mRegI dst, stackSlotI src)
12227 %{
12228 match(Set dst src);
12230 ins_cost(125);
12231 format %{ "lw $dst, $src\t# int stk @ loadSSI" %}
12232 ins_encode %{
12233 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSI) !");
12234 __ lw($dst$$Register, SP, $src$$disp);
12235 %}
12236 ins_pipe(ialu_loadI);
12237 %}
12239 instruct storeSSI(stackSlotI dst, mRegI src)
12240 %{
12241 match(Set dst src);
12243 ins_cost(100);
12244 format %{ "sw $dst, $src\t# int stk @ storeSSI" %}
12245 ins_encode %{
12246 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSI) !");
12247 __ sw($src$$Register, SP, $dst$$disp);
12248 %}
12249 ins_pipe(ialu_storeI);
12250 %}
12252 instruct loadSSL(mRegL dst, stackSlotL src)
12253 %{
12254 match(Set dst src);
12256 ins_cost(125);
12257 format %{ "ld $dst, $src\t# long stk @ loadSSL" %}
12258 ins_encode %{
12259 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSL) !");
12260 __ ld($dst$$Register, SP, $src$$disp);
12261 %}
12262 ins_pipe(ialu_loadI);
12263 %}
12265 instruct storeSSL(stackSlotL dst, mRegL src)
12266 %{
12267 match(Set dst src);
12269 ins_cost(100);
12270 format %{ "sd $dst, $src\t# long stk @ storeSSL" %}
12271 ins_encode %{
12272 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSL) !");
12273 __ sd($src$$Register, SP, $dst$$disp);
12274 %}
12275 ins_pipe(ialu_storeI);
12276 %}
12278 instruct loadSSP(mRegP dst, stackSlotP src)
12279 %{
12280 match(Set dst src);
12282 ins_cost(125);
12283 format %{ "ld $dst, $src\t# ptr stk @ loadSSP" %}
12284 ins_encode %{
12285 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSP) !");
12286 __ ld($dst$$Register, SP, $src$$disp);
12287 %}
12288 ins_pipe(ialu_loadI);
12289 %}
12291 instruct storeSSP(stackSlotP dst, mRegP src)
12292 %{
12293 match(Set dst src);
12295 ins_cost(100);
12296 format %{ "sd $dst, $src\t# ptr stk @ storeSSP" %}
12297 ins_encode %{
12298 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSP) !");
12299 __ sd($src$$Register, SP, $dst$$disp);
12300 %}
12301 ins_pipe(ialu_storeI);
12302 %}
12304 instruct loadSSF(regF dst, stackSlotF src)
12305 %{
12306 match(Set dst src);
12308 ins_cost(125);
12309 format %{ "lwc1 $dst, $src\t# float stk @ loadSSF" %}
12310 ins_encode %{
12311 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSF) !");
12312 __ lwc1($dst$$FloatRegister, SP, $src$$disp);
12313 %}
12314 ins_pipe(ialu_loadI);
12315 %}
12317 instruct storeSSF(stackSlotF dst, regF src)
12318 %{
12319 match(Set dst src);
12321 ins_cost(100);
12322 format %{ "swc1 $dst, $src\t# float stk @ storeSSF" %}
12323 ins_encode %{
12324 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSF) !");
12325 __ swc1($src$$FloatRegister, SP, $dst$$disp);
12326 %}
12327 ins_pipe(fpu_storeF);
12328 %}
12330 // Use the same format since predicate() can not be used here.
12331 instruct loadSSD(regD dst, stackSlotD src)
12332 %{
12333 match(Set dst src);
12335 ins_cost(125);
12336 format %{ "ldc1 $dst, $src\t# double stk @ loadSSD" %}
12337 ins_encode %{
12338 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSD) !");
12339 __ ldc1($dst$$FloatRegister, SP, $src$$disp);
12340 %}
12341 ins_pipe(ialu_loadI);
12342 %}
12344 instruct storeSSD(stackSlotD dst, regD src)
12345 %{
12346 match(Set dst src);
12348 ins_cost(100);
12349 format %{ "sdc1 $dst, $src\t# double stk @ storeSSD" %}
12350 ins_encode %{
12351 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSD) !");
12352 __ sdc1($src$$FloatRegister, SP, $dst$$disp);
12353 %}
12354 ins_pipe(fpu_storeF);
12355 %}
12357 instruct cmpFastLock( FlagsReg cr, mRegP object, s0_RegP box, mRegI tmp, mRegP scr) %{
12358 match( Set cr (FastLock object box) );
12359 effect( TEMP tmp, TEMP scr, USE_KILL box );
12360 ins_cost(300);
12361 format %{ "FASTLOCK $cr $object, $box, $tmp #@ cmpFastLock" %}
12362 ins_encode %{
12363 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register);
12364 %}
12366 ins_pipe( pipe_slow );
12367 ins_pc_relative(1);
12368 %}
12370 instruct cmpFastUnlock( FlagsReg cr, mRegP object, s0_RegP box, mRegP tmp ) %{
12371 match( Set cr (FastUnlock object box) );
12372 effect( TEMP tmp, USE_KILL box );
12373 ins_cost(300);
12374 format %{ "FASTUNLOCK $object, $box, $tmp #@cmpFastUnlock" %}
12375 ins_encode %{
12376 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
12377 %}
12379 ins_pipe( pipe_slow );
12380 ins_pc_relative(1);
12381 %}
12383 // Store CMS card-mark Immediate
12384 instruct storeImmCM(memory mem, immI8 src) %{
12385 match(Set mem (StoreCM mem src));
12387 ins_cost(150);
12388 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
12389 // opcode(0xC6);
12390 ins_encode(store_B_immI_enc_sync(mem, src));
12391 ins_pipe( ialu_storeI );
12392 %}
12394 // Die now
12395 instruct ShouldNotReachHere( )
12396 %{
12397 match(Halt);
12398 ins_cost(300);
12400 // Use the following format syntax
12401 format %{ "ILLTRAP ;#@ShouldNotReachHere" %}
12402 ins_encode %{
12403 // Here we should emit illtrap !
12405 __ stop("in ShoudNotReachHere");
12407 %}
12408 ins_pipe( pipe_jump );
12409 %}
12411 instruct leaP8Narrow(mRegP dst, indOffset8Narrow mem)
12412 %{
12413 predicate(Universe::narrow_oop_shift() == 0);
12414 match(Set dst mem);
12416 ins_cost(110);
12417 format %{ "leaq $dst, $mem\t# ptr off8narrow @ leaP8Narrow" %}
12418 ins_encode %{
12419 Register dst = $dst$$Register;
12420 Register base = as_Register($mem$$base);
12421 int disp = $mem$$disp;
12423 __ daddiu(dst, base, disp);
12424 %}
12425 ins_pipe( ialu_regI_imm16 );
12426 %}
12428 instruct leaPPosIdxScaleOff8(mRegP dst, basePosIndexScaleOffset8 mem)
12429 %{
12430 match(Set dst mem);
12432 ins_cost(110);
12433 format %{ "leaq $dst, $mem\t# @ PosIdxScaleOff8" %}
12434 ins_encode %{
12435 Register dst = $dst$$Register;
12436 Register base = as_Register($mem$$base);
12437 Register index = as_Register($mem$$index);
12438 int scale = $mem$$scale;
12439 int disp = $mem$$disp;
12441 if (scale == 0) {
12442 __ daddu(AT, base, index);
12443 __ daddiu(dst, AT, disp);
12444 } else {
12445 __ dsll(AT, index, scale);
12446 __ daddu(AT, base, AT);
12447 __ daddiu(dst, AT, disp);
12448 }
12449 %}
12451 ins_pipe( ialu_regI_imm16 );
12452 %}
12454 instruct leaPIdxScale(mRegP dst, indIndexScale mem)
12455 %{
12456 match(Set dst mem);
12458 ins_cost(110);
12459 format %{ "leaq $dst, $mem\t# @ leaPIdxScale" %}
12460 ins_encode %{
12461 Register dst = $dst$$Register;
12462 Register base = as_Register($mem$$base);
12463 Register index = as_Register($mem$$index);
12464 int scale = $mem$$scale;
12466 if (scale == 0) {
12467 __ daddu(dst, base, index);
12468 } else {
12469 __ dsll(AT, index, scale);
12470 __ daddu(dst, base, AT);
12471 }
12472 %}
12474 ins_pipe( ialu_regI_imm16 );
12475 %}
12477 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12478 instruct jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{
12479 match(CountedLoopEnd cop (CmpI src1 src2));
12480 effect(USE labl);
12482 ins_cost(300);
12483 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd" %}
12484 ins_encode %{
12485 Register op1 = $src1$$Register;
12486 Register op2 = $src2$$Register;
12487 Label &L = *($labl$$label);
12488 int flag = $cop$$cmpcode;
12490 switch(flag)
12491 {
12492 case 0x01: //equal
12493 if (&L)
12494 __ beq(op1, op2, L);
12495 else
12496 __ beq(op1, op2, (int)0);
12497 break;
12498 case 0x02: //not_equal
12499 if (&L)
12500 __ bne(op1, op2, L);
12501 else
12502 __ bne(op1, op2, (int)0);
12503 break;
12504 case 0x03: //above
12505 __ slt(AT, op2, op1);
12506 if(&L)
12507 __ bne(AT, R0, L);
12508 else
12509 __ bne(AT, R0, (int)0);
12510 break;
12511 case 0x04: //above_equal
12512 __ slt(AT, op1, op2);
12513 if(&L)
12514 __ beq(AT, R0, L);
12515 else
12516 __ beq(AT, R0, (int)0);
12517 break;
12518 case 0x05: //below
12519 __ slt(AT, op1, op2);
12520 if(&L)
12521 __ bne(AT, R0, L);
12522 else
12523 __ bne(AT, R0, (int)0);
12524 break;
12525 case 0x06: //below_equal
12526 __ slt(AT, op2, op1);
12527 if(&L)
12528 __ beq(AT, R0, L);
12529 else
12530 __ beq(AT, R0, (int)0);
12531 break;
12532 default:
12533 Unimplemented();
12534 }
12535 __ nop();
12536 %}
12537 ins_pipe( pipe_jump );
12538 ins_pc_relative(1);
12539 %}
12542 instruct jmpLoopEnd_reg_imm16_sub(cmpOp cop, mRegI src1, immI16_sub src2, label labl) %{
12543 match(CountedLoopEnd cop (CmpI src1 src2));
12544 effect(USE labl);
12546 ins_cost(250);
12547 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_imm16_sub" %}
12548 ins_encode %{
12549 Register op1 = $src1$$Register;
12550 int op2 = $src2$$constant;
12551 Label &L = *($labl$$label);
12552 int flag = $cop$$cmpcode;
12554 __ addiu32(AT, op1, -1 * op2);
12556 switch(flag)
12557 {
12558 case 0x01: //equal
12559 if (&L)
12560 __ beq(AT, R0, L);
12561 else
12562 __ beq(AT, R0, (int)0);
12563 break;
12564 case 0x02: //not_equal
12565 if (&L)
12566 __ bne(AT, R0, L);
12567 else
12568 __ bne(AT, R0, (int)0);
12569 break;
12570 case 0x03: //above
12571 if(&L)
12572 __ bgtz(AT, L);
12573 else
12574 __ bgtz(AT, (int)0);
12575 break;
12576 case 0x04: //above_equal
12577 if(&L)
12578 __ bgez(AT, L);
12579 else
12580 __ bgez(AT,(int)0);
12581 break;
12582 case 0x05: //below
12583 if(&L)
12584 __ bltz(AT, L);
12585 else
12586 __ bltz(AT, (int)0);
12587 break;
12588 case 0x06: //below_equal
12589 if(&L)
12590 __ blez(AT, L);
12591 else
12592 __ blez(AT, (int)0);
12593 break;
12594 default:
12595 Unimplemented();
12596 }
12597 __ nop();
12598 %}
12599 ins_pipe( pipe_jump );
12600 ins_pc_relative(1);
12601 %}
12604 /*
12605 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12606 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12607 match(CountedLoopEnd cop cmp);
12608 effect(USE labl);
12610 ins_cost(300);
12611 format %{ "J$cop,u $labl\t# Loop end" %}
12612 size(6);
12613 opcode(0x0F, 0x80);
12614 ins_encode( Jcc( cop, labl) );
12615 ins_pipe( pipe_jump );
12616 ins_pc_relative(1);
12617 %}
12619 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12620 match(CountedLoopEnd cop cmp);
12621 effect(USE labl);
12623 ins_cost(200);
12624 format %{ "J$cop,u $labl\t# Loop end" %}
12625 opcode(0x0F, 0x80);
12626 ins_encode( Jcc( cop, labl) );
12627 ins_pipe( pipe_jump );
12628 ins_pc_relative(1);
12629 %}
12630 */
12632 // This match pattern is created for StoreIConditional since I cannot match IfNode without a RegFlags! fujie 2012/07/17
12633 instruct jmpCon_flags(cmpOp cop, FlagsReg cr, label labl) %{
12634 match(If cop cr);
12635 effect(USE labl);
12637 ins_cost(300);
12638 format %{ "J$cop $labl #mips uses AT as eflag @jmpCon_flags" %}
12640 ins_encode %{
12641 Label &L = *($labl$$label);
12642 switch($cop$$cmpcode)
12643 {
12644 case 0x01: //equal
12645 if (&L)
12646 __ bne(AT, R0, L);
12647 else
12648 __ bne(AT, R0, (int)0);
12649 break;
12650 case 0x02: //not equal
12651 if (&L)
12652 __ beq(AT, R0, L);
12653 else
12654 __ beq(AT, R0, (int)0);
12655 break;
12656 default:
12657 Unimplemented();
12658 }
12659 __ nop();
12660 %}
12662 ins_pipe( pipe_jump );
12663 ins_pc_relative(1);
12664 %}
12667 // ============================================================================
12668 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12669 // array for an instance of the superklass. Set a hidden internal cache on a
12670 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12671 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12672 instruct partialSubtypeCheck( mRegP result, no_T8_mRegP sub, no_T8_mRegP super, mT8RegI tmp ) %{
12673 match(Set result (PartialSubtypeCheck sub super));
12674 effect(KILL tmp);
12675 ins_cost(1100); // slightly larger than the next version
12676 format %{ "partialSubtypeCheck result=$result, sub=$sub, super=$super, tmp=$tmp " %}
12678 ins_encode( enc_PartialSubtypeCheck(result, sub, super, tmp) );
12679 ins_pipe( pipe_slow );
12680 %}
12683 // Conditional-store of an int value.
12684 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
12685 instruct storeIConditional( memory mem, mRegI oldval, mRegI newval, FlagsReg cr ) %{
12686 match(Set cr (StoreIConditional mem (Binary oldval newval)));
12687 // effect(KILL oldval);
12688 format %{ "CMPXCHG $newval, $mem, $oldval \t# @storeIConditional" %}
12690 ins_encode %{
12691 Register oldval = $oldval$$Register;
12692 Register newval = $newval$$Register;
12693 Address addr(as_Register($mem$$base), $mem$$disp);
12694 Label again, failure;
12696 // int base = $mem$$base;
12697 int index = $mem$$index;
12698 int scale = $mem$$scale;
12699 int disp = $mem$$disp;
12701 guarantee(Assembler::is_simm16(disp), "");
12703 if( index != 0 ) {
12704 __ stop("in storeIConditional: index != 0");
12705 } else {
12706 __ bind(again);
12707 __ sync();
12708 __ ll(AT, addr);
12709 __ bne(AT, oldval, failure);
12710 __ delayed()->addu(AT, R0, R0);
12712 __ addu(AT, newval, R0);
12713 __ sc(AT, addr);
12714 __ beq(AT, R0, again);
12715 __ delayed()->addiu(AT, R0, 0xFF);
12716 __ bind(failure);
12717 __ sync();
12718 }
12719 %}
12721 ins_pipe( long_memory_op );
12722 %}
12724 // Conditional-store of a long value.
12725 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
12726 instruct storeLConditional(memory mem, t2RegL oldval, mRegL newval, FlagsReg cr )
12727 %{
12728 match(Set cr (StoreLConditional mem (Binary oldval newval)));
12729 effect(KILL oldval);
12731 format %{ "cmpxchg $mem, $newval\t# If $oldval == $mem then store $newval into $mem" %}
12732 ins_encode%{
12733 Register oldval = $oldval$$Register;
12734 Register newval = $newval$$Register;
12735 Address addr((Register)$mem$$base, $mem$$disp);
12737 int index = $mem$$index;
12738 int scale = $mem$$scale;
12739 int disp = $mem$$disp;
12741 guarantee(Assembler::is_simm16(disp), "");
12743 if( index != 0 ) {
12744 __ stop("in storeIConditional: index != 0");
12745 } else {
12746 __ cmpxchg(newval, addr, oldval);
12747 }
12748 %}
12749 ins_pipe( long_memory_op );
12750 %}
12753 instruct compareAndSwapI( mRegI res, mRegP mem_ptr, mS2RegI oldval, mRegI newval) %{
12754 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
12755 effect(KILL oldval);
12756 // match(CompareAndSwapI mem_ptr (Binary oldval newval));
12757 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapI\n\t"
12758 "MOV $res, 1 @ compareAndSwapI\n\t"
12759 "BNE AT, R0 @ compareAndSwapI\n\t"
12760 "MOV $res, 0 @ compareAndSwapI\n"
12761 "L:" %}
12762 ins_encode %{
12763 Register newval = $newval$$Register;
12764 Register oldval = $oldval$$Register;
12765 Register res = $res$$Register;
12766 Address addr($mem_ptr$$Register, 0);
12767 Label L;
12769 __ cmpxchg32(newval, addr, oldval);
12770 __ move(res, AT);
12771 %}
12772 ins_pipe( long_memory_op );
12773 %}
12775 //FIXME:
12776 instruct compareAndSwapP( mRegI res, mRegP mem_ptr, s2_RegP oldval, mRegP newval) %{
12777 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
12778 effect(KILL oldval);
12779 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapP\n\t"
12780 "MOV $res, AT @ compareAndSwapP\n\t"
12781 "L:" %}
12782 ins_encode %{
12783 Register newval = $newval$$Register;
12784 Register oldval = $oldval$$Register;
12785 Register res = $res$$Register;
12786 Address addr($mem_ptr$$Register, 0);
12787 Label L;
12789 __ cmpxchg(newval, addr, oldval);
12790 __ move(res, AT);
12791 %}
12792 ins_pipe( long_memory_op );
12793 %}
12795 instruct compareAndSwapN( mRegI res, mRegP mem_ptr, t2_RegN oldval, mRegN newval) %{
12796 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
12797 effect(KILL oldval);
12798 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapN\n\t"
12799 "MOV $res, AT @ compareAndSwapN\n\t"
12800 "L:" %}
12801 ins_encode %{
12802 Register newval = $newval$$Register;
12803 Register oldval = $oldval$$Register;
12804 Register res = $res$$Register;
12805 Address addr($mem_ptr$$Register, 0);
12806 Label L;
12808 /* 2013/7/19 Jin: cmpxchg32 is implemented with ll/sc, which will do sign extension.
12809 * Thus, we should extend oldval's sign for correct comparision.
12810 */
12811 __ sll(oldval, oldval, 0);
12813 __ cmpxchg32(newval, addr, oldval);
12814 __ move(res, AT);
12815 %}
12816 ins_pipe( long_memory_op );
12817 %}
12819 //----------Max and Min--------------------------------------------------------
12820 // Min Instructions
12821 ////
12822 // *** Min and Max using the conditional move are slower than the
12823 // *** branch version on a Pentium III.
12824 // // Conditional move for min
12825 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12826 // effect( USE_DEF op2, USE op1, USE cr );
12827 // format %{ "CMOVlt $op2,$op1\t! min" %}
12828 // opcode(0x4C,0x0F);
12829 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12830 // ins_pipe( pipe_cmov_reg );
12831 //%}
12832 //
12833 //// Min Register with Register (P6 version)
12834 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12835 // predicate(VM_Version::supports_cmov() );
12836 // match(Set op2 (MinI op1 op2));
12837 // ins_cost(200);
12838 // expand %{
12839 // eFlagsReg cr;
12840 // compI_eReg(cr,op1,op2);
12841 // cmovI_reg_lt(op2,op1,cr);
12842 // %}
12843 //%}
12845 // Min Register with Register (generic version)
12846 instruct minI_Reg_Reg(mRegI dst, mRegI src) %{
12847 match(Set dst (MinI dst src));
12848 //effect(KILL flags);
12849 ins_cost(80);
12851 format %{ "MIN $dst, $src @minI_Reg_Reg" %}
12852 ins_encode %{
12853 Register dst = $dst$$Register;
12854 Register src = $src$$Register;
12856 __ slt(AT, src, dst);
12857 __ movn(dst, src, AT);
12859 %}
12861 ins_pipe( pipe_slow );
12862 %}
12864 // Max Register with Register
12865 // *** Min and Max using the conditional move are slower than the
12866 // *** branch version on a Pentium III.
12867 // // Conditional move for max
12868 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12869 // effect( USE_DEF op2, USE op1, USE cr );
12870 // format %{ "CMOVgt $op2,$op1\t! max" %}
12871 // opcode(0x4F,0x0F);
12872 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12873 // ins_pipe( pipe_cmov_reg );
12874 //%}
12875 //
12876 // // Max Register with Register (P6 version)
12877 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12878 // predicate(VM_Version::supports_cmov() );
12879 // match(Set op2 (MaxI op1 op2));
12880 // ins_cost(200);
12881 // expand %{
12882 // eFlagsReg cr;
12883 // compI_eReg(cr,op1,op2);
12884 // cmovI_reg_gt(op2,op1,cr);
12885 // %}
12886 //%}
12888 // Max Register with Register (generic version)
12889 instruct maxI_Reg_Reg(mRegI dst, mRegI src) %{
12890 match(Set dst (MaxI dst src));
12891 ins_cost(80);
12893 format %{ "MAX $dst, $src @maxI_Reg_Reg" %}
12895 ins_encode %{
12896 Register dst = $dst$$Register;
12897 Register src = $src$$Register;
12899 __ slt(AT, dst, src);
12900 __ movn(dst, src, AT);
12902 %}
12904 ins_pipe( pipe_slow );
12905 %}
12907 instruct maxI_Reg_zero(mRegI dst, immI0 zero) %{
12908 match(Set dst (MaxI dst zero));
12909 ins_cost(50);
12911 format %{ "MAX $dst, 0 @maxI_Reg_zero" %}
12913 ins_encode %{
12914 Register dst = $dst$$Register;
12916 __ slt(AT, dst, R0);
12917 __ movn(dst, R0, AT);
12919 %}
12921 ins_pipe( pipe_slow );
12922 %}
12924 instruct zerox_long_reg_reg(mRegL dst, mRegL src, immL_32bits mask)
12925 %{
12926 match(Set dst (AndL src mask));
12928 format %{ "movl $dst, $src\t# zero-extend long @ zerox_long_reg_reg" %}
12929 ins_encode %{
12930 Register dst = $dst$$Register;
12931 Register src = $src$$Register;
12933 __ dsll32(dst, src, 0);
12934 __ dsrl32(dst, dst, 0);
12935 %}
12936 ins_pipe(ialu_regI_regI);
12937 %}
12939 // Zero-extend convert int to long
12940 instruct convI2L_reg_reg_zex(mRegL dst, mRegI src, immL_32bits mask)
12941 %{
12942 match(Set dst (AndL (ConvI2L src) mask));
12944 format %{ "movl $dst, $src\t# i2l zero-extend @ convI2L_reg_reg_zex" %}
12945 ins_encode %{
12946 Register dst = $dst$$Register;
12947 Register src = $src$$Register;
12949 __ dsll32(dst, src, 0);
12950 __ dsrl32(dst, dst, 0);
12951 %}
12952 ins_pipe(ialu_regI_regI);
12953 %}
12956 // Match loading integer and casting it to unsigned int in long register.
12957 // LoadI + ConvI2L + AndL 0xffffffff.
12958 instruct loadUI2L_rmask(mRegL dst, memory mem, immL_32bits mask) %{
12959 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
12961 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_rmask" %}
12962 ins_encode (load_N_enc(dst, mem));
12963 ins_pipe(ialu_loadI);
12964 %}
12966 instruct loadUI2L_lmask(mRegL dst, memory mem, immL_32bits mask) %{
12967 match(Set dst (AndL mask (ConvI2L (LoadI mem))));
12969 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_lmask" %}
12970 ins_encode (load_N_enc(dst, mem));
12971 ins_pipe(ialu_loadI);
12972 %}
12975 // ============================================================================
12976 // Safepoint Instruction
12977 instruct safePoint_poll(mRegP poll) %{
12978 match(SafePoint poll);
12979 effect(USE poll);
12981 ins_cost(125);
12982 format %{ "Safepoint @ [$poll] : poll for GC @ safePoint_poll" %}
12984 ins_encode %{
12985 Register poll_reg = $poll$$Register;
12987 __ block_comment("Safepoint:");
12988 __ relocate(relocInfo::poll_type);
12989 __ lw(AT, poll_reg, 0);
12990 %}
12992 ins_pipe( ialu_storeI );
12993 %}
12995 //----------Arithmetic Conversion Instructions---------------------------------
12997 instruct roundFloat_nop(regF dst)
12998 %{
12999 match(Set dst (RoundFloat dst));
13001 ins_cost(0);
13002 ins_encode();
13003 ins_pipe(empty);
13004 %}
13006 instruct roundDouble_nop(regD dst)
13007 %{
13008 match(Set dst (RoundDouble dst));
13010 ins_cost(0);
13011 ins_encode();
13012 ins_pipe(empty);
13013 %}
13015 //---------- Zeros Count Instructions ------------------------------------------
13016 // CountLeadingZerosINode CountTrailingZerosINode
13017 instruct countLeadingZerosI(mRegI dst, mRegI src) %{
13018 predicate(UseCountLeadingZerosInstruction);
13019 match(Set dst (CountLeadingZerosI src));
13021 format %{ "clz $dst, $src\t# count leading zeros (int)" %}
13022 ins_encode %{
13023 __ clz($dst$$Register, $src$$Register);
13024 %}
13025 ins_pipe( ialu_regL_regL );
13026 %}
13028 instruct countLeadingZerosL(mRegI dst, mRegL src) %{
13029 predicate(UseCountLeadingZerosInstruction);
13030 match(Set dst (CountLeadingZerosL src));
13032 format %{ "dclz $dst, $src\t# count leading zeros (long)" %}
13033 ins_encode %{
13034 __ dclz($dst$$Register, $src$$Register);
13035 %}
13036 ins_pipe( ialu_regL_regL );
13037 %}
13039 instruct countTrailingZerosI(mRegI dst, mRegI src) %{
13040 predicate(UseCountTrailingZerosInstruction);
13041 match(Set dst (CountTrailingZerosI src));
13043 format %{ "ctz $dst, $src\t# count trailing zeros (int)" %}
13044 ins_encode %{
13045 // ctz and dctz is gs instructions.
13046 __ ctz($dst$$Register, $src$$Register);
13047 %}
13048 ins_pipe( ialu_regL_regL );
13049 %}
13051 instruct countTrailingZerosL(mRegI dst, mRegL src) %{
13052 predicate(UseCountTrailingZerosInstruction);
13053 match(Set dst (CountTrailingZerosL src));
13055 format %{ "dcto $dst, $src\t# count trailing zeros (long)" %}
13056 ins_encode %{
13057 __ dctz($dst$$Register, $src$$Register);
13058 %}
13059 ins_pipe( ialu_regL_regL );
13060 %}
13062 // ====================VECTOR INSTRUCTIONS=====================================
13064 // Load vectors (8 bytes long)
13065 instruct loadV8(vecD dst, memory mem) %{
13066 predicate(n->as_LoadVector()->memory_size() == 8);
13067 match(Set dst (LoadVector mem));
13068 ins_cost(125);
13069 format %{ "load $dst, $mem\t! load vector (8 bytes)" %}
13070 ins_encode(load_D_enc(dst, mem));
13071 ins_pipe( fpu_loadF );
13072 %}
13074 // Store vectors (8 bytes long)
13075 instruct storeV8(memory mem, vecD src) %{
13076 predicate(n->as_StoreVector()->memory_size() == 8);
13077 match(Set mem (StoreVector mem src));
13078 ins_cost(145);
13079 format %{ "store $mem, $src\t! store vector (8 bytes)" %}
13080 ins_encode(store_D_reg_enc(mem, src));
13081 ins_pipe( fpu_storeF );
13082 %}
13084 instruct Repl8B(vecD dst, mRegI src) %{
13085 predicate(n->as_Vector()->length() == 8);
13086 match(Set dst (ReplicateB src));
13087 format %{ "replv_ob AT, $src\n\t"
13088 "dmtc1 AT, $dst\t! replicate8B" %}
13089 ins_encode %{
13090 __ replv_ob(AT, $src$$Register);
13091 __ dmtc1(AT, $dst$$FloatRegister);
13092 %}
13093 ins_pipe( pipe_mtc1 );
13094 %}
13096 instruct Repl8B_imm(vecD dst, immI con) %{
13097 predicate(n->as_Vector()->length() == 8);
13098 match(Set dst (ReplicateB con));
13099 format %{ "repl_ob AT, [$con]\n\t"
13100 "dmtc1 AT, $dst,0x00\t! replicate8B($con)" %}
13101 ins_encode %{
13102 int val = $con$$constant;
13103 __ repl_ob(AT, val);
13104 __ dmtc1(AT, $dst$$FloatRegister);
13105 %}
13106 ins_pipe( pipe_mtc1 );
13107 %}
13109 instruct Repl8B_zero(vecD dst, immI0 zero) %{
13110 predicate(n->as_Vector()->length() == 8);
13111 match(Set dst (ReplicateB zero));
13112 format %{ "dmtc1 R0, $dst\t! replicate8B zero" %}
13113 ins_encode %{
13114 __ dmtc1(R0, $dst$$FloatRegister);
13115 %}
13116 ins_pipe( pipe_mtc1 );
13117 %}
13119 instruct Repl8B_M1(vecD dst, immI_M1 M1) %{
13120 predicate(n->as_Vector()->length() == 8);
13121 match(Set dst (ReplicateB M1));
13122 format %{ "dmtc1 -1, $dst\t! replicate8B -1" %}
13123 ins_encode %{
13124 __ nor(AT, R0, R0);
13125 __ dmtc1(AT, $dst$$FloatRegister);
13126 %}
13127 ins_pipe( pipe_mtc1 );
13128 %}
13130 instruct Repl4S(vecD dst, mRegI src) %{
13131 predicate(n->as_Vector()->length() == 4);
13132 match(Set dst (ReplicateS src));
13133 format %{ "replv_qh AT, $src\n\t"
13134 "dmtc1 AT, $dst\t! replicate4S" %}
13135 ins_encode %{
13136 __ replv_qh(AT, $src$$Register);
13137 __ dmtc1(AT, $dst$$FloatRegister);
13138 %}
13139 ins_pipe( pipe_mtc1 );
13140 %}
13142 instruct Repl4S_imm(vecD dst, immI con) %{
13143 predicate(n->as_Vector()->length() == 4);
13144 match(Set dst (ReplicateS con));
13145 format %{ "replv_qh AT, [$con]\n\t"
13146 "dmtc1 AT, $dst\t! replicate4S($con)" %}
13147 ins_encode %{
13148 int val = $con$$constant;
13149 if ( Assembler::is_simm(val, 10)) {
13150 //repl_qh supports 10 bits immediate
13151 __ repl_qh(AT, val);
13152 } else {
13153 __ li32(AT, val);
13154 __ replv_qh(AT, AT);
13155 }
13156 __ dmtc1(R0, $dst$$FloatRegister);
13157 %}
13158 ins_pipe( pipe_mtc1 );
13159 %}
13161 instruct Repl4S_zero(vecD dst, immI0 zero) %{
13162 predicate(n->as_Vector()->length() == 4);
13163 match(Set dst (ReplicateS zero));
13164 format %{ "dmtc1 R0, $dst\t! replicate4S zero" %}
13165 ins_encode %{
13166 __ dmtc1(R0, $dst$$FloatRegister);
13167 %}
13168 ins_pipe( pipe_mtc1 );
13169 %}
13171 instruct Repl4S_M1(vecD dst, immI_M1 M1) %{
13172 predicate(n->as_Vector()->length() == 4);
13173 match(Set dst (ReplicateS M1));
13174 format %{ "dmtc1 -1, $dst\t! replicate4S -1" %}
13175 ins_encode %{
13176 __ nor(AT, R0, R0);
13177 __ dmtc1(AT, $dst$$FloatRegister);
13178 %}
13179 ins_pipe( pipe_mtc1 );
13180 %}
13182 // Replicate integer (4 byte) scalar to be vector
13183 instruct Repl2I(vecD dst, mRegI src) %{
13184 predicate(n->as_Vector()->length() == 2);
13185 match(Set dst (ReplicateI src));
13186 format %{ "dins AT, $src, 0, 32\n\t"
13187 "dinsu AT, $src, 32, 32\n\t"
13188 "dmtc1 AT, $dst\t! replicate2I" %}
13189 ins_encode %{
13190 __ dins(AT, $src$$Register, 0, 32);
13191 __ dinsu(AT, $src$$Register, 32, 32);
13192 __ dmtc1(AT, $dst$$FloatRegister);
13193 %}
13194 ins_pipe( pipe_mtc1 );
13195 %}
13197 // Replicate integer (4 byte) scalar immediate to be vector by loading from const table.
13198 instruct Repl2I_imm(vecD dst, immI con, mA7RegI tmp) %{
13199 predicate(n->as_Vector()->length() == 2);
13200 match(Set dst (ReplicateI con));
13201 effect(KILL tmp);
13202 format %{ "li32 AT, [$con], 32\n\t"
13203 "replv_pw AT, AT\n\t"
13204 "dmtc1 AT, $dst\t! replicate2I($con)" %}
13205 ins_encode %{
13206 int val = $con$$constant;
13207 __ li32(AT, val);
13208 __ replv_pw(AT, AT);
13209 __ dmtc1(AT, $dst$$FloatRegister);
13210 %}
13211 ins_pipe( pipe_mtc1 );
13212 %}
13214 // Replicate integer (4 byte) scalar zero to be vector
13215 instruct Repl2I_zero(vecD dst, immI0 zero) %{
13216 predicate(n->as_Vector()->length() == 2);
13217 match(Set dst (ReplicateI zero));
13218 format %{ "dmtc1 R0, $dst\t! replicate2I zero" %}
13219 ins_encode %{
13220 __ dmtc1(R0, $dst$$FloatRegister);
13221 %}
13222 ins_pipe( pipe_mtc1 );
13223 %}
13225 // Replicate integer (4 byte) scalar -1 to be vector
13226 instruct Repl2I_M1(vecD dst, immI_M1 M1) %{
13227 predicate(n->as_Vector()->length() == 2);
13228 match(Set dst (ReplicateI M1));
13229 format %{ "dmtc1 -1, $dst\t! replicate2I -1, use AT" %}
13230 ins_encode %{
13231 __ nor(AT, R0, R0);
13232 __ dmtc1(AT, $dst$$FloatRegister);
13233 %}
13234 ins_pipe( pipe_mtc1 );
13235 %}
13237 // Replicate float (4 byte) scalar to be vector
13238 instruct Repl2F(vecD dst, regF src) %{
13239 predicate(n->as_Vector()->length() == 2);
13240 match(Set dst (ReplicateF src));
13241 format %{ "cvt.ps $dst, $src, $src\t! replicate2F" %}
13242 ins_encode %{
13243 __ cvt_ps_s($dst$$FloatRegister, $src$$FloatRegister, $src$$FloatRegister);
13244 %}
13245 ins_pipe( pipe_slow );
13246 %}
13248 // Replicate float (4 byte) scalar zero to be vector
13249 instruct Repl2F_zero(vecD dst, immF0 zero) %{
13250 predicate(n->as_Vector()->length() == 2);
13251 match(Set dst (ReplicateF zero));
13252 format %{ "dmtc1 R0, $dst\t! replicate2F zero" %}
13253 ins_encode %{
13254 __ dmtc1(R0, $dst$$FloatRegister);
13255 %}
13256 ins_pipe( pipe_mtc1 );
13257 %}
13260 // ====================VECTOR ARITHMETIC=======================================
13262 // --------------------------------- ADD --------------------------------------
13264 // Floats vector add
13265 instruct vadd2F(vecD dst, vecD src) %{
13266 predicate(n->as_Vector()->length() == 2);
13267 match(Set dst (AddVF dst src));
13268 format %{ "add.ps $dst,$src\t! add packed2F" %}
13269 ins_encode %{
13270 __ add_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13271 %}
13272 ins_pipe( pipe_slow );
13273 %}
13275 instruct vadd2F3(vecD dst, vecD src1, vecD src2) %{
13276 predicate(n->as_Vector()->length() == 2);
13277 match(Set dst (AddVF src1 src2));
13278 format %{ "add.ps $dst,$src1,$src2\t! add packed2F" %}
13279 ins_encode %{
13280 __ add_ps($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13281 %}
13282 ins_pipe( fpu_regF_regF );
13283 %}
13285 // --------------------------------- SUB --------------------------------------
13287 // Floats vector sub
13288 instruct vsub2F(vecD dst, vecD src) %{
13289 predicate(n->as_Vector()->length() == 2);
13290 match(Set dst (SubVF dst src));
13291 format %{ "sub.ps $dst,$src\t! sub packed2F" %}
13292 ins_encode %{
13293 __ sub_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13294 %}
13295 ins_pipe( fpu_regF_regF );
13296 %}
13298 // --------------------------------- MUL --------------------------------------
13300 // Floats vector mul
13301 instruct vmul2F(vecD dst, vecD src) %{
13302 predicate(n->as_Vector()->length() == 2);
13303 match(Set dst (MulVF dst src));
13304 format %{ "mul.ps $dst, $src\t! mul packed2F" %}
13305 ins_encode %{
13306 __ mul_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13307 %}
13308 ins_pipe( fpu_regF_regF );
13309 %}
13311 instruct vmul2F3(vecD dst, vecD src1, vecD src2) %{
13312 predicate(n->as_Vector()->length() == 2);
13313 match(Set dst (MulVF src1 src2));
13314 format %{ "mul.ps $dst, $src1, $src2\t! mul packed2F" %}
13315 ins_encode %{
13316 __ mul_ps($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13317 %}
13318 ins_pipe( fpu_regF_regF );
13319 %}
13321 // --------------------------------- DIV --------------------------------------
13322 // MIPS do not have div.ps
13325 //----------PEEPHOLE RULES-----------------------------------------------------
13326 // These must follow all instruction definitions as they use the names
13327 // defined in the instructions definitions.
13328 //
13329 // peepmatch ( root_instr_name [preceeding_instruction]* );
13330 //
13331 // peepconstraint %{
13332 // (instruction_number.operand_name relational_op instruction_number.operand_name
13333 // [, ...] );
13334 // // instruction numbers are zero-based using left to right order in peepmatch
13335 //
13336 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13337 // // provide an instruction_number.operand_name for each operand that appears
13338 // // in the replacement instruction's match rule
13339 //
13340 // ---------VM FLAGS---------------------------------------------------------
13341 //
13342 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13343 //
13344 // Each peephole rule is given an identifying number starting with zero and
13345 // increasing by one in the order seen by the parser. An individual peephole
13346 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13347 // on the command-line.
13348 //
13349 // ---------CURRENT LIMITATIONS----------------------------------------------
13350 //
13351 // Only match adjacent instructions in same basic block
13352 // Only equality constraints
13353 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13354 // Only one replacement instruction
13355 //
13356 // ---------EXAMPLE----------------------------------------------------------
13357 //
13358 // // pertinent parts of existing instructions in architecture description
13359 // instruct movI(eRegI dst, eRegI src) %{
13360 // match(Set dst (CopyI src));
13361 // %}
13362 //
13363 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13364 // match(Set dst (AddI dst src));
13365 // effect(KILL cr);
13366 // %}
13367 //
13368 // // Change (inc mov) to lea
13369 // peephole %{
13370 // // increment preceeded by register-register move
13371 // peepmatch ( incI_eReg movI );
13372 // // require that the destination register of the increment
13373 // // match the destination register of the move
13374 // peepconstraint ( 0.dst == 1.dst );
13375 // // construct a replacement instruction that sets
13376 // // the destination to ( move's source register + one )
13377 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13378 // %}
13379 //
13380 // Implementation no longer uses movX instructions since
13381 // machine-independent system no longer uses CopyX nodes.
13382 //
13383 // peephole %{
13384 // peepmatch ( incI_eReg movI );
13385 // peepconstraint ( 0.dst == 1.dst );
13386 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13387 // %}
13388 //
13389 // peephole %{
13390 // peepmatch ( decI_eReg movI );
13391 // peepconstraint ( 0.dst == 1.dst );
13392 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13393 // %}
13394 //
13395 // peephole %{
13396 // peepmatch ( addI_eReg_imm movI );
13397 // peepconstraint ( 0.dst == 1.dst );
13398 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13399 // %}
13400 //
13401 // peephole %{
13402 // peepmatch ( addP_eReg_imm movP );
13403 // peepconstraint ( 0.dst == 1.dst );
13404 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13405 // %}
13407 // // Change load of spilled value to only a spill
13408 // instruct storeI(memory mem, eRegI src) %{
13409 // match(Set mem (StoreI mem src));
13410 // %}
13411 //
13412 // instruct loadI(eRegI dst, memory mem) %{
13413 // match(Set dst (LoadI mem));
13414 // %}
13415 //
13416 //peephole %{
13417 // peepmatch ( loadI storeI );
13418 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13419 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13420 //%}
13422 //----------SMARTSPILL RULES---------------------------------------------------
13423 // These must follow all instruction definitions as they use the names
13424 // defined in the instructions definitions.
