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src/cpu/mips/vm/mips_64.ad@28e6fbbe225f
src/cpu/mips/vm/mips_64.ad
Sat, 18 Feb 2017 18:56:55 -0500
- author
- fujie
- date
- Sat, 18 Feb 2017 18:56:55 -0500
- changeset 316
- 28e6fbbe225f
- parent 314
- 5682475ccb5d
- child 317
- 001d396b2d46
- permissions
- -rw-r--r--
[C2] Add rolI_Reg_immI_0_31 and rorI_Reg_immI_0_31 in mips_64.ad
1 //
2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
26 // GodSon3 Architecture Description File
28 //----------REGISTER DEFINITION BLOCK------------------------------------------
29 // This information is used by the matcher and the register allocator to
30 // describe individual registers and classes of registers within the target
31 // archtecture.
33 // format:
34 // reg_def name (call convention, c-call convention, ideal type, encoding);
35 // call convention :
36 // NS = No-Save
37 // SOC = Save-On-Call
38 // SOE = Save-On-Entry
39 // AS = Always-Save
40 // ideal type :
41 // see opto/opcodes.hpp for more info
42 // reg_class name (reg, ...);
43 // alloc_class name (reg, ...);
44 register %{
46 // General Registers
47 // Integer Registers
48 reg_def R0 ( NS, NS, Op_RegI, 0, VMRegImpl::Bad());
49 reg_def AT ( NS, NS, Op_RegI, 1, AT->as_VMReg());
50 reg_def AT_H ( NS, NS, Op_RegI, 1, AT->as_VMReg()->next());
51 reg_def V0 (SOC, SOC, Op_RegI, 2, V0->as_VMReg());
52 reg_def V0_H (SOC, SOC, Op_RegI, 2, V0->as_VMReg()->next());
53 reg_def V1 (SOC, SOC, Op_RegI, 3, V1->as_VMReg());
54 reg_def V1_H (SOC, SOC, Op_RegI, 3, V1->as_VMReg()->next());
55 reg_def A0 (SOC, SOC, Op_RegI, 4, A0->as_VMReg());
56 reg_def A0_H (SOC, SOC, Op_RegI, 4, A0->as_VMReg()->next());
57 reg_def A1 (SOC, SOC, Op_RegI, 5, A1->as_VMReg());
58 reg_def A1_H (SOC, SOC, Op_RegI, 5, A1->as_VMReg()->next());
59 reg_def A2 (SOC, SOC, Op_RegI, 6, A2->as_VMReg());
60 reg_def A2_H (SOC, SOC, Op_RegI, 6, A2->as_VMReg()->next());
61 reg_def A3 (SOC, SOC, Op_RegI, 7, A3->as_VMReg());
62 reg_def A3_H (SOC, SOC, Op_RegI, 7, A3->as_VMReg()->next());
63 reg_def A4 (SOC, SOC, Op_RegI, 8, A4->as_VMReg());
64 reg_def A4_H (SOC, SOC, Op_RegI, 8, A4->as_VMReg()->next());
65 reg_def A5 (SOC, SOC, Op_RegI, 9, A5->as_VMReg());
66 reg_def A5_H (SOC, SOC, Op_RegI, 9, A5->as_VMReg()->next());
67 reg_def A6 (SOC, SOC, Op_RegI, 10, A6->as_VMReg());
68 reg_def A6_H (SOC, SOC, Op_RegI, 10, A6->as_VMReg()->next());
69 reg_def A7 (SOC, SOC, Op_RegI, 11, A7->as_VMReg());
70 reg_def A7_H (SOC, SOC, Op_RegI, 11, A7->as_VMReg()->next());
71 reg_def T0 (SOC, SOC, Op_RegI, 12, T0->as_VMReg());
72 reg_def T0_H (SOC, SOC, Op_RegI, 12, T0->as_VMReg()->next());
73 reg_def T1 (SOC, SOC, Op_RegI, 13, T1->as_VMReg());
74 reg_def T1_H (SOC, SOC, Op_RegI, 13, T1->as_VMReg()->next());
75 reg_def T2 (SOC, SOC, Op_RegI, 14, T2->as_VMReg());
76 reg_def T2_H (SOC, SOC, Op_RegI, 14, T2->as_VMReg()->next());
77 reg_def T3 (SOC, SOC, Op_RegI, 15, T3->as_VMReg());
78 reg_def T3_H (SOC, SOC, Op_RegI, 15, T3->as_VMReg()->next());
79 reg_def S0 (SOC, SOE, Op_RegI, 16, S0->as_VMReg());
80 reg_def S0_H (SOC, SOE, Op_RegI, 16, S0->as_VMReg()->next());
81 reg_def S1 (SOC, SOE, Op_RegI, 17, S1->as_VMReg());
82 reg_def S1_H (SOC, SOE, Op_RegI, 17, S1->as_VMReg()->next());
83 reg_def S2 (SOC, SOE, Op_RegI, 18, S2->as_VMReg());
84 reg_def S2_H (SOC, SOE, Op_RegI, 18, S2->as_VMReg()->next());
85 reg_def S3 (SOC, SOE, Op_RegI, 19, S3->as_VMReg());
86 reg_def S3_H (SOC, SOE, Op_RegI, 19, S3->as_VMReg()->next());
87 reg_def S4 (SOC, SOE, Op_RegI, 20, S4->as_VMReg());
88 reg_def S4_H (SOC, SOE, Op_RegI, 20, S4->as_VMReg()->next());
89 reg_def S5 (SOC, SOE, Op_RegI, 21, S5->as_VMReg());
90 reg_def S5_H (SOC, SOE, Op_RegI, 21, S5->as_VMReg()->next());
91 reg_def S6 (SOC, SOE, Op_RegI, 22, S6->as_VMReg());
92 reg_def S6_H (SOC, SOE, Op_RegI, 22, S6->as_VMReg()->next());
93 reg_def S7 (SOC, SOE, Op_RegI, 23, S7->as_VMReg());
94 reg_def S7_H (SOC, SOE, Op_RegI, 23, S7->as_VMReg()->next());
95 reg_def T8 (SOC, SOC, Op_RegI, 24, T8->as_VMReg());
96 reg_def T8_H (SOC, SOC, Op_RegI, 24, T8->as_VMReg()->next());
97 reg_def T9 (SOC, SOC, Op_RegI, 25, T9->as_VMReg());
98 reg_def T9_H (SOC, SOC, Op_RegI, 25, T9->as_VMReg()->next());
100 // Special Registers
101 reg_def K0 ( NS, NS, Op_RegI, 26, K0->as_VMReg());
102 reg_def K1 ( NS, NS, Op_RegI, 27, K1->as_VMReg());
103 reg_def GP ( NS, NS, Op_RegI, 28, GP->as_VMReg());
104 reg_def GP_H ( NS, NS, Op_RegI, 28, GP->as_VMReg()->next());
105 reg_def SP ( NS, NS, Op_RegI, 29, SP->as_VMReg());
106 reg_def SP_H ( NS, NS, Op_RegI, 29, SP->as_VMReg()->next());
107 reg_def FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
108 reg_def FP_H ( NS, NS, Op_RegI, 30, FP->as_VMReg()->next());
109 reg_def RA ( NS, NS, Op_RegI, 31, RA->as_VMReg());
110 reg_def RA_H ( NS, NS, Op_RegI, 31, RA->as_VMReg()->next());
112 // Floating registers.
113 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
114 reg_def F0_H ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()->next());
115 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
116 reg_def F1_H ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()->next());
117 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
118 reg_def F2_H ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()->next());
119 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
120 reg_def F3_H ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()->next());
121 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
122 reg_def F4_H ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()->next());
123 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
124 reg_def F5_H ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()->next());
125 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
126 reg_def F6_H ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()->next());
127 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
128 reg_def F7_H ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()->next());
129 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
130 reg_def F8_H ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()->next());
131 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
132 reg_def F9_H ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()->next());
133 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
134 reg_def F10_H ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()->next());
135 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
136 reg_def F11_H ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()->next());
137 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
138 reg_def F12_H ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()->next());
139 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
140 reg_def F13_H ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()->next());
141 reg_def F14 ( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
142 reg_def F14_H ( SOC, SOC, Op_RegF, 14, F14->as_VMReg()->next());
143 reg_def F15 ( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
144 reg_def F15_H ( SOC, SOC, Op_RegF, 15, F15->as_VMReg()->next());
145 reg_def F16 ( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
146 reg_def F16_H ( SOC, SOC, Op_RegF, 16, F16->as_VMReg()->next());
147 reg_def F17 ( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
148 reg_def F17_H ( SOC, SOC, Op_RegF, 17, F17->as_VMReg()->next());
149 reg_def F18 ( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
150 reg_def F18_H ( SOC, SOC, Op_RegF, 18, F18->as_VMReg()->next());
151 reg_def F19 ( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
152 reg_def F19_H ( SOC, SOC, Op_RegF, 19, F19->as_VMReg()->next());
153 reg_def F20 ( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
154 reg_def F20_H ( SOC, SOC, Op_RegF, 20, F20->as_VMReg()->next());
155 reg_def F21 ( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
156 reg_def F21_H ( SOC, SOC, Op_RegF, 21, F21->as_VMReg()->next());
157 reg_def F22 ( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
158 reg_def F22_H ( SOC, SOC, Op_RegF, 22, F22->as_VMReg()->next());
159 reg_def F23 ( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
160 reg_def F23_H ( SOC, SOC, Op_RegF, 23, F23->as_VMReg()->next());
161 reg_def F24 ( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
162 reg_def F24_H ( SOC, SOC, Op_RegF, 24, F24->as_VMReg()->next());
163 reg_def F25 ( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
164 reg_def F25_H ( SOC, SOC, Op_RegF, 25, F25->as_VMReg()->next());
165 reg_def F26 ( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
166 reg_def F26_H ( SOC, SOC, Op_RegF, 26, F26->as_VMReg()->next());
167 reg_def F27 ( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
168 reg_def F27_H ( SOC, SOC, Op_RegF, 27, F27->as_VMReg()->next());
169 reg_def F28 ( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
170 reg_def F28_H ( SOC, SOC, Op_RegF, 28, F28->as_VMReg()->next());
171 reg_def F29 ( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
172 reg_def F29_H ( SOC, SOC, Op_RegF, 29, F29->as_VMReg()->next());
173 reg_def F30 ( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
174 reg_def F30_H ( SOC, SOC, Op_RegF, 30, F30->as_VMReg()->next());
175 reg_def F31 ( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
176 reg_def F31_H ( SOC, SOC, Op_RegF, 31, F31->as_VMReg()->next());
179 // ----------------------------
180 // Special Registers
181 // Condition Codes Flag Registers
182 reg_def MIPS_FLAG (SOC, SOC, Op_RegFlags, 1, as_Register(1)->as_VMReg());
183 //S6 is used for get_thread(S6)
184 //S5 is uesd for heapbase of compressed oop
185 alloc_class chunk0(
186 S7, S7_H,
187 S0, S0_H,
188 S1, S1_H,
189 S2, S2_H,
190 S4, S4_H,
191 S5, S5_H,
192 S6, S6_H,
193 S3, S3_H,
194 T2, T2_H,
195 T3, T3_H,
196 T8, T8_H,
197 T9, T9_H,
198 T1, T1_H, // inline_cache_reg
199 V1, V1_H,
200 A7, A7_H,
201 A6, A6_H,
202 A5, A5_H,
203 A4, A4_H,
204 V0, V0_H,
205 A3, A3_H,
206 A2, A2_H,
207 A1, A1_H,
208 A0, A0_H,
209 T0, T0_H,
210 GP, GP_H
211 RA, RA_H,
212 SP, SP_H, // stack_pointer
213 FP, FP_H // frame_pointer
214 );
216 alloc_class chunk1( F0, F0_H,
217 F1, F1_H,
218 F2, F2_H,
219 F3, F3_H,
220 F4, F4_H,
221 F5, F5_H,
222 F6, F6_H,
223 F7, F7_H,
224 F8, F8_H,
225 F9, F9_H,
226 F10, F10_H,
227 F11, F11_H,
228 F20, F20_H,
229 F21, F21_H,
230 F22, F22_H,
231 F23, F23_H,
232 F24, F24_H,
233 F25, F25_H,
234 F26, F26_H,
235 F27, F27_H,
236 F28, F28_H,
237 F19, F19_H,
238 F18, F18_H,
239 F17, F17_H,
240 F16, F16_H,
241 F15, F15_H,
242 F14, F14_H,
243 F13, F13_H,
244 F12, F12_H,
245 F29, F29_H,
246 F30, F30_H,
247 F31, F31_H);
249 alloc_class chunk2(MIPS_FLAG);
251 reg_class s_reg( S0, S1, S2, S3, S4, S5, S6, S7 );
252 reg_class s0_reg( S0 );
253 reg_class s1_reg( S1 );
254 reg_class s2_reg( S2 );
255 reg_class s3_reg( S3 );
256 reg_class s4_reg( S4 );
257 reg_class s5_reg( S5 );
258 reg_class s6_reg( S6 );
259 reg_class s7_reg( S7 );
261 reg_class t_reg( T0, T1, T2, T3, T8, T9 );
262 reg_class t0_reg( T0 );
263 reg_class t1_reg( T1 );
264 reg_class t2_reg( T2 );
265 reg_class t3_reg( T3 );
266 reg_class t8_reg( T8 );
267 reg_class t9_reg( T9 );
269 reg_class a_reg( A0, A1, A2, A3, A4, A5, A6, A7 );
270 reg_class a0_reg( A0 );
271 reg_class a1_reg( A1 );
272 reg_class a2_reg( A2 );
273 reg_class a3_reg( A3 );
274 reg_class a4_reg( A4 );
275 reg_class a5_reg( A5 );
276 reg_class a6_reg( A6 );
277 reg_class a7_reg( A7 );
279 reg_class v0_reg( V0 );
280 reg_class v1_reg( V1 );
282 reg_class sp_reg( SP, SP_H );
283 reg_class fp_reg( FP, FP_H );
285 reg_class mips_flags(MIPS_FLAG);
287 reg_class v0_long_reg( V0, V0_H );
288 reg_class v1_long_reg( V1, V1_H );
289 reg_class a0_long_reg( A0, A0_H );
290 reg_class a1_long_reg( A1, A1_H );
291 reg_class a2_long_reg( A2, A2_H );
292 reg_class a3_long_reg( A3, A3_H );
293 reg_class a4_long_reg( A4, A4_H );
294 reg_class a5_long_reg( A5, A5_H );
295 reg_class a6_long_reg( A6, A6_H );
296 reg_class a7_long_reg( A7, A7_H );
297 reg_class t0_long_reg( T0, T0_H );
298 reg_class t1_long_reg( T1, T1_H );
299 reg_class t2_long_reg( T2, T2_H );
300 reg_class t3_long_reg( T3, T3_H );
301 reg_class t8_long_reg( T8, T8_H );
302 reg_class t9_long_reg( T9, T9_H );
303 reg_class s0_long_reg( S0, S0_H );
304 reg_class s1_long_reg( S1, S1_H );
305 reg_class s2_long_reg( S2, S2_H );
306 reg_class s3_long_reg( S3, S3_H );
307 reg_class s4_long_reg( S4, S4_H );
308 reg_class s5_long_reg( S5, S5_H );
309 reg_class s6_long_reg( S6, S6_H );
310 reg_class s7_long_reg( S7, S7_H );
312 reg_class int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, A7, A6, A5, A4, V0, A3, A2, A1, A0, T0 );
314 reg_class no_Ax_int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, V0, T0 );
316 reg_class p_reg(
317 S7, S7_H,
318 S0, S0_H,
319 S1, S1_H,
320 S2, S2_H,
321 S4, S4_H,
322 S3, S3_H,
323 T8, T8_H,
324 T2, T2_H,
325 T3, T3_H,
326 T1, T1_H,
327 A7, A7_H,
328 A6, A6_H,
329 A5, A5_H,
330 A4, A4_H,
331 A3, A3_H,
332 A2, A2_H,
333 A1, A1_H,
334 A0, A0_H,
335 T0, T0_H
336 );
338 reg_class no_T8_p_reg(
339 S7, S7_H,
340 S0, S0_H,
341 S1, S1_H,
342 S2, S2_H,
343 S4, S4_H,
344 S3, S3_H,
345 T2, T2_H,
346 T3, T3_H,
347 T1, T1_H,
348 A7, A7_H,
349 A6, A6_H,
350 A5, A5_H,
351 A4, A4_H,
352 A3, A3_H,
353 A2, A2_H,
354 A1, A1_H,
355 A0, A0_H,
356 T0, T0_H
357 );
359 reg_class long_reg(
360 S7, S7_H,
361 S0, S0_H,
362 S1, S1_H,
363 S2, S2_H,
364 S4, S4_H,
365 S3, S3_H,
366 T8, T8_H,
367 T2, T2_H,
368 T3, T3_H,
369 T1, T1_H,
370 A7, A7_H,
371 A6, A6_H,
372 A5, A5_H,
373 A4, A4_H,
374 A3, A3_H,
375 A2, A2_H,
376 A1, A1_H,
377 A0, A0_H,
378 T0, T0_H
379 );
382 // Floating point registers.
383 // 2012/8/23 Fu: F30/F31 are used as temporary registers in D2I
384 // 2016/12/1 aoqi: F31 are not used as temporary registers in D2I
385 reg_class flt_reg( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17 F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F31);
386 reg_class dbl_reg( F0, F0_H,
387 F1, F1_H,
388 F2, F2_H,
389 F3, F3_H,
390 F4, F4_H,
391 F5, F5_H,
392 F6, F6_H,
393 F7, F7_H,
394 F8, F8_H,
395 F9, F9_H,
396 F10, F10_H,
397 F11, F11_H,
398 F12, F12_H,
399 F13, F13_H,
400 F14, F14_H,
401 F15, F15_H,
402 F16, F16_H,
403 F17, F17_H,
404 F18, F18_H,
405 F19, F19_H,
406 F20, F20_H,
407 F21, F21_H,
408 F22, F22_H,
409 F23, F23_H,
410 F24, F24_H,
411 F25, F25_H,
412 F26, F26_H,
413 F27, F27_H,
414 F28, F28_H,
415 F29, F29_H,
416 F31, F31_H);
418 reg_class flt_arg0( F12 );
419 reg_class dbl_arg0( F12, F12_H );
420 reg_class dbl_arg1( F14, F14_H );
422 %}
424 //----------DEFINITION BLOCK---------------------------------------------------
425 // Define name --> value mappings to inform the ADLC of an integer valued name
426 // Current support includes integer values in the range [0, 0x7FFFFFFF]
427 // Format:
428 // int_def <name> ( <int_value>, <expression>);
429 // Generated Code in ad_<arch>.hpp
430 // #define <name> (<expression>)
431 // // value == <int_value>
432 // Generated code in ad_<arch>.cpp adlc_verification()
433 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
434 //
435 definitions %{
436 int_def DEFAULT_COST ( 100, 100);
437 int_def HUGE_COST (1000000, 1000000);
439 // Memory refs are twice as expensive as run-of-the-mill.
440 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
442 // Branches are even more expensive.
443 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
444 // we use jr instruction to construct call, so more expensive
445 // by yjl 2/28/2006
446 int_def CALL_COST ( 500, DEFAULT_COST * 5);
447 /*
448 int_def EQUAL ( 1, 1 );
449 int_def NOT_EQUAL ( 2, 2 );
450 int_def GREATER ( 3, 3 );
451 int_def GREATER_EQUAL ( 4, 4 );
452 int_def LESS ( 5, 5 );
453 int_def LESS_EQUAL ( 6, 6 );
454 */
455 %}
459 //----------SOURCE BLOCK-------------------------------------------------------
460 // This is a block of C++ code which provides values, functions, and
461 // definitions necessary in the rest of the architecture description
463 source_hpp %{
464 // Header information of the source block.
465 // Method declarations/definitions which are used outside
466 // the ad-scope can conveniently be defined here.
467 //
468 // To keep related declarations/definitions/uses close together,
469 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
471 class CallStubImpl {
473 //--------------------------------------------------------------
474 //---< Used for optimization in Compile::shorten_branches >---
475 //--------------------------------------------------------------
477 public:
478 // Size of call trampoline stub.
479 static uint size_call_trampoline() {
480 return 0; // no call trampolines on this platform
481 }
483 // number of relocations needed by a call trampoline stub
484 static uint reloc_call_trampoline() {
485 return 0; // no call trampolines on this platform
486 }
487 };
489 class HandlerImpl {
491 public:
493 static int emit_exception_handler(CodeBuffer &cbuf);
494 static int emit_deopt_handler(CodeBuffer& cbuf);
496 static uint size_exception_handler() {
497 // NativeCall instruction size is the same as NativeJump.
498 // exception handler starts out as jump and can be patched to
499 // a call be deoptimization. (4932387)
500 // Note that this value is also credited (in output.cpp) to
501 // the size of the code section.
502 // return NativeJump::instruction_size;
503 int size = NativeCall::instruction_size;
504 return round_to(size, 16);
505 }
507 #ifdef _LP64
508 static uint size_deopt_handler() {
509 int size = NativeCall::instruction_size;
510 return round_to(size, 16);
511 }
512 #else
513 static uint size_deopt_handler() {
514 // NativeCall instruction size is the same as NativeJump.
515 // exception handler starts out as jump and can be patched to
516 // a call be deoptimization. (4932387)
517 // Note that this value is also credited (in output.cpp) to
518 // the size of the code section.
519 return 5 + NativeJump::instruction_size; // pushl(); jmp;
520 }
521 #endif
522 };
524 %} // end source_hpp
526 source %{
528 #define NO_INDEX 0
529 #define RELOC_IMM64 Assembler::imm_operand
530 #define RELOC_DISP32 Assembler::disp32_operand
533 #define __ _masm.
536 // Emit exception handler code.
537 // Stuff framesize into a register and call a VM stub routine.
538 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
539 /*
540 // Note that the code buffer's insts_mark is always relative to insts.
541 // That's why we must use the macroassembler to generate a handler.
542 MacroAssembler _masm(&cbuf);
543 address base = __ start_a_stub(size_exception_handler());
544 if (base == NULL) return 0; // CodeBuffer::expand failed
545 int offset = __ offset();
546 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
547 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
548 __ end_a_stub();
549 return offset;
550 */
551 // Note that the code buffer's insts_mark is always relative to insts.
552 // That's why we must use the macroassembler to generate a handler.
553 MacroAssembler _masm(&cbuf);
554 address base =
555 __ start_a_stub(size_exception_handler());
556 if (base == NULL) return 0; // CodeBuffer::expand failed
557 int offset = __ offset();
559 __ block_comment("; emit_exception_handler");
561 /* 2012/9/25 FIXME Jin: According to X86, we should use direct jumpt.
562 * * However, this will trigger an assert after the 40th method:
563 * *
564 * * 39 b java.lang.Throwable::<init> (25 bytes)
565 * * --- ns java.lang.Throwable::fillInStackTrace
566 * * 40 !b java.net.URLClassLoader::findClass (29 bytes)
567 * * /vm/opto/runtime.cpp, 900 , assert(caller.is_compiled_frame(),"must be")
568 * * 40 made not entrant (2) java.net.URLClassLoader::findClass (29 bytes)
569 * *
570 * * If we change from JR to JALR, the assert will disappear, but WebClient will
571 * * fail after the 403th method with unknown reason.
572 * */
573 __ li48(T9, (long)OptoRuntime::exception_blob()->entry_point());
574 __ jr(T9);
575 __ delayed()->nop();
576 __ align(16);
577 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
578 __ end_a_stub();
579 return offset;
580 }
582 // Emit deopt handler code.
583 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
584 /*
585 // Note that the code buffer's insts_mark is always relative to insts.
586 // That's why we must use the macroassembler to generate a handler.
587 MacroAssembler _masm(&cbuf);
588 address base = __ start_a_stub(size_deopt_handler());
589 if (base == NULL) return 0; // CodeBuffer::expand failed
590 int offset = __ offset();
592 #ifdef _LP64
593 address the_pc = (address) __ pc();
594 Label next;
595 // push a "the_pc" on the stack without destroying any registers
596 // as they all may be live.
598 // push address of "next"
599 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
600 __ bind(next);
601 // adjust it so it matches "the_pc"
602 __ subptr(Address(rsp, 0), __ offset() - offset);
603 #else
604 InternalAddress here(__ pc());
605 __ pushptr(here.addr());
606 #endif
608 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
609 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
610 __ end_a_stub();
611 return offset;
612 */
613 // Note that the code buffer's insts_mark is always relative to insts.
614 // That's why we must use the macroassembler to generate a handler.
615 MacroAssembler _masm(&cbuf);
616 address base =
617 __ start_a_stub(size_deopt_handler());
619 // FIXME
620 if (base == NULL) return 0; // CodeBuffer::expand failed
621 int offset = __ offset();
623 __ block_comment("; emit_deopt_handler");
625 cbuf.set_insts_mark();
626 __ relocate(relocInfo::runtime_call_type);
628 __ li48(T9, (long)SharedRuntime::deopt_blob()->unpack());
629 __ jalr(T9);
630 __ delayed()->nop();
631 __ align(16);
632 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
633 __ end_a_stub();
634 return offset;
635 }
638 const bool Matcher::match_rule_supported(int opcode) {
639 if (!has_match_rule(opcode))
640 return false;
642 switch (opcode) {
643 //Op_CountLeadingZerosI Op_CountLeadingZerosL can be deleted, all MIPS CPUs support clz & dclz.
644 case Op_CountLeadingZerosI:
645 case Op_CountLeadingZerosL:
646 if (!UseCountLeadingZerosInstruction)
647 return false;
648 break;
649 case Op_CountTrailingZerosI:
650 case Op_CountTrailingZerosL:
651 if (!UseCountTrailingZerosInstruction)
652 return false;
653 break;
654 }
656 return true; // Per default match rules are supported.
657 }
659 //FIXME
660 // emit call stub, compiled java to interpreter
661 void emit_java_to_interp(CodeBuffer &cbuf ) {
662 // Stub is fixed up when the corresponding call is converted from calling
663 // compiled code to calling interpreted code.
664 // mov rbx,0
665 // jmp -1
667 address mark = cbuf.insts_mark(); // get mark within main instrs section
669 // Note that the code buffer's insts_mark is always relative to insts.
670 // That's why we must use the macroassembler to generate a stub.
671 MacroAssembler _masm(&cbuf);
673 address base =
674 __ start_a_stub(Compile::MAX_stubs_size);
675 if (base == NULL) return; // CodeBuffer::expand failed
676 // static stub relocation stores the instruction address of the call
678 __ relocate(static_stub_Relocation::spec(mark), 0);
680 /* 2012/10/29 Jin: Rmethod contains methodOop, it should be relocated for GC */
681 /*
682 int oop_index = __ oop_recorder()->allocate_index(NULL);
683 RelocationHolder rspec = oop_Relocation::spec(oop_index);
684 __ relocate(rspec);
685 */
687 // static stub relocation also tags the methodOop in the code-stream.
688 __ li48(S3, (long)0);
689 // This is recognized as unresolved by relocs/nativeInst/ic code
691 __ relocate(relocInfo::runtime_call_type);
693 cbuf.set_insts_mark();
694 address call_pc = (address)-1;
695 __ li48(AT, (long)call_pc);
696 __ jr(AT);
697 __ nop();
698 __ align(16);
699 __ end_a_stub();
700 // Update current stubs pointer and restore code_end.
701 }
703 // size of call stub, compiled java to interpretor
704 uint size_java_to_interp() {
705 int size = 4 * 4 + NativeCall::instruction_size; // sizeof(li48) + NativeCall::instruction_size
706 return round_to(size, 16);
707 }
709 // relocation entries for call stub, compiled java to interpreter
710 uint reloc_java_to_interp() {
711 return 16; // in emit_java_to_interp + in Java_Static_Call
712 }
714 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
715 if( Assembler::is_simm16(offset) ) return true;
716 else
717 {
718 assert(false, "Not implemented yet !" );
719 Unimplemented();
720 }
721 }
724 // No additional cost for CMOVL.
725 const int Matcher::long_cmove_cost() { return 0; }
727 // No CMOVF/CMOVD with SSE2
728 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
730 // Does the CPU require late expand (see block.cpp for description of late expand)?
731 const bool Matcher::require_postalloc_expand = false;
733 // Should the Matcher clone shifts on addressing modes, expecting them
734 // to be subsumed into complex addressing expressions or compute them
735 // into registers? True for Intel but false for most RISCs
736 const bool Matcher::clone_shift_expressions = false;
738 // Do we need to mask the count passed to shift instructions or does
739 // the cpu only look at the lower 5/6 bits anyway?
740 const bool Matcher::need_masked_shift_count = false;
742 bool Matcher::narrow_oop_use_complex_address() {
743 NOT_LP64(ShouldNotCallThis());
744 assert(UseCompressedOops, "only for compressed oops code");
745 return false;
746 }
748 bool Matcher::narrow_klass_use_complex_address() {
749 NOT_LP64(ShouldNotCallThis());
750 assert(UseCompressedClassPointers, "only for compressed klass code");
751 return false;
752 }
754 // This is UltraSparc specific, true just means we have fast l2f conversion
755 const bool Matcher::convL2FSupported(void) {
756 return true;
757 }
759 // Max vector size in bytes. 0 if not supported.
760 const int Matcher::vector_width_in_bytes(BasicType bt) {
761 assert(MaxVectorSize == 8, "");
762 return 8;
763 }
765 // Vector ideal reg
766 const int Matcher::vector_ideal_reg(int size) {
767 assert(MaxVectorSize == 8, "");
768 switch(size) {
769 case 8: return Op_VecD;
770 }
771 ShouldNotReachHere();
772 return 0;
773 }
775 // Only lowest bits of xmm reg are used for vector shift count.
776 const int Matcher::vector_shift_count_ideal_reg(int size) {
777 fatal("vector shift is not supported");
778 return Node::NotAMachineReg;
779 }
781 // Limits on vector size (number of elements) loaded into vector.
782 const int Matcher::max_vector_size(const BasicType bt) {
783 assert(is_java_primitive(bt), "only primitive type vectors");
784 return vector_width_in_bytes(bt)/type2aelembytes(bt);
785 }
787 const int Matcher::min_vector_size(const BasicType bt) {
788 return max_vector_size(bt); // Same as max.
789 }
791 // MIPS supports misaligned vectors store/load? FIXME
792 const bool Matcher::misaligned_vectors_ok() {
793 return false;
794 //return !AlignVector; // can be changed by flag
795 }
797 // Register for DIVI projection of divmodI
798 RegMask Matcher::divI_proj_mask() {
799 ShouldNotReachHere();
800 return RegMask();
801 }
803 // Register for MODI projection of divmodI
804 RegMask Matcher::modI_proj_mask() {
805 ShouldNotReachHere();
806 return RegMask();
807 }
809 // Register for DIVL projection of divmodL
810 RegMask Matcher::divL_proj_mask() {
811 ShouldNotReachHere();
812 return RegMask();
813 }
815 int Matcher::regnum_to_fpu_offset(int regnum) {
816 return regnum - 32; // The FP registers are in the second chunk
817 }
820 const bool Matcher::isSimpleConstant64(jlong value) {
821 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
822 return true;
823 }
826 // Return whether or not this register is ever used as an argument. This
827 // function is used on startup to build the trampoline stubs in generateOptoStub.
828 // Registers not mentioned will be killed by the VM call in the trampoline, and
829 // arguments in those registers not be available to the callee.
830 bool Matcher::can_be_java_arg( int reg ) {
831 /* Refer to: [sharedRuntime_mips_64.cpp] SharedRuntime::java_calling_convention() */
832 if ( reg == T0_num || reg == T0_H_num
833 || reg == A0_num || reg == A0_H_num
834 || reg == A1_num || reg == A1_H_num
835 || reg == A2_num || reg == A2_H_num
836 || reg == A3_num || reg == A3_H_num
837 || reg == A4_num || reg == A4_H_num
838 || reg == A5_num || reg == A5_H_num
839 || reg == A6_num || reg == A6_H_num
840 || reg == A7_num || reg == A7_H_num )
841 return true;
843 if ( reg == F12_num || reg == F12_H_num
844 || reg == F13_num || reg == F13_H_num
845 || reg == F14_num || reg == F14_H_num
846 || reg == F15_num || reg == F15_H_num
847 || reg == F16_num || reg == F16_H_num
848 || reg == F17_num || reg == F17_H_num
849 || reg == F18_num || reg == F18_H_num
850 || reg == F19_num || reg == F19_H_num )
851 return true;
853 return false;
854 }
856 bool Matcher::is_spillable_arg( int reg ) {
857 return can_be_java_arg(reg);
858 }
860 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
861 return false;
862 }
864 // Register for MODL projection of divmodL
865 RegMask Matcher::modL_proj_mask() {
866 ShouldNotReachHere();
867 return RegMask();
868 }
870 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
871 return FP_REG_mask();
872 }
874 // MIPS doesn't support AES intrinsics
875 const bool Matcher::pass_original_key_for_aes() {
876 return false;
877 }
879 // The address of the call instruction needs to be 16-byte aligned to
880 // ensure that it does not span a cache line so that it can be patched.
882 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
883 //lui
884 //ori
885 //dsll
886 //ori
888 //jalr
889 //nop
891 return round_to(current_offset, alignment_required()) - current_offset;
892 }
894 // The address of the call instruction needs to be 16-byte aligned to
895 // ensure that it does not span a cache line so that it can be patched.
896 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
897 //li64 <--- skip
899 //lui
900 //ori
901 //dsll
902 //ori
904 //jalr
905 //nop
907 current_offset += 4 * 6; // skip li64
908 return round_to(current_offset, alignment_required()) - current_offset;
909 }
911 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
912 //lui
913 //ori
914 //dsll
915 //ori
917 //jalr
918 //nop
920 return round_to(current_offset, alignment_required()) - current_offset;
921 }
923 int CallLeafDirectNode::compute_padding(int current_offset) const {
924 //lui
925 //ori
926 //dsll
927 //ori
929 //jalr
930 //nop
932 return round_to(current_offset, alignment_required()) - current_offset;
933 }
935 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
936 //lui
937 //ori
938 //dsll
939 //ori
941 //jalr
942 //nop
944 return round_to(current_offset, alignment_required()) - current_offset;
945 }
947 // If CPU can load and store mis-aligned doubles directly then no fixup is
948 // needed. Else we split the double into 2 integer pieces and move it
949 // piece-by-piece. Only happens when passing doubles into C code as the
950 // Java calling convention forces doubles to be aligned.
951 const bool Matcher::misaligned_doubles_ok = false;
952 // Do floats take an entire double register or just half?
953 //const bool Matcher::float_in_double = true;
954 bool Matcher::float_in_double() { return false; }
955 // Threshold size for cleararray.
956 const int Matcher::init_array_short_size = 8 * BytesPerLong;
957 // Do ints take an entire long register or just half?
958 const bool Matcher::int_in_long = true;
959 // Is it better to copy float constants, or load them directly from memory?
960 // Intel can load a float constant from a direct address, requiring no
961 // extra registers. Most RISCs will have to materialize an address into a
962 // register first, so they would do better to copy the constant from stack.
963 const bool Matcher::rematerialize_float_constants = false;
964 // Advertise here if the CPU requires explicit rounding operations
965 // to implement the UseStrictFP mode.
966 const bool Matcher::strict_fp_requires_explicit_rounding = false;
967 // The ecx parameter to rep stos for the ClearArray node is in dwords.
968 const bool Matcher::init_array_count_is_in_bytes = false;
971 // Indicate if the safepoint node needs the polling page as an input.
972 // Since MIPS doesn't have absolute addressing, it needs.
973 bool SafePointNode::needs_polling_address_input() {
974 return true;
975 }
977 // !!!!! Special hack to get all type of calls to specify the byte offset
978 // from the start of the call to the point where the return address
979 // will point.
980 int MachCallStaticJavaNode::ret_addr_offset() {
981 assert(NativeCall::instruction_size == 24, "in MachCallStaticJavaNode::ret_addr_offset");
982 //The value ought to be 16 bytes.
983 //lui
984 //ori
985 //dsll
986 //ori
987 //jalr
988 //nop
989 return NativeCall::instruction_size;
990 }
992 int MachCallDynamicJavaNode::ret_addr_offset() {
993 /* 2012/9/10 Jin: must be kept in sync with Java_Dynamic_Call */
995 // return NativeCall::instruction_size;
996 assert(NativeCall::instruction_size == 24, "in MachCallDynamicJavaNode::ret_addr_offset");
997 //The value ought to be 4 + 16 bytes.
998 //lui IC_Klass,
999 //ori IC_Klass,
1000 //dsll IC_Klass
1001 //ori IC_Klass
1002 //lui T9
1003 //ori T9
1004 //dsll T9
1005 //ori T9
1006 //jalr T9
1007 //nop
1008 return 6 * 4 + NativeCall::instruction_size;
1010 }
1012 /*
1013 // EMIT_OPCODE()
1014 void emit_opcode(CodeBuffer &cbuf, int code) {
1015 *(cbuf.code_end()) = (unsigned char)code;
1016 cbuf.set_code_end(cbuf.code_end() + 1);
1017 }
1018 */
1020 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
1021 int format) {
1022 cbuf.relocate(cbuf.insts_mark(), reloc, format);
1023 cbuf.insts()->emit_int32(d32);
1024 }
1026 //=============================================================================
1028 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1029 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1030 static enum RC rc_class( OptoReg::Name reg ) {
1031 if( !OptoReg::is_valid(reg) ) return rc_bad;
1032 if (OptoReg::is_stack(reg)) return rc_stack;
1033 VMReg r = OptoReg::as_VMReg(reg);
1034 if (r->is_Register()) return rc_int;
1035 assert(r->is_FloatRegister(), "must be");
1036 return rc_float;
1037 }
1039 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
1040 // Get registers to move
1041 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1042 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1043 OptoReg::Name dst_second = ra_->get_reg_second(this );
1044 OptoReg::Name dst_first = ra_->get_reg_first(this );
1046 enum RC src_second_rc = rc_class(src_second);
1047 enum RC src_first_rc = rc_class(src_first);
1048 enum RC dst_second_rc = rc_class(dst_second);
1049 enum RC dst_first_rc = rc_class(dst_first);
1051 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1053 // Generate spill code!
1054 int size = 0;
1056 if( src_first == dst_first && src_second == dst_second )
1057 return 0; // Self copy, no move
1059 if (src_first_rc == rc_stack) {
1060 // mem ->
1061 if (dst_first_rc == rc_stack) {
1062 // mem -> mem
1063 assert(src_second != dst_first, "overlap");
1064 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1065 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1066 // 64-bit
1067 int src_offset = ra_->reg2offset(src_first);
1068 int dst_offset = ra_->reg2offset(dst_first);
1069 if (cbuf) {
1070 MacroAssembler _masm(cbuf);
1071 __ ld(AT, Address(SP, src_offset));
1072 __ sd(AT, Address(SP, dst_offset));
1073 #ifndef PRODUCT
1074 } else {
1075 if(!do_size){
1076 if (size != 0) st->print("\n\t");
1077 st->print("ld AT, [SP + #%d]\t# 64-bit mem-mem spill 1\n\t"
1078 "sd AT, [SP + #%d]",
1079 src_offset, dst_offset);
1080 }
1081 #endif
1082 }
1083 size += 8;
1084 } else {
1085 // 32-bit
1086 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1087 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1088 // No pushl/popl, so:
1089 int src_offset = ra_->reg2offset(src_first);
1090 int dst_offset = ra_->reg2offset(dst_first);
1091 if (cbuf) {
1092 MacroAssembler _masm(cbuf);
1093 __ lw(AT, Address(SP, src_offset));
1094 __ sw(AT, Address(SP, dst_offset));
1095 #ifndef PRODUCT
1096 } else {
1097 if(!do_size){
1098 if (size != 0) st->print("\n\t");
1099 st->print("lw AT, [SP + #%d] spill 2\n\t"
1100 "sw AT, [SP + #%d]\n\t",
1101 src_offset, dst_offset);
1102 }
1103 #endif
1104 }
1105 size += 8;
1106 }
1107 return size;
1108 } else if (dst_first_rc == rc_int) {
1109 // mem -> gpr
1110 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1111 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1112 // 64-bit
1113 int offset = ra_->reg2offset(src_first);
1114 if (cbuf) {
1115 MacroAssembler _masm(cbuf);
1116 __ ld(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1117 #ifndef PRODUCT
1118 } else {
1119 if(!do_size){
1120 if (size != 0) st->print("\n\t");
1121 st->print("ld %s, [SP + #%d]\t# spill 3",
1122 Matcher::regName[dst_first],
1123 offset);
1124 }
1125 #endif
1126 }
1127 size += 4;
1128 } else {
1129 // 32-bit
1130 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1131 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1132 int offset = ra_->reg2offset(src_first);
1133 if (cbuf) {
1134 MacroAssembler _masm(cbuf);
1135 if (this->ideal_reg() == Op_RegI)
1136 __ lw(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1137 else
1138 __ lwu(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1139 #ifndef PRODUCT
1140 } else {
1141 if(!do_size){
1142 if (size != 0) st->print("\n\t");
1143 if (this->ideal_reg() == Op_RegI)
1144 st->print("lw %s, [SP + #%d]\t# spill 4",
1145 Matcher::regName[dst_first],
1146 offset);
1147 else
1148 st->print("lwu %s, [SP + #%d]\t# spill 5",
1149 Matcher::regName[dst_first],
1150 offset);
1151 }
1152 #endif
1153 }
1154 size += 4;
1155 }
1156 return size;
1157 } else if (dst_first_rc == rc_float) {
1158 // mem-> xmm
1159 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1160 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1161 // 64-bit
1162 int offset = ra_->reg2offset(src_first);
1163 if (cbuf) {
1164 MacroAssembler _masm(cbuf);
1165 __ ldc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1166 #ifndef PRODUCT
1167 } else {
1168 if(!do_size){
1169 if (size != 0) st->print("\n\t");
1170 st->print("ldc1 %s, [SP + #%d]\t# spill 6",
1171 Matcher::regName[dst_first],
1172 offset);
1173 }
1174 #endif
1175 }
1176 size += 4;
1177 } else {
1178 // 32-bit
1179 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1180 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1181 int offset = ra_->reg2offset(src_first);
1182 if (cbuf) {
1183 MacroAssembler _masm(cbuf);
1184 __ lwc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1185 #ifndef PRODUCT
1186 } else {
1187 if(!do_size){
1188 if (size != 0) st->print("\n\t");
1189 st->print("lwc1 %s, [SP + #%d]\t# spill 7",
1190 Matcher::regName[dst_first],
1191 offset);
1192 }
1193 #endif
1194 }
1195 size += 4;
1196 }
1197 return size;
1198 }
1199 } else if (src_first_rc == rc_int) {
1200 // gpr ->
1201 if (dst_first_rc == rc_stack) {
1202 // gpr -> mem
1203 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1204 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1205 // 64-bit
1206 int offset = ra_->reg2offset(dst_first);
1207 if (cbuf) {
1208 MacroAssembler _masm(cbuf);
1209 __ sd(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1210 #ifndef PRODUCT
1211 } else {
1212 if(!do_size){
1213 if (size != 0) st->print("\n\t");
1214 st->print("sd %s, [SP + #%d] # spill 8",
1215 Matcher::regName[src_first],
1216 offset);
1217 }
1218 #endif
1219 }
1220 size += 4;
1221 } else {
1222 // 32-bit
1223 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1224 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1225 int offset = ra_->reg2offset(dst_first);
1226 if (cbuf) {
1227 MacroAssembler _masm(cbuf);
1228 __ sw(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1229 #ifndef PRODUCT
1230 } else {
1231 if(!do_size){
1232 if (size != 0) st->print("\n\t");
1233 st->print("sw %s, [SP + #%d]\t# spill 9",
1234 Matcher::regName[src_first], offset);
1235 }
1236 #endif
1237 }
1238 size += 4;
1239 }
1240 return size;
1241 } else if (dst_first_rc == rc_int) {
1242 // gpr -> gpr
1243 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1244 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1245 // 64-bit
1246 if (cbuf) {
1247 MacroAssembler _masm(cbuf);
1248 __ move(as_Register(Matcher::_regEncode[dst_first]),
1249 as_Register(Matcher::_regEncode[src_first]));
1250 #ifndef PRODUCT
1251 } else {
1252 if(!do_size){
1253 if (size != 0) st->print("\n\t");
1254 st->print("move(64bit) %s <-- %s\t# spill 10",
1255 Matcher::regName[dst_first],
1256 Matcher::regName[src_first]);
1257 }
1258 #endif
1259 }
1260 size += 4;
1261 return size;
1262 } else {
1263 // 32-bit
1264 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1265 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1266 if (cbuf) {
1267 MacroAssembler _masm(cbuf);
1268 if (this->ideal_reg() == Op_RegI)
1269 __ move_u32(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1270 else
1271 __ daddu(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]), R0);
1273 #ifndef PRODUCT
1274 } else {
1275 if(!do_size){
1276 if (size != 0) st->print("\n\t");
1277 st->print("move(32-bit) %s <-- %s\t# spill 11",
1278 Matcher::regName[dst_first],
1279 Matcher::regName[src_first]);
1280 }
1281 #endif
1282 }
1283 size += 4;
1284 return size;
1285 }
1286 } else if (dst_first_rc == rc_float) {
1287 // gpr -> xmm
1288 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1289 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1290 // 64-bit
1291 if (cbuf) {
1292 MacroAssembler _masm(cbuf);
1293 __ dmtc1(as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]));
1294 #ifndef PRODUCT
1295 } else {
1296 if(!do_size){
1297 if (size != 0) st->print("\n\t");
1298 st->print("dmtc1 %s, %s\t# spill 12",
1299 Matcher::regName[dst_first],
1300 Matcher::regName[src_first]);
1301 }
1302 #endif
1303 }
1304 size += 4;
1305 } else {
1306 // 32-bit
1307 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1308 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1309 if (cbuf) {
1310 MacroAssembler _masm(cbuf);
1311 __ mtc1( as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]) );
1312 #ifndef PRODUCT
1313 } else {
1314 if(!do_size){
1315 if (size != 0) st->print("\n\t");
1316 st->print("mtc1 %s, %s\t# spill 13",
1317 Matcher::regName[dst_first],
1318 Matcher::regName[src_first]);
1319 }
1320 #endif
1321 }
1322 size += 4;
1323 }
1324 return size;
1325 }
1326 } else if (src_first_rc == rc_float) {
1327 // xmm ->
1328 if (dst_first_rc == rc_stack) {
1329 // xmm -> mem
1330 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1331 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1332 // 64-bit
1333 int offset = ra_->reg2offset(dst_first);
1334 if (cbuf) {
1335 MacroAssembler _masm(cbuf);
1336 __ sdc1( as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset) );
1337 #ifndef PRODUCT
1338 } else {
1339 if(!do_size){
1340 if (size != 0) st->print("\n\t");
1341 st->print("sdc1 %s, [SP + #%d]\t# spill 14",
1342 Matcher::regName[src_first],
1343 offset);
1344 }
1345 #endif
1346 }
1347 size += 4;
1348 } else {
1349 // 32-bit
1350 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1351 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1352 int offset = ra_->reg2offset(dst_first);
1353 if (cbuf) {
1354 MacroAssembler _masm(cbuf);
1355 __ swc1(as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset));
1356 #ifndef PRODUCT
1357 } else {
1358 if(!do_size){
1359 if (size != 0) st->print("\n\t");
1360 st->print("swc1 %s, [SP + #%d]\t# spill 15",
1361 Matcher::regName[src_first],
1362 offset);
1363 }
1364 #endif
1365 }
1366 size += 4;
1367 }
1368 return size;
1369 } else if (dst_first_rc == rc_int) {
1370 // xmm -> gpr
1371 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1372 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1373 // 64-bit
1374 if (cbuf) {
1375 MacroAssembler _masm(cbuf);
1376 __ dmfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1377 #ifndef PRODUCT
1378 } else {
1379 if(!do_size){
1380 if (size != 0) st->print("\n\t");
1381 st->print("dmfc1 %s, %s\t# spill 16",
1382 Matcher::regName[dst_first],
1383 Matcher::regName[src_first]);
1384 }
1385 #endif
1386 }
1387 size += 4;
1388 } else {
1389 // 32-bit
1390 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1391 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1392 if (cbuf) {
1393 MacroAssembler _masm(cbuf);
1394 __ mfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1395 #ifndef PRODUCT
1396 } else {
1397 if(!do_size){
1398 if (size != 0) st->print("\n\t");
1399 st->print("mfc1 %s, %s\t# spill 17",
1400 Matcher::regName[dst_first],
1401 Matcher::regName[src_first]);
1402 }
1403 #endif
1404 }
1405 size += 4;
1406 }
1407 return size;
1408 } else if (dst_first_rc == rc_float) {
1409 // xmm -> xmm
1410 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1411 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1412 // 64-bit
1413 if (cbuf) {
1414 MacroAssembler _masm(cbuf);
1415 __ mov_d( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1416 #ifndef PRODUCT
1417 } else {
1418 if(!do_size){
1419 if (size != 0) st->print("\n\t");
1420 st->print("mov_d %s <-- %s\t# spill 18",
1421 Matcher::regName[dst_first],
1422 Matcher::regName[src_first]);
1423 }
1424 #endif
1425 }
1426 size += 4;
1427 } else {
1428 // 32-bit
1429 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1430 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1431 if (cbuf) {
1432 MacroAssembler _masm(cbuf);
1433 __ mov_s( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1434 #ifndef PRODUCT
1435 } else {
1436 if(!do_size){
1437 if (size != 0) st->print("\n\t");
1438 st->print("mov_s %s <-- %s\t# spill 19",
1439 Matcher::regName[dst_first],
1440 Matcher::regName[src_first]);
1441 }
1442 #endif
1443 }
1444 size += 4;
1445 }
1446 return size;
1447 }
1448 }
1450 assert(0," foo ");
1451 Unimplemented();
1452 return size;
1454 }
1456 #ifndef PRODUCT
1457 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1458 implementation( NULL, ra_, false, st );
1459 }
1460 #endif
1462 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1463 implementation( &cbuf, ra_, false, NULL );
1464 }
1466 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1467 return implementation( NULL, ra_, true, NULL );
1468 }
1470 //=============================================================================
1471 #
1473 #ifndef PRODUCT
1474 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
1475 st->print("INT3");
1476 }
1477 #endif
1479 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
1480 MacroAssembler _masm(&cbuf);
1481 __ int3();
1482 }
1484 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
1485 return MachNode::size(ra_);
1486 }
1489 //=============================================================================
1490 #ifndef PRODUCT
1491 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1492 Compile *C = ra_->C;
1493 int framesize = C->frame_size_in_bytes();
1495 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1497 st->print("daddiu SP, SP, %d # Rlease stack @ MachEpilogNode",framesize);
1498 st->cr(); st->print("\t");
1499 if (UseLoongsonISA) {
1500 st->print("gslq RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
1501 } else {
1502 st->print("ld RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
1503 st->cr(); st->print("\t");
1504 st->print("ld FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
1505 }
1507 if( do_polling() && C->is_method_compilation() ) {
1508 st->print("Poll Safepoint # MachEpilogNode");
1509 }
1510 }
1511 #endif
1513 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1514 Compile *C = ra_->C;
1515 MacroAssembler _masm(&cbuf);
1516 int framesize = C->frame_size_in_bytes();
1518 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1520 __ daddiu(SP, SP, framesize);
1522 if (UseLoongsonISA) {
1523 __ gslq(RA, FP, SP, -wordSize*2);
1524 } else {
1525 __ ld(RA, SP, -wordSize );
1526 __ ld(FP, SP, -wordSize*2 );
1527 }
1529 /* 2012/11/19 Jin: The epilog in a RuntimeStub should not contain a safepoint */
1530 if( do_polling() && C->is_method_compilation() ) {
1531 #ifndef OPT_SAFEPOINT
1532 __ set64(AT, (long)os::get_polling_page());
1533 __ relocate(relocInfo::poll_return_type);
1534 __ lw(AT, AT, 0);
1535 #else
1536 __ lui(AT, Assembler::split_high((intptr_t)os::get_polling_page()));
1537 __ relocate(relocInfo::poll_return_type);
1538 __ lw(AT, AT, Assembler::split_low((intptr_t)os::get_polling_page()));
1539 #endif
1540 }
1541 }
1543 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1544 return MachNode::size(ra_); // too many variables; just compute it the hard way fujie debug
1545 }
1547 int MachEpilogNode::reloc() const {
1548 return 0; // a large enough number
1549 }
1551 const Pipeline * MachEpilogNode::pipeline() const {
1552 return MachNode::pipeline_class();
1553 }
1555 int MachEpilogNode::safepoint_offset() const { return 0; }
1557 //=============================================================================
1559 #ifndef PRODUCT
1560 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1561 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1562 int reg = ra_->get_reg_first(this);
1563 st->print("ADDI %s, SP, %d @BoxLockNode",Matcher::regName[reg],offset);
1564 }
1565 #endif
1568 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1569 return 4;
1570 }
1572 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1573 MacroAssembler _masm(&cbuf);
1574 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1575 int reg = ra_->get_encode(this);
1577 __ addi(as_Register(reg), SP, offset);
1578 /*
1579 if( offset >= 128 ) {
1580 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1581 emit_rm(cbuf, 0x2, reg, 0x04);
1582 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1583 emit_d32(cbuf, offset);
1584 }
1585 else {
1586 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1587 emit_rm(cbuf, 0x1, reg, 0x04);
1588 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1589 emit_d8(cbuf, offset);
1590 }
1591 */
1592 }
1595 //static int sizeof_FFree_Float_Stack_All = -1;
1597 int MachCallRuntimeNode::ret_addr_offset() {
1598 //lui
1599 //ori
1600 //dsll
1601 //ori
1602 //jalr
1603 //nop
1604 assert(NativeCall::instruction_size == 24, "in MachCallRuntimeNode::ret_addr_offset()");
1605 return NativeCall::instruction_size;
1606 // return 16;
1607 }
1613 //=============================================================================
1614 #ifndef PRODUCT
1615 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1616 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1617 }
1618 #endif
1620 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1621 MacroAssembler _masm(&cbuf);
1622 int i = 0;
1623 for(i = 0; i < _count; i++)
1624 __ nop();
1625 }
1627 uint MachNopNode::size(PhaseRegAlloc *) const {
1628 return 4 * _count;
1629 }
1630 const Pipeline* MachNopNode::pipeline() const {
1631 return MachNode::pipeline_class();
1632 }
1634 //=============================================================================
1636 //=============================================================================
1637 #ifndef PRODUCT
1638 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1639 st->print_cr("load_klass(AT, T0)");
1640 st->print_cr("\tbeq(AT, iCache, L)");
1641 st->print_cr("\tnop");
1642 st->print_cr("\tjmp(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type)");
1643 st->print_cr("\tnop");
1644 st->print_cr("\tnop");
1645 st->print_cr(" L:");
1646 }
1647 #endif
1650 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1651 MacroAssembler _masm(&cbuf);
1652 #ifdef ASSERT
1653 //uint code_size = cbuf.code_size();
1654 #endif
1655 int ic_reg = Matcher::inline_cache_reg_encode();
1656 Label L;
1657 Register receiver = T0;
1658 Register iCache = as_Register(ic_reg);
1659 __ load_klass(AT, receiver);
1660 __ beq(AT, iCache, L);
1661 __ nop();
1663 __ relocate(relocInfo::runtime_call_type);
1664 __ li48(T9, (long)SharedRuntime::get_ic_miss_stub());
1665 __ jr(T9);
1666 __ nop();
1668 /* WARNING these NOPs are critical so that verified entry point is properly
1669 * 8 bytes aligned for patching by NativeJump::patch_verified_entry() */
1670 __ align(CodeEntryAlignment);
1671 __ bind(L);
1672 }
1674 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1675 return MachNode::size(ra_);
1676 }
1680 //=============================================================================
1682 const RegMask& MachConstantBaseNode::_out_RegMask = P_REG_mask();
1684 int Compile::ConstantTable::calculate_table_base_offset() const {
1685 return 0; // absolute addressing, no offset
1686 }
1688 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1689 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1690 ShouldNotReachHere();
1691 }
1693 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1694 Compile* C = ra_->C;
1695 Compile::ConstantTable& constant_table = C->constant_table();
1696 MacroAssembler _masm(&cbuf);
1698 Register Rtoc = as_Register(ra_->get_encode(this));
1699 CodeSection* consts_section = __ code()->consts();
1700 int consts_size = consts_section->align_at_start(consts_section->size());
1701 assert(constant_table.size() == consts_size, "must be equal");
1703 if (consts_section->size()) {
1704 // Materialize the constant table base.
1705 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1706 // RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1707 __ relocate(relocInfo::internal_pc_type);
1708 __ li48(Rtoc, (long)baseaddr);
1709 }
1710 }
1712 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1713 // li48 (4 insts)
1714 return 4 * 4;
1715 }
1717 #ifndef PRODUCT
1718 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1719 Register r = as_Register(ra_->get_encode(this));
1720 st->print("li48 %s, &constanttable (constant table base) @ MachConstantBaseNode", r->name());
1721 }
1722 #endif
1725 //=============================================================================
1726 #ifndef PRODUCT
1727 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1728 Compile* C = ra_->C;
1730 int framesize = C->frame_size_in_bytes();
1731 int bangsize = C->bang_size_in_bytes();
1732 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1734 // Calls to C2R adapters often do not accept exceptional returns.
1735 // We require that their callers must bang for them. But be careful, because
1736 // some VM calls (such as call site linkage) can use several kilobytes of
1737 // stack. But the stack safety zone should account for that.
1738 // See bugs 4446381, 4468289, 4497237.
1739 if (C->need_stack_bang(bangsize)) {
1740 st->print_cr("# stack bang"); st->print("\t");
1741 }
1742 if (UseLoongsonISA) {
1743 st->print("gssq RA, FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1744 } else {
1745 st->print("sd RA, %d(SP) @ MachPrologNode\n\t", -wordSize);
1746 st->print("sd FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1747 }
1748 st->print("daddiu FP, SP, -%d \n\t", wordSize*2);
1749 st->print("daddiu SP, SP, -%d \t",framesize);
1750 }
1751 #endif
1754 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1755 Compile* C = ra_->C;
1756 MacroAssembler _masm(&cbuf);
1758 int framesize = C->frame_size_in_bytes();
1759 int bangsize = C->bang_size_in_bytes();
1761 // __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
1763 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1765 if (C->need_stack_bang(framesize)) {
1766 __ generate_stack_overflow_check(framesize);
1767 }
1769 if (UseLoongsonISA) {
1770 __ gssq(RA, FP, SP, -wordSize*2);
1771 } else {
1772 __ sd(RA, SP, -wordSize);
1773 __ sd(FP, SP, -wordSize*2);
1774 }
1775 __ daddiu(FP, SP, -wordSize*2);
1776 __ daddiu(SP, SP, -framesize);
1777 __ nop(); /* 2013.10.22 Jin: Make enough room for patch_verified_entry() */
1778 __ nop();
1780 C->set_frame_complete(cbuf.insts_size());
1781 if (C->has_mach_constant_base_node()) {
1782 // NOTE: We set the table base offset here because users might be
1783 // emitted before MachConstantBaseNode.
1784 Compile::ConstantTable& constant_table = C->constant_table();
1785 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1786 }
1788 }
1791 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1792 //fprintf(stderr, "\nPrologNode::size(ra_)= %d \n", MachNode::size(ra_));//fujie debug
1793 return MachNode::size(ra_); // too many variables; just compute it the hard way
1794 }
1796 int MachPrologNode::reloc() const {
1797 return 0; // a large enough number
1798 }
1800 %}
1802 //----------ENCODING BLOCK-----------------------------------------------------
1803 // This block specifies the encoding classes used by the compiler to output
1804 // byte streams. Encoding classes generate functions which are called by
1805 // Machine Instruction Nodes in order to generate the bit encoding of the
1806 // instruction. Operands specify their base encoding interface with the
1807 // interface keyword. There are currently supported four interfaces,
1808 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1809 // operand to generate a function which returns its register number when
1810 // queried. CONST_INTER causes an operand to generate a function which
1811 // returns the value of the constant when queried. MEMORY_INTER causes an
1812 // operand to generate four functions which return the Base Register, the
1813 // Index Register, the Scale Value, and the Offset Value of the operand when
1814 // queried. COND_INTER causes an operand to generate six functions which
1815 // return the encoding code (ie - encoding bits for the instruction)
1816 // associated with each basic boolean condition for a conditional instruction.
1817 // Instructions specify two basic values for encoding. They use the
1818 // ins_encode keyword to specify their encoding class (which must be one of
1819 // the class names specified in the encoding block), and they use the
1820 // opcode keyword to specify, in order, their primary, secondary, and
1821 // tertiary opcode. Only the opcode sections which a particular instruction
1822 // needs for encoding need to be specified.
1823 encode %{
1824 /*
1825 Alias:
1826 1044 b java.io.ObjectInputStream::readHandle (130 bytes)
1827 118 B14: # B19 B15 <- B13 Freq: 0.899955
1828 118 add S1, S2, V0 #@addP_reg_reg
1829 11c lb S0, [S1 + #-8257524] #@loadB
1830 120 BReq S0, #3, B19 #@branchConI_reg_imm P=0.100000 C=-1.000000
1831 */
1832 //Load byte signed
1833 enc_class load_B_enc (mRegI dst, memory mem) %{
1834 MacroAssembler _masm(&cbuf);
1835 int dst = $dst$$reg;
1836 int base = $mem$$base;
1837 int index = $mem$$index;
1838 int scale = $mem$$scale;
1839 int disp = $mem$$disp;
1841 if( index != 0 ) {
1842 if( Assembler::is_simm16(disp) ) {
1843 if( UseLoongsonISA ) {
1844 if (scale == 0) {
1845 __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1846 } else {
1847 __ dsll(AT, as_Register(index), scale);
1848 __ gslbx(as_Register(dst), as_Register(base), AT, disp);
1849 }
1850 } else {
1851 if (scale == 0) {
1852 __ addu(AT, as_Register(base), as_Register(index));
1853 } else {
1854 __ dsll(AT, as_Register(index), scale);
1855 __ addu(AT, as_Register(base), AT);
1856 }
1857 __ lb(as_Register(dst), AT, disp);
1858 }
1859 } else {
1860 if (scale == 0) {
1861 __ addu(AT, as_Register(base), as_Register(index));
1862 } else {
1863 __ dsll(AT, as_Register(index), scale);
1864 __ addu(AT, as_Register(base), AT);
1865 }
1866 __ move(T9, disp);
1867 if( UseLoongsonISA ) {
1868 __ gslbx(as_Register(dst), AT, T9, 0);
1869 } else {
1870 __ addu(AT, AT, T9);
1871 __ lb(as_Register(dst), AT, 0);
1872 }
1873 }
1874 } else {
1875 if( Assembler::is_simm16(disp) ) {
1876 __ lb(as_Register(dst), as_Register(base), disp);
1877 } else {
1878 __ move(T9, disp);
1879 if( UseLoongsonISA ) {
1880 __ gslbx(as_Register(dst), as_Register(base), T9, 0);
1881 } else {
1882 __ addu(AT, as_Register(base), T9);
1883 __ lb(as_Register(dst), AT, 0);
1884 }
1885 }
1886 }
1887 %}
1889 //Load byte unsigned
1890 enc_class load_UB_enc (mRegI dst, memory mem) %{
1891 MacroAssembler _masm(&cbuf);
1892 int dst = $dst$$reg;
1893 int base = $mem$$base;
1894 int index = $mem$$index;
1895 int scale = $mem$$scale;
1896 int disp = $mem$$disp;
1898 if( index != 0 ) {
1899 if (scale == 0) {
1900 __ daddu(AT, as_Register(base), as_Register(index));
1901 } else {
1902 __ dsll(AT, as_Register(index), scale);
1903 __ daddu(AT, as_Register(base), AT);
1904 }
1905 if( Assembler::is_simm16(disp) ) {
1906 __ lbu(as_Register(dst), AT, disp);
1907 } else {
1908 __ move(T9, disp);
1909 __ daddu(AT, AT, T9);
1910 __ lbu(as_Register(dst), AT, 0);
1911 }
1912 } else {
1913 if( Assembler::is_simm16(disp) ) {
1914 __ lbu(as_Register(dst), as_Register(base), disp);
1915 } else {
1916 __ move(T9, disp);
1917 __ daddu(AT, as_Register(base), T9);
1918 __ lbu(as_Register(dst), AT, 0);
1919 }
1920 }
1921 %}
1923 enc_class store_B_reg_enc (memory mem, mRegI src) %{
1924 MacroAssembler _masm(&cbuf);
1925 int src = $src$$reg;
1926 int base = $mem$$base;
1927 int index = $mem$$index;
1928 int scale = $mem$$scale;
1929 int disp = $mem$$disp;
1931 if( index != 0 ) {
1932 if (scale == 0) {
1933 if( Assembler::is_simm(disp, 8) ) {
1934 if (UseLoongsonISA) {
1935 __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
1936 } else {
1937 __ addu(AT, as_Register(base), as_Register(index));
1938 __ sb(as_Register(src), AT, disp);
1939 }
1940 } else if( Assembler::is_simm16(disp) ) {
1941 __ addu(AT, as_Register(base), as_Register(index));
1942 __ sb(as_Register(src), AT, disp);
1943 } else {
1944 __ addu(AT, as_Register(base), as_Register(index));
1945 __ move(T9, disp);
1946 if (UseLoongsonISA) {
1947 __ gssbx(as_Register(src), AT, T9, 0);
1948 } else {
1949 __ addu(AT, AT, T9);
1950 __ sb(as_Register(src), AT, 0);
1951 }
1952 }
1953 } else {
1954 __ dsll(AT, as_Register(index), scale);
1955 if( Assembler::is_simm(disp, 8) ) {
1956 if (UseLoongsonISA) {
1957 __ gssbx(as_Register(src), AT, as_Register(base), disp);
1958 } else {
1959 __ addu(AT, as_Register(base), AT);
1960 __ sb(as_Register(src), AT, disp);
1961 }
1962 } else if( Assembler::is_simm16(disp) ) {
1963 __ addu(AT, as_Register(base), AT);
1964 __ sb(as_Register(src), AT, disp);
1965 } else {
1966 __ addu(AT, as_Register(base), AT);
1967 __ move(T9, disp);
1968 if (UseLoongsonISA) {
1969 __ gssbx(as_Register(src), AT, T9, 0);
1970 } else {
1971 __ addu(AT, AT, T9);
1972 __ sb(as_Register(src), AT, 0);
1973 }
1974 }
1975 }
1976 } else {
1977 if( Assembler::is_simm16(disp) ) {
1978 __ sb(as_Register(src), as_Register(base), disp);
1979 } else {
1980 __ move(T9, disp);
1981 if (UseLoongsonISA) {
1982 __ gssbx(as_Register(src), as_Register(base), T9, 0);
1983 } else {
1984 __ addu(AT, as_Register(base), T9);
1985 __ sb(as_Register(src), AT, 0);
1986 }
1987 }
1988 }
1989 %}
1991 enc_class store_B_immI_enc (memory mem, immI8 src) %{
1992 MacroAssembler _masm(&cbuf);
1993 int base = $mem$$base;
1994 int index = $mem$$index;
1995 int scale = $mem$$scale;
1996 int disp = $mem$$disp;
1997 int value = $src$$constant;
1999 if( index != 0 ) {
2000 if (!UseLoongsonISA) {
2001 if (scale == 0) {
2002 __ daddu(AT, as_Register(base), as_Register(index));
2003 } else {
2004 __ dsll(AT, as_Register(index), scale);
2005 __ daddu(AT, as_Register(base), AT);
2006 }
2007 if( Assembler::is_simm16(disp) ) {
2008 if (value == 0) {
2009 __ sb(R0, AT, disp);
2010 } else {
2011 __ move(T9, value);
2012 __ sb(T9, AT, disp);
2013 }
2014 } else {
2015 if (value == 0) {
2016 __ move(T9, disp);
2017 __ daddu(AT, AT, T9);
2018 __ sb(R0, AT, 0);
2019 } else {
2020 __ move(T9, disp);
2021 __ daddu(AT, AT, T9);
2022 __ move(T9, value);
2023 __ sb(T9, AT, 0);
2024 }
2025 }
2026 } else {
2028 if (scale == 0) {
2029 if( Assembler::is_simm(disp, 8) ) {
2030 if (value == 0) {
2031 __ gssbx(R0, as_Register(base), as_Register(index), disp);
2032 } else {
2033 __ move(T9, value);
2034 __ gssbx(T9, as_Register(base), as_Register(index), disp);
2035 }
2036 } else if( Assembler::is_simm16(disp) ) {
2037 __ daddu(AT, as_Register(base), as_Register(index));
2038 if (value == 0) {
2039 __ sb(R0, AT, disp);
2040 } else {
2041 __ move(T9, value);
2042 __ sb(T9, AT, disp);
2043 }
2044 } else {
2045 if (value == 0) {
2046 __ daddu(AT, as_Register(base), as_Register(index));
2047 __ move(T9, disp);
2048 __ gssbx(R0, AT, T9, 0);
2049 } else {
2050 __ move(AT, disp);
2051 __ move(T9, value);
2052 __ daddu(AT, as_Register(base), AT);
2053 __ gssbx(T9, AT, as_Register(index), 0);
2054 }
2055 }
2057 } else {
2059 if( Assembler::is_simm(disp, 8) ) {
2060 __ dsll(AT, as_Register(index), scale);
2061 if (value == 0) {
2062 __ gssbx(R0, as_Register(base), AT, disp);
2063 } else {
2064 __ move(T9, value);
2065 __ gssbx(T9, as_Register(base), AT, disp);
2066 }
2067 } else if( Assembler::is_simm16(disp) ) {
2068 __ dsll(AT, as_Register(index), scale);
2069 __ daddu(AT, as_Register(base), AT);
2070 if (value == 0) {
2071 __ sb(R0, AT, disp);
2072 } else {
2073 __ move(T9, value);
2074 __ sb(T9, AT, disp);
2075 }
2076 } else {
2077 __ dsll(AT, as_Register(index), scale);
2078 if (value == 0) {
2079 __ daddu(AT, as_Register(base), AT);
2080 __ move(T9, disp);
2081 __ gssbx(R0, AT, T9, 0);
2082 } else {
2083 __ move(T9, disp);
2084 __ daddu(AT, AT, T9);
2085 __ move(T9, value);
2086 __ gssbx(T9, as_Register(base), AT, 0);
2087 }
2088 }
2089 }
2090 }
2091 } else {
2092 if( Assembler::is_simm16(disp) ) {
2093 if (value == 0) {
2094 __ sb(R0, as_Register(base), disp);
2095 } else {
2096 __ move(AT, value);
2097 __ sb(AT, as_Register(base), disp);
2098 }
2099 } else {
2100 if (value == 0) {
2101 __ move(T9, disp);
2102 if (UseLoongsonISA) {
2103 __ gssbx(R0, as_Register(base), T9, 0);
2104 } else {
2105 __ daddu(AT, as_Register(base), T9);
2106 __ sb(R0, AT, 0);
2107 }
2108 } else {
2109 __ move(T9, disp);
2110 if (UseLoongsonISA) {
2111 __ move(AT, value);
2112 __ gssbx(AT, as_Register(base), T9, 0);
2113 } else {
2114 __ daddu(AT, as_Register(base), T9);
2115 __ move(T9, value);
2116 __ sb(T9, AT, 0);
2117 }
2118 }
2119 }
2120 }
2121 %}
2124 enc_class store_B_immI_enc_sync (memory mem, immI8 src) %{
2125 MacroAssembler _masm(&cbuf);
2126 int base = $mem$$base;
2127 int index = $mem$$index;
2128 int scale = $mem$$scale;
2129 int disp = $mem$$disp;
2130 int value = $src$$constant;
2132 if( index != 0 ) {
2133 if (scale == 0) {
2134 __ daddu(AT, as_Register(base), as_Register(index));
2135 } else {
2136 __ dsll(AT, as_Register(index), scale);
2137 __ daddu(AT, as_Register(base), AT);
2138 }
2139 if( Assembler::is_simm16(disp) ) {
2140 if (value == 0) {
2141 __ sb(R0, AT, disp);
2142 } else {
2143 __ move(T9, value);
2144 __ sb(T9, AT, disp);
2145 }
2146 } else {
2147 if (value == 0) {
2148 __ move(T9, disp);
2149 __ daddu(AT, AT, T9);
2150 __ sb(R0, AT, 0);
2151 } else {
2152 __ move(T9, disp);
2153 __ daddu(AT, AT, T9);
2154 __ move(T9, value);
2155 __ sb(T9, AT, 0);
2156 }
2157 }
2158 } else {
2159 if( Assembler::is_simm16(disp) ) {
2160 if (value == 0) {
2161 __ sb(R0, as_Register(base), disp);
2162 } else {
2163 __ move(AT, value);
2164 __ sb(AT, as_Register(base), disp);
2165 }
2166 } else {
2167 if (value == 0) {
2168 __ move(T9, disp);
2169 __ daddu(AT, as_Register(base), T9);
2170 __ sb(R0, AT, 0);
2171 } else {
2172 __ move(T9, disp);
2173 __ daddu(AT, as_Register(base), T9);
2174 __ move(T9, value);
2175 __ sb(T9, AT, 0);
2176 }
2177 }
2178 }
2180 __ sync();
2181 %}
2183 // Load Short (16bit signed)
2184 enc_class load_S_enc (mRegI dst, memory mem) %{
2185 MacroAssembler _masm(&cbuf);
2186 int dst = $dst$$reg;
2187 int base = $mem$$base;
2188 int index = $mem$$index;
2189 int scale = $mem$$scale;
2190 int disp = $mem$$disp;
2192 if( index != 0 ) {
2193 if (scale == 0) {
2194 __ daddu(AT, as_Register(base), as_Register(index));
2195 } else {
2196 __ dsll(AT, as_Register(index), scale);
2197 __ daddu(AT, as_Register(base), AT);
2198 }
2199 if( Assembler::is_simm16(disp) ) {
2200 __ lh(as_Register(dst), AT, disp);
2201 } else {
2202 __ move(T9, disp);
2203 __ addu(AT, AT, T9);
2204 __ lh(as_Register(dst), AT, 0);
2205 }
2206 } else {
2207 if( Assembler::is_simm16(disp) ) {
2208 __ lh(as_Register(dst), as_Register(base), disp);
2209 } else {
2210 __ move(T9, disp);
2211 __ addu(AT, as_Register(base), T9);
2212 __ lh(as_Register(dst), AT, 0);
2213 }
2214 }
2215 %}
2217 // Load Char (16bit unsigned)
2218 enc_class load_C_enc (mRegI dst, memory mem) %{
2219 MacroAssembler _masm(&cbuf);
2220 int dst = $dst$$reg;
2221 int base = $mem$$base;
2222 int index = $mem$$index;
2223 int scale = $mem$$scale;
2224 int disp = $mem$$disp;
2226 if( index != 0 ) {
2227 if (scale == 0) {
2228 __ daddu(AT, as_Register(base), as_Register(index));
2229 } else {
2230 __ dsll(AT, as_Register(index), scale);
2231 __ daddu(AT, as_Register(base), AT);
2232 }
2233 if( Assembler::is_simm16(disp) ) {
2234 __ lhu(as_Register(dst), AT, disp);
2235 } else {
2236 __ move(T9, disp);
2237 __ addu(AT, AT, T9);
2238 __ lhu(as_Register(dst), AT, 0);
2239 }
2240 } else {
2241 if( Assembler::is_simm16(disp) ) {
2242 __ lhu(as_Register(dst), as_Register(base), disp);
2243 } else {
2244 __ move(T9, disp);
2245 __ daddu(AT, as_Register(base), T9);
2246 __ lhu(as_Register(dst), AT, 0);
2247 }
2248 }
2249 %}
2251 // Store Char (16bit unsigned)
2252 enc_class store_C_reg_enc (memory mem, mRegI src) %{
2253 MacroAssembler _masm(&cbuf);
2254 int src = $src$$reg;
2255 int base = $mem$$base;
2256 int index = $mem$$index;
2257 int scale = $mem$$scale;
2258 int disp = $mem$$disp;
2260 if( index != 0 ) {
2261 if( Assembler::is_simm16(disp) ) {
2262 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2263 if (scale == 0) {
2264 __ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
2265 } else {
2266 __ dsll(AT, as_Register(index), scale);
2267 __ gsshx(as_Register(src), as_Register(base), AT, disp);
2268 }
2269 } else {
2270 if (scale == 0) {
2271 __ addu(AT, as_Register(base), as_Register(index));
2272 } else {
2273 __ dsll(AT, as_Register(index), scale);
2274 __ addu(AT, as_Register(base), AT);
2275 }
2276 __ sh(as_Register(src), AT, disp);
2277 }
2278 } else {
2279 if (scale == 0) {
2280 __ addu(AT, as_Register(base), as_Register(index));
2281 } else {
2282 __ dsll(AT, as_Register(index), scale);
2283 __ addu(AT, as_Register(base), AT);
2284 }
2285 __ move(T9, disp);
2286 if( UseLoongsonISA ) {
2287 __ gsshx(as_Register(src), AT, T9, 0);
2288 } else {
2289 __ addu(AT, AT, T9);
2290 __ sh(as_Register(src), AT, 0);
2291 }
2292 }
2293 } else {
2294 if( Assembler::is_simm16(disp) ) {
2295 __ sh(as_Register(src), as_Register(base), disp);
2296 } else {
2297 __ move(T9, disp);
2298 if( UseLoongsonISA ) {
2299 __ gsshx(as_Register(src), as_Register(base), T9, 0);
2300 } else {
2301 __ addu(AT, as_Register(base), T9);
2302 __ sh(as_Register(src), AT, 0);
2303 }
2304 }
2305 }
2306 %}
2308 enc_class load_I_enc (mRegI dst, memory mem) %{
2309 MacroAssembler _masm(&cbuf);
2310 int dst = $dst$$reg;
2311 int base = $mem$$base;
2312 int index = $mem$$index;
2313 int scale = $mem$$scale;
2314 int disp = $mem$$disp;
2316 if( index != 0 ) {
2317 if( Assembler::is_simm16(disp) ) {
2318 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2319 if (scale == 0) {
2320 __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
2321 } else {
2322 __ dsll(AT, as_Register(index), scale);
2323 __ gslwx(as_Register(dst), as_Register(base), AT, disp);
2324 }
2325 } else {
2326 if (scale == 0) {
2327 __ addu(AT, as_Register(base), as_Register(index));
2328 } else {
2329 __ dsll(AT, as_Register(index), scale);
2330 __ addu(AT, as_Register(base), AT);
2331 }
2332 __ lw(as_Register(dst), AT, disp);
2333 }
2334 } else {
2335 if (scale == 0) {
2336 __ addu(AT, as_Register(base), as_Register(index));
2337 } else {
2338 __ dsll(AT, as_Register(index), scale);
2339 __ addu(AT, as_Register(base), AT);
2340 }
2341 __ move(T9, disp);
2342 if( UseLoongsonISA ) {
2343 __ gslwx(as_Register(dst), AT, T9, 0);
2344 } else {
2345 __ addu(AT, AT, T9);
2346 __ lw(as_Register(dst), AT, 0);
2347 }
2348 }
2349 } else {
2350 if( Assembler::is_simm16(disp) ) {
2351 __ lw(as_Register(dst), as_Register(base), disp);
2352 } else {
2353 __ move(T9, disp);
2354 if( UseLoongsonISA ) {
2355 __ gslwx(as_Register(dst), as_Register(base), T9, 0);
2356 } else {
2357 __ addu(AT, as_Register(base), T9);
2358 __ lw(as_Register(dst), AT, 0);
2359 }
2360 }
2361 }
2362 %}
2364 enc_class store_I_reg_enc (memory mem, mRegI src) %{
2365 MacroAssembler _masm(&cbuf);
2366 int src = $src$$reg;
2367 int base = $mem$$base;
2368 int index = $mem$$index;
2369 int scale = $mem$$scale;
2370 int disp = $mem$$disp;
2372 if( index != 0 ) {
2373 if( Assembler::is_simm16(disp) ) {
2374 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2375 if (scale == 0) {
2376 __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
2377 } else {
2378 __ dsll(AT, as_Register(index), scale);
2379 __ gsswx(as_Register(src), as_Register(base), AT, disp);
2380 }
2381 } else {
2382 if (scale == 0) {
2383 __ addu(AT, as_Register(base), as_Register(index));
2384 } else {
2385 __ dsll(AT, as_Register(index), scale);
2386 __ addu(AT, as_Register(base), AT);
2387 }
2388 __ sw(as_Register(src), AT, disp);
2389 }
2390 } else {
2391 if (scale == 0) {
2392 __ addu(AT, as_Register(base), as_Register(index));
2393 } else {
2394 __ dsll(AT, as_Register(index), scale);
2395 __ addu(AT, as_Register(base), AT);
2396 }
2397 __ move(T9, disp);
2398 if( UseLoongsonISA ) {
2399 __ gsswx(as_Register(src), AT, T9, 0);
2400 } else {
2401 __ addu(AT, AT, T9);
2402 __ sw(as_Register(src), AT, 0);
2403 }
2404 }
2405 } else {
2406 if( Assembler::is_simm16(disp) ) {
2407 __ sw(as_Register(src), as_Register(base), disp);
2408 } else {
2409 __ move(T9, disp);
2410 if( UseLoongsonISA ) {
2411 __ gsswx(as_Register(src), as_Register(base), T9, 0);
2412 } else {
2413 __ addu(AT, as_Register(base), T9);
2414 __ sw(as_Register(src), AT, 0);
2415 }
2416 }
2417 }
2418 %}
2420 enc_class store_I_immI_enc (memory mem, immI src) %{
2421 MacroAssembler _masm(&cbuf);
2422 int base = $mem$$base;
2423 int index = $mem$$index;
2424 int scale = $mem$$scale;
2425 int disp = $mem$$disp;
2426 int value = $src$$constant;
2428 if( index != 0 ) {
2429 if (scale == 0) {
2430 __ daddu(AT, as_Register(base), as_Register(index));
2431 } else {
2432 __ dsll(AT, as_Register(index), scale);
2433 __ daddu(AT, as_Register(base), AT);
2434 }
2435 if( Assembler::is_simm16(disp) ) {
2436 if (value == 0) {
2437 __ sw(R0, AT, disp);
2438 } else {
2439 __ move(T9, value);
2440 __ sw(T9, AT, disp);
2441 }
2442 } else {
2443 if (value == 0) {
2444 __ move(T9, disp);
2445 __ addu(AT, AT, T9);
2446 __ sw(R0, AT, 0);
2447 } else {
2448 __ move(T9, disp);
2449 __ addu(AT, AT, T9);
2450 __ move(T9, value);
2451 __ sw(T9, AT, 0);
2452 }
2453 }
2454 } else {
2455 if( Assembler::is_simm16(disp) ) {
2456 if (value == 0) {
2457 __ sw(R0, as_Register(base), disp);
2458 } else {
2459 __ move(AT, value);
2460 __ sw(AT, as_Register(base), disp);
2461 }
2462 } else {
2463 if (value == 0) {
2464 __ move(T9, disp);
2465 __ addu(AT, as_Register(base), T9);
2466 __ sw(R0, AT, 0);
2467 } else {
2468 __ move(T9, disp);
2469 __ addu(AT, as_Register(base), T9);
2470 __ move(T9, value);
2471 __ sw(T9, AT, 0);
2472 }
2473 }
2474 }
2475 %}
2477 enc_class load_N_enc (mRegN dst, memory mem) %{
2478 MacroAssembler _masm(&cbuf);
2479 int dst = $dst$$reg;
2480 int base = $mem$$base;
2481 int index = $mem$$index;
2482 int scale = $mem$$scale;
2483 int disp = $mem$$disp;
2484 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2485 assert(disp_reloc == relocInfo::none, "cannot have disp");
2487 if( index != 0 ) {
2488 if (scale == 0) {
2489 __ daddu(AT, as_Register(base), as_Register(index));
2490 } else {
2491 __ dsll(AT, as_Register(index), scale);
2492 __ daddu(AT, as_Register(base), AT);
2493 }
2494 if( Assembler::is_simm16(disp) ) {
2495 __ lwu(as_Register(dst), AT, disp);
2496 } else {
2497 __ li(T9, disp);
2498 __ daddu(AT, AT, T9);
2499 __ lwu(as_Register(dst), AT, 0);
2500 }
2501 } else {
2502 if( Assembler::is_simm16(disp) ) {
2503 __ lwu(as_Register(dst), as_Register(base), disp);
2504 } else {
2505 __ li(T9, disp);
2506 __ daddu(AT, as_Register(base), T9);
2507 __ lwu(as_Register(dst), AT, 0);
2508 }
2509 }
2511 %}
2514 enc_class load_P_enc (mRegP dst, memory mem) %{
2515 MacroAssembler _masm(&cbuf);
2516 int dst = $dst$$reg;
2517 int base = $mem$$base;
2518 int index = $mem$$index;
2519 int scale = $mem$$scale;
2520 int disp = $mem$$disp;
2521 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2522 assert(disp_reloc == relocInfo::none, "cannot have disp");
2524 if( index != 0 ) {
2525 if (scale == 0) {
2526 __ daddu(AT, as_Register(base), as_Register(index));
2527 } else {
2528 __ dsll(AT, as_Register(index), scale);
2529 __ daddu(AT, as_Register(base), AT);
2530 }
2531 if( Assembler::is_simm16(disp) ) {
2532 __ ld(as_Register(dst), AT, disp);
2533 } else {
2534 __ li(T9, disp);
2535 __ daddu(AT, AT, T9);
2536 __ ld(as_Register(dst), AT, 0);
2537 }
2538 } else {
2539 if( Assembler::is_simm16(disp) ) {
2540 __ ld(as_Register(dst), as_Register(base), disp);
2541 } else {
2542 __ li(T9, disp);
2543 __ daddu(AT, as_Register(base), T9);
2544 __ ld(as_Register(dst), AT, 0);
2545 }
2546 }
2547 // if( disp_reloc != relocInfo::none) __ ld(as_Register(dst), as_Register(dst), 0);
2548 %}
2550 enc_class store_P_reg_enc (memory mem, mRegP src) %{
2551 MacroAssembler _masm(&cbuf);
2552 int src = $src$$reg;
2553 int base = $mem$$base;
2554 int index = $mem$$index;
2555 int scale = $mem$$scale;
2556 int disp = $mem$$disp;
2558 if( index != 0 ) {
2559 if (scale == 0) {
2560 __ daddu(AT, as_Register(base), as_Register(index));
2561 } else {
2562 __ dsll(AT, as_Register(index), scale);
2563 __ daddu(AT, as_Register(base), AT);
2564 }
2565 if( Assembler::is_simm16(disp) ) {
2566 __ sd(as_Register(src), AT, disp);
2567 } else {
2568 __ move(T9, disp);
2569 __ daddu(AT, AT, T9);
2570 __ sd(as_Register(src), AT, 0);
2571 }
2572 } else {
2573 if( Assembler::is_simm16(disp) ) {
2574 __ sd(as_Register(src), as_Register(base), disp);
2575 } else {
2576 __ move(T9, disp);
2577 __ daddu(AT, as_Register(base), T9);
2578 __ sd(as_Register(src), AT, 0);
2579 }
2580 }
2581 %}
2583 enc_class store_N_reg_enc (memory mem, mRegN src) %{
2584 MacroAssembler _masm(&cbuf);
2585 int src = $src$$reg;
2586 int base = $mem$$base;
2587 int index = $mem$$index;
2588 int scale = $mem$$scale;
2589 int disp = $mem$$disp;
2591 if( index != 0 ) {
2592 if (scale == 0) {
2593 __ daddu(AT, as_Register(base), as_Register(index));
2594 } else {
2595 __ dsll(AT, as_Register(index), scale);
2596 __ daddu(AT, as_Register(base), AT);
2597 }
2598 if( Assembler::is_simm16(disp) ) {
2599 __ sw(as_Register(src), AT, disp);
2600 } else {
2601 __ move(T9, disp);
2602 __ addu(AT, AT, T9);
2603 __ sw(as_Register(src), AT, 0);
2604 }
2605 } else {
2606 if( Assembler::is_simm16(disp) ) {
2607 __ sw(as_Register(src), as_Register(base), disp);
2608 } else {
2609 __ move(T9, disp);
2610 __ addu(AT, as_Register(base), T9);
2611 __ sw(as_Register(src), AT, 0);
2612 }
2613 }
2614 %}
2616 enc_class store_P_immP_enc (memory mem, immP31 src) %{
2617 MacroAssembler _masm(&cbuf);
2618 int base = $mem$$base;
2619 int index = $mem$$index;
2620 int scale = $mem$$scale;
2621 int disp = $mem$$disp;
2622 long value = $src$$constant;
2624 if( index != 0 ) {
2625 if (scale == 0) {
2626 __ daddu(AT, as_Register(base), as_Register(index));
2627 } else {
2628 __ dsll(AT, as_Register(index), scale);
2629 __ daddu(AT, as_Register(base), AT);
2630 }
2631 if( Assembler::is_simm16(disp) ) {
2632 if (value == 0) {
2633 __ sd(R0, AT, disp);
2634 } else {
2635 __ move(T9, value);
2636 __ sd(T9, AT, disp);
2637 }
2638 } else {
2639 if (value == 0) {
2640 __ move(T9, disp);
2641 __ daddu(AT, AT, T9);
2642 __ sd(R0, AT, 0);
2643 } else {
2644 __ move(T9, disp);
2645 __ daddu(AT, AT, T9);
2646 __ move(T9, value);
2647 __ sd(T9, AT, 0);
2648 }
2649 }
2650 } else {
2651 if( Assembler::is_simm16(disp) ) {
2652 if (value == 0) {
2653 __ sd(R0, as_Register(base), disp);
2654 } else {
2655 __ move(AT, value);
2656 __ sd(AT, as_Register(base), disp);
2657 }
2658 } else {
2659 if (value == 0) {
2660 __ move(T9, disp);
2661 __ daddu(AT, as_Register(base), T9);
2662 __ sd(R0, AT, 0);
2663 } else {
2664 __ move(T9, disp);
2665 __ daddu(AT, as_Register(base), T9);
2666 __ move(T9, value);
2667 __ sd(T9, AT, 0);
2668 }
2669 }
2670 }
2671 %}
2673 /*
2674 * 1d4 storeImmN [S0 + #16 (8-bit)], narrowoop: spec/benchmarks/_213_javac/Identifier:exact *
2675 * # compressed ptr ! Field: spec/benchmarks/_213_javac/Identifier.value
2676 * 0x00000055648065d4: daddu at, s0, zero
2677 * 0x00000055648065d8: lui t9, 0x0 ; {oop(a 'spec/benchmarks/_213_javac/Identifier')}
2678 * 0x00000055648065dc: ori t9, t9, 0xfffff610
2679 * 0x00000055648065e0: dsll t9, t9, 16
2680 * 0x00000055648065e4: ori t9, t9, 0xffffc628
2681 * 0x00000055648065e8: sw t9, 0x10(at)
2682 */
2683 enc_class storeImmN_enc (memory mem, immN src) %{
2684 MacroAssembler _masm(&cbuf);
2685 int base = $mem$$base;
2686 int index = $mem$$index;
2687 int scale = $mem$$scale;
2688 int disp = $mem$$disp;
2689 long * value = (long *)$src$$constant;
2691 if (value == NULL) {
2692 guarantee(Assembler::is_simm16(disp), "FIXME: disp is not simm16!");
2693 if (index == 0) {
2694 __ sw(R0, as_Register(base), disp);
2695 } else {
2696 if (scale == 0) {
2697 __ daddu(AT, as_Register(base), as_Register(index));
2698 } else {
2699 __ dsll(AT, as_Register(index), scale);
2700 __ daddu(AT, as_Register(base), AT);
2701 }
2702 __ sw(R0, AT, disp);
2703 }
2705 return;
2706 }
2708 int oop_index = __ oop_recorder()->find_index((jobject)value);
2709 RelocationHolder rspec = oop_Relocation::spec(oop_index);
2711 guarantee(scale == 0, "FIXME: scale is not zero !");
2712 guarantee(value != 0, "FIXME: value is zero !");
2714 if (index != 0) {
2715 if (scale == 0) {
2716 __ daddu(AT, as_Register(base), as_Register(index));
2717 } else {
2718 __ dsll(AT, as_Register(index), scale);
2719 __ daddu(AT, as_Register(base), AT);
2720 }
2721 if( Assembler::is_simm16(disp) ) {
2722 if(rspec.type() != relocInfo::none) {
2723 __ relocate(rspec, Assembler::narrow_oop_operand);
2724 __ li48(T9, oop_index);
2725 } else {
2726 __ set64(T9, oop_index);
2727 }
2728 __ sw(T9, AT, disp);
2729 } else {
2730 __ move(T9, disp);
2731 __ addu(AT, AT, T9);
2733 if(rspec.type() != relocInfo::none) {
2734 __ relocate(rspec, Assembler::narrow_oop_operand);
2735 __ li48(T9, oop_index);
2736 } else {
2737 __ set64(T9, oop_index);
2738 }
2739 __ sw(T9, AT, 0);
2740 }
2741 }
2742 else {
2743 if( Assembler::is_simm16(disp) ) {
2744 if($src->constant_reloc() != relocInfo::none) {
2745 __ relocate(rspec, Assembler::narrow_oop_operand);
2746 __ li48(T9, oop_index);
2747 } else {
2748 __ set64(T9, oop_index);
2749 }
2750 __ sw(T9, as_Register(base), disp);
2751 } else {
2752 __ move(T9, disp);
2753 __ daddu(AT, as_Register(base), T9);
2755 if($src->constant_reloc() != relocInfo::none){
2756 __ relocate(rspec, Assembler::narrow_oop_operand);
2757 __ li48(T9, oop_index);
2758 } else {
2759 __ set64(T9, oop_index);
2760 }
2761 __ sw(T9, AT, 0);
2762 }
2763 }
2764 %}
2766 enc_class storeImmNKlass_enc (memory mem, immNKlass src) %{
2767 MacroAssembler _masm(&cbuf);
2769 assert (UseCompressedOops, "should only be used for compressed headers");
2770 assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
2772 int base = $mem$$base;
2773 int index = $mem$$index;
2774 int scale = $mem$$scale;
2775 int disp = $mem$$disp;
2776 long value = $src$$constant;
2778 int klass_index = __ oop_recorder()->find_index((Klass*)value);
2779 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
2780 long narrowp = Klass::encode_klass((Klass*)value);
2782 if(index!=0){
2783 if (scale == 0) {
2784 __ daddu(AT, as_Register(base), as_Register(index));
2785 } else {
2786 __ dsll(AT, as_Register(index), scale);
2787 __ daddu(AT, as_Register(base), AT);
2788 }
2790 if( Assembler::is_simm16(disp) ) {
2791 if(rspec.type() != relocInfo::none){
2792 __ relocate(rspec, Assembler::narrow_oop_operand);
2793 __ li48(T9, narrowp);
2794 } else {
2795 __ set64(T9, narrowp);
2796 }
2797 __ sw(T9, AT, disp);
2798 } else {
2799 __ move(T9, disp);
2800 __ daddu(AT, AT, T9);
2802 if(rspec.type() != relocInfo::none){
2803 __ relocate(rspec, Assembler::narrow_oop_operand);
2804 __ li48(T9, narrowp);
2805 } else {
2806 __ set64(T9, narrowp);
2807 }
2809 __ sw(T9, AT, 0);
2810 }
2811 } else {
2812 if( Assembler::is_simm16(disp) ) {
2813 if(rspec.type() != relocInfo::none){
2814 __ relocate(rspec, Assembler::narrow_oop_operand);
2815 __ li48(T9, narrowp);
2816 }
2817 else {
2818 __ set64(T9, narrowp);
2819 }
2820 __ sw(T9, as_Register(base), disp);
2821 } else {
2822 __ move(T9, disp);
2823 __ daddu(AT, as_Register(base), T9);
2825 if(rspec.type() != relocInfo::none){
2826 __ relocate(rspec, Assembler::narrow_oop_operand);
2827 __ li48(T9, narrowp);
2828 } else {
2829 __ set64(T9, narrowp);
2830 }
2831 __ sw(T9, AT, 0);
2832 }
2833 }
2834 %}
2836 enc_class storeImmN0_enc(memory mem, ImmN0 src) %{
2837 MacroAssembler _masm(&cbuf);
2838 int base = $mem$$base;
2839 int index = $mem$$index;
2840 int scale = $mem$$scale;
2841 int disp = $mem$$disp;
2843 if(index!=0){
2844 if (scale == 0) {
2845 __ daddu(AT, as_Register(base), as_Register(index));
2846 } else {
2847 __ dsll(AT, as_Register(index), scale);
2848 __ daddu(AT, as_Register(base), AT);
2849 }
2851 if( Assembler::is_simm16(disp) ) {
2852 __ sw(R0, AT, disp);
2853 } else {
2854 __ move(T9, disp);
2855 __ daddu(AT, AT, T9);
2856 __ sw(R0, AT, 0);
2857 }
2858 }
2859 else {
2860 if( Assembler::is_simm16(disp) ) {
2861 __ sw(R0, as_Register(base), disp);
2862 } else {
2863 __ move(T9, disp);
2864 __ daddu(AT, as_Register(base), T9);
2865 __ sw(R0, AT, 0);
2866 }
2867 }
2868 %}
2870 enc_class load_L_enc (mRegL dst, memory mem) %{
2871 MacroAssembler _masm(&cbuf);
2872 int base = $mem$$base;
2873 int index = $mem$$index;
2874 int scale = $mem$$scale;
2875 int disp = $mem$$disp;
2876 Register dst_reg = as_Register($dst$$reg);
2878 /*********************2013/03/27**************************
2879 * Jin: $base may contain a null object.
2880 * Server JIT force the exception_offset to be the pos of
2881 * the first instruction.
2882 * I insert such a 'null_check' at the beginning.
2883 *******************************************************/
2885 __ lw(AT, as_Register(base), 0);
2887 /*********************2012/10/04**************************
2888 * Error case found in SortTest
2889 * 337 b java.util.Arrays::sort1 (401 bytes)
2890 * B73:
2891 * d34 lw T4.lo, [T4 + #16] #@loadL-lo
2892 * lw T4.hi, [T4 + #16]+4 #@loadL-hi
2893 *
2894 * The original instructions generated here are :
2895 * __ lw(dst_lo, as_Register(base), disp);
2896 * __ lw(dst_hi, as_Register(base), disp + 4);
2897 *******************************************************/
2899 if( index != 0 ) {
2900 if (scale == 0) {
2901 __ daddu(AT, as_Register(base), as_Register(index));
2902 } else {
2903 __ dsll(AT, as_Register(index), scale);
2904 __ daddu(AT, as_Register(base), AT);
2905 }
2906 if( Assembler::is_simm16(disp) ) {
2907 __ ld(dst_reg, AT, disp);
2908 } else {
2909 __ move(T9, disp);
2910 __ daddu(AT, AT, T9);
2911 __ ld(dst_reg, AT, 0);
2912 }
2913 } else {
2914 if( Assembler::is_simm16(disp) ) {
2915 __ move(AT, as_Register(base));
2916 __ ld(dst_reg, AT, disp);
2917 } else {
2918 __ move(T9, disp);
2919 __ daddu(AT, as_Register(base), T9);
2920 __ ld(dst_reg, AT, 0);
2921 }
2922 }
2923 %}
2925 enc_class store_L_reg_enc (memory mem, mRegL src) %{
2926 MacroAssembler _masm(&cbuf);
2927 int base = $mem$$base;
2928 int index = $mem$$index;
2929 int scale = $mem$$scale;
2930 int disp = $mem$$disp;
2931 Register src_reg = as_Register($src$$reg);
2933 if( index != 0 ) {
2934 if (scale == 0) {
2935 __ daddu(AT, as_Register(base), as_Register(index));
2936 } else {
2937 __ dsll(AT, as_Register(index), scale);
2938 __ daddu(AT, as_Register(base), AT);
2939 }
2940 if( Assembler::is_simm16(disp) ) {
2941 __ sd(src_reg, AT, disp);
2942 } else {
2943 __ move(T9, disp);
2944 __ daddu(AT, AT, T9);
2945 __ sd(src_reg, AT, 0);
2946 }
2947 } else {
2948 if( Assembler::is_simm16(disp) ) {
2949 __ move(AT, as_Register(base));
2950 __ sd(src_reg, AT, disp);
2951 } else {
2952 __ move(T9, disp);
2953 __ daddu(AT, as_Register(base), T9);
2954 __ sd(src_reg, AT, 0);
2955 }
2956 }
2957 %}
2959 enc_class store_L_immL0_enc (memory mem, immL0 src) %{
2960 MacroAssembler _masm(&cbuf);
2961 int base = $mem$$base;
2962 int index = $mem$$index;
2963 int scale = $mem$$scale;
2964 int disp = $mem$$disp;
2966 if( index != 0 ) {
2967 if (scale == 0) {
2968 __ daddu(AT, as_Register(base), as_Register(index));
2969 } else {
2970 __ dsll(AT, as_Register(index), scale);
2971 __ daddu(AT, as_Register(base), AT);
2972 }
2973 if( Assembler::is_simm16(disp) ) {
2974 __ sd(R0, AT, disp);
2975 } else {
2976 __ move(T9, disp);
2977 __ addu(AT, AT, T9);
2978 __ sd(R0, AT, 0);
2979 }
2980 } else {
2981 if( Assembler::is_simm16(disp) ) {
2982 __ move(AT, as_Register(base));
2983 __ sd(R0, AT, disp);
2984 } else {
2985 __ move(T9, disp);
2986 __ addu(AT, as_Register(base), T9);
2987 __ sd(R0, AT, 0);
2988 }
2989 }
2990 %}
2992 enc_class store_L_immL_enc (memory mem, immL src) %{
2993 MacroAssembler _masm(&cbuf);
2994 int base = $mem$$base;
2995 int index = $mem$$index;
2996 int scale = $mem$$scale;
2997 int disp = $mem$$disp;
2998 long imm = $src$$constant;
3000 if( index != 0 ) {
3001 if (scale == 0) {
3002 __ daddu(AT, as_Register(base), as_Register(index));
3003 } else {
3004 __ dsll(AT, as_Register(index), scale);
3005 __ daddu(AT, as_Register(base), AT);
3006 }
3007 if( Assembler::is_simm16(disp) ) {
3008 __ li(T9, imm);
3009 __ sd(T9, AT, disp);
3010 } else {
3011 __ move(T9, disp);
3012 __ addu(AT, AT, T9);
3013 __ li(T9, imm);
3014 __ sd(T9, AT, 0);
3015 }
3016 } else {
3017 if( Assembler::is_simm16(disp) ) {
3018 __ move(AT, as_Register(base));
3019 __ li(T9, imm);
3020 __ sd(T9, AT, disp);
3021 } else {
3022 __ move(T9, disp);
3023 __ addu(AT, as_Register(base), T9);
3024 __ li(T9, imm);
3025 __ sd(T9, AT, 0);
3026 }
3027 }
3028 %}
3030 enc_class load_F_enc (regF dst, memory mem) %{
3031 MacroAssembler _masm(&cbuf);
3032 int base = $mem$$base;
3033 int index = $mem$$index;
3034 int scale = $mem$$scale;
3035 int disp = $mem$$disp;
3036 FloatRegister dst = $dst$$FloatRegister;
3038 if( index != 0 ) {
3039 if( Assembler::is_simm16(disp) ) {
3040 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3041 if (scale == 0) {
3042 __ gslwxc1(dst, as_Register(base), as_Register(index), disp);
3043 } else {
3044 __ dsll(AT, as_Register(index), scale);
3045 __ gslwxc1(dst, as_Register(base), AT, disp);
3046 }
3047 } else {
3048 if (scale == 0) {
3049 __ daddu(AT, as_Register(base), as_Register(index));
3050 } else {
3051 __ dsll(AT, as_Register(index), scale);
3052 __ daddu(AT, as_Register(base), AT);
3053 }
3054 __ lwc1(dst, AT, disp);
3055 }
3056 } else {
3057 if (scale == 0) {
3058 __ daddu(AT, as_Register(base), as_Register(index));
3059 } else {
3060 __ dsll(AT, as_Register(index), scale);
3061 __ daddu(AT, as_Register(base), AT);
3062 }
3063 __ move(T9, disp);
3064 if( UseLoongsonISA ) {
3065 __ gslwxc1(dst, AT, T9, 0);
3066 } else {
3067 __ daddu(AT, AT, T9);
3068 __ lwc1(dst, AT, 0);
3069 }
3070 }
3071 } else {
3072 if( Assembler::is_simm16(disp) ) {
3073 __ lwc1(dst, as_Register(base), disp);
3074 } else {
3075 __ move(T9, disp);
3076 if( UseLoongsonISA ) {
3077 __ gslwxc1(dst, as_Register(base), T9, 0);
3078 } else {
3079 __ daddu(AT, as_Register(base), T9);
3080 __ lwc1(dst, AT, 0);
3081 }
3082 }
3083 }
3084 %}
3086 enc_class store_F_reg_enc (memory mem, regF src) %{
3087 MacroAssembler _masm(&cbuf);
3088 int base = $mem$$base;
3089 int index = $mem$$index;
3090 int scale = $mem$$scale;
3091 int disp = $mem$$disp;
3092 FloatRegister src = $src$$FloatRegister;
3094 if( index != 0 ) {
3095 if( Assembler::is_simm16(disp) ) {
3096 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3097 if (scale == 0) {
3098 __ gsswxc1(src, as_Register(base), as_Register(index), disp);
3099 } else {
3100 __ dsll(AT, as_Register(index), scale);
3101 __ gsswxc1(src, as_Register(base), AT, disp);
3102 }
3103 } else {
3104 if (scale == 0) {
3105 __ daddu(AT, as_Register(base), as_Register(index));
3106 } else {
3107 __ dsll(AT, as_Register(index), scale);
3108 __ daddu(AT, as_Register(base), AT);
3109 }
3110 __ swc1(src, AT, disp);
3111 }
3112 } else {
3113 if (scale == 0) {
3114 __ daddu(AT, as_Register(base), as_Register(index));
3115 } else {
3116 __ dsll(AT, as_Register(index), scale);
3117 __ daddu(AT, as_Register(base), AT);
3118 }
3119 __ move(T9, disp);
3120 if( UseLoongsonISA ) {
3121 __ gsswxc1(src, AT, T9, 0);
3122 } else {
3123 __ daddu(AT, AT, T9);
3124 __ swc1(src, AT, 0);
3125 }
3126 }
3127 } else {
3128 if( Assembler::is_simm16(disp) ) {
3129 __ swc1(src, as_Register(base), disp);
3130 } else {
3131 __ move(T9, disp);
3132 if( UseLoongsonISA ) {
3133 __ gslwxc1(src, as_Register(base), T9, 0);
3134 } else {
3135 __ daddu(AT, as_Register(base), T9);
3136 __ swc1(src, AT, 0);
3137 }
3138 }
3139 }
3140 %}
3142 enc_class load_D_enc (regD dst, memory mem) %{
3143 MacroAssembler _masm(&cbuf);
3144 int base = $mem$$base;
3145 int index = $mem$$index;
3146 int scale = $mem$$scale;
3147 int disp = $mem$$disp;
3148 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3150 if( index != 0 ) {
3151 if( Assembler::is_simm16(disp) ) {
3152 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3153 if (scale == 0) {
3154 __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
3155 } else {
3156 __ dsll(AT, as_Register(index), scale);
3157 __ gsldxc1(dst_reg, as_Register(base), AT, disp);
3158 }
3159 } else {
3160 if (scale == 0) {
3161 __ daddu(AT, as_Register(base), as_Register(index));
3162 } else {
3163 __ dsll(AT, as_Register(index), scale);
3164 __ daddu(AT, as_Register(base), AT);
3165 }
3166 __ ldc1(dst_reg, AT, disp);
3167 }
3168 } else {
3169 if (scale == 0) {
3170 __ daddu(AT, as_Register(base), as_Register(index));
3171 } else {
3172 __ dsll(AT, as_Register(index), scale);
3173 __ daddu(AT, as_Register(base), AT);
3174 }
3175 __ move(T9, disp);
3176 if( UseLoongsonISA ) {
3177 __ gsldxc1(dst_reg, AT, T9, 0);
3178 } else {
3179 __ addu(AT, AT, T9);
3180 __ ldc1(dst_reg, AT, 0);
3181 }
3182 }
3183 } else {
3184 if( Assembler::is_simm16(disp) ) {
3185 __ ldc1(dst_reg, as_Register(base), disp);
3186 } else {
3187 __ move(T9, disp);
3188 if( UseLoongsonISA ) {
3189 __ gsldxc1(dst_reg, as_Register(base), T9, 0);
3190 } else {
3191 __ addu(AT, as_Register(base), T9);
3192 __ ldc1(dst_reg, AT, 0);
3193 }
3194 }
3195 }
3196 %}
3198 enc_class store_D_reg_enc (memory mem, regD src) %{
3199 MacroAssembler _masm(&cbuf);
3200 int base = $mem$$base;
3201 int index = $mem$$index;
3202 int scale = $mem$$scale;
3203 int disp = $mem$$disp;
3204 FloatRegister src_reg = as_FloatRegister($src$$reg);
3206 if( index != 0 ) {
3207 if( Assembler::is_simm16(disp) ) {
3208 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3209 if (scale == 0) {
3210 __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
3211 } else {
3212 __ dsll(AT, as_Register(index), scale);
3213 __ gssdxc1(src_reg, as_Register(base), AT, disp);
3214 }
3215 } else {
3216 if (scale == 0) {
3217 __ daddu(AT, as_Register(base), as_Register(index));
3218 } else {
3219 __ dsll(AT, as_Register(index), scale);
3220 __ daddu(AT, as_Register(base), AT);
3221 }
3222 __ sdc1(src_reg, AT, disp);
3223 }
3224 } else {
3225 if (scale == 0) {
3226 __ daddu(AT, as_Register(base), as_Register(index));
3227 } else {
3228 __ dsll(AT, as_Register(index), scale);
3229 __ daddu(AT, as_Register(base), AT);
3230 }
3231 __ move(T9, disp);
3232 if( UseLoongsonISA ) {
3233 __ gssdxc1(src_reg, AT, T9, 0);
3234 } else {
3235 __ addu(AT, AT, T9);
3236 __ sdc1(src_reg, AT, 0);
3237 }
3238 }
3239 } else {
3240 if( Assembler::is_simm16(disp) ) {
3241 __ sdc1(src_reg, as_Register(base), disp);
3242 } else {
3243 __ move(T9, disp);
3244 if( UseLoongsonISA ) {
3245 __ gssdxc1(src_reg, as_Register(base), T9, 0);
3246 } else {
3247 __ addu(AT, as_Register(base), T9);
3248 __ sdc1(src_reg, AT, 0);
3249 }
3250 }
3251 }
3252 %}
3254 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
3255 MacroAssembler _masm(&cbuf);
3256 // This is the instruction starting address for relocation info.
3257 __ block_comment("Java_To_Runtime");
3258 cbuf.set_insts_mark();
3259 __ relocate(relocInfo::runtime_call_type);
3261 __ li48(T9, (long)$meth$$method);
3262 __ jalr(T9);
3263 __ nop();
3264 %}
3266 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
3267 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
3268 // who we intended to call.
3269 MacroAssembler _masm(&cbuf);
3270 cbuf.set_insts_mark();
3272 if ( !_method ) {
3273 __ relocate(relocInfo::runtime_call_type);
3274 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
3275 // runtime_call_Relocation::spec(), RELOC_IMM32 );
3276 } else if(_optimized_virtual) {
3277 __ relocate(relocInfo::opt_virtual_call_type);
3278 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
3279 // opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
3280 } else {
3281 __ relocate(relocInfo::static_call_type);
3282 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
3283 // static_call_Relocation::spec(), RELOC_IMM32 );
3284 }
3286 __ li(T9, $meth$$method);
3287 __ jalr(T9);
3288 __ nop();
3289 if( _method ) { // Emit stub for static call
3290 emit_java_to_interp(cbuf);
3291 }
3292 %}
3295 /*
3296 * [Ref: LIR_Assembler::ic_call() ]
3297 */
3298 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
3299 MacroAssembler _masm(&cbuf);
3300 __ block_comment("Java_Dynamic_Call");
3301 __ ic_call((address)$meth$$method);
3302 %}
3305 enc_class Set_Flags_After_Fast_Lock_Unlock(FlagsReg cr) %{
3306 Register flags = $cr$$Register;
3307 Label L;
3309 MacroAssembler _masm(&cbuf);
3311 __ addu(flags, R0, R0);
3312 __ beq(AT, R0, L);
3313 __ delayed()->nop();
3314 __ move(flags, 0xFFFFFFFF);
3315 __ bind(L);
3316 %}
3318 enc_class enc_PartialSubtypeCheck(mRegP result, mRegP sub, mRegP super, mRegI tmp) %{
3319 Register result = $result$$Register;
3320 Register sub = $sub$$Register;
3321 Register super = $super$$Register;
3322 Register length = $tmp$$Register;
3323 Register tmp = T9;
3324 Label miss;
3326 /* 2012/9/28 Jin: result may be the same as sub
3327 * 47c B40: # B21 B41 <- B20 Freq: 0.155379
3328 * 47c partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
3329 * 4bc mov S2, NULL #@loadConP
3330 * 4c0 beq S1, S2, B21 #@branchConP P=0.999999 C=-1.000000
3331 */
3332 MacroAssembler _masm(&cbuf);
3333 Label done;
3334 __ check_klass_subtype_slow_path(sub, super, length, tmp,
3335 NULL, &miss,
3336 /*set_cond_codes:*/ true);
3337 /* 2013/7/22 Jin: Refer to X86_64's RDI */
3338 __ move(result, 0);
3339 __ b(done);
3340 __ nop();
3342 __ bind(miss);
3343 __ move(result, 1);
3344 __ bind(done);
3345 %}
3347 %}
3350 //---------MIPS FRAME--------------------------------------------------------------
3351 // Definition of frame structure and management information.
3352 //
3353 // S T A C K L A Y O U T Allocators stack-slot number
3354 // | (to get allocators register number
3355 // G Owned by | | v add SharedInfo::stack0)
3356 // r CALLER | |
3357 // o | +--------+ pad to even-align allocators stack-slot
3358 // w V | pad0 | numbers; owned by CALLER
3359 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3360 // h ^ | in | 5
3361 // | | args | 4 Holes in incoming args owned by SELF
3362 // | | old | | 3
3363 // | | SP-+--------+----> Matcher::_old_SP, even aligned
3364 // v | | ret | 3 return address
3365 // Owned by +--------+
3366 // Self | pad2 | 2 pad to align old SP
3367 // | +--------+ 1
3368 // | | locks | 0
3369 // | +--------+----> SharedInfo::stack0, even aligned
3370 // | | pad1 | 11 pad to align new SP
3371 // | +--------+
3372 // | | | 10
3373 // | | spills | 9 spills
3374 // V | | 8 (pad0 slot for callee)
3375 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3376 // ^ | out | 7
3377 // | | args | 6 Holes in outgoing args owned by CALLEE
3378 // Owned by new | |
3379 // Callee SP-+--------+----> Matcher::_new_SP, even aligned
3380 // | |
3381 //
3382 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3383 // known from SELF's arguments and the Java calling convention.
3384 // Region 6-7 is determined per call site.
3385 // Note 2: If the calling convention leaves holes in the incoming argument
3386 // area, those holes are owned by SELF. Holes in the outgoing area
3387 // are owned by the CALLEE. Holes should not be nessecary in the
3388 // incoming area, as the Java calling convention is completely under
3389 // the control of the AD file. Doubles can be sorted and packed to
3390 // avoid holes. Holes in the outgoing arguments may be nessecary for
3391 // varargs C calling conventions.
3392 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3393 // even aligned with pad0 as needed.
3394 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3395 // region 6-11 is even aligned; it may be padded out more so that
3396 // the region from SP to FP meets the minimum stack alignment.
3397 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
3398 // alignment. Region 11, pad1, may be dynamically extended so that
3399 // SP meets the minimum alignment.
3402 frame %{
3404 stack_direction(TOWARDS_LOW);
3406 // These two registers define part of the calling convention
3407 // between compiled code and the interpreter.
3408 // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention
3409 // for more information. by yjl 3/16/2006
3411 inline_cache_reg(T1); // Inline Cache Register
3412 interpreter_method_oop_reg(S3); // Method Oop Register when calling interpreter
3413 /*
3414 inline_cache_reg(T1); // Inline Cache Register or methodOop for I2C
3415 interpreter_arg_ptr_reg(A0); // Argument pointer for I2C adapters
3416 */
3418 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3419 cisc_spilling_operand_name(indOffset32);
3421 // Number of stack slots consumed by locking an object
3422 // generate Compile::sync_stack_slots
3423 #ifdef _LP64
3424 sync_stack_slots(2);
3425 #else
3426 sync_stack_slots(1);
3427 #endif
3429 frame_pointer(SP);
3431 // Interpreter stores its frame pointer in a register which is
3432 // stored to the stack by I2CAdaptors.
3433 // I2CAdaptors convert from interpreted java to compiled java.
3435 interpreter_frame_pointer(FP);
3437 // generate Matcher::stack_alignment
3438 stack_alignment(StackAlignmentInBytes); //wordSize = sizeof(char*);
3440 // Number of stack slots between incoming argument block and the start of
3441 // a new frame. The PROLOG must add this many slots to the stack. The
3442 // EPILOG must remove this many slots. Intel needs one slot for
3443 // return address.
3444 // generate Matcher::in_preserve_stack_slots
3445 //in_preserve_stack_slots(VerifyStackAtCalls + 2); //Now VerifyStackAtCalls is defined as false ! Leave one stack slot for ra and fp
3446 in_preserve_stack_slots(4); //Now VerifyStackAtCalls is defined as false ! Leave two stack slots for ra and fp
3448 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3449 // for calls to C. Supports the var-args backing area for register parms.
3450 varargs_C_out_slots_killed(0);
3452 // The after-PROLOG location of the return address. Location of
3453 // return address specifies a type (REG or STACK) and a number
3454 // representing the register number (i.e. - use a register name) or
3455 // stack slot.
3456 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3457 // Otherwise, it is above the locks and verification slot and alignment word
3458 //return_addr(STACK -1+ round_to(1+VerifyStackAtCalls+Compile::current()->sync()*Compile::current()->sync_stack_slots(),WordsPerLong));
3459 return_addr(REG RA);
3461 // Body of function which returns an integer array locating
3462 // arguments either in registers or in stack slots. Passed an array
3463 // of ideal registers called "sig" and a "length" count. Stack-slot
3464 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3465 // arguments for a CALLEE. Incoming stack arguments are
3466 // automatically biased by the preserve_stack_slots field above.
3469 // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing)
3470 // StartNode::calling_convention call this. by yjl 3/16/2006
3471 calling_convention %{
3472 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3473 %}
3478 // Body of function which returns an integer array locating
3479 // arguments either in registers or in stack slots. Passed an array
3480 // of ideal registers called "sig" and a "length" count. Stack-slot
3481 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3482 // arguments for a CALLEE. Incoming stack arguments are
3483 // automatically biased by the preserve_stack_slots field above.
3486 // SEE CallRuntimeNode::calling_convention for more information. by yjl 3/16/2006
3487 c_calling_convention %{
3488 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3489 %}
3492 // Location of C & interpreter return values
3493 // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR.
3494 // SEE Matcher::match. by yjl 3/16/2006
3495 c_return_value %{
3496 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3497 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3498 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3499 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num };
3500 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3501 %}
3503 // Location of return values
3504 // register(s) contain(s) return value for Op_StartC2I and Op_Start.
3505 // SEE Matcher::match. by yjl 3/16/2006
3507 return_value %{
3508 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3509 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3510 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3511 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num};
3512 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3513 %}
3515 %}
3517 //----------ATTRIBUTES---------------------------------------------------------
3518 //----------Operand Attributes-------------------------------------------------
3519 op_attrib op_cost(0); // Required cost attribute
3521 //----------Instruction Attributes---------------------------------------------
3522 ins_attrib ins_cost(100); // Required cost attribute
3523 ins_attrib ins_size(32); // Required size attribute (in bits)
3524 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3525 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3526 // non-matching short branch variant of some
3527 // long branch?
3528 ins_attrib ins_alignment(4); // Required alignment attribute (must be a power of 2)
3529 // specifies the alignment that some part of the instruction (not
3530 // necessarily the start) requires. If > 1, a compute_padding()
3531 // function must be provided for the instruction
3533 //----------OPERANDS-----------------------------------------------------------
3534 // Operand definitions must precede instruction definitions for correct parsing
3535 // in the ADLC because operands constitute user defined types which are used in
3536 // instruction definitions.
3538 // Vectors
3539 operand vecD() %{
3540 constraint(ALLOC_IN_RC(dbl_reg));
3541 match(VecD);
3543 format %{ %}
3544 interface(REG_INTER);
3545 %}
3547 // Flags register, used as output of compare instructions
3548 operand FlagsReg() %{
3549 constraint(ALLOC_IN_RC(mips_flags));
3550 match(RegFlags);
3552 format %{ "EFLAGS" %}
3553 interface(REG_INTER);
3554 %}
3556 //----------Simple Operands----------------------------------------------------
3557 //TODO: Should we need to define some more special immediate number ?
3558 // Immediate Operands
3559 // Integer Immediate
3560 operand immI() %{
3561 match(ConI);
3562 //TODO: should not match immI8 here LEE
3563 match(immI8);
3565 op_cost(20);
3566 format %{ %}
3567 interface(CONST_INTER);
3568 %}
3570 // Long Immediate 8-bit
3571 operand immL8()
3572 %{
3573 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3574 match(ConL);
3576 op_cost(5);
3577 format %{ %}
3578 interface(CONST_INTER);
3579 %}
3581 // Constant for test vs zero
3582 operand immI0() %{
3583 predicate(n->get_int() == 0);
3584 match(ConI);
3586 op_cost(0);
3587 format %{ %}
3588 interface(CONST_INTER);
3589 %}
3591 // Constant for increment
3592 operand immI1() %{
3593 predicate(n->get_int() == 1);
3594 match(ConI);
3596 op_cost(0);
3597 format %{ %}
3598 interface(CONST_INTER);
3599 %}
3601 // Constant for decrement
3602 operand immI_M1() %{
3603 predicate(n->get_int() == -1);
3604 match(ConI);
3606 op_cost(0);
3607 format %{ %}
3608 interface(CONST_INTER);
3609 %}
3611 // Valid scale values for addressing modes
3612 operand immI2() %{
3613 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3614 match(ConI);
3616 format %{ %}
3617 interface(CONST_INTER);
3618 %}
3620 operand immI8() %{
3621 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3622 match(ConI);
3624 op_cost(5);
3625 format %{ %}
3626 interface(CONST_INTER);
3627 %}
3629 operand immI16() %{
3630 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3631 match(ConI);
3633 op_cost(10);
3634 format %{ %}
3635 interface(CONST_INTER);
3636 %}
3638 // Constant for long shifts
3639 operand immI_32() %{
3640 predicate( n->get_int() == 32 );
3641 match(ConI);
3643 op_cost(0);
3644 format %{ %}
3645 interface(CONST_INTER);
3646 %}
3648 operand immI_63() %{
3649 predicate( n->get_int() == 63 );
3650 match(ConI);
3652 op_cost(0);
3653 format %{ %}
3654 interface(CONST_INTER);
3655 %}
3657 operand immI_0_31() %{
3658 predicate( n->get_int() >= 0 && n->get_int() <= 31 );
3659 match(ConI);
3661 op_cost(0);
3662 format %{ %}
3663 interface(CONST_INTER);
3664 %}
3666 // Operand for non-negtive integer mask
3667 operand immI_nonneg_mask() %{
3668 predicate( (n->get_int() >= 0) && (Assembler::is_int_mask(n->get_int()) != -1) );
3669 match(ConI);
3671 op_cost(0);
3672 format %{ %}
3673 interface(CONST_INTER);
3674 %}
3676 operand immI_32_63() %{
3677 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3678 match(ConI);
3679 op_cost(0);
3681 format %{ %}
3682 interface(CONST_INTER);
3683 %}
3685 operand immI16_sub() %{
3686 predicate((-32767 <= n->get_int()) && (n->get_int() <= 32768));
3687 match(ConI);
3689 op_cost(10);
3690 format %{ %}
3691 interface(CONST_INTER);
3692 %}
3694 operand immI_0_32767() %{
3695 predicate( n->get_int() >= 0 && n->get_int() <= 32767 );
3696 match(ConI);
3697 op_cost(0);
3699 format %{ %}
3700 interface(CONST_INTER);
3701 %}
3703 operand immI_0_65535() %{
3704 predicate( n->get_int() >= 0 && n->get_int() <= 65535 );
3705 match(ConI);
3706 op_cost(0);
3708 format %{ %}
3709 interface(CONST_INTER);
3710 %}
3712 operand immI_1() %{
3713 predicate( n->get_int() == 1 );
3714 match(ConI);
3716 op_cost(0);
3717 format %{ %}
3718 interface(CONST_INTER);
3719 %}
3721 operand immI_2() %{
3722 predicate( n->get_int() == 2 );
3723 match(ConI);
3725 op_cost(0);
3726 format %{ %}
3727 interface(CONST_INTER);
3728 %}
3730 operand immI_3() %{
3731 predicate( n->get_int() == 3 );
3732 match(ConI);
3734 op_cost(0);
3735 format %{ %}
3736 interface(CONST_INTER);
3737 %}
3739 operand immI_7() %{
3740 predicate( n->get_int() == 7 );
3741 match(ConI);
3743 format %{ %}
3744 interface(CONST_INTER);
3745 %}
3747 // Immediates for special shifts (sign extend)
3749 // Constants for increment
3750 operand immI_16() %{
3751 predicate( n->get_int() == 16 );
3752 match(ConI);
3754 format %{ %}
3755 interface(CONST_INTER);
3756 %}
3758 operand immI_24() %{
3759 predicate( n->get_int() == 24 );
3760 match(ConI);
3762 format %{ %}
3763 interface(CONST_INTER);
3764 %}
3766 // Constant for byte-wide masking
3767 operand immI_255() %{
3768 predicate( n->get_int() == 255 );
3769 match(ConI);
3771 op_cost(0);
3772 format %{ %}
3773 interface(CONST_INTER);
3774 %}
3776 operand immI_65535() %{
3777 predicate( n->get_int() == 65535 );
3778 match(ConI);
3780 op_cost(5);
3781 format %{ %}
3782 interface(CONST_INTER);
3783 %}
3785 operand immI_65536() %{
3786 predicate( n->get_int() == 65536 );
3787 match(ConI);
3789 op_cost(5);
3790 format %{ %}
3791 interface(CONST_INTER);
3792 %}
3794 // Pointer Immediate
3795 operand immP() %{
3796 match(ConP);
3798 op_cost(10);
3799 format %{ %}
3800 interface(CONST_INTER);
3801 %}
3803 operand immP31()
3804 %{
3805 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3806 && (n->get_ptr() >> 31) == 0);
3807 match(ConP);
3809 op_cost(5);
3810 format %{ %}
3811 interface(CONST_INTER);
3812 %}
3814 // NULL Pointer Immediate
3815 operand immP0() %{
3816 predicate( n->get_ptr() == 0 );
3817 match(ConP);
3818 op_cost(0);
3820 format %{ %}
3821 interface(CONST_INTER);
3822 %}
3824 // Pointer Immediate: 64-bit
3825 operand immP_set() %{
3826 match(ConP);
3828 op_cost(5);
3829 // formats are generated automatically for constants and base registers
3830 format %{ %}
3831 interface(CONST_INTER);
3832 %}
3834 // Pointer Immediate: 64-bit
3835 operand immP_load() %{
3836 predicate(n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set64(n->get_ptr()) > 3));
3837 match(ConP);
3839 op_cost(5);
3840 // formats are generated automatically for constants and base registers
3841 format %{ %}
3842 interface(CONST_INTER);
3843 %}
3845 // Pointer Immediate: 64-bit
3846 operand immP_no_oop_cheap() %{
3847 predicate(!n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set64(n->get_ptr()) <= 3));
3848 match(ConP);
3850 op_cost(5);
3851 // formats are generated automatically for constants and base registers
3852 format %{ %}
3853 interface(CONST_INTER);
3854 %}
3856 // Pointer for polling page
3857 operand immP_poll() %{
3858 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3859 match(ConP);
3860 op_cost(5);
3862 format %{ %}
3863 interface(CONST_INTER);
3864 %}
3866 // Pointer Immediate
3867 operand immN() %{
3868 match(ConN);
3870 op_cost(10);
3871 format %{ %}
3872 interface(CONST_INTER);
3873 %}
3875 operand immNKlass() %{
3876 match(ConNKlass);
3878 op_cost(10);
3879 format %{ %}
3880 interface(CONST_INTER);
3881 %}
3883 // NULL Pointer Immediate
3884 operand immN0() %{
3885 predicate(n->get_narrowcon() == 0);
3886 match(ConN);
3888 op_cost(5);
3889 format %{ %}
3890 interface(CONST_INTER);
3891 %}
3893 // Long Immediate
3894 operand immL() %{
3895 match(ConL);
3897 op_cost(20);
3898 format %{ %}
3899 interface(CONST_INTER);
3900 %}
3902 // Long Immediate zero
3903 operand immL0() %{
3904 predicate( n->get_long() == 0L );
3905 match(ConL);
3906 op_cost(0);
3908 format %{ %}
3909 interface(CONST_INTER);
3910 %}
3912 operand immL7() %{
3913 predicate( n->get_long() == 7L );
3914 match(ConL);
3915 op_cost(0);
3917 format %{ %}
3918 interface(CONST_INTER);
3919 %}
3921 operand immL_M1() %{
3922 predicate( n->get_long() == -1L );
3923 match(ConL);
3924 op_cost(0);
3926 format %{ %}
3927 interface(CONST_INTER);
3928 %}
3930 // bit 0..2 zero
3931 operand immL_M8() %{
3932 predicate( n->get_long() == -8L );
3933 match(ConL);
3934 op_cost(0);
3936 format %{ %}
3937 interface(CONST_INTER);
3938 %}
3940 // bit 2 zero
3941 operand immL_M5() %{
3942 predicate( n->get_long() == -5L );
3943 match(ConL);
3944 op_cost(0);
3946 format %{ %}
3947 interface(CONST_INTER);
3948 %}
3950 // bit 1..2 zero
3951 operand immL_M7() %{
3952 predicate( n->get_long() == -7L );
3953 match(ConL);
3954 op_cost(0);
3956 format %{ %}
3957 interface(CONST_INTER);
3958 %}
3960 // bit 0..1 zero
3961 operand immL_M4() %{
3962 predicate( n->get_long() == -4L );
3963 match(ConL);
3964 op_cost(0);
3966 format %{ %}
3967 interface(CONST_INTER);
3968 %}
3970 // bit 3..6 zero
3971 operand immL_M121() %{
3972 predicate( n->get_long() == -121L );
3973 match(ConL);
3974 op_cost(0);
3976 format %{ %}
3977 interface(CONST_INTER);
3978 %}
3980 // Long immediate from 0 to 127.
3981 // Used for a shorter form of long mul by 10.
3982 operand immL_127() %{
3983 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3984 match(ConL);
3985 op_cost(0);
3987 format %{ %}
3988 interface(CONST_INTER);
3989 %}
3991 // Operand for non-negtive long mask
3992 operand immL_nonneg_mask() %{
3993 predicate( (n->get_long() >= 0) && (Assembler::is_jlong_mask(n->get_long()) != -1) );
3994 match(ConL);
3996 op_cost(0);
3997 format %{ %}
3998 interface(CONST_INTER);
3999 %}
4001 operand immL_0_65535() %{
4002 predicate( n->get_long() >= 0 && n->get_long() <= 65535 );
4003 match(ConL);
4004 op_cost(0);
4006 format %{ %}
4007 interface(CONST_INTER);
4008 %}
4010 // Long Immediate: cheap (materialize in <= 3 instructions)
4011 operand immL_cheap() %{
4012 predicate(MacroAssembler::insts_for_set64(n->get_long()) <= 3);
4013 match(ConL);
4014 op_cost(0);
4016 format %{ %}
4017 interface(CONST_INTER);
4018 %}
4020 // Long Immediate: expensive (materialize in > 3 instructions)
4021 operand immL_expensive() %{
4022 predicate(MacroAssembler::insts_for_set64(n->get_long()) > 3);
4023 match(ConL);
4024 op_cost(0);
4026 format %{ %}
4027 interface(CONST_INTER);
4028 %}
4030 operand immL16() %{
4031 predicate((-32768 <= n->get_long()) && (n->get_long() <= 32767));
4032 match(ConL);
4034 op_cost(10);
4035 format %{ %}
4036 interface(CONST_INTER);
4037 %}
4039 operand immL16_sub() %{
4040 predicate((-32767 <= n->get_long()) && (n->get_long() <= 32768));
4041 match(ConL);
4043 op_cost(10);
4044 format %{ %}
4045 interface(CONST_INTER);
4046 %}
4048 // Long Immediate: low 32-bit mask
4049 operand immL_32bits() %{
4050 predicate(n->get_long() == 0xFFFFFFFFL);
4051 match(ConL);
4052 op_cost(20);
4054 format %{ %}
4055 interface(CONST_INTER);
4056 %}
4058 // Long Immediate 32-bit signed
4059 operand immL32()
4060 %{
4061 predicate(n->get_long() == (int) (n->get_long()));
4062 match(ConL);
4064 op_cost(15);
4065 format %{ %}
4066 interface(CONST_INTER);
4067 %}
4070 //single-precision floating-point zero
4071 operand immF0() %{
4072 predicate(jint_cast(n->getf()) == 0);
4073 match(ConF);
4075 op_cost(5);
4076 format %{ %}
4077 interface(CONST_INTER);
4078 %}
4080 //single-precision floating-point immediate
4081 operand immF() %{
4082 match(ConF);
4084 op_cost(20);
4085 format %{ %}
4086 interface(CONST_INTER);
4087 %}
4089 //double-precision floating-point zero
4090 operand immD0() %{
4091 predicate(jlong_cast(n->getd()) == 0);
4092 match(ConD);
4094 op_cost(5);
4095 format %{ %}
4096 interface(CONST_INTER);
4097 %}
4099 //double-precision floating-point immediate
4100 operand immD() %{
4101 match(ConD);
4103 op_cost(20);
4104 format %{ %}
4105 interface(CONST_INTER);
4106 %}
4108 // Register Operands
4109 // Integer Register
4110 operand mRegI() %{
4111 constraint(ALLOC_IN_RC(int_reg));
4112 match(RegI);
4114 format %{ %}
4115 interface(REG_INTER);
4116 %}
4118 operand no_Ax_mRegI() %{
4119 constraint(ALLOC_IN_RC(no_Ax_int_reg));
4120 match(RegI);
4121 match(mRegI);
4123 format %{ %}
4124 interface(REG_INTER);
4125 %}
4127 operand mS0RegI() %{
4128 constraint(ALLOC_IN_RC(s0_reg));
4129 match(RegI);
4130 match(mRegI);
4132 format %{ "S0" %}
4133 interface(REG_INTER);
4134 %}
4136 operand mS1RegI() %{
4137 constraint(ALLOC_IN_RC(s1_reg));
4138 match(RegI);
4139 match(mRegI);
4141 format %{ "S1" %}
4142 interface(REG_INTER);
4143 %}
4145 operand mS2RegI() %{
4146 constraint(ALLOC_IN_RC(s2_reg));
4147 match(RegI);
4148 match(mRegI);
4150 format %{ "S2" %}
4151 interface(REG_INTER);
4152 %}
4154 operand mS3RegI() %{
4155 constraint(ALLOC_IN_RC(s3_reg));
4156 match(RegI);
4157 match(mRegI);
4159 format %{ "S3" %}
4160 interface(REG_INTER);
4161 %}
4163 operand mS4RegI() %{
4164 constraint(ALLOC_IN_RC(s4_reg));
4165 match(RegI);
4166 match(mRegI);
4168 format %{ "S4" %}
4169 interface(REG_INTER);
4170 %}
4172 operand mS5RegI() %{
4173 constraint(ALLOC_IN_RC(s5_reg));
4174 match(RegI);
4175 match(mRegI);
4177 format %{ "S5" %}
4178 interface(REG_INTER);
4179 %}
4181 operand mS6RegI() %{
4182 constraint(ALLOC_IN_RC(s6_reg));
4183 match(RegI);
4184 match(mRegI);
4186 format %{ "S6" %}
4187 interface(REG_INTER);
4188 %}
4190 operand mS7RegI() %{
4191 constraint(ALLOC_IN_RC(s7_reg));
4192 match(RegI);
4193 match(mRegI);
4195 format %{ "S7" %}
4196 interface(REG_INTER);
4197 %}
4200 operand mT0RegI() %{
4201 constraint(ALLOC_IN_RC(t0_reg));
4202 match(RegI);
4203 match(mRegI);
4205 format %{ "T0" %}
4206 interface(REG_INTER);
4207 %}
4209 operand mT1RegI() %{
4210 constraint(ALLOC_IN_RC(t1_reg));
4211 match(RegI);
4212 match(mRegI);
4214 format %{ "T1" %}
4215 interface(REG_INTER);
4216 %}
4218 operand mT2RegI() %{
4219 constraint(ALLOC_IN_RC(t2_reg));
4220 match(RegI);
4221 match(mRegI);
4223 format %{ "T2" %}
4224 interface(REG_INTER);
4225 %}
4227 operand mT3RegI() %{
4228 constraint(ALLOC_IN_RC(t3_reg));
4229 match(RegI);
4230 match(mRegI);
4232 format %{ "T3" %}
4233 interface(REG_INTER);
4234 %}
4236 operand mT8RegI() %{
4237 constraint(ALLOC_IN_RC(t8_reg));
4238 match(RegI);
4239 match(mRegI);
4241 format %{ "T8" %}
4242 interface(REG_INTER);
4243 %}
4245 operand mT9RegI() %{
4246 constraint(ALLOC_IN_RC(t9_reg));
4247 match(RegI);
4248 match(mRegI);
4250 format %{ "T9" %}
4251 interface(REG_INTER);
4252 %}
4254 operand mA0RegI() %{
4255 constraint(ALLOC_IN_RC(a0_reg));
4256 match(RegI);
4257 match(mRegI);
4259 format %{ "A0" %}
4260 interface(REG_INTER);
4261 %}
4263 operand mA1RegI() %{
4264 constraint(ALLOC_IN_RC(a1_reg));
4265 match(RegI);
4266 match(mRegI);
4268 format %{ "A1" %}
4269 interface(REG_INTER);
4270 %}
4272 operand mA2RegI() %{
4273 constraint(ALLOC_IN_RC(a2_reg));
4274 match(RegI);
4275 match(mRegI);
4277 format %{ "A2" %}
4278 interface(REG_INTER);
4279 %}
4281 operand mA3RegI() %{
4282 constraint(ALLOC_IN_RC(a3_reg));
4283 match(RegI);
4284 match(mRegI);
4286 format %{ "A3" %}
4287 interface(REG_INTER);
4288 %}
4290 operand mA4RegI() %{
4291 constraint(ALLOC_IN_RC(a4_reg));
4292 match(RegI);
4293 match(mRegI);
4295 format %{ "A4" %}
4296 interface(REG_INTER);
4297 %}
4299 operand mA5RegI() %{
4300 constraint(ALLOC_IN_RC(a5_reg));
4301 match(RegI);
4302 match(mRegI);
4304 format %{ "A5" %}
4305 interface(REG_INTER);
4306 %}
4308 operand mA6RegI() %{
4309 constraint(ALLOC_IN_RC(a6_reg));
4310 match(RegI);
4311 match(mRegI);
4313 format %{ "A6" %}
4314 interface(REG_INTER);
4315 %}
4317 operand mA7RegI() %{
4318 constraint(ALLOC_IN_RC(a7_reg));
4319 match(RegI);
4320 match(mRegI);
4322 format %{ "A7" %}
4323 interface(REG_INTER);
4324 %}
4326 operand mV0RegI() %{
4327 constraint(ALLOC_IN_RC(v0_reg));
4328 match(RegI);
4329 match(mRegI);
4331 format %{ "V0" %}
4332 interface(REG_INTER);
4333 %}
4335 operand mV1RegI() %{
4336 constraint(ALLOC_IN_RC(v1_reg));
4337 match(RegI);
4338 match(mRegI);
4340 format %{ "V1" %}
4341 interface(REG_INTER);
4342 %}
4344 operand mRegN() %{
4345 constraint(ALLOC_IN_RC(int_reg));
4346 match(RegN);
4348 format %{ %}
4349 interface(REG_INTER);
4350 %}
4352 operand t0_RegN() %{
4353 constraint(ALLOC_IN_RC(t0_reg));
4354 match(RegN);
4355 match(mRegN);
4357 format %{ %}
4358 interface(REG_INTER);
4359 %}
4361 operand t1_RegN() %{
4362 constraint(ALLOC_IN_RC(t1_reg));
4363 match(RegN);
4364 match(mRegN);
4366 format %{ %}
4367 interface(REG_INTER);
4368 %}
4370 operand t2_RegN() %{
4371 constraint(ALLOC_IN_RC(t2_reg));
4372 match(RegN);
4373 match(mRegN);
4375 format %{ %}
4376 interface(REG_INTER);
4377 %}
4379 operand t3_RegN() %{
4380 constraint(ALLOC_IN_RC(t3_reg));
4381 match(RegN);
4382 match(mRegN);
4384 format %{ %}
4385 interface(REG_INTER);
4386 %}
4388 operand t8_RegN() %{
4389 constraint(ALLOC_IN_RC(t8_reg));
4390 match(RegN);
4391 match(mRegN);
4393 format %{ %}
4394 interface(REG_INTER);
4395 %}
4397 operand t9_RegN() %{
4398 constraint(ALLOC_IN_RC(t9_reg));
4399 match(RegN);
4400 match(mRegN);
4402 format %{ %}
4403 interface(REG_INTER);
4404 %}
4406 operand a0_RegN() %{
4407 constraint(ALLOC_IN_RC(a0_reg));
4408 match(RegN);
4409 match(mRegN);
4411 format %{ %}
4412 interface(REG_INTER);
4413 %}
4415 operand a1_RegN() %{
4416 constraint(ALLOC_IN_RC(a1_reg));
4417 match(RegN);
4418 match(mRegN);
4420 format %{ %}
4421 interface(REG_INTER);
4422 %}
4424 operand a2_RegN() %{
4425 constraint(ALLOC_IN_RC(a2_reg));
4426 match(RegN);
4427 match(mRegN);
4429 format %{ %}
4430 interface(REG_INTER);
4431 %}
4433 operand a3_RegN() %{
4434 constraint(ALLOC_IN_RC(a3_reg));
4435 match(RegN);
4436 match(mRegN);
4438 format %{ %}
4439 interface(REG_INTER);
4440 %}
4442 operand a4_RegN() %{
4443 constraint(ALLOC_IN_RC(a4_reg));
4444 match(RegN);
4445 match(mRegN);
4447 format %{ %}
4448 interface(REG_INTER);
4449 %}
4451 operand a5_RegN() %{
4452 constraint(ALLOC_IN_RC(a5_reg));
4453 match(RegN);
4454 match(mRegN);
4456 format %{ %}
4457 interface(REG_INTER);
4458 %}
4460 operand a6_RegN() %{
4461 constraint(ALLOC_IN_RC(a6_reg));
4462 match(RegN);
4463 match(mRegN);
4465 format %{ %}
4466 interface(REG_INTER);
4467 %}
4469 operand a7_RegN() %{
4470 constraint(ALLOC_IN_RC(a7_reg));
4471 match(RegN);
4472 match(mRegN);
4474 format %{ %}
4475 interface(REG_INTER);
4476 %}
4478 operand s0_RegN() %{
4479 constraint(ALLOC_IN_RC(s0_reg));
4480 match(RegN);
4481 match(mRegN);
4483 format %{ %}
4484 interface(REG_INTER);
4485 %}
4487 operand s1_RegN() %{
4488 constraint(ALLOC_IN_RC(s1_reg));
4489 match(RegN);
4490 match(mRegN);
4492 format %{ %}
4493 interface(REG_INTER);
4494 %}
4496 operand s2_RegN() %{
4497 constraint(ALLOC_IN_RC(s2_reg));
4498 match(RegN);
4499 match(mRegN);
4501 format %{ %}
4502 interface(REG_INTER);
4503 %}
4505 operand s3_RegN() %{
4506 constraint(ALLOC_IN_RC(s3_reg));
4507 match(RegN);
4508 match(mRegN);
4510 format %{ %}
4511 interface(REG_INTER);
4512 %}
4514 operand s4_RegN() %{
4515 constraint(ALLOC_IN_RC(s4_reg));
4516 match(RegN);
4517 match(mRegN);
4519 format %{ %}
4520 interface(REG_INTER);
4521 %}
4523 operand s5_RegN() %{
4524 constraint(ALLOC_IN_RC(s5_reg));
4525 match(RegN);
4526 match(mRegN);
4528 format %{ %}
4529 interface(REG_INTER);
4530 %}
4532 operand s6_RegN() %{
4533 constraint(ALLOC_IN_RC(s6_reg));
4534 match(RegN);
4535 match(mRegN);
4537 format %{ %}
4538 interface(REG_INTER);
4539 %}
4541 operand s7_RegN() %{
4542 constraint(ALLOC_IN_RC(s7_reg));
4543 match(RegN);
4544 match(mRegN);
4546 format %{ %}
4547 interface(REG_INTER);
4548 %}
4550 operand v0_RegN() %{
4551 constraint(ALLOC_IN_RC(v0_reg));
4552 match(RegN);
4553 match(mRegN);
4555 format %{ %}
4556 interface(REG_INTER);
4557 %}
4559 operand v1_RegN() %{
4560 constraint(ALLOC_IN_RC(v1_reg));
4561 match(RegN);
4562 match(mRegN);
4564 format %{ %}
4565 interface(REG_INTER);
4566 %}
4568 // Pointer Register
4569 operand mRegP() %{
4570 constraint(ALLOC_IN_RC(p_reg));
4571 match(RegP);
4573 format %{ %}
4574 interface(REG_INTER);
4575 %}
4577 operand no_T8_mRegP() %{
4578 constraint(ALLOC_IN_RC(no_T8_p_reg));
4579 match(RegP);
4580 match(mRegP);
4582 format %{ %}
4583 interface(REG_INTER);
4584 %}
4586 operand s0_RegP()
4587 %{
4588 constraint(ALLOC_IN_RC(s0_long_reg));
4589 match(RegP);
4590 match(mRegP);
4591 match(no_T8_mRegP);
4593 format %{ %}
4594 interface(REG_INTER);
4595 %}
4597 operand s1_RegP()
4598 %{
4599 constraint(ALLOC_IN_RC(s1_long_reg));
4600 match(RegP);
4601 match(mRegP);
4602 match(no_T8_mRegP);
4604 format %{ %}
4605 interface(REG_INTER);
4606 %}
4608 operand s2_RegP()
4609 %{
4610 constraint(ALLOC_IN_RC(s2_long_reg));
4611 match(RegP);
4612 match(mRegP);
4613 match(no_T8_mRegP);
4615 format %{ %}
4616 interface(REG_INTER);
4617 %}
4619 operand s3_RegP()
4620 %{
4621 constraint(ALLOC_IN_RC(s3_long_reg));
4622 match(RegP);
4623 match(mRegP);
4624 match(no_T8_mRegP);
4626 format %{ %}
4627 interface(REG_INTER);
4628 %}
4630 operand s4_RegP()
4631 %{
4632 constraint(ALLOC_IN_RC(s4_long_reg));
4633 match(RegP);
4634 match(mRegP);
4635 match(no_T8_mRegP);
4637 format %{ %}
4638 interface(REG_INTER);
4639 %}
4641 operand s5_RegP()
4642 %{
4643 constraint(ALLOC_IN_RC(s5_long_reg));
4644 match(RegP);
4645 match(mRegP);
4646 match(no_T8_mRegP);
4648 format %{ %}
4649 interface(REG_INTER);
4650 %}
4652 operand s6_RegP()
4653 %{
4654 constraint(ALLOC_IN_RC(s6_long_reg));
4655 match(RegP);
4656 match(mRegP);
4657 match(no_T8_mRegP);
4659 format %{ %}
4660 interface(REG_INTER);
4661 %}
4663 operand s7_RegP()
4664 %{
4665 constraint(ALLOC_IN_RC(s7_long_reg));
4666 match(RegP);
4667 match(mRegP);
4668 match(no_T8_mRegP);
4670 format %{ %}
4671 interface(REG_INTER);
4672 %}
4674 operand t0_RegP()
4675 %{
4676 constraint(ALLOC_IN_RC(t0_long_reg));
4677 match(RegP);
4678 match(mRegP);
4679 match(no_T8_mRegP);
4681 format %{ %}
4682 interface(REG_INTER);
4683 %}
4685 operand t1_RegP()
4686 %{
4687 constraint(ALLOC_IN_RC(t1_long_reg));
4688 match(RegP);
4689 match(mRegP);
4690 match(no_T8_mRegP);
4692 format %{ %}
4693 interface(REG_INTER);
4694 %}
4696 operand t2_RegP()
4697 %{
4698 constraint(ALLOC_IN_RC(t2_long_reg));
4699 match(RegP);
4700 match(mRegP);
4701 match(no_T8_mRegP);
4703 format %{ %}
4704 interface(REG_INTER);
4705 %}
4707 operand t3_RegP()
4708 %{
4709 constraint(ALLOC_IN_RC(t3_long_reg));
4710 match(RegP);
4711 match(mRegP);
4712 match(no_T8_mRegP);
4714 format %{ %}
4715 interface(REG_INTER);
4716 %}
4718 operand t8_RegP()
4719 %{
4720 constraint(ALLOC_IN_RC(t8_long_reg));
4721 match(RegP);
4722 match(mRegP);
4724 format %{ %}
4725 interface(REG_INTER);
4726 %}
4728 operand t9_RegP()
4729 %{
4730 constraint(ALLOC_IN_RC(t9_long_reg));
4731 match(RegP);
4732 match(mRegP);
4733 match(no_T8_mRegP);
4735 format %{ %}
4736 interface(REG_INTER);
4737 %}
4739 operand a0_RegP()
4740 %{
4741 constraint(ALLOC_IN_RC(a0_long_reg));
4742 match(RegP);
4743 match(mRegP);
4744 match(no_T8_mRegP);
4746 format %{ %}
4747 interface(REG_INTER);
4748 %}
4750 operand a1_RegP()
4751 %{
4752 constraint(ALLOC_IN_RC(a1_long_reg));
4753 match(RegP);
4754 match(mRegP);
4755 match(no_T8_mRegP);
4757 format %{ %}
4758 interface(REG_INTER);
4759 %}
4761 operand a2_RegP()
4762 %{
4763 constraint(ALLOC_IN_RC(a2_long_reg));
4764 match(RegP);
4765 match(mRegP);
4766 match(no_T8_mRegP);
4768 format %{ %}
4769 interface(REG_INTER);
4770 %}
4772 operand a3_RegP()
4773 %{
4774 constraint(ALLOC_IN_RC(a3_long_reg));
4775 match(RegP);
4776 match(mRegP);
4777 match(no_T8_mRegP);
4779 format %{ %}
4780 interface(REG_INTER);
4781 %}
4783 operand a4_RegP()
4784 %{
4785 constraint(ALLOC_IN_RC(a4_long_reg));
4786 match(RegP);
4787 match(mRegP);
4788 match(no_T8_mRegP);
4790 format %{ %}
4791 interface(REG_INTER);
4792 %}
4795 operand a5_RegP()
4796 %{
4797 constraint(ALLOC_IN_RC(a5_long_reg));
4798 match(RegP);
4799 match(mRegP);
4800 match(no_T8_mRegP);
4802 format %{ %}
4803 interface(REG_INTER);
4804 %}
4806 operand a6_RegP()
4807 %{
4808 constraint(ALLOC_IN_RC(a6_long_reg));
4809 match(RegP);
4810 match(mRegP);
4811 match(no_T8_mRegP);
4813 format %{ %}
4814 interface(REG_INTER);
4815 %}
4817 operand a7_RegP()
4818 %{
4819 constraint(ALLOC_IN_RC(a7_long_reg));
4820 match(RegP);
4821 match(mRegP);
4822 match(no_T8_mRegP);
4824 format %{ %}
4825 interface(REG_INTER);
4826 %}
4828 operand v0_RegP()
4829 %{
4830 constraint(ALLOC_IN_RC(v0_long_reg));
4831 match(RegP);
4832 match(mRegP);
4833 match(no_T8_mRegP);
4835 format %{ %}
4836 interface(REG_INTER);
4837 %}
4839 operand v1_RegP()
4840 %{
4841 constraint(ALLOC_IN_RC(v1_long_reg));
4842 match(RegP);
4843 match(mRegP);
4844 match(no_T8_mRegP);
4846 format %{ %}
4847 interface(REG_INTER);
4848 %}
4850 /*
4851 operand mSPRegP(mRegP reg) %{
4852 constraint(ALLOC_IN_RC(sp_reg));
4853 match(reg);
4855 format %{ "SP" %}
4856 interface(REG_INTER);
4857 %}
4859 operand mFPRegP(mRegP reg) %{
4860 constraint(ALLOC_IN_RC(fp_reg));
4861 match(reg);
4863 format %{ "FP" %}
4864 interface(REG_INTER);
4865 %}
4866 */
4868 operand mRegL() %{
4869 constraint(ALLOC_IN_RC(long_reg));
4870 match(RegL);
4872 format %{ %}
4873 interface(REG_INTER);
4874 %}
4876 operand v0RegL() %{
4877 constraint(ALLOC_IN_RC(v0_long_reg));
4878 match(RegL);
4879 match(mRegL);
4881 format %{ %}
4882 interface(REG_INTER);
4883 %}
4885 operand v1RegL() %{
4886 constraint(ALLOC_IN_RC(v1_long_reg));
4887 match(RegL);
4888 match(mRegL);
4890 format %{ %}
4891 interface(REG_INTER);
4892 %}
4894 operand a0RegL() %{
4895 constraint(ALLOC_IN_RC(a0_long_reg));
4896 match(RegL);
4897 match(mRegL);
4899 format %{ "A0" %}
4900 interface(REG_INTER);
4901 %}
4903 operand a1RegL() %{
4904 constraint(ALLOC_IN_RC(a1_long_reg));
4905 match(RegL);
4906 match(mRegL);
4908 format %{ %}
4909 interface(REG_INTER);
4910 %}
4912 operand a2RegL() %{
4913 constraint(ALLOC_IN_RC(a2_long_reg));
4914 match(RegL);
4915 match(mRegL);
4917 format %{ %}
4918 interface(REG_INTER);
4919 %}
4921 operand a3RegL() %{
4922 constraint(ALLOC_IN_RC(a3_long_reg));
4923 match(RegL);
4924 match(mRegL);
4926 format %{ %}
4927 interface(REG_INTER);
4928 %}
4930 operand t0RegL() %{
4931 constraint(ALLOC_IN_RC(t0_long_reg));
4932 match(RegL);
4933 match(mRegL);
4935 format %{ %}
4936 interface(REG_INTER);
4937 %}
4939 operand t1RegL() %{
4940 constraint(ALLOC_IN_RC(t1_long_reg));
4941 match(RegL);
4942 match(mRegL);
4944 format %{ %}
4945 interface(REG_INTER);
4946 %}
4948 operand t2RegL() %{
4949 constraint(ALLOC_IN_RC(t2_long_reg));
4950 match(RegL);
4951 match(mRegL);
4953 format %{ %}
4954 interface(REG_INTER);
4955 %}
4957 operand t3RegL() %{
4958 constraint(ALLOC_IN_RC(t3_long_reg));
4959 match(RegL);
4960 match(mRegL);
4962 format %{ %}
4963 interface(REG_INTER);
4964 %}
4966 operand t8RegL() %{
4967 constraint(ALLOC_IN_RC(t8_long_reg));
4968 match(RegL);
4969 match(mRegL);
4971 format %{ %}
4972 interface(REG_INTER);
4973 %}
4975 operand a4RegL() %{
4976 constraint(ALLOC_IN_RC(a4_long_reg));
4977 match(RegL);
4978 match(mRegL);
4980 format %{ %}
4981 interface(REG_INTER);
4982 %}
4984 operand a5RegL() %{
4985 constraint(ALLOC_IN_RC(a5_long_reg));
4986 match(RegL);
4987 match(mRegL);
4989 format %{ %}
4990 interface(REG_INTER);
4991 %}
4993 operand a6RegL() %{
4994 constraint(ALLOC_IN_RC(a6_long_reg));
4995 match(RegL);
4996 match(mRegL);
4998 format %{ %}
4999 interface(REG_INTER);
5000 %}
5002 operand a7RegL() %{
5003 constraint(ALLOC_IN_RC(a7_long_reg));
5004 match(RegL);
5005 match(mRegL);
5007 format %{ %}
5008 interface(REG_INTER);
5009 %}
5011 operand s0RegL() %{
5012 constraint(ALLOC_IN_RC(s0_long_reg));
5013 match(RegL);
5014 match(mRegL);
5016 format %{ %}
5017 interface(REG_INTER);
5018 %}
5020 operand s1RegL() %{
5021 constraint(ALLOC_IN_RC(s1_long_reg));
5022 match(RegL);
5023 match(mRegL);
5025 format %{ %}
5026 interface(REG_INTER);
5027 %}
5029 operand s2RegL() %{
5030 constraint(ALLOC_IN_RC(s2_long_reg));
5031 match(RegL);
5032 match(mRegL);
5034 format %{ %}
5035 interface(REG_INTER);
5036 %}
5038 operand s3RegL() %{
5039 constraint(ALLOC_IN_RC(s3_long_reg));
5040 match(RegL);
5041 match(mRegL);
5043 format %{ %}
5044 interface(REG_INTER);
5045 %}
5047 operand s4RegL() %{
5048 constraint(ALLOC_IN_RC(s4_long_reg));
5049 match(RegL);
5050 match(mRegL);
5052 format %{ %}
5053 interface(REG_INTER);
5054 %}
5056 operand s7RegL() %{
5057 constraint(ALLOC_IN_RC(s7_long_reg));
5058 match(RegL);
5059 match(mRegL);
5061 format %{ %}
5062 interface(REG_INTER);
5063 %}
5065 // Floating register operands
5066 operand regF() %{
5067 constraint(ALLOC_IN_RC(flt_reg));
5068 match(RegF);
5070 format %{ %}
5071 interface(REG_INTER);
5072 %}
5074 //Double Precision Floating register operands
5075 operand regD() %{
5076 constraint(ALLOC_IN_RC(dbl_reg));
5077 match(RegD);
5079 format %{ %}
5080 interface(REG_INTER);
5081 %}
5083 //----------Memory Operands----------------------------------------------------
5084 // Indirect Memory Operand
5085 operand indirect(mRegP reg) %{
5086 constraint(ALLOC_IN_RC(p_reg));
5087 match(reg);
5089 format %{ "[$reg] @ indirect" %}
5090 interface(MEMORY_INTER) %{
5091 base($reg);
5092 index(0x0); /* NO_INDEX */
5093 scale(0x0);
5094 disp(0x0);
5095 %}
5096 %}
5098 // Indirect Memory Plus Short Offset Operand
5099 operand indOffset8(mRegP reg, immL8 off)
5100 %{
5101 constraint(ALLOC_IN_RC(p_reg));
5102 match(AddP reg off);
5104 format %{ "[$reg + $off (8-bit)] @ indOffset8" %}
5105 interface(MEMORY_INTER) %{
5106 base($reg);
5107 index(0x0); /* NO_INDEX */
5108 scale(0x0);
5109 disp($off);
5110 %}
5111 %}
5113 // Indirect Memory Times Scale Plus Index Register
5114 operand indIndexScale(mRegP reg, mRegL lreg, immI2 scale)
5115 %{
5116 constraint(ALLOC_IN_RC(p_reg));
5117 match(AddP reg (LShiftL lreg scale));
5119 op_cost(10);
5120 format %{"[$reg + $lreg << $scale] @ indIndexScale" %}
5121 interface(MEMORY_INTER) %{
5122 base($reg);
5123 index($lreg);
5124 scale($scale);
5125 disp(0x0);
5126 %}
5127 %}
5130 // [base + index + offset]
5131 operand baseIndexOffset8(mRegP base, mRegL index, immL8 off)
5132 %{
5133 constraint(ALLOC_IN_RC(p_reg));
5134 op_cost(5);
5135 match(AddP (AddP base index) off);
5137 format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8" %}
5138 interface(MEMORY_INTER) %{
5139 base($base);
5140 index($index);
5141 scale(0x0);
5142 disp($off);
5143 %}
5144 %}
5146 // [base + index + offset]
5147 operand baseIndexOffset8_convI2L(mRegP base, mRegI index, immL8 off)
5148 %{
5149 constraint(ALLOC_IN_RC(p_reg));
5150 op_cost(5);
5151 match(AddP (AddP base (ConvI2L index)) off);
5153 format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8_convI2L" %}
5154 interface(MEMORY_INTER) %{
5155 base($base);
5156 index($index);
5157 scale(0x0);
5158 disp($off);
5159 %}
5160 %}
5162 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5163 operand indIndexScaleOffset8(mRegP reg, immL8 off, mRegL lreg, immI2 scale)
5164 %{
5165 constraint(ALLOC_IN_RC(p_reg));
5166 match(AddP (AddP reg (LShiftL lreg scale)) off);
5168 op_cost(10);
5169 format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffset8" %}
5170 interface(MEMORY_INTER) %{
5171 base($reg);
5172 index($lreg);
5173 scale($scale);
5174 disp($off);
5175 %}
5176 %}
5178 operand indIndexScaleOffset8_convI2L(mRegP reg, immL8 off, mRegI ireg, immI2 scale)
5179 %{
5180 constraint(ALLOC_IN_RC(p_reg));
5181 match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off);
5183 op_cost(10);
5184 format %{"[$reg + $off + $ireg << $scale] @ indIndexScaleOffset8_convI2L" %}
5185 interface(MEMORY_INTER) %{
5186 base($reg);
5187 index($ireg);
5188 scale($scale);
5189 disp($off);
5190 %}
5191 %}
5193 // [base + index<<scale + offset]
5194 operand basePosIndexScaleOffset8(mRegP base, mRegI index, immL8 off, immI_0_31 scale)
5195 %{
5196 constraint(ALLOC_IN_RC(p_reg));
5197 //predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5198 op_cost(10);
5199 match(AddP (AddP base (LShiftL (ConvI2L index) scale)) off);
5201 format %{ "[$base + $index << $scale + $off (8-bit)] @ basePosIndexScaleOffset8" %}
5202 interface(MEMORY_INTER) %{
5203 base($base);
5204 index($index);
5205 scale($scale);
5206 disp($off);
5207 %}
5208 %}
5210 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5211 operand indIndexScaleOffsetNarrow(mRegN reg, immL8 off, mRegL lreg, immI2 scale)
5212 %{
5213 predicate(Universe::narrow_oop_shift() == 0);
5214 constraint(ALLOC_IN_RC(p_reg));
5215 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
5217 op_cost(10);
5218 format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffsetNarrow" %}
5219 interface(MEMORY_INTER) %{
5220 base($reg);
5221 index($lreg);
5222 scale($scale);
5223 disp($off);
5224 %}
5225 %}
5227 // [base + index<<scale + offset] for compressd Oops
5228 operand indPosIndexI2LScaleOffset8Narrow(mRegN base, mRegI index, immL8 off, immI_0_31 scale)
5229 %{
5230 constraint(ALLOC_IN_RC(p_reg));
5231 //predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5232 predicate(Universe::narrow_oop_shift() == 0);
5233 op_cost(10);
5234 match(AddP (AddP (DecodeN base) (LShiftL (ConvI2L index) scale)) off);
5236 format %{ "[$base + $index << $scale + $off (8-bit)] @ indPosIndexI2LScaleOffset8Narrow" %}
5237 interface(MEMORY_INTER) %{
5238 base($base);
5239 index($index);
5240 scale($scale);
5241 disp($off);
5242 %}
5243 %}
5245 //FIXME: I think it's better to limit the immI to be 16-bit at most!
5246 // Indirect Memory Plus Long Offset Operand
5247 operand indOffset32(mRegP reg, immL32 off) %{
5248 constraint(ALLOC_IN_RC(p_reg));
5249 op_cost(20);
5250 match(AddP reg off);
5252 format %{ "[$reg + $off (32-bit)] @ indOffset32" %}
5253 interface(MEMORY_INTER) %{
5254 base($reg);
5255 index(0x0); /* NO_INDEX */
5256 scale(0x0);
5257 disp($off);
5258 %}
5259 %}
5261 // Indirect Memory Plus Index Register
5262 operand indIndex(mRegP addr, mRegL index) %{
5263 constraint(ALLOC_IN_RC(p_reg));
5264 match(AddP addr index);
5266 op_cost(20);
5267 format %{"[$addr + $index] @ indIndex" %}
5268 interface(MEMORY_INTER) %{
5269 base($addr);
5270 index($index);
5271 scale(0x0);
5272 disp(0x0);
5273 %}
5274 %}
5276 operand indirectNarrowKlass(mRegN reg)
5277 %{
5278 predicate(Universe::narrow_klass_shift() == 0);
5279 constraint(ALLOC_IN_RC(p_reg));
5280 op_cost(10);
5281 match(DecodeNKlass reg);
5283 format %{ "[$reg] @ indirectNarrowKlass" %}
5284 interface(MEMORY_INTER) %{
5285 base($reg);
5286 index(0x0);
5287 scale(0x0);
5288 disp(0x0);
5289 %}
5290 %}
5292 operand indOffset8NarrowKlass(mRegN reg, immL8 off)
5293 %{
5294 predicate(Universe::narrow_klass_shift() == 0);
5295 constraint(ALLOC_IN_RC(p_reg));
5296 op_cost(10);
5297 match(AddP (DecodeNKlass reg) off);
5299 format %{ "[$reg + $off (8-bit)] @ indOffset8NarrowKlass" %}
5300 interface(MEMORY_INTER) %{
5301 base($reg);
5302 index(0x0);
5303 scale(0x0);
5304 disp($off);
5305 %}
5306 %}
5308 operand indOffset32NarrowKlass(mRegN reg, immL32 off)
5309 %{
5310 predicate(Universe::narrow_klass_shift() == 0);
5311 constraint(ALLOC_IN_RC(p_reg));
5312 op_cost(10);
5313 match(AddP (DecodeNKlass reg) off);
5315 format %{ "[$reg + $off (32-bit)] @ indOffset32NarrowKlass" %}
5316 interface(MEMORY_INTER) %{
5317 base($reg);
5318 index(0x0);
5319 scale(0x0);
5320 disp($off);
5321 %}
5322 %}
5324 operand indIndexOffsetNarrowKlass(mRegN reg, mRegL lreg, immL32 off)
5325 %{
5326 predicate(Universe::narrow_klass_shift() == 0);
5327 constraint(ALLOC_IN_RC(p_reg));
5328 match(AddP (AddP (DecodeNKlass reg) lreg) off);
5330 op_cost(10);
5331 format %{"[$reg + $off + $lreg] @ indIndexOffsetNarrowKlass" %}
5332 interface(MEMORY_INTER) %{
5333 base($reg);
5334 index($lreg);
5335 scale(0x0);
5336 disp($off);
5337 %}
5338 %}
5340 operand indIndexNarrowKlass(mRegN reg, mRegL lreg)
5341 %{
5342 predicate(Universe::narrow_klass_shift() == 0);
5343 constraint(ALLOC_IN_RC(p_reg));
5344 match(AddP (DecodeNKlass reg) lreg);
5346 op_cost(10);
5347 format %{"[$reg + $lreg] @ indIndexNarrowKlass" %}
5348 interface(MEMORY_INTER) %{
5349 base($reg);
5350 index($lreg);
5351 scale(0x0);
5352 disp(0x0);
5353 %}
5354 %}
5356 // Indirect Memory Operand
5357 operand indirectNarrow(mRegN reg)
5358 %{
5359 predicate(Universe::narrow_oop_shift() == 0);
5360 constraint(ALLOC_IN_RC(p_reg));
5361 op_cost(10);
5362 match(DecodeN reg);
5364 format %{ "[$reg] @ indirectNarrow" %}
5365 interface(MEMORY_INTER) %{
5366 base($reg);
5367 index(0x0);
5368 scale(0x0);
5369 disp(0x0);
5370 %}
5371 %}
5373 // Indirect Memory Plus Short Offset Operand
5374 operand indOffset8Narrow(mRegN reg, immL8 off)
5375 %{
5376 predicate(Universe::narrow_oop_shift() == 0);
5377 constraint(ALLOC_IN_RC(p_reg));
5378 op_cost(10);
5379 match(AddP (DecodeN reg) off);
5381 format %{ "[$reg + $off (8-bit)] @ indOffset8Narrow" %}
5382 interface(MEMORY_INTER) %{
5383 base($reg);
5384 index(0x0);
5385 scale(0x0);
5386 disp($off);
5387 %}
5388 %}
5390 // Indirect Memory Plus Index Register Plus Offset Operand
5391 operand indIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off)
5392 %{
5393 predicate(Universe::narrow_oop_shift() == 0);
5394 constraint(ALLOC_IN_RC(p_reg));
5395 match(AddP (AddP (DecodeN reg) lreg) off);
5397 op_cost(10);
5398 format %{"[$reg + $off + $lreg] @ indIndexOffset8Narrow" %}
5399 interface(MEMORY_INTER) %{
5400 base($reg);
5401 index($lreg);
5402 scale(0x0);
5403 disp($off);
5404 %}
5405 %}
5407 //----------Load Long Memory Operands------------------------------------------
5408 // The load-long idiom will use it's address expression again after loading
5409 // the first word of the long. If the load-long destination overlaps with
5410 // registers used in the addressing expression, the 2nd half will be loaded
5411 // from a clobbered address. Fix this by requiring that load-long use
5412 // address registers that do not overlap with the load-long target.
5414 // load-long support
5415 operand load_long_RegP() %{
5416 constraint(ALLOC_IN_RC(p_reg));
5417 match(RegP);
5418 match(mRegP);
5419 op_cost(100);
5420 format %{ %}
5421 interface(REG_INTER);
5422 %}
5424 // Indirect Memory Operand Long
5425 operand load_long_indirect(load_long_RegP reg) %{
5426 constraint(ALLOC_IN_RC(p_reg));
5427 match(reg);
5429 format %{ "[$reg]" %}
5430 interface(MEMORY_INTER) %{
5431 base($reg);
5432 index(0x0);
5433 scale(0x0);
5434 disp(0x0);
5435 %}
5436 %}
5438 // Indirect Memory Plus Long Offset Operand
5439 operand load_long_indOffset32(load_long_RegP reg, immL32 off) %{
5440 match(AddP reg off);
5442 format %{ "[$reg + $off]" %}
5443 interface(MEMORY_INTER) %{
5444 base($reg);
5445 index(0x0);
5446 scale(0x0);
5447 disp($off);
5448 %}
5449 %}
5451 //----------Conditional Branch Operands----------------------------------------
5452 // Comparison Op - This is the operation of the comparison, and is limited to
5453 // the following set of codes:
5454 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5455 //
5456 // Other attributes of the comparison, such as unsignedness, are specified
5457 // by the comparison instruction that sets a condition code flags register.
5458 // That result is represented by a flags operand whose subtype is appropriate
5459 // to the unsignedness (etc.) of the comparison.
5460 //
5461 // Later, the instruction which matches both the Comparison Op (a Bool) and
5462 // the flags (produced by the Cmp) specifies the coding of the comparison op
5463 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5465 // Comparision Code
5466 operand cmpOp() %{
5467 match(Bool);
5469 format %{ "" %}
5470 interface(COND_INTER) %{
5471 equal(0x01);
5472 not_equal(0x02);
5473 greater(0x03);
5474 greater_equal(0x04);
5475 less(0x05);
5476 less_equal(0x06);
5477 overflow(0x7);
5478 no_overflow(0x8);
5479 %}
5480 %}
5483 // Comparision Code
5484 // Comparison Code, unsigned compare. Used by FP also, with
5485 // C2 (unordered) turned into GT or LT already. The other bits
5486 // C0 and C3 are turned into Carry & Zero flags.
5487 operand cmpOpU() %{
5488 match(Bool);
5490 format %{ "" %}
5491 interface(COND_INTER) %{
5492 equal(0x01);
5493 not_equal(0x02);
5494 greater(0x03);
5495 greater_equal(0x04);
5496 less(0x05);
5497 less_equal(0x06);
5498 overflow(0x7);
5499 no_overflow(0x8);
5500 %}
5501 %}
5503 /*
5504 // Comparison Code, unsigned compare. Used by FP also, with
5505 // C2 (unordered) turned into GT or LT already. The other bits
5506 // C0 and C3 are turned into Carry & Zero flags.
5507 operand cmpOpU() %{
5508 match(Bool);
5510 format %{ "" %}
5511 interface(COND_INTER) %{
5512 equal(0x4);
5513 not_equal(0x5);
5514 less(0x2);
5515 greater_equal(0x3);
5516 less_equal(0x6);
5517 greater(0x7);
5518 %}
5519 %}
5520 */
5521 /*
5522 // Comparison Code for FP conditional move
5523 operand cmpOp_fcmov() %{
5524 match(Bool);
5526 format %{ "" %}
5527 interface(COND_INTER) %{
5528 equal (0x01);
5529 not_equal (0x02);
5530 greater (0x03);
5531 greater_equal(0x04);
5532 less (0x05);
5533 less_equal (0x06);
5534 %}
5535 %}
5537 // Comparision Code used in long compares
5538 operand cmpOp_commute() %{
5539 match(Bool);
5541 format %{ "" %}
5542 interface(COND_INTER) %{
5543 equal(0x4);
5544 not_equal(0x5);
5545 less(0xF);
5546 greater_equal(0xE);
5547 less_equal(0xD);
5548 greater(0xC);
5549 %}
5550 %}
5551 */
5553 //----------Special Memory Operands--------------------------------------------
5554 // Stack Slot Operand - This operand is used for loading and storing temporary
5555 // values on the stack where a match requires a value to
5556 // flow through memory.
5557 operand stackSlotP(sRegP reg) %{
5558 constraint(ALLOC_IN_RC(stack_slots));
5559 // No match rule because this operand is only generated in matching
5560 op_cost(50);
5561 format %{ "[$reg]" %}
5562 interface(MEMORY_INTER) %{
5563 base(0x1d); // SP
5564 index(0x0); // No Index
5565 scale(0x0); // No Scale
5566 disp($reg); // Stack Offset
5567 %}
5568 %}
5570 operand stackSlotI(sRegI reg) %{
5571 constraint(ALLOC_IN_RC(stack_slots));
5572 // No match rule because this operand is only generated in matching
5573 op_cost(50);
5574 format %{ "[$reg]" %}
5575 interface(MEMORY_INTER) %{
5576 base(0x1d); // SP
5577 index(0x0); // No Index
5578 scale(0x0); // No Scale
5579 disp($reg); // Stack Offset
5580 %}
5581 %}
5583 operand stackSlotF(sRegF reg) %{
5584 constraint(ALLOC_IN_RC(stack_slots));
5585 // No match rule because this operand is only generated in matching
5586 op_cost(50);
5587 format %{ "[$reg]" %}
5588 interface(MEMORY_INTER) %{
5589 base(0x1d); // SP
5590 index(0x0); // No Index
5591 scale(0x0); // No Scale
5592 disp($reg); // Stack Offset
5593 %}
5594 %}
5596 operand stackSlotD(sRegD reg) %{
5597 constraint(ALLOC_IN_RC(stack_slots));
5598 // No match rule because this operand is only generated in matching
5599 op_cost(50);
5600 format %{ "[$reg]" %}
5601 interface(MEMORY_INTER) %{
5602 base(0x1d); // SP
5603 index(0x0); // No Index
5604 scale(0x0); // No Scale
5605 disp($reg); // Stack Offset
5606 %}
5607 %}
5609 operand stackSlotL(sRegL reg) %{
5610 constraint(ALLOC_IN_RC(stack_slots));
5611 // No match rule because this operand is only generated in matching
5612 op_cost(50);
5613 format %{ "[$reg]" %}
5614 interface(MEMORY_INTER) %{
5615 base(0x1d); // SP
5616 index(0x0); // No Index
5617 scale(0x0); // No Scale
5618 disp($reg); // Stack Offset
5619 %}
5620 %}
5623 //------------------------OPERAND CLASSES--------------------------------------
5624 //opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset );
5625 opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, indIndexScale, load_long_indirect, load_long_indOffset32, baseIndexOffset8, baseIndexOffset8_convI2L, indIndexScaleOffset8, indIndexScaleOffset8_convI2L, basePosIndexScaleOffset8, indIndexScaleOffsetNarrow, indPosIndexI2LScaleOffset8Narrow, indOffset8Narrow, indIndexOffset8Narrow);
5628 //----------PIPELINE-----------------------------------------------------------
5629 // Rules which define the behavior of the target architectures pipeline.
5631 pipeline %{
5633 //----------ATTRIBUTES---------------------------------------------------------
5634 attributes %{
5635 fixed_size_instructions; // Fixed size instructions
5636 branch_has_delay_slot; // branch have delay slot in gs2
5637 max_instructions_per_bundle = 1; // 1 instruction per bundle
5638 max_bundles_per_cycle = 4; // Up to 4 bundles per cycle
5639 bundle_unit_size=4;
5640 instruction_unit_size = 4; // An instruction is 4 bytes long
5641 instruction_fetch_unit_size = 16; // The processor fetches one line
5642 instruction_fetch_units = 1; // of 16 bytes
5644 // List of nop instructions
5645 nops( MachNop );
5646 %}
5648 //----------RESOURCES----------------------------------------------------------
5649 // Resources are the functional units available to the machine
5651 resources(D1, D2, D3, D4, DECODE = D1 | D2 | D3| D4, ALU1, ALU2, ALU = ALU1 | ALU2, FPU1, FPU2, FPU = FPU1 | FPU2, MEM, BR);
5653 //----------PIPELINE DESCRIPTION-----------------------------------------------
5654 // Pipeline Description specifies the stages in the machine's pipeline
5656 // IF: fetch
5657 // ID: decode
5658 // RD: read
5659 // CA: caculate
5660 // WB: write back
5661 // CM: commit
5663 pipe_desc(IF, ID, RD, CA, WB, CM);
5666 //----------PIPELINE CLASSES---------------------------------------------------
5667 // Pipeline Classes describe the stages in which input and output are
5668 // referenced by the hardware pipeline.
5670 //No.1 Integer ALU reg-reg operation : dst <-- reg1 op reg2
5671 pipe_class ialu_regI_regI(mRegI dst, mRegI src1, mRegI src2) %{
5672 single_instruction;
5673 src1 : RD(read);
5674 src2 : RD(read);
5675 dst : WB(write)+1;
5676 DECODE : ID;
5677 ALU : CA;
5678 %}
5680 //No.19 Integer mult operation : dst <-- reg1 mult reg2
5681 pipe_class ialu_mult(mRegI dst, mRegI src1, mRegI src2) %{
5682 src1 : RD(read);
5683 src2 : RD(read);
5684 dst : WB(write)+5;
5685 DECODE : ID;
5686 ALU2 : CA;
5687 %}
5689 pipe_class mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
5690 src1 : RD(read);
5691 src2 : RD(read);
5692 dst : WB(write)+10;
5693 DECODE : ID;
5694 ALU2 : CA;
5695 %}
5697 //No.19 Integer div operation : dst <-- reg1 div reg2
5698 pipe_class ialu_div(mRegI dst, mRegI src1, mRegI src2) %{
5699 src1 : RD(read);
5700 src2 : RD(read);
5701 dst : WB(write)+10;
5702 DECODE : ID;
5703 ALU2 : CA;
5704 %}
5706 //No.19 Integer mod operation : dst <-- reg1 mod reg2
5707 pipe_class ialu_mod(mRegI dst, mRegI src1, mRegI src2) %{
5708 instruction_count(2);
5709 src1 : RD(read);
5710 src2 : RD(read);
5711 dst : WB(write)+10;
5712 DECODE : ID;
5713 ALU2 : CA;
5714 %}
5716 //No.15 Long ALU reg-reg operation : dst <-- reg1 op reg2
5717 pipe_class ialu_regL_regL(mRegL dst, mRegL src1, mRegL src2) %{
5718 instruction_count(2);
5719 src1 : RD(read);
5720 src2 : RD(read);
5721 dst : WB(write);
5722 DECODE : ID;
5723 ALU : CA;
5724 %}
5726 //No.18 Long ALU reg-imm16 operation : dst <-- reg1 op imm16
5727 pipe_class ialu_regL_imm16(mRegL dst, mRegL src) %{
5728 instruction_count(2);
5729 src : RD(read);
5730 dst : WB(write);
5731 DECODE : ID;
5732 ALU : CA;
5733 %}
5735 //no.16 load Long from memory :
5736 pipe_class ialu_loadL(mRegL dst, memory mem) %{
5737 instruction_count(2);
5738 mem : RD(read);
5739 dst : WB(write)+5;
5740 DECODE : ID;
5741 MEM : RD;
5742 %}
5744 //No.17 Store Long to Memory :
5745 pipe_class ialu_storeL(mRegL src, memory mem) %{
5746 instruction_count(2);
5747 mem : RD(read);
5748 src : RD(read);
5749 DECODE : ID;
5750 MEM : RD;
5751 %}
5753 //No.2 Integer ALU reg-imm16 operation : dst <-- reg1 op imm16
5754 pipe_class ialu_regI_imm16(mRegI dst, mRegI src) %{
5755 single_instruction;
5756 src : RD(read);
5757 dst : WB(write);
5758 DECODE : ID;
5759 ALU : CA;
5760 %}
5762 //No.3 Integer move operation : dst <-- reg
5763 pipe_class ialu_regI_mov(mRegI dst, mRegI src) %{
5764 src : RD(read);
5765 dst : WB(write);
5766 DECODE : ID;
5767 ALU : CA;
5768 %}
5770 //No.4 No instructions : do nothing
5771 pipe_class empty( ) %{
5772 instruction_count(0);
5773 %}
5775 //No.5 UnConditional branch :
5776 pipe_class pipe_jump( label labl ) %{
5777 multiple_bundles;
5778 DECODE : ID;
5779 BR : RD;
5780 %}
5782 //No.6 ALU Conditional branch :
5783 pipe_class pipe_alu_branch(mRegI src1, mRegI src2, label labl ) %{
5784 multiple_bundles;
5785 src1 : RD(read);
5786 src2 : RD(read);
5787 DECODE : ID;
5788 BR : RD;
5789 %}
5791 //no.7 load integer from memory :
5792 pipe_class ialu_loadI(mRegI dst, memory mem) %{
5793 mem : RD(read);
5794 dst : WB(write)+3;
5795 DECODE : ID;
5796 MEM : RD;
5797 %}
5799 //No.8 Store Integer to Memory :
5800 pipe_class ialu_storeI(mRegI src, memory mem) %{
5801 mem : RD(read);
5802 src : RD(read);
5803 DECODE : ID;
5804 MEM : RD;
5805 %}
5808 //No.10 Floating FPU reg-reg operation : dst <-- reg1 op reg2
5809 pipe_class fpu_regF_regF(regF dst, regF src1, regF src2) %{
5810 src1 : RD(read);
5811 src2 : RD(read);
5812 dst : WB(write);
5813 DECODE : ID;
5814 FPU : CA;
5815 %}
5817 //No.22 Floating div operation : dst <-- reg1 div reg2
5818 pipe_class fpu_div(regF dst, regF src1, regF src2) %{
5819 src1 : RD(read);
5820 src2 : RD(read);
5821 dst : WB(write);
5822 DECODE : ID;
5823 FPU2 : CA;
5824 %}
5826 pipe_class fcvt_I2D(regD dst, mRegI src) %{
5827 src : RD(read);
5828 dst : WB(write);
5829 DECODE : ID;
5830 FPU1 : CA;
5831 %}
5833 pipe_class fcvt_D2I(mRegI dst, regD src) %{
5834 src : RD(read);
5835 dst : WB(write);
5836 DECODE : ID;
5837 FPU1 : CA;
5838 %}
5840 pipe_class pipe_mfc1(mRegI dst, regD src) %{
5841 src : RD(read);
5842 dst : WB(write);
5843 DECODE : ID;
5844 MEM : RD;
5845 %}
5847 pipe_class pipe_mtc1(regD dst, mRegI src) %{
5848 src : RD(read);
5849 dst : WB(write);
5850 DECODE : ID;
5851 MEM : RD(5);
5852 %}
5854 //No.23 Floating sqrt operation : dst <-- reg1 sqrt reg2
5855 pipe_class fpu_sqrt(regF dst, regF src1, regF src2) %{
5856 multiple_bundles;
5857 src1 : RD(read);
5858 src2 : RD(read);
5859 dst : WB(write);
5860 DECODE : ID;
5861 FPU2 : CA;
5862 %}
5864 //No.11 Load Floating from Memory :
5865 pipe_class fpu_loadF(regF dst, memory mem) %{
5866 instruction_count(1);
5867 mem : RD(read);
5868 dst : WB(write)+3;
5869 DECODE : ID;
5870 MEM : RD;
5871 %}
5873 //No.12 Store Floating to Memory :
5874 pipe_class fpu_storeF(regF src, memory mem) %{
5875 instruction_count(1);
5876 mem : RD(read);
5877 src : RD(read);
5878 DECODE : ID;
5879 MEM : RD;
5880 %}
5882 //No.13 FPU Conditional branch :
5883 pipe_class pipe_fpu_branch(regF src1, regF src2, label labl ) %{
5884 multiple_bundles;
5885 src1 : RD(read);
5886 src2 : RD(read);
5887 DECODE : ID;
5888 BR : RD;
5889 %}
5891 //No.14 Floating FPU reg operation : dst <-- op reg
5892 pipe_class fpu1_regF(regF dst, regF src) %{
5893 src : RD(read);
5894 dst : WB(write);
5895 DECODE : ID;
5896 FPU : CA;
5897 %}
5899 pipe_class long_memory_op() %{
5900 instruction_count(10); multiple_bundles; force_serialization;
5901 fixed_latency(30);
5902 %}
5904 pipe_class simple_call() %{
5905 instruction_count(10); multiple_bundles; force_serialization;
5906 fixed_latency(200);
5907 BR : RD;
5908 %}
5910 pipe_class call() %{
5911 instruction_count(10); multiple_bundles; force_serialization;
5912 fixed_latency(200);
5913 %}
5915 //FIXME:
5916 //No.9 Piple slow : for multi-instructions
5917 pipe_class pipe_slow( ) %{
5918 instruction_count(20);
5919 force_serialization;
5920 multiple_bundles;
5921 fixed_latency(50);
5922 %}
5924 %}
5928 //----------INSTRUCTIONS-------------------------------------------------------
5929 //
5930 // match -- States which machine-independent subtree may be replaced
5931 // by this instruction.
5932 // ins_cost -- The estimated cost of this instruction is used by instruction
5933 // selection to identify a minimum cost tree of machine
5934 // instructions that matches a tree of machine-independent
5935 // instructions.
5936 // format -- A string providing the disassembly for this instruction.
5937 // The value of an instruction's operand may be inserted
5938 // by referring to it with a '$' prefix.
5939 // opcode -- Three instruction opcodes may be provided. These are referred
5940 // to within an encode class as $primary, $secondary, and $tertiary
5941 // respectively. The primary opcode is commonly used to
5942 // indicate the type of machine instruction, while secondary
5943 // and tertiary are often used for prefix options or addressing
5944 // modes.
5945 // ins_encode -- A list of encode classes with parameters. The encode class
5946 // name must have been defined in an 'enc_class' specification
5947 // in the encode section of the architecture description.
5950 // Load Integer
5951 instruct loadI(mRegI dst, memory mem) %{
5952 match(Set dst (LoadI mem));
5954 ins_cost(125);
5955 format %{ "lw $dst, $mem #@loadI" %}
5956 ins_encode (load_I_enc(dst, mem));
5957 ins_pipe( ialu_loadI );
5958 %}
5960 instruct loadI_convI2L(mRegL dst, memory mem) %{
5961 match(Set dst (ConvI2L (LoadI mem)));
5963 ins_cost(125);
5964 format %{ "lw $dst, $mem #@loadI_convI2L" %}
5965 ins_encode (load_I_enc(dst, mem));
5966 ins_pipe( ialu_loadI );
5967 %}
5969 // Load Integer (32 bit signed) to Byte (8 bit signed)
5970 instruct loadI2B(mRegI dst, memory mem, immI_24 twentyfour) %{
5971 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5973 ins_cost(125);
5974 format %{ "lb $dst, $mem\t# int -> byte #@loadI2B" %}
5975 ins_encode(load_B_enc(dst, mem));
5976 ins_pipe(ialu_loadI);
5977 %}
5979 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5980 instruct loadI2UB(mRegI dst, memory mem, immI_255 mask) %{
5981 match(Set dst (AndI (LoadI mem) mask));
5983 ins_cost(125);
5984 format %{ "lbu $dst, $mem\t# int -> ubyte #@loadI2UB" %}
5985 ins_encode(load_UB_enc(dst, mem));
5986 ins_pipe(ialu_loadI);
5987 %}
5989 // Load Integer (32 bit signed) to Short (16 bit signed)
5990 instruct loadI2S(mRegI dst, memory mem, immI_16 sixteen) %{
5991 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5993 ins_cost(125);
5994 format %{ "lh $dst, $mem\t# int -> short #@loadI2S" %}
5995 ins_encode(load_S_enc(dst, mem));
5996 ins_pipe(ialu_loadI);
5997 %}
5999 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6000 instruct loadI2US(mRegI dst, memory mem, immI_65535 mask) %{
6001 match(Set dst (AndI (LoadI mem) mask));
6003 ins_cost(125);
6004 format %{ "lhu $dst, $mem\t# int -> ushort/char #@loadI2US" %}
6005 ins_encode(load_C_enc(dst, mem));
6006 ins_pipe(ialu_loadI);
6007 %}
6009 // Load Long.
6010 instruct loadL(mRegL dst, memory mem) %{
6011 // predicate(!((LoadLNode*)n)->require_atomic_access());
6012 match(Set dst (LoadL mem));
6014 ins_cost(250);
6015 format %{ "ld $dst, $mem #@loadL" %}
6016 ins_encode(load_L_enc(dst, mem));
6017 ins_pipe( ialu_loadL );
6018 %}
6020 // Load Long - UNaligned
6021 instruct loadL_unaligned(mRegL dst, memory mem) %{
6022 match(Set dst (LoadL_unaligned mem));
6024 // FIXME: Jin: Need more effective ldl/ldr
6025 ins_cost(450);
6026 format %{ "ld $dst, $mem #@loadL_unaligned\n\t" %}
6027 ins_encode(load_L_enc(dst, mem));
6028 ins_pipe( ialu_loadL );
6029 %}
6031 // Store Long
6032 instruct storeL_reg(memory mem, mRegL src) %{
6033 predicate(!((StoreLNode*)n)->require_atomic_access());
6034 match(Set mem (StoreL mem src));
6036 ins_cost(200);
6037 format %{ "sd $mem, $src #@storeL_reg\n" %}
6038 ins_encode(store_L_reg_enc(mem, src));
6039 ins_pipe( ialu_storeL );
6040 %}
6042 //FIXME:volatile! atomic!
6043 // Volatile Store Long. Must be atomic, so move it into
6044 // the FP TOS and then do a 64-bit FIST. Has to probe the
6045 // target address before the store (for null-ptr checks)
6046 // so the memory operand is used twice in the encoding.
6047 instruct storeL_reg_atomic(memory mem, mRegL src) %{
6048 predicate(((StoreLNode*)n)->require_atomic_access());
6049 match(Set mem (StoreL mem src));
6051 ins_cost(200);
6052 format %{ "sw $mem, $src #@storeL_reg_atomic\n" %}
6053 ins_encode %{
6054 Register src = as_Register($src$$reg);
6056 int base = $mem$$base;
6057 int index = $mem$$index;
6058 int scale = $mem$$scale;
6059 int disp = $mem$$disp;
6061 if( index != 0 ) {
6062 if( Assembler::is_simm16(disp) ) {
6063 if (scale == 0) {
6064 __ addu(AT, as_Register(base), as_Register(index));
6065 } else {
6066 __ dsll(AT, as_Register(index), scale);
6067 __ addu(AT, as_Register(base), AT);
6068 }
6069 __ sd(src, AT, disp);
6070 } else {
6071 if (scale == 0) {
6072 __ addu(AT, as_Register(base), as_Register(index));
6073 } else {
6074 __ dsll(AT, as_Register(index), scale);
6075 __ addu(AT, as_Register(base), AT);
6076 }
6077 __ move(T9, disp);
6078 __ addu(AT, AT, T9);
6079 __ sd(src, AT, 0);
6080 }
6081 } else {
6082 if( Assembler::is_simm16(disp) ) {
6083 __ move(AT, as_Register(base));
6084 __ sd(src, AT, disp);
6085 } else {
6086 __ move(AT, as_Register(base));
6087 __ move(T9, disp);
6088 __ addu(AT, AT, T9);
6089 __ sd(src, AT, 0);
6090 }
6091 }
6093 %}
6094 ins_pipe( ialu_storeL );
6095 %}
6097 instruct storeL_immL0(memory mem, immL0 zero) %{
6098 match(Set mem (StoreL mem zero));
6100 ins_cost(180);
6101 format %{ "sd $mem, zero #@storeL_immL0" %}
6102 ins_encode(store_L_immL0_enc(mem, zero));
6103 ins_pipe( ialu_storeL );
6104 %}
6106 instruct storeL_imm(memory mem, immL src) %{
6107 match(Set mem (StoreL mem src));
6109 ins_cost(200);
6110 format %{ "sw $mem, $src #@storeL_imm" %}
6111 ins_encode(store_L_immL_enc(mem, src));
6112 ins_pipe( ialu_storeL );
6113 %}
6115 // Load Compressed Pointer
6116 instruct loadN(mRegN dst, memory mem)
6117 %{
6118 match(Set dst (LoadN mem));
6120 ins_cost(125); // XXX
6121 format %{ "lwu $dst, $mem\t# compressed ptr @ loadN" %}
6122 ins_encode (load_N_enc(dst, mem));
6123 ins_pipe( ialu_loadI ); // XXX
6124 %}
6126 // Load Pointer
6127 instruct loadP(mRegP dst, memory mem) %{
6128 match(Set dst (LoadP mem));
6130 ins_cost(125);
6131 format %{ "ld $dst, $mem #@loadP" %}
6132 ins_encode (load_P_enc(dst, mem));
6133 ins_pipe( ialu_loadI );
6134 %}
6136 // Load Klass Pointer
6137 instruct loadKlass(mRegP dst, memory mem) %{
6138 match(Set dst (LoadKlass mem));
6140 ins_cost(125);
6141 format %{ "MOV $dst,$mem @ loadKlass" %}
6142 ins_encode (load_P_enc(dst, mem));
6143 ins_pipe( ialu_loadI );
6144 %}
6146 // Load narrow Klass Pointer
6147 instruct loadNKlass(mRegN dst, memory mem)
6148 %{
6149 match(Set dst (LoadNKlass mem));
6151 ins_cost(125); // XXX
6152 format %{ "lwu $dst, $mem\t# compressed klass ptr @ loadNKlass" %}
6153 ins_encode (load_N_enc(dst, mem));
6154 ins_pipe( ialu_loadI ); // XXX
6155 %}
6157 // Load Constant
6158 instruct loadConI(mRegI dst, immI src) %{
6159 match(Set dst src);
6161 ins_cost(150);
6162 format %{ "mov $dst, $src #@loadConI" %}
6163 ins_encode %{
6164 Register dst = $dst$$Register;
6165 int value = $src$$constant;
6166 __ move(dst, value);
6167 %}
6168 ins_pipe( ialu_regI_regI );
6169 %}
6172 instruct loadConL_set64(mRegL dst, immL src) %{
6173 match(Set dst src);
6174 ins_cost(120);
6175 format %{ "li $dst, $src @ loadConL_set64" %}
6176 ins_encode %{
6177 __ set64($dst$$Register, $src$$constant);
6178 %}
6179 ins_pipe(ialu_regL_regL);
6180 %}
6182 /*
6183 // Load long value from constant table (predicated by immL_expensive).
6184 instruct loadConL_load(mRegL dst, immL_expensive src) %{
6185 match(Set dst src);
6186 ins_cost(150);
6187 format %{ "ld $dst, $constantoffset[$constanttablebase] # load long $src from table @ loadConL_ldx" %}
6188 ins_encode %{
6189 int con_offset = $constantoffset($src);
6191 if (Assembler::is_simm16(con_offset)) {
6192 __ ld($dst$$Register, $constanttablebase, con_offset);
6193 } else {
6194 __ set64(AT, con_offset);
6195 if (UseLoongsonISA) {
6196 __ gsldx($dst$$Register, $constanttablebase, AT, 0);
6197 } else {
6198 __ daddu(AT, $constanttablebase, AT);
6199 __ ld($dst$$Register, AT, 0);
6200 }
6201 }
6202 %}
6203 ins_pipe(ialu_loadI);
6204 %}
6205 */
6207 instruct loadConL16(mRegL dst, immL16 src) %{
6208 match(Set dst src);
6209 ins_cost(105);
6210 format %{ "mov $dst, $src #@loadConL16" %}
6211 ins_encode %{
6212 Register dst_reg = as_Register($dst$$reg);
6213 int value = $src$$constant;
6214 __ daddiu(dst_reg, R0, value);
6215 %}
6216 ins_pipe( ialu_regL_regL );
6217 %}
6220 instruct loadConL0(mRegL dst, immL0 src) %{
6221 match(Set dst src);
6222 ins_cost(100);
6223 format %{ "mov $dst, zero #@loadConL0" %}
6224 ins_encode %{
6225 Register dst_reg = as_Register($dst$$reg);
6226 __ daddu(dst_reg, R0, R0);
6227 %}
6228 ins_pipe( ialu_regL_regL );
6229 %}
6231 // Load Range
6232 instruct loadRange(mRegI dst, memory mem) %{
6233 match(Set dst (LoadRange mem));
6235 ins_cost(125);
6236 format %{ "MOV $dst,$mem @ loadRange" %}
6237 ins_encode(load_I_enc(dst, mem));
6238 ins_pipe( ialu_loadI );
6239 %}
6242 instruct storeP(memory mem, mRegP src ) %{
6243 match(Set mem (StoreP mem src));
6245 ins_cost(125);
6246 format %{ "sd $src, $mem #@storeP" %}
6247 ins_encode(store_P_reg_enc(mem, src));
6248 ins_pipe( ialu_storeI );
6249 %}
6251 /*
6252 [Ref: loadConP]
6254 Error:
6255 0x2d4b6d40: lui t9, 0x4f <--- handle
6256 0x2d4b6d44: addiu t9, t9, 0xffff808c
6257 0x2d4b6d48: sw t9, 0x4(s2)
6259 OK:
6260 0x2cc5ed40: lui t9, 0x336a <--- klass
6261 0x2cc5ed44: addiu t9, t9, 0x5a10
6262 0x2cc5ed48: sw t9, 0x4(s2)
6263 */
6264 // Store Pointer Immediate; null pointers or constant oops that do not
6265 // need card-mark barriers.
6267 // Store NULL Pointer, mark word, or other simple pointer constant.
6268 instruct storeImmP(memory mem, immP31 src) %{
6269 match(Set mem (StoreP mem src));
6271 ins_cost(150);
6272 format %{ "mov $mem, $src #@storeImmP" %}
6273 ins_encode(store_P_immP_enc(mem, src));
6274 ins_pipe( ialu_storeI );
6275 %}
6277 // Store Byte Immediate
6278 instruct storeImmB(memory mem, immI8 src) %{
6279 match(Set mem (StoreB mem src));
6281 ins_cost(150);
6282 format %{ "movb $mem, $src #@storeImmB" %}
6283 ins_encode(store_B_immI_enc(mem, src));
6284 ins_pipe( ialu_storeI );
6285 %}
6287 // Store Compressed Pointer
6288 instruct storeN(memory mem, mRegN src)
6289 %{
6290 match(Set mem (StoreN mem src));
6292 ins_cost(125); // XXX
6293 format %{ "sw $mem, $src\t# compressed ptr @ storeN" %}
6294 ins_encode(store_N_reg_enc(mem, src));
6295 ins_pipe( ialu_storeI );
6296 %}
6298 instruct storeNKlass(memory mem, mRegN src)
6299 %{
6300 match(Set mem (StoreNKlass mem src));
6302 ins_cost(125); // XXX
6303 format %{ "sw $mem, $src\t# compressed klass ptr @ storeNKlass" %}
6304 ins_encode(store_N_reg_enc(mem, src));
6305 ins_pipe( ialu_storeI );
6306 %}
6308 instruct storeImmN0(memory mem, immN0 zero)
6309 %{
6310 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6311 match(Set mem (StoreN mem zero));
6313 ins_cost(125); // XXX
6314 format %{ "storeN0 $mem, R12\t# compressed ptr" %}
6315 ins_encode(storeImmN0_enc(mem, zero));
6316 ins_pipe( ialu_storeI );
6317 %}
6319 instruct storeImmN(memory mem, immN src)
6320 %{
6321 match(Set mem (StoreN mem src));
6323 ins_cost(150); // XXX
6324 format %{ "storeImmN $mem, $src\t# compressed ptr @ storeImmN" %}
6325 ins_encode(storeImmN_enc(mem, src));
6326 ins_pipe( ialu_storeI );
6327 %}
6329 instruct storeImmNKlass(memory mem, immNKlass src)
6330 %{
6331 match(Set mem (StoreNKlass mem src));
6333 ins_cost(150); // XXX
6334 format %{ "sw $mem, $src\t# compressed klass ptr @ storeImmNKlass" %}
6335 ins_encode(storeImmNKlass_enc(mem, src));
6336 ins_pipe( ialu_storeI );
6337 %}
6339 // Store Byte
6340 instruct storeB(memory mem, mRegI src) %{
6341 match(Set mem (StoreB mem src));
6343 ins_cost(125);
6344 format %{ "sb $src, $mem #@storeB" %}
6345 ins_encode(store_B_reg_enc(mem, src));
6346 ins_pipe( ialu_storeI );
6347 %}
6349 // Load Byte (8bit signed)
6350 instruct loadB(mRegI dst, memory mem) %{
6351 match(Set dst (LoadB mem));
6353 ins_cost(125);
6354 format %{ "lb $dst, $mem #@loadB" %}
6355 ins_encode(load_B_enc(dst, mem));
6356 ins_pipe( ialu_loadI );
6357 %}
6359 instruct loadB_convI2L(mRegL dst, memory mem) %{
6360 match(Set dst (ConvI2L (LoadB mem)));
6362 ins_cost(125);
6363 format %{ "lb $dst, $mem #@loadB_convI2L" %}
6364 ins_encode(load_B_enc(dst, mem));
6365 ins_pipe( ialu_loadI );
6366 %}
6368 // Load Byte (8bit UNsigned)
6369 instruct loadUB(mRegI dst, memory mem) %{
6370 match(Set dst (LoadUB mem));
6372 ins_cost(125);
6373 format %{ "lbu $dst, $mem #@loadUB" %}
6374 ins_encode(load_UB_enc(dst, mem));
6375 ins_pipe( ialu_loadI );
6376 %}
6378 instruct loadUB_convI2L(mRegL dst, memory mem) %{
6379 match(Set dst (ConvI2L (LoadUB mem)));
6381 ins_cost(125);
6382 format %{ "lbu $dst, $mem #@loadUB_convI2L" %}
6383 ins_encode(load_UB_enc(dst, mem));
6384 ins_pipe( ialu_loadI );
6385 %}
6387 // Load Short (16bit signed)
6388 instruct loadS(mRegI dst, memory mem) %{
6389 match(Set dst (LoadS mem));
6391 ins_cost(125);
6392 format %{ "lh $dst, $mem #@loadS" %}
6393 ins_encode(load_S_enc(dst, mem));
6394 ins_pipe( ialu_loadI );
6395 %}
6397 // Load Short (16 bit signed) to Byte (8 bit signed)
6398 instruct loadS2B(mRegI dst, memory mem, immI_24 twentyfour) %{
6399 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6401 ins_cost(125);
6402 format %{ "lb $dst, $mem\t# short -> byte #@loadS2B" %}
6403 ins_encode(load_B_enc(dst, mem));
6404 ins_pipe(ialu_loadI);
6405 %}
6407 instruct loadS_convI2L(mRegL dst, memory mem) %{
6408 match(Set dst (ConvI2L (LoadS mem)));
6410 ins_cost(125);
6411 format %{ "lh $dst, $mem #@loadS_convI2L" %}
6412 ins_encode(load_S_enc(dst, mem));
6413 ins_pipe( ialu_loadI );
6414 %}
6416 // Store Integer Immediate
6417 instruct storeImmI(memory mem, immI src) %{
6418 match(Set mem (StoreI mem src));
6420 ins_cost(150);
6421 format %{ "mov $mem, $src #@storeImmI" %}
6422 ins_encode(store_I_immI_enc(mem, src));
6423 ins_pipe( ialu_storeI );
6424 %}
6426 // Store Integer
6427 instruct storeI(memory mem, mRegI src) %{
6428 match(Set mem (StoreI mem src));
6430 ins_cost(125);
6431 format %{ "sw $mem, $src #@storeI" %}
6432 ins_encode(store_I_reg_enc(mem, src));
6433 ins_pipe( ialu_storeI );
6434 %}
6436 instruct storeI_convL2I(memory mem, mRegL src) %{
6437 match(Set mem (StoreI mem (ConvL2I src)));
6439 ins_cost(125);
6440 format %{ "sw $mem, $src #@storeI_convL2I" %}
6441 ins_encode(store_I_reg_enc(mem, src));
6442 ins_pipe( ialu_storeI );
6443 %}
6445 // Load Float
6446 instruct loadF(regF dst, memory mem) %{
6447 match(Set dst (LoadF mem));
6449 ins_cost(150);
6450 format %{ "loadF $dst, $mem #@loadF" %}
6451 ins_encode(load_F_enc(dst, mem));
6452 ins_pipe( ialu_loadI );
6453 %}
6455 instruct loadConP_general(mRegP dst, immP src) %{
6456 match(Set dst src);
6458 ins_cost(120);
6459 format %{ "li $dst, $src #@loadConP_general" %}
6461 ins_encode %{
6462 Register dst = $dst$$Register;
6463 long* value = (long*)$src$$constant;
6464 bool is_need_reloc = $src->constant_reloc() != relocInfo::none;
6466 /* During GC, klassOop may be moved to new position in the heap.
6467 * It must be relocated.
6468 * Refer: [c1_LIRAssembler_mips.cpp] jobject2reg()
6469 */
6470 if (is_need_reloc) {
6471 if($src->constant_reloc() == relocInfo::metadata_type){
6472 int klass_index = __ oop_recorder()->find_index((Klass*)value);
6473 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6475 __ relocate(rspec);
6476 __ li48(dst, (long)value);
6477 }
6479 if($src->constant_reloc() == relocInfo::oop_type){
6480 int oop_index = __ oop_recorder()->find_index((jobject)value);
6481 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6483 __ relocate(rspec);
6484 __ li48(dst, (long)value);
6485 }
6486 } else {
6487 __ set64(dst, (long)value);
6488 }
6489 %}
6491 ins_pipe( ialu_regI_regI );
6492 %}
6494 /*
6495 instruct loadConP_load(mRegP dst, immP_load src) %{
6496 match(Set dst src);
6498 ins_cost(100);
6499 format %{ "ld $dst, [$constanttablebase + $constantoffset] load from constant table: ptr=$src @ loadConP_load" %}
6501 ins_encode %{
6503 int con_offset = $constantoffset($src);
6505 if (Assembler::is_simm16(con_offset)) {
6506 __ ld($dst$$Register, $constanttablebase, con_offset);
6507 } else {
6508 __ set64(AT, con_offset);
6509 if (UseLoongsonISA) {
6510 __ gsldx($dst$$Register, $constanttablebase, AT, 0);
6511 } else {
6512 __ daddu(AT, $constanttablebase, AT);
6513 __ ld($dst$$Register, AT, 0);
6514 }
6515 }
6516 %}
6518 ins_pipe(ialu_loadI);
6519 %}
6520 */
6522 instruct loadConP_no_oop_cheap(mRegP dst, immP_no_oop_cheap src) %{
6523 match(Set dst src);
6525 ins_cost(80);
6526 format %{ "li $dst, $src @ loadConP_no_oop_cheap" %}
6528 ins_encode %{
6529 __ set64($dst$$Register, $src$$constant);
6530 %}
6532 ins_pipe(ialu_regI_regI);
6533 %}
6536 instruct loadConP_poll(mRegP dst, immP_poll src) %{
6537 match(Set dst src);
6539 ins_cost(50);
6540 format %{ "li $dst, $src #@loadConP_poll" %}
6542 ins_encode %{
6543 Register dst = $dst$$Register;
6544 intptr_t value = (intptr_t)$src$$constant;
6546 __ set64(dst, (jlong)value);
6547 %}
6549 ins_pipe( ialu_regI_regI );
6550 %}
6552 instruct loadConP0(mRegP dst, immP0 src)
6553 %{
6554 match(Set dst src);
6556 ins_cost(50);
6557 format %{ "mov $dst, R0\t# ptr" %}
6558 ins_encode %{
6559 Register dst_reg = $dst$$Register;
6560 __ daddu(dst_reg, R0, R0);
6561 %}
6562 ins_pipe( ialu_regI_regI );
6563 %}
6565 instruct loadConN0(mRegN dst, immN0 src) %{
6566 match(Set dst src);
6567 format %{ "move $dst, R0\t# compressed NULL ptr" %}
6568 ins_encode %{
6569 __ move($dst$$Register, R0);
6570 %}
6571 ins_pipe( ialu_regI_regI );
6572 %}
6574 instruct loadConN(mRegN dst, immN src) %{
6575 match(Set dst src);
6577 ins_cost(125);
6578 format %{ "li $dst, $src\t# compressed ptr @ loadConN" %}
6579 ins_encode %{
6580 address con = (address)$src$$constant;
6581 if (con == NULL) {
6582 ShouldNotReachHere();
6583 } else {
6584 assert (UseCompressedOops, "should only be used for compressed headers");
6585 assert (Universe::heap() != NULL, "java heap should be initialized");
6586 assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6588 Register dst = $dst$$Register;
6589 long* value = (long*)$src$$constant;
6590 int oop_index = __ oop_recorder()->find_index((jobject)value);
6591 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6592 if(rspec.type()!=relocInfo::none){
6593 __ relocate(rspec, Assembler::narrow_oop_operand);
6594 __ li48(dst, oop_index);
6595 } else {
6596 __ set64(dst, oop_index);
6597 }
6598 }
6599 %}
6600 ins_pipe( ialu_regI_regI ); // XXX
6601 %}
6603 instruct loadConNKlass(mRegN dst, immNKlass src) %{
6604 match(Set dst src);
6606 ins_cost(125);
6607 format %{ "li $dst, $src\t# compressed klass ptr @ loadConNKlass" %}
6608 ins_encode %{
6609 address con = (address)$src$$constant;
6610 if (con == NULL) {
6611 ShouldNotReachHere();
6612 } else {
6613 Register dst = $dst$$Register;
6614 long* value = (long*)$src$$constant;
6616 int klass_index = __ oop_recorder()->find_index((Klass*)value);
6617 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6618 long narrowp = (long)Klass::encode_klass((Klass*)value);
6620 if(rspec.type()!=relocInfo::none){
6621 __ relocate(rspec, Assembler::narrow_oop_operand);
6622 __ li48(dst, narrowp);
6623 } else {
6624 __ set64(dst, narrowp);
6625 }
6626 }
6627 %}
6628 ins_pipe( ialu_regI_regI ); // XXX
6629 %}
6631 //FIXME
6632 // Tail Call; Jump from runtime stub to Java code.
6633 // Also known as an 'interprocedural jump'.
6634 // Target of jump will eventually return to caller.
6635 // TailJump below removes the return address.
6636 instruct TailCalljmpInd(mRegP jump_target, mRegP method_oop) %{
6637 match(TailCall jump_target method_oop );
6638 ins_cost(300);
6639 format %{ "JMP $jump_target \t# @TailCalljmpInd" %}
6641 ins_encode %{
6642 Register target = $jump_target$$Register;
6643 Register oop = $method_oop$$Register;
6645 /* 2012/10/12 Jin: RA will be used in generate_forward_exception() */
6646 __ push(RA);
6648 __ move(S3, oop);
6649 __ jr(target);
6650 __ nop();
6651 %}
6653 ins_pipe( pipe_jump );
6654 %}
6656 // Create exception oop: created by stack-crawling runtime code.
6657 // Created exception is now available to this handler, and is setup
6658 // just prior to jumping to this handler. No code emitted.
6659 instruct CreateException( a0_RegP ex_oop )
6660 %{
6661 match(Set ex_oop (CreateEx));
6663 // use the following format syntax
6664 format %{ "# exception oop is in A0; no code emitted @CreateException" %}
6665 ins_encode %{
6666 /* Jin: X86 leaves this function empty */
6667 __ block_comment("CreateException is empty in X86/MIPS");
6668 %}
6669 ins_pipe( empty );
6670 // ins_pipe( pipe_jump );
6671 %}
6674 /* 2012/9/14 Jin: The mechanism of exception handling is clear now.
6676 - Common try/catch:
6677 2012/9/14 Jin: [stubGenerator_mips.cpp] generate_forward_exception()
6678 |- V0, V1 are created
6679 |- T9 <= SharedRuntime::exception_handler_for_return_address
6680 `- jr T9
6681 `- the caller's exception_handler
6682 `- jr OptoRuntime::exception_blob
6683 `- here
6684 - Rethrow(e.g. 'unwind'):
6685 * The callee:
6686 |- an exception is triggered during execution
6687 `- exits the callee method through RethrowException node
6688 |- The callee pushes exception_oop(T0) and exception_pc(RA)
6689 `- The callee jumps to OptoRuntime::rethrow_stub()
6690 * In OptoRuntime::rethrow_stub:
6691 |- The VM calls _rethrow_Java to determine the return address in the caller method
6692 `- exits the stub with tailjmpInd
6693 |- pops exception_oop(V0) and exception_pc(V1)
6694 `- jumps to the return address(usually an exception_handler)
6695 * The caller:
6696 `- continues processing the exception_blob with V0/V1
6697 */
6699 /*
6700 Disassembling OptoRuntime::rethrow_stub()
6702 ; locals
6703 0x2d3bf320: addiu sp, sp, 0xfffffff8
6704 0x2d3bf324: sw ra, 0x4(sp)
6705 0x2d3bf328: sw fp, 0x0(sp)
6706 0x2d3bf32c: addu fp, sp, zero
6707 0x2d3bf330: addiu sp, sp, 0xfffffff0
6708 0x2d3bf334: sw ra, 0x8(sp)
6709 0x2d3bf338: sw t0, 0x4(sp)
6710 0x2d3bf33c: sw sp, 0x0(sp)
6712 ; get_thread(S2)
6713 0x2d3bf340: addu s2, sp, zero
6714 0x2d3bf344: srl s2, s2, 12
6715 0x2d3bf348: sll s2, s2, 2
6716 0x2d3bf34c: lui at, 0x2c85
6717 0x2d3bf350: addu at, at, s2
6718 0x2d3bf354: lw s2, 0xffffcc80(at)
6720 0x2d3bf358: lw s0, 0x0(sp)
6721 0x2d3bf35c: sw s0, 0x118(s2) // last_sp -> threa
6722 0x2d3bf360: sw s2, 0xc(sp)
6724 ; OptoRuntime::rethrow_C(oopDesc* exception, JavaThread* thread, address ret_pc)
6725 0x2d3bf364: lw a0, 0x4(sp)
6726 0x2d3bf368: lw a1, 0xc(sp)
6727 0x2d3bf36c: lw a2, 0x8(sp)
6728 ;; Java_To_Runtime
6729 0x2d3bf370: lui t9, 0x2c34
6730 0x2d3bf374: addiu t9, t9, 0xffff8a48
6731 0x2d3bf378: jalr t9
6732 0x2d3bf37c: nop
6734 0x2d3bf380: addu s3, v0, zero ; S3: SharedRuntime::raw_exception_handler_for_return_address()
6736 0x2d3bf384: lw s0, 0xc(sp)
6737 0x2d3bf388: sw zero, 0x118(s0)
6738 0x2d3bf38c: sw zero, 0x11c(s0)
6739 0x2d3bf390: lw s1, 0x144(s0) ; ex_oop: S1
6740 0x2d3bf394: addu s2, s0, zero
6741 0x2d3bf398: sw zero, 0x144(s2)
6742 0x2d3bf39c: lw s0, 0x4(s2)
6743 0x2d3bf3a0: addiu s4, zero, 0x0
6744 0x2d3bf3a4: bne s0, s4, 0x2d3bf3d4
6745 0x2d3bf3a8: nop
6746 0x2d3bf3ac: addiu sp, sp, 0x10
6747 0x2d3bf3b0: addiu sp, sp, 0x8
6748 0x2d3bf3b4: lw ra, 0xfffffffc(sp)
6749 0x2d3bf3b8: lw fp, 0xfffffff8(sp)
6750 0x2d3bf3bc: lui at, 0x2b48
6751 0x2d3bf3c0: lw at, 0x100(at)
6753 ; tailjmpInd: Restores exception_oop & exception_pc
6754 0x2d3bf3c4: addu v1, ra, zero
6755 0x2d3bf3c8: addu v0, s1, zero
6756 0x2d3bf3cc: jr s3
6757 0x2d3bf3d0: nop
6758 ; Exception:
6759 0x2d3bf3d4: lui s1, 0x2cc8 ; generate_forward_exception()
6760 0x2d3bf3d8: addiu s1, s1, 0x40
6761 0x2d3bf3dc: addiu s2, zero, 0x0
6762 0x2d3bf3e0: addiu sp, sp, 0x10
6763 0x2d3bf3e4: addiu sp, sp, 0x8
6764 0x2d3bf3e8: lw ra, 0xfffffffc(sp)
6765 0x2d3bf3ec: lw fp, 0xfffffff8(sp)
6766 0x2d3bf3f0: lui at, 0x2b48
6767 0x2d3bf3f4: lw at, 0x100(at)
6768 ; TailCalljmpInd
6769 __ push(RA); ; to be used in generate_forward_exception()
6770 0x2d3bf3f8: addu t7, s2, zero
6771 0x2d3bf3fc: jr s1
6772 0x2d3bf400: nop
6773 */
6774 // Rethrow exception:
6775 // The exception oop will come in the first argument position.
6776 // Then JUMP (not call) to the rethrow stub code.
6777 instruct RethrowException()
6778 %{
6779 match(Rethrow);
6781 // use the following format syntax
6782 format %{ "JMP rethrow_stub #@RethrowException" %}
6783 ins_encode %{
6784 __ block_comment("@ RethrowException");
6786 cbuf.set_insts_mark();
6787 cbuf.relocate(cbuf.insts_mark(), runtime_call_Relocation::spec());
6789 // call OptoRuntime::rethrow_stub to get the exception handler in parent method
6790 __ li(T9, OptoRuntime::rethrow_stub());
6791 __ jr(T9);
6792 __ nop();
6793 %}
6794 ins_pipe( pipe_jump );
6795 %}
6797 instruct branchConP_zero(cmpOpU cmp, mRegP op1, immP0 zero, label labl) %{
6798 match(If cmp (CmpP op1 zero));
6799 effect(USE labl);
6801 ins_cost(180);
6802 format %{ "b$cmp $op1, R0, $labl #@branchConP_zero" %}
6804 ins_encode %{
6805 Register op1 = $op1$$Register;
6806 Register op2 = R0;
6807 Label &L = *($labl$$label);
6808 int flag = $cmp$$cmpcode;
6810 switch(flag)
6811 {
6812 case 0x01: //equal
6813 if (&L)
6814 __ beq(op1, op2, L);
6815 else
6816 __ beq(op1, op2, (int)0);
6817 break;
6818 case 0x02: //not_equal
6819 if (&L)
6820 __ bne(op1, op2, L);
6821 else
6822 __ bne(op1, op2, (int)0);
6823 break;
6824 /*
6825 case 0x03: //above
6826 __ sltu(AT, op2, op1);
6827 if(&L)
6828 __ bne(R0, AT, L);
6829 else
6830 __ bne(R0, AT, (int)0);
6831 break;
6832 case 0x04: //above_equal
6833 __ sltu(AT, op1, op2);
6834 if(&L)
6835 __ beq(AT, R0, L);
6836 else
6837 __ beq(AT, R0, (int)0);
6838 break;
6839 case 0x05: //below
6840 __ sltu(AT, op1, op2);
6841 if(&L)
6842 __ bne(R0, AT, L);
6843 else
6844 __ bne(R0, AT, (int)0);
6845 break;
6846 case 0x06: //below_equal
6847 __ sltu(AT, op2, op1);
6848 if(&L)
6849 __ beq(AT, R0, L);
6850 else
6851 __ beq(AT, R0, (int)0);
6852 break;
6853 */
6854 default:
6855 Unimplemented();
6856 }
6857 __ nop();
6858 %}
6860 ins_pc_relative(1);
6861 ins_pipe( pipe_alu_branch );
6862 %}
6865 instruct branchConP(cmpOpU cmp, mRegP op1, mRegP op2, label labl) %{
6866 match(If cmp (CmpP op1 op2));
6867 // predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
6868 effect(USE labl);
6870 ins_cost(200);
6871 format %{ "b$cmp $op1, $op2, $labl #@branchConP" %}
6873 ins_encode %{
6874 Register op1 = $op1$$Register;
6875 Register op2 = $op2$$Register;
6876 Label &L = *($labl$$label);
6877 int flag = $cmp$$cmpcode;
6879 switch(flag)
6880 {
6881 case 0x01: //equal
6882 if (&L)
6883 __ beq(op1, op2, L);
6884 else
6885 __ beq(op1, op2, (int)0);
6886 break;
6887 case 0x02: //not_equal
6888 if (&L)
6889 __ bne(op1, op2, L);
6890 else
6891 __ bne(op1, op2, (int)0);
6892 break;
6893 case 0x03: //above
6894 __ sltu(AT, op2, op1);
6895 if(&L)
6896 __ bne(R0, AT, L);
6897 else
6898 __ bne(R0, AT, (int)0);
6899 break;
6900 case 0x04: //above_equal
6901 __ sltu(AT, op1, op2);
6902 if(&L)
6903 __ beq(AT, R0, L);
6904 else
6905 __ beq(AT, R0, (int)0);
6906 break;
6907 case 0x05: //below
6908 __ sltu(AT, op1, op2);
6909 if(&L)
6910 __ bne(R0, AT, L);
6911 else
6912 __ bne(R0, AT, (int)0);
6913 break;
6914 case 0x06: //below_equal
6915 __ sltu(AT, op2, op1);
6916 if(&L)
6917 __ beq(AT, R0, L);
6918 else
6919 __ beq(AT, R0, (int)0);
6920 break;
6921 default:
6922 Unimplemented();
6923 }
6924 __ nop();
6925 %}
6927 ins_pc_relative(1);
6928 ins_pipe( pipe_alu_branch );
6929 %}
6931 instruct cmpN_null_branch(cmpOp cmp, mRegN op1, immN0 null, label labl) %{
6932 match(If cmp (CmpN op1 null));
6933 effect(USE labl);
6935 ins_cost(180);
6936 format %{ "CMP $op1,0\t! compressed ptr\n\t"
6937 "BP$cmp $labl @ cmpN_null_branch" %}
6938 ins_encode %{
6939 Register op1 = $op1$$Register;
6940 Register op2 = R0;
6941 Label &L = *($labl$$label);
6942 int flag = $cmp$$cmpcode;
6944 switch(flag)
6945 {
6946 case 0x01: //equal
6947 if (&L)
6948 __ beq(op1, op2, L);
6949 else
6950 __ beq(op1, op2, (int)0);
6951 break;
6952 case 0x02: //not_equal
6953 if (&L)
6954 __ bne(op1, op2, L);
6955 else
6956 __ bne(op1, op2, (int)0);
6957 break;
6958 default:
6959 Unimplemented();
6960 }
6961 __ nop();
6962 %}
6963 //TODO: pipe_branchP or create pipe_branchN LEE
6964 ins_pc_relative(1);
6965 ins_pipe( pipe_alu_branch );
6966 %}
6968 instruct cmpN_reg_branch(cmpOp cmp, mRegN op1, mRegN op2, label labl) %{
6969 match(If cmp (CmpN op1 op2));
6970 effect(USE labl);
6972 ins_cost(180);
6973 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
6974 "BP$cmp $labl" %}
6975 ins_encode %{
6976 Register op1_reg = $op1$$Register;
6977 Register op2_reg = $op2$$Register;
6978 Label &L = *($labl$$label);
6979 int flag = $cmp$$cmpcode;
6981 switch(flag)
6982 {
6983 case 0x01: //equal
6984 if (&L)
6985 __ beq(op1_reg, op2_reg, L);
6986 else
6987 __ beq(op1_reg, op2_reg, (int)0);
6988 break;
6989 case 0x02: //not_equal
6990 if (&L)
6991 __ bne(op1_reg, op2_reg, L);
6992 else
6993 __ bne(op1_reg, op2_reg, (int)0);
6994 break;
6995 case 0x03: //above
6996 __ sltu(AT, op2_reg, op1_reg);
6997 if(&L)
6998 __ bne(R0, AT, L);
6999 else
7000 __ bne(R0, AT, (int)0);
7001 break;
7002 case 0x04: //above_equal
7003 __ sltu(AT, op1_reg, op2_reg);
7004 if(&L)
7005 __ beq(AT, R0, L);
7006 else
7007 __ beq(AT, R0, (int)0);
7008 break;
7009 case 0x05: //below
7010 __ sltu(AT, op1_reg, op2_reg);
7011 if(&L)
7012 __ bne(R0, AT, L);
7013 else
7014 __ bne(R0, AT, (int)0);
7015 break;
7016 case 0x06: //below_equal
7017 __ sltu(AT, op2_reg, op1_reg);
7018 if(&L)
7019 __ beq(AT, R0, L);
7020 else
7021 __ beq(AT, R0, (int)0);
7022 break;
7023 default:
7024 Unimplemented();
7025 }
7026 __ nop();
7027 %}
7028 ins_pc_relative(1);
7029 ins_pipe( pipe_alu_branch );
7030 %}
7032 instruct branchConIU_reg_reg(cmpOpU cmp, mRegI src1, mRegI src2, label labl) %{
7033 match( If cmp (CmpU src1 src2) );
7034 effect(USE labl);
7035 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_reg" %}
7037 ins_encode %{
7038 Register op1 = $src1$$Register;
7039 Register op2 = $src2$$Register;
7040 Label &L = *($labl$$label);
7041 int flag = $cmp$$cmpcode;
7043 switch(flag)
7044 {
7045 case 0x01: //equal
7046 if (&L)
7047 __ beq(op1, op2, L);
7048 else
7049 __ beq(op1, op2, (int)0);
7050 break;
7051 case 0x02: //not_equal
7052 if (&L)
7053 __ bne(op1, op2, L);
7054 else
7055 __ bne(op1, op2, (int)0);
7056 break;
7057 case 0x03: //above
7058 __ sltu(AT, op2, op1);
7059 if(&L)
7060 __ bne(AT, R0, L);
7061 else
7062 __ bne(AT, R0, (int)0);
7063 break;
7064 case 0x04: //above_equal
7065 __ sltu(AT, op1, op2);
7066 if(&L)
7067 __ beq(AT, R0, L);
7068 else
7069 __ beq(AT, R0, (int)0);
7070 break;
7071 case 0x05: //below
7072 __ sltu(AT, op1, op2);
7073 if(&L)
7074 __ bne(AT, R0, L);
7075 else
7076 __ bne(AT, R0, (int)0);
7077 break;
7078 case 0x06: //below_equal
7079 __ sltu(AT, op2, op1);
7080 if(&L)
7081 __ beq(AT, R0, L);
7082 else
7083 __ beq(AT, R0, (int)0);
7084 break;
7085 default:
7086 Unimplemented();
7087 }
7088 __ nop();
7089 %}
7091 ins_pc_relative(1);
7092 ins_pipe( pipe_alu_branch );
7093 %}
7096 instruct branchConIU_reg_imm(cmpOpU cmp, mRegI src1, immI src2, label labl) %{
7097 match( If cmp (CmpU src1 src2) );
7098 effect(USE labl);
7099 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_imm" %}
7101 ins_encode %{
7102 Register op1 = $src1$$Register;
7103 int val = $src2$$constant;
7104 Label &L = *($labl$$label);
7105 int flag = $cmp$$cmpcode;
7107 __ move(AT, val);
7108 switch(flag)
7109 {
7110 case 0x01: //equal
7111 if (&L)
7112 __ beq(op1, AT, L);
7113 else
7114 __ beq(op1, AT, (int)0);
7115 break;
7116 case 0x02: //not_equal
7117 if (&L)
7118 __ bne(op1, AT, L);
7119 else
7120 __ bne(op1, AT, (int)0);
7121 break;
7122 case 0x03: //above
7123 __ sltu(AT, AT, op1);
7124 if(&L)
7125 __ bne(R0, AT, L);
7126 else
7127 __ bne(R0, AT, (int)0);
7128 break;
7129 case 0x04: //above_equal
7130 __ sltu(AT, op1, AT);
7131 if(&L)
7132 __ beq(AT, R0, L);
7133 else
7134 __ beq(AT, R0, (int)0);
7135 break;
7136 case 0x05: //below
7137 __ sltu(AT, op1, AT);
7138 if(&L)
7139 __ bne(R0, AT, L);
7140 else
7141 __ bne(R0, AT, (int)0);
7142 break;
7143 case 0x06: //below_equal
7144 __ sltu(AT, AT, op1);
7145 if(&L)
7146 __ beq(AT, R0, L);
7147 else
7148 __ beq(AT, R0, (int)0);
7149 break;
7150 default:
7151 Unimplemented();
7152 }
7153 __ nop();
7154 %}
7156 ins_pc_relative(1);
7157 ins_pipe( pipe_alu_branch );
7158 %}
7160 instruct branchConI_reg_reg(cmpOp cmp, mRegI src1, mRegI src2, label labl) %{
7161 match( If cmp (CmpI src1 src2) );
7162 effect(USE labl);
7163 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_reg" %}
7165 ins_encode %{
7166 Register op1 = $src1$$Register;
7167 Register op2 = $src2$$Register;
7168 Label &L = *($labl$$label);
7169 int flag = $cmp$$cmpcode;
7171 switch(flag)
7172 {
7173 case 0x01: //equal
7174 if (&L)
7175 __ beq(op1, op2, L);
7176 else
7177 __ beq(op1, op2, (int)0);
7178 break;
7179 case 0x02: //not_equal
7180 if (&L)
7181 __ bne(op1, op2, L);
7182 else
7183 __ bne(op1, op2, (int)0);
7184 break;
7185 case 0x03: //above
7186 __ slt(AT, op2, op1);
7187 if(&L)
7188 __ bne(R0, AT, L);
7189 else
7190 __ bne(R0, AT, (int)0);
7191 break;
7192 case 0x04: //above_equal
7193 __ slt(AT, op1, op2);
7194 if(&L)
7195 __ beq(AT, R0, L);
7196 else
7197 __ beq(AT, R0, (int)0);
7198 break;
7199 case 0x05: //below
7200 __ slt(AT, op1, op2);
7201 if(&L)
7202 __ bne(R0, AT, L);
7203 else
7204 __ bne(R0, AT, (int)0);
7205 break;
7206 case 0x06: //below_equal
7207 __ slt(AT, op2, op1);
7208 if(&L)
7209 __ beq(AT, R0, L);
7210 else
7211 __ beq(AT, R0, (int)0);
7212 break;
7213 default:
7214 Unimplemented();
7215 }
7216 __ nop();
7217 %}
7219 ins_pc_relative(1);
7220 ins_pipe( pipe_alu_branch );
7221 %}
7223 instruct branchConI_reg_imm0(cmpOp cmp, mRegI src1, immI0 src2, label labl) %{
7224 match( If cmp (CmpI src1 src2) );
7225 effect(USE labl);
7226 ins_cost(170);
7227 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm0" %}
7229 ins_encode %{
7230 Register op1 = $src1$$Register;
7231 // int val = $src2$$constant;
7232 Label &L = *($labl$$label);
7233 int flag = $cmp$$cmpcode;
7235 //__ move(AT, val);
7236 switch(flag)
7237 {
7238 case 0x01: //equal
7239 if (&L)
7240 __ beq(op1, R0, L);
7241 else
7242 __ beq(op1, R0, (int)0);
7243 break;
7244 case 0x02: //not_equal
7245 if (&L)
7246 __ bne(op1, R0, L);
7247 else
7248 __ bne(op1, R0, (int)0);
7249 break;
7250 case 0x03: //greater
7251 if(&L)
7252 __ bgtz(op1, L);
7253 else
7254 __ bgtz(op1, (int)0);
7255 break;
7256 case 0x04: //greater_equal
7257 if(&L)
7258 __ bgez(op1, L);
7259 else
7260 __ bgez(op1, (int)0);
7261 break;
7262 case 0x05: //less
7263 if(&L)
7264 __ bltz(op1, L);
7265 else
7266 __ bltz(op1, (int)0);
7267 break;
7268 case 0x06: //less_equal
7269 if(&L)
7270 __ blez(op1, L);
7271 else
7272 __ blez(op1, (int)0);
7273 break;
7274 default:
7275 Unimplemented();
7276 }
7277 __ nop();
7278 %}
7280 ins_pc_relative(1);
7281 ins_pipe( pipe_alu_branch );
7282 %}
7285 instruct branchConI_reg_imm(cmpOp cmp, mRegI src1, immI src2, label labl) %{
7286 match( If cmp (CmpI src1 src2) );
7287 effect(USE labl);
7288 ins_cost(200);
7289 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm" %}
7291 ins_encode %{
7292 Register op1 = $src1$$Register;
7293 int val = $src2$$constant;
7294 Label &L = *($labl$$label);
7295 int flag = $cmp$$cmpcode;
7297 __ move(AT, val);
7298 switch(flag)
7299 {
7300 case 0x01: //equal
7301 if (&L)
7302 __ beq(op1, AT, L);
7303 else
7304 __ beq(op1, AT, (int)0);
7305 break;
7306 case 0x02: //not_equal
7307 if (&L)
7308 __ bne(op1, AT, L);
7309 else
7310 __ bne(op1, AT, (int)0);
7311 break;
7312 case 0x03: //greater
7313 __ slt(AT, AT, op1);
7314 if(&L)
7315 __ bne(R0, AT, L);
7316 else
7317 __ bne(R0, AT, (int)0);
7318 break;
7319 case 0x04: //greater_equal
7320 __ slt(AT, op1, AT);
7321 if(&L)
7322 __ beq(AT, R0, L);
7323 else
7324 __ beq(AT, R0, (int)0);
7325 break;
7326 case 0x05: //less
7327 __ slt(AT, op1, AT);
7328 if(&L)
7329 __ bne(R0, AT, L);
7330 else
7331 __ bne(R0, AT, (int)0);
7332 break;
7333 case 0x06: //less_equal
7334 __ slt(AT, AT, op1);
7335 if(&L)
7336 __ beq(AT, R0, L);
7337 else
7338 __ beq(AT, R0, (int)0);
7339 break;
7340 default:
7341 Unimplemented();
7342 }
7343 __ nop();
7344 %}
7346 ins_pc_relative(1);
7347 ins_pipe( pipe_alu_branch );
7348 %}
7350 instruct branchConIU_reg_imm0(cmpOpU cmp, mRegI src1, immI0 zero, label labl) %{
7351 match( If cmp (CmpU src1 zero) );
7352 effect(USE labl);
7353 format %{ "BR$cmp $src1, zero, $labl #@branchConIU_reg_imm0" %}
7355 ins_encode %{
7356 Register op1 = $src1$$Register;
7357 Label &L = *($labl$$label);
7358 int flag = $cmp$$cmpcode;
7360 switch(flag)
7361 {
7362 case 0x01: //equal
7363 if (&L)
7364 __ beq(op1, R0, L);
7365 else
7366 __ beq(op1, R0, (int)0);
7367 break;
7368 case 0x02: //not_equal
7369 if (&L)
7370 __ bne(op1, R0, L);
7371 else
7372 __ bne(op1, R0, (int)0);
7373 break;
7374 case 0x03: //above
7375 if(&L)
7376 __ bne(R0, op1, L);
7377 else
7378 __ bne(R0, op1, (int)0);
7379 break;
7380 case 0x04: //above_equal
7381 if(&L)
7382 __ beq(R0, R0, L);
7383 else
7384 __ beq(R0, R0, (int)0);
7385 break;
7386 case 0x05: //below
7387 return;
7388 break;
7389 case 0x06: //below_equal
7390 if(&L)
7391 __ beq(op1, R0, L);
7392 else
7393 __ beq(op1, R0, (int)0);
7394 break;
7395 default:
7396 Unimplemented();
7397 }
7398 __ nop();
7399 %}
7401 ins_pc_relative(1);
7402 ins_pipe( pipe_alu_branch );
7403 %}
7406 instruct branchConIU_reg_immI16(cmpOpU cmp, mRegI src1, immI16 src2, label labl) %{
7407 match( If cmp (CmpU src1 src2) );
7408 effect(USE labl);
7409 ins_cost(180);
7410 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_immI16" %}
7412 ins_encode %{
7413 Register op1 = $src1$$Register;
7414 int val = $src2$$constant;
7415 Label &L = *($labl$$label);
7416 int flag = $cmp$$cmpcode;
7418 switch(flag)
7419 {
7420 case 0x01: //equal
7421 __ move(AT, val);
7422 if (&L)
7423 __ beq(op1, AT, L);
7424 else
7425 __ beq(op1, AT, (int)0);
7426 break;
7427 case 0x02: //not_equal
7428 __ move(AT, val);
7429 if (&L)
7430 __ bne(op1, AT, L);
7431 else
7432 __ bne(op1, AT, (int)0);
7433 break;
7434 case 0x03: //above
7435 __ move(AT, val);
7436 __ sltu(AT, AT, op1);
7437 if(&L)
7438 __ bne(R0, AT, L);
7439 else
7440 __ bne(R0, AT, (int)0);
7441 break;
7442 case 0x04: //above_equal
7443 __ sltiu(AT, op1, val);
7444 if(&L)
7445 __ beq(AT, R0, L);
7446 else
7447 __ beq(AT, R0, (int)0);
7448 break;
7449 case 0x05: //below
7450 __ sltiu(AT, op1, val);
7451 if(&L)
7452 __ bne(R0, AT, L);
7453 else
7454 __ bne(R0, AT, (int)0);
7455 break;
7456 case 0x06: //below_equal
7457 __ move(AT, val);
7458 __ sltu(AT, AT, op1);
7459 if(&L)
7460 __ beq(AT, R0, L);
7461 else
7462 __ beq(AT, R0, (int)0);
7463 break;
7464 default:
7465 Unimplemented();
7466 }
7467 __ nop();
7468 %}
7470 ins_pc_relative(1);
7471 ins_pipe( pipe_alu_branch );
7472 %}
7475 instruct branchConL_regL_regL(cmpOp cmp, mRegL src1, mRegL src2, label labl) %{
7476 match( If cmp (CmpL src1 src2) );
7477 effect(USE labl);
7478 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_regL_regL" %}
7479 ins_cost(250);
7481 ins_encode %{
7482 Register opr1_reg = as_Register($src1$$reg);
7483 Register opr2_reg = as_Register($src2$$reg);
7485 Label &target = *($labl$$label);
7486 int flag = $cmp$$cmpcode;
7488 switch(flag)
7489 {
7490 case 0x01: //equal
7491 if (&target)
7492 __ beq(opr1_reg, opr2_reg, target);
7493 else
7494 __ beq(opr1_reg, opr2_reg, (int)0);
7495 __ delayed()->nop();
7496 break;
7498 case 0x02: //not_equal
7499 if(&target)
7500 __ bne(opr1_reg, opr2_reg, target);
7501 else
7502 __ bne(opr1_reg, opr2_reg, (int)0);
7503 __ delayed()->nop();
7504 break;
7506 case 0x03: //greater
7507 __ slt(AT, opr2_reg, opr1_reg);
7508 if(&target)
7509 __ bne(AT, R0, target);
7510 else
7511 __ bne(AT, R0, (int)0);
7512 __ delayed()->nop();
7513 break;
7515 case 0x04: //greater_equal
7516 __ slt(AT, opr1_reg, opr2_reg);
7517 if(&target)
7518 __ beq(AT, R0, target);
7519 else
7520 __ beq(AT, R0, (int)0);
7521 __ delayed()->nop();
7523 break;
7525 case 0x05: //less
7526 __ slt(AT, opr1_reg, opr2_reg);
7527 if(&target)
7528 __ bne(AT, R0, target);
7529 else
7530 __ bne(AT, R0, (int)0);
7531 __ delayed()->nop();
7533 break;
7535 case 0x06: //less_equal
7536 __ slt(AT, opr2_reg, opr1_reg);
7538 if(&target)
7539 __ beq(AT, R0, target);
7540 else
7541 __ beq(AT, R0, (int)0);
7542 __ delayed()->nop();
7544 break;
7546 default:
7547 Unimplemented();
7548 }
7549 %}
7552 ins_pc_relative(1);
7553 ins_pipe( pipe_alu_branch );
7554 %}
7556 instruct branchConL_reg_immL16_sub(cmpOp cmp, mRegL src1, immL16_sub src2, label labl) %{
7557 match( If cmp (CmpL src1 src2) );
7558 effect(USE labl);
7559 ins_cost(180);
7560 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_reg_immL16_sub" %}
7562 ins_encode %{
7563 Register op1 = $src1$$Register;
7564 int val = $src2$$constant;
7565 Label &L = *($labl$$label);
7566 int flag = $cmp$$cmpcode;
7568 __ daddiu(AT, op1, -1 * val);
7569 switch(flag)
7570 {
7571 case 0x01: //equal
7572 if (&L)
7573 __ beq(R0, AT, L);
7574 else
7575 __ beq(R0, AT, (int)0);
7576 break;
7577 case 0x02: //not_equal
7578 if (&L)
7579 __ bne(R0, AT, L);
7580 else
7581 __ bne(R0, AT, (int)0);
7582 break;
7583 case 0x03: //greater
7584 if(&L)
7585 __ bgtz(AT, L);
7586 else
7587 __ bgtz(AT, (int)0);
7588 break;
7589 case 0x04: //greater_equal
7590 if(&L)
7591 __ bgez(AT, L);
7592 else
7593 __ bgez(AT, (int)0);
7594 break;
7595 case 0x05: //less
7596 if(&L)
7597 __ bltz(AT, L);
7598 else
7599 __ bltz(AT, (int)0);
7600 break;
7601 case 0x06: //less_equal
7602 if(&L)
7603 __ blez(AT, L);
7604 else
7605 __ blez(AT, (int)0);
7606 break;
7607 default:
7608 Unimplemented();
7609 }
7610 __ nop();
7611 %}
7613 ins_pc_relative(1);
7614 ins_pipe( pipe_alu_branch );
7615 %}
7618 instruct branchConI_reg_imm16_sub(cmpOp cmp, mRegI src1, immI16_sub src2, label labl) %{
7619 match( If cmp (CmpI src1 src2) );
7620 effect(USE labl);
7621 ins_cost(180);
7622 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm16_sub" %}
7624 ins_encode %{
7625 Register op1 = $src1$$Register;
7626 int val = $src2$$constant;
7627 Label &L = *($labl$$label);
7628 int flag = $cmp$$cmpcode;
7630 __ addiu32(AT, op1, -1 * val);
7631 switch(flag)
7632 {
7633 case 0x01: //equal
7634 if (&L)
7635 __ beq(R0, AT, L);
7636 else
7637 __ beq(R0, AT, (int)0);
7638 break;
7639 case 0x02: //not_equal
7640 if (&L)
7641 __ bne(R0, AT, L);
7642 else
7643 __ bne(R0, AT, (int)0);
7644 break;
7645 case 0x03: //greater
7646 if(&L)
7647 __ bgtz(AT, L);
7648 else
7649 __ bgtz(AT, (int)0);
7650 break;
7651 case 0x04: //greater_equal
7652 if(&L)
7653 __ bgez(AT, L);
7654 else
7655 __ bgez(AT, (int)0);
7656 break;
7657 case 0x05: //less
7658 if(&L)
7659 __ bltz(AT, L);
7660 else
7661 __ bltz(AT, (int)0);
7662 break;
7663 case 0x06: //less_equal
7664 if(&L)
7665 __ blez(AT, L);
7666 else
7667 __ blez(AT, (int)0);
7668 break;
7669 default:
7670 Unimplemented();
7671 }
7672 __ nop();
7673 %}
7675 ins_pc_relative(1);
7676 ins_pipe( pipe_alu_branch );
7677 %}
7679 instruct branchConL_regL_immL0(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{
7680 match( If cmp (CmpL src1 zero) );
7681 effect(USE labl);
7682 format %{ "BR$cmp $src1, zero, $labl #@branchConL_regL_immL0" %}
7683 ins_cost(150);
7685 ins_encode %{
7686 Register opr1_reg = as_Register($src1$$reg);
7687 Label &target = *($labl$$label);
7688 int flag = $cmp$$cmpcode;
7690 switch(flag)
7691 {
7692 case 0x01: //equal
7693 if (&target)
7694 __ beq(opr1_reg, R0, target);
7695 else
7696 __ beq(opr1_reg, R0, int(0));
7697 break;
7699 case 0x02: //not_equal
7700 if(&target)
7701 __ bne(opr1_reg, R0, target);
7702 else
7703 __ bne(opr1_reg, R0, (int)0);
7704 break;
7706 case 0x03: //greater
7707 if(&target)
7708 __ bgtz(opr1_reg, target);
7709 else
7710 __ bgtz(opr1_reg, (int)0);
7711 break;
7713 case 0x04: //greater_equal
7714 if(&target)
7715 __ bgez(opr1_reg, target);
7716 else
7717 __ bgez(opr1_reg, (int)0);
7718 break;
7720 case 0x05: //less
7721 __ slt(AT, opr1_reg, R0);
7722 if(&target)
7723 __ bne(AT, R0, target);
7724 else
7725 __ bne(AT, R0, (int)0);
7726 break;
7728 case 0x06: //less_equal
7729 if (&target)
7730 __ blez(opr1_reg, target);
7731 else
7732 __ blez(opr1_reg, int(0));
7733 break;
7735 default:
7736 Unimplemented();
7737 }
7738 __ delayed()->nop();
7739 %}
7742 ins_pc_relative(1);
7743 ins_pipe( pipe_alu_branch );
7744 %}
7747 //FIXME
7748 instruct branchConF_reg_reg(cmpOp cmp, regF src1, regF src2, label labl) %{
7749 match( If cmp (CmpF src1 src2) );
7750 effect(USE labl);
7751 format %{ "BR$cmp $src1, $src2, $labl #@branchConF_reg_reg" %}
7753 ins_encode %{
7754 FloatRegister reg_op1 = $src1$$FloatRegister;
7755 FloatRegister reg_op2 = $src2$$FloatRegister;
7756 Label &L = *($labl$$label);
7757 int flag = $cmp$$cmpcode;
7759 switch(flag)
7760 {
7761 case 0x01: //equal
7762 __ c_eq_s(reg_op1, reg_op2);
7763 if (&L)
7764 __ bc1t(L);
7765 else
7766 __ bc1t((int)0);
7767 break;
7768 case 0x02: //not_equal
7769 __ c_eq_s(reg_op1, reg_op2);
7770 if (&L)
7771 __ bc1f(L);
7772 else
7773 __ bc1f((int)0);
7774 break;
7775 case 0x03: //greater
7776 __ c_ule_s(reg_op1, reg_op2);
7777 if(&L)
7778 __ bc1f(L);
7779 else
7780 __ bc1f((int)0);
7781 break;
7782 case 0x04: //greater_equal
7783 __ c_ult_s(reg_op1, reg_op2);
7784 if(&L)
7785 __ bc1f(L);
7786 else
7787 __ bc1f((int)0);
7788 break;
7789 case 0x05: //less
7790 __ c_ult_s(reg_op1, reg_op2);
7791 if(&L)
7792 __ bc1t(L);
7793 else
7794 __ bc1t((int)0);
7795 break;
7796 case 0x06: //less_equal
7797 __ c_ule_s(reg_op1, reg_op2);
7798 if(&L)
7799 __ bc1t(L);
7800 else
7801 __ bc1t((int)0);
7802 break;
7803 default:
7804 Unimplemented();
7805 }
7806 __ nop();
7807 %}
7809 ins_pc_relative(1);
7810 ins_pipe(pipe_slow);
7811 %}
7813 instruct branchConD_reg_reg(cmpOp cmp, regD src1, regD src2, label labl) %{
7814 match( If cmp (CmpD src1 src2) );
7815 effect(USE labl);
7816 format %{ "BR$cmp $src1, $src2, $labl #@branchConD_reg_reg" %}
7818 ins_encode %{
7819 FloatRegister reg_op1 = $src1$$FloatRegister;
7820 FloatRegister reg_op2 = $src2$$FloatRegister;
7821 Label &L = *($labl$$label);
7822 int flag = $cmp$$cmpcode;
7824 switch(flag)
7825 {
7826 case 0x01: //equal
7827 __ c_eq_d(reg_op1, reg_op2);
7828 if (&L)
7829 __ bc1t(L);
7830 else
7831 __ bc1t((int)0);
7832 break;
7833 case 0x02: //not_equal
7834 //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
7835 __ c_eq_d(reg_op1, reg_op2);
7836 if (&L)
7837 __ bc1f(L);
7838 else
7839 __ bc1f((int)0);
7840 break;
7841 case 0x03: //greater
7842 __ c_ule_d(reg_op1, reg_op2);
7843 if(&L)
7844 __ bc1f(L);
7845 else
7846 __ bc1f((int)0);
7847 break;
7848 case 0x04: //greater_equal
7849 __ c_ult_d(reg_op1, reg_op2);
7850 if(&L)
7851 __ bc1f(L);
7852 else
7853 __ bc1f((int)0);
7854 break;
7855 case 0x05: //less
7856 __ c_ult_d(reg_op1, reg_op2);
7857 if(&L)
7858 __ bc1t(L);
7859 else
7860 __ bc1t((int)0);
7861 break;
7862 case 0x06: //less_equal
7863 __ c_ule_d(reg_op1, reg_op2);
7864 if(&L)
7865 __ bc1t(L);
7866 else
7867 __ bc1t((int)0);
7868 break;
7869 default:
7870 Unimplemented();
7871 }
7872 __ nop();
7873 %}
7875 ins_pc_relative(1);
7876 ins_pipe(pipe_slow);
7877 %}
7880 // Call Runtime Instruction
7881 instruct CallRuntimeDirect(method meth) %{
7882 match(CallRuntime );
7883 effect(USE meth);
7885 ins_cost(300);
7886 format %{ "CALL,runtime #@CallRuntimeDirect" %}
7887 ins_encode( Java_To_Runtime( meth ) );
7888 ins_pipe( pipe_slow );
7889 ins_alignment(16);
7890 %}
7894 //------------------------MemBar Instructions-------------------------------
7895 //Memory barrier flavors
7897 instruct membar_acquire() %{
7898 match(MemBarAcquire);
7899 ins_cost(0);
7901 size(0);
7902 format %{ "MEMBAR-acquire (empty) @ membar_acquire" %}
7903 ins_encode();
7904 ins_pipe(empty);
7905 %}
7907 instruct load_fence() %{
7908 match(LoadFence);
7909 ins_cost(400);
7911 format %{ "MEMBAR @ load_fence" %}
7912 ins_encode %{
7913 __ sync();
7914 %}
7915 ins_pipe(pipe_slow);
7916 %}
7918 instruct membar_acquire_lock()
7919 %{
7920 match(MemBarAcquireLock);
7921 ins_cost(0);
7923 size(0);
7924 format %{ "MEMBAR-acquire (acquire as part of CAS in prior FastLock so empty encoding) @ membar_acquire_lock" %}
7925 ins_encode();
7926 ins_pipe(empty);
7927 %}
7929 instruct membar_release() %{
7930 match(MemBarRelease);
7931 ins_cost(0);
7933 size(0);
7934 format %{ "MEMBAR-release (empty) @ membar_release" %}
7935 ins_encode();
7936 ins_pipe(empty);
7937 %}
7939 instruct store_fence() %{
7940 match(StoreFence);
7941 ins_cost(400);
7943 format %{ "MEMBAR @ store_fence" %}
7945 ins_encode %{
7946 __ sync();
7947 %}
7949 ins_pipe(pipe_slow);
7950 %}
7952 instruct membar_release_lock()
7953 %{
7954 match(MemBarReleaseLock);
7955 ins_cost(0);
7957 size(0);
7958 format %{ "MEMBAR-release-lock (release in FastUnlock so empty) @ membar_release_lock" %}
7959 ins_encode();
7960 ins_pipe(empty);
7961 %}
7964 instruct membar_volatile() %{
7965 match(MemBarVolatile);
7966 ins_cost(400);
7968 format %{ "MEMBAR-volatile" %}
7969 ins_encode %{
7970 if( !os::is_MP() ) return; // Not needed on single CPU
7971 __ sync();
7973 %}
7974 ins_pipe(pipe_slow);
7975 %}
7977 instruct unnecessary_membar_volatile() %{
7978 match(MemBarVolatile);
7979 predicate(Matcher::post_store_load_barrier(n));
7980 ins_cost(0);
7982 size(0);
7983 format %{ "MEMBAR-volatile (unnecessary so empty encoding) @ unnecessary_membar_volatile" %}
7984 ins_encode( );
7985 ins_pipe(empty);
7986 %}
7988 instruct membar_storestore() %{
7989 match(MemBarStoreStore);
7991 ins_cost(0);
7992 size(0);
7993 format %{ "MEMBAR-storestore (empty encoding) @ membar_storestore" %}
7994 ins_encode( );
7995 ins_pipe(empty);
7996 %}
7998 //----------Move Instructions--------------------------------------------------
7999 instruct castX2P(mRegP dst, mRegL src) %{
8000 match(Set dst (CastX2P src));
8001 format %{ "castX2P $dst, $src @ castX2P" %}
8002 ins_encode %{
8003 Register src = $src$$Register;
8004 Register dst = $dst$$Register;
8006 if(src != dst)
8007 __ move(dst, src);
8008 %}
8009 ins_cost(10);
8010 ins_pipe( ialu_regI_mov );
8011 %}
8013 instruct castP2X(mRegL dst, mRegP src ) %{
8014 match(Set dst (CastP2X src));
8016 format %{ "mov $dst, $src\t #@castP2X" %}
8017 ins_encode %{
8018 Register src = $src$$Register;
8019 Register dst = $dst$$Register;
8021 if(src != dst)
8022 __ move(dst, src);
8023 %}
8024 ins_pipe( ialu_regI_mov );
8025 %}
8027 instruct MoveF2I_reg_reg(mRegI dst, regF src) %{
8028 match(Set dst (MoveF2I src));
8029 effect(DEF dst, USE src);
8030 ins_cost(85);
8031 format %{ "MoveF2I $dst, $src @ MoveF2I_reg_reg" %}
8032 ins_encode %{
8033 Register dst = as_Register($dst$$reg);
8034 FloatRegister src = as_FloatRegister($src$$reg);
8036 __ mfc1(dst, src);
8037 %}
8038 ins_pipe( pipe_slow );
8039 %}
8041 instruct MoveI2F_reg_reg(regF dst, mRegI src) %{
8042 match(Set dst (MoveI2F src));
8043 effect(DEF dst, USE src);
8044 ins_cost(85);
8045 format %{ "MoveI2F $dst, $src @ MoveI2F_reg_reg" %}
8046 ins_encode %{
8047 Register src = as_Register($src$$reg);
8048 FloatRegister dst = as_FloatRegister($dst$$reg);
8050 __ mtc1(src, dst);
8051 %}
8052 ins_pipe( pipe_slow );
8053 %}
8055 instruct MoveD2L_reg_reg(mRegL dst, regD src) %{
8056 match(Set dst (MoveD2L src));
8057 effect(DEF dst, USE src);
8058 ins_cost(85);
8059 format %{ "MoveD2L $dst, $src @ MoveD2L_reg_reg" %}
8060 ins_encode %{
8061 Register dst = as_Register($dst$$reg);
8062 FloatRegister src = as_FloatRegister($src$$reg);
8064 __ dmfc1(dst, src);
8065 %}
8066 ins_pipe( pipe_slow );
8067 %}
8069 instruct MoveL2D_reg_reg(regD dst, mRegL src) %{
8070 match(Set dst (MoveL2D src));
8071 effect(DEF dst, USE src);
8072 ins_cost(85);
8073 format %{ "MoveL2D $dst, $src @ MoveL2D_reg_reg" %}
8074 ins_encode %{
8075 FloatRegister dst = as_FloatRegister($dst$$reg);
8076 Register src = as_Register($src$$reg);
8078 __ dmtc1(src, dst);
8079 %}
8080 ins_pipe( pipe_slow );
8081 %}
8083 //----------Conditional Move---------------------------------------------------
8084 // Conditional move
8085 instruct cmovI_cmpI_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8086 match(Set dst (CMoveI (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8087 ins_cost(80);
8088 format %{
8089 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpI_reg_reg\n"
8090 "\tCMOV $dst,$src \t @cmovI_cmpI_reg_reg"
8091 %}
8093 ins_encode %{
8094 Register op1 = $tmp1$$Register;
8095 Register op2 = $tmp2$$Register;
8096 Register dst = $dst$$Register;
8097 Register src = $src$$Register;
8098 int flag = $cop$$cmpcode;
8100 switch(flag)
8101 {
8102 case 0x01: //equal
8103 __ subu32(AT, op1, op2);
8104 __ movz(dst, src, AT);
8105 break;
8107 case 0x02: //not_equal
8108 __ subu32(AT, op1, op2);
8109 __ movn(dst, src, AT);
8110 break;
8112 case 0x03: //great
8113 __ slt(AT, op2, op1);
8114 __ movn(dst, src, AT);
8115 break;
8117 case 0x04: //great_equal
8118 __ slt(AT, op1, op2);
8119 __ movz(dst, src, AT);
8120 break;
8122 case 0x05: //less
8123 __ slt(AT, op1, op2);
8124 __ movn(dst, src, AT);
8125 break;
8127 case 0x06: //less_equal
8128 __ slt(AT, op2, op1);
8129 __ movz(dst, src, AT);
8130 break;
8132 default:
8133 Unimplemented();
8134 }
8135 %}
8137 ins_pipe( pipe_slow );
8138 %}
8140 instruct cmovI_cmpP_reg_reg(mRegI dst, mRegI src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8141 match(Set dst (CMoveI (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8142 ins_cost(80);
8143 format %{
8144 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpP_reg_reg\n\t"
8145 "CMOV $dst,$src\t @cmovI_cmpP_reg_reg"
8146 %}
8147 ins_encode %{
8148 Register op1 = $tmp1$$Register;
8149 Register op2 = $tmp2$$Register;
8150 Register dst = $dst$$Register;
8151 Register src = $src$$Register;
8152 int flag = $cop$$cmpcode;
8154 switch(flag)
8155 {
8156 case 0x01: //equal
8157 __ subu(AT, op1, op2);
8158 __ movz(dst, src, AT);
8159 break;
8161 case 0x02: //not_equal
8162 __ subu(AT, op1, op2);
8163 __ movn(dst, src, AT);
8164 break;
8166 case 0x03: //above
8167 __ sltu(AT, op2, op1);
8168 __ movn(dst, src, AT);
8169 break;
8171 case 0x04: //above_equal
8172 __ sltu(AT, op1, op2);
8173 __ movz(dst, src, AT);
8174 break;
8176 case 0x05: //below
8177 __ sltu(AT, op1, op2);
8178 __ movn(dst, src, AT);
8179 break;
8181 case 0x06: //below_equal
8182 __ sltu(AT, op2, op1);
8183 __ movz(dst, src, AT);
8184 break;
8186 default:
8187 Unimplemented();
8188 }
8189 %}
8191 ins_pipe( pipe_slow );
8192 %}
8194 instruct cmovI_cmpN_reg_reg(mRegI dst, mRegI src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8195 match(Set dst (CMoveI (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8196 ins_cost(80);
8197 format %{
8198 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpN_reg_reg\n\t"
8199 "CMOV $dst,$src\t @cmovI_cmpN_reg_reg"
8200 %}
8201 ins_encode %{
8202 Register op1 = $tmp1$$Register;
8203 Register op2 = $tmp2$$Register;
8204 Register dst = $dst$$Register;
8205 Register src = $src$$Register;
8206 int flag = $cop$$cmpcode;
8208 switch(flag)
8209 {
8210 case 0x01: //equal
8211 __ subu32(AT, op1, op2);
8212 __ movz(dst, src, AT);
8213 break;
8215 case 0x02: //not_equal
8216 __ subu32(AT, op1, op2);
8217 __ movn(dst, src, AT);
8218 break;
8220 case 0x03: //above
8221 __ sltu(AT, op2, op1);
8222 __ movn(dst, src, AT);
8223 break;
8225 case 0x04: //above_equal
8226 __ sltu(AT, op1, op2);
8227 __ movz(dst, src, AT);
8228 break;
8230 case 0x05: //below
8231 __ sltu(AT, op1, op2);
8232 __ movn(dst, src, AT);
8233 break;
8235 case 0x06: //below_equal
8236 __ sltu(AT, op2, op1);
8237 __ movz(dst, src, AT);
8238 break;
8240 default:
8241 Unimplemented();
8242 }
8243 %}
8245 ins_pipe( pipe_slow );
8246 %}
8248 instruct cmovP_cmpN_reg_reg(mRegP dst, mRegP src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8249 match(Set dst (CMoveP (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8250 ins_cost(80);
8251 format %{
8252 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpN_reg_reg\n\t"
8253 "CMOV $dst,$src\t @cmovP_cmpN_reg_reg"
8254 %}
8255 ins_encode %{
8256 Register op1 = $tmp1$$Register;
8257 Register op2 = $tmp2$$Register;
8258 Register dst = $dst$$Register;
8259 Register src = $src$$Register;
8260 int flag = $cop$$cmpcode;
8262 switch(flag)
8263 {
8264 case 0x01: //equal
8265 __ subu32(AT, op1, op2);
8266 __ movz(dst, src, AT);
8267 break;
8269 case 0x02: //not_equal
8270 __ subu32(AT, op1, op2);
8271 __ movn(dst, src, AT);
8272 break;
8274 case 0x03: //above
8275 __ sltu(AT, op2, op1);
8276 __ movn(dst, src, AT);
8277 break;
8279 case 0x04: //above_equal
8280 __ sltu(AT, op1, op2);
8281 __ movz(dst, src, AT);
8282 break;
8284 case 0x05: //below
8285 __ sltu(AT, op1, op2);
8286 __ movn(dst, src, AT);
8287 break;
8289 case 0x06: //below_equal
8290 __ sltu(AT, op2, op1);
8291 __ movz(dst, src, AT);
8292 break;
8294 default:
8295 Unimplemented();
8296 }
8297 %}
8299 ins_pipe( pipe_slow );
8300 %}
8302 instruct cmovN_cmpP_reg_reg(mRegN dst, mRegN src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8303 match(Set dst (CMoveN (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8304 ins_cost(80);
8305 format %{
8306 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpP_reg_reg\n\t"
8307 "CMOV $dst,$src\t @cmovN_cmpP_reg_reg"
8308 %}
8309 ins_encode %{
8310 Register op1 = $tmp1$$Register;
8311 Register op2 = $tmp2$$Register;
8312 Register dst = $dst$$Register;
8313 Register src = $src$$Register;
8314 int flag = $cop$$cmpcode;
8316 switch(flag)
8317 {
8318 case 0x01: //equal
8319 __ subu(AT, op1, op2);
8320 __ movz(dst, src, AT);
8321 break;
8323 case 0x02: //not_equal
8324 __ subu(AT, op1, op2);
8325 __ movn(dst, src, AT);
8326 break;
8328 case 0x03: //above
8329 __ sltu(AT, op2, op1);
8330 __ movn(dst, src, AT);
8331 break;
8333 case 0x04: //above_equal
8334 __ sltu(AT, op1, op2);
8335 __ movz(dst, src, AT);
8336 break;
8338 case 0x05: //below
8339 __ sltu(AT, op1, op2);
8340 __ movn(dst, src, AT);
8341 break;
8343 case 0x06: //below_equal
8344 __ sltu(AT, op2, op1);
8345 __ movz(dst, src, AT);
8346 break;
8348 default:
8349 Unimplemented();
8350 }
8351 %}
8353 ins_pipe( pipe_slow );
8354 %}
8356 instruct cmovP_cmpD_reg_reg(mRegP dst, mRegP src, regD tmp1, regD tmp2, cmpOp cop ) %{
8357 match(Set dst (CMoveP (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8358 ins_cost(80);
8359 format %{
8360 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpD_reg_reg\n"
8361 "\tCMOV $dst,$src \t @cmovP_cmpD_reg_reg"
8362 %}
8363 ins_encode %{
8364 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8365 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8366 Register dst = as_Register($dst$$reg);
8367 Register src = as_Register($src$$reg);
8369 int flag = $cop$$cmpcode;
8371 switch(flag)
8372 {
8373 case 0x01: //equal
8374 __ c_eq_d(reg_op1, reg_op2);
8375 __ movt(dst, src);
8376 break;
8377 case 0x02: //not_equal
8378 __ c_eq_d(reg_op1, reg_op2);
8379 __ movf(dst, src);
8380 break;
8381 case 0x03: //greater
8382 __ c_ole_d(reg_op1, reg_op2);
8383 __ movf(dst, src);
8384 break;
8385 case 0x04: //greater_equal
8386 __ c_olt_d(reg_op1, reg_op2);
8387 __ movf(dst, src);
8388 break;
8389 case 0x05: //less
8390 __ c_ult_d(reg_op1, reg_op2);
8391 __ movt(dst, src);
8392 break;
8393 case 0x06: //less_equal
8394 __ c_ule_d(reg_op1, reg_op2);
8395 __ movt(dst, src);
8396 break;
8397 default:
8398 Unimplemented();
8399 }
8400 %}
8402 ins_pipe( pipe_slow );
8403 %}
8406 instruct cmovN_cmpN_reg_reg(mRegN dst, mRegN src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8407 match(Set dst (CMoveN (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8408 ins_cost(80);
8409 format %{
8410 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpN_reg_reg\n\t"
8411 "CMOV $dst,$src\t @cmovN_cmpN_reg_reg"
8412 %}
8413 ins_encode %{
8414 Register op1 = $tmp1$$Register;
8415 Register op2 = $tmp2$$Register;
8416 Register dst = $dst$$Register;
8417 Register src = $src$$Register;
8418 int flag = $cop$$cmpcode;
8420 switch(flag)
8421 {
8422 case 0x01: //equal
8423 __ subu32(AT, op1, op2);
8424 __ movz(dst, src, AT);
8425 break;
8427 case 0x02: //not_equal
8428 __ subu32(AT, op1, op2);
8429 __ movn(dst, src, AT);
8430 break;
8432 case 0x03: //above
8433 __ sltu(AT, op2, op1);
8434 __ movn(dst, src, AT);
8435 break;
8437 case 0x04: //above_equal
8438 __ sltu(AT, op1, op2);
8439 __ movz(dst, src, AT);
8440 break;
8442 case 0x05: //below
8443 __ sltu(AT, op1, op2);
8444 __ movn(dst, src, AT);
8445 break;
8447 case 0x06: //below_equal
8448 __ sltu(AT, op2, op1);
8449 __ movz(dst, src, AT);
8450 break;
8452 default:
8453 Unimplemented();
8454 }
8455 %}
8457 ins_pipe( pipe_slow );
8458 %}
8461 instruct cmovI_cmpU_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{
8462 match(Set dst (CMoveI (Binary cop (CmpU tmp1 tmp2)) (Binary dst src)));
8463 ins_cost(80);
8464 format %{
8465 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpU_reg_reg\n\t"
8466 "CMOV $dst,$src\t @cmovI_cmpU_reg_reg"
8467 %}
8468 ins_encode %{
8469 Register op1 = $tmp1$$Register;
8470 Register op2 = $tmp2$$Register;
8471 Register dst = $dst$$Register;
8472 Register src = $src$$Register;
8473 int flag = $cop$$cmpcode;
8475 switch(flag)
8476 {
8477 case 0x01: //equal
8478 __ subu(AT, op1, op2);
8479 __ movz(dst, src, AT);
8480 break;
8482 case 0x02: //not_equal
8483 __ subu(AT, op1, op2);
8484 __ movn(dst, src, AT);
8485 break;
8487 case 0x03: //above
8488 __ sltu(AT, op2, op1);
8489 __ movn(dst, src, AT);
8490 break;
8492 case 0x04: //above_equal
8493 __ sltu(AT, op1, op2);
8494 __ movz(dst, src, AT);
8495 break;
8497 case 0x05: //below
8498 __ sltu(AT, op1, op2);
8499 __ movn(dst, src, AT);
8500 break;
8502 case 0x06: //below_equal
8503 __ sltu(AT, op2, op1);
8504 __ movz(dst, src, AT);
8505 break;
8507 default:
8508 Unimplemented();
8509 }
8510 %}
8512 ins_pipe( pipe_slow );
8513 %}
8515 instruct cmovI_cmpL_reg_reg(mRegI dst, mRegI src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8516 match(Set dst (CMoveI (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8517 ins_cost(80);
8518 format %{
8519 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpL_reg_reg\n"
8520 "\tCMOV $dst,$src \t @cmovI_cmpL_reg_reg"
8521 %}
8522 ins_encode %{
8523 Register opr1 = as_Register($tmp1$$reg);
8524 Register opr2 = as_Register($tmp2$$reg);
8525 Register dst = $dst$$Register;
8526 Register src = $src$$Register;
8527 int flag = $cop$$cmpcode;
8529 switch(flag)
8530 {
8531 case 0x01: //equal
8532 __ subu(AT, opr1, opr2);
8533 __ movz(dst, src, AT);
8534 break;
8536 case 0x02: //not_equal
8537 __ subu(AT, opr1, opr2);
8538 __ movn(dst, src, AT);
8539 break;
8541 case 0x03: //greater
8542 __ slt(AT, opr2, opr1);
8543 __ movn(dst, src, AT);
8544 break;
8546 case 0x04: //greater_equal
8547 __ slt(AT, opr1, opr2);
8548 __ movz(dst, src, AT);
8549 break;
8551 case 0x05: //less
8552 __ slt(AT, opr1, opr2);
8553 __ movn(dst, src, AT);
8554 break;
8556 case 0x06: //less_equal
8557 __ slt(AT, opr2, opr1);
8558 __ movz(dst, src, AT);
8559 break;
8561 default:
8562 Unimplemented();
8563 }
8564 %}
8566 ins_pipe( pipe_slow );
8567 %}
8569 instruct cmovP_cmpL_reg_reg(mRegP dst, mRegP src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8570 match(Set dst (CMoveP (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8571 ins_cost(80);
8572 format %{
8573 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpL_reg_reg\n"
8574 "\tCMOV $dst,$src \t @cmovP_cmpL_reg_reg"
8575 %}
8576 ins_encode %{
8577 Register opr1 = as_Register($tmp1$$reg);
8578 Register opr2 = as_Register($tmp2$$reg);
8579 Register dst = $dst$$Register;
8580 Register src = $src$$Register;
8581 int flag = $cop$$cmpcode;
8583 switch(flag)
8584 {
8585 case 0x01: //equal
8586 __ subu(AT, opr1, opr2);
8587 __ movz(dst, src, AT);
8588 break;
8590 case 0x02: //not_equal
8591 __ subu(AT, opr1, opr2);
8592 __ movn(dst, src, AT);
8593 break;
8595 case 0x03: //greater
8596 __ slt(AT, opr2, opr1);
8597 __ movn(dst, src, AT);
8598 break;
8600 case 0x04: //greater_equal
8601 __ slt(AT, opr1, opr2);
8602 __ movz(dst, src, AT);
8603 break;
8605 case 0x05: //less
8606 __ slt(AT, opr1, opr2);
8607 __ movn(dst, src, AT);
8608 break;
8610 case 0x06: //less_equal
8611 __ slt(AT, opr2, opr1);
8612 __ movz(dst, src, AT);
8613 break;
8615 default:
8616 Unimplemented();
8617 }
8618 %}
8620 ins_pipe( pipe_slow );
8621 %}
8623 instruct cmovI_cmpD_reg_reg(mRegI dst, mRegI src, regD tmp1, regD tmp2, cmpOp cop ) %{
8624 match(Set dst (CMoveI (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8625 ins_cost(80);
8626 format %{
8627 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpD_reg_reg\n"
8628 "\tCMOV $dst,$src \t @cmovI_cmpD_reg_reg"
8629 %}
8630 ins_encode %{
8631 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8632 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8633 Register dst = as_Register($dst$$reg);
8634 Register src = as_Register($src$$reg);
8636 int flag = $cop$$cmpcode;
8638 switch(flag)
8639 {
8640 case 0x01: //equal
8641 __ c_eq_d(reg_op1, reg_op2);
8642 __ movt(dst, src);
8643 break;
8644 case 0x02: //not_equal
8645 //2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
8646 __ c_eq_d(reg_op1, reg_op2);
8647 __ movf(dst, src);
8648 break;
8649 case 0x03: //greater
8650 __ c_ole_d(reg_op1, reg_op2);
8651 __ movf(dst, src);
8652 break;
8653 case 0x04: //greater_equal
8654 __ c_olt_d(reg_op1, reg_op2);
8655 __ movf(dst, src);
8656 break;
8657 case 0x05: //less
8658 __ c_ult_d(reg_op1, reg_op2);
8659 __ movt(dst, src);
8660 break;
8661 case 0x06: //less_equal
8662 __ c_ule_d(reg_op1, reg_op2);
8663 __ movt(dst, src);
8664 break;
8665 default:
8666 Unimplemented();
8667 }
8668 %}
8670 ins_pipe( pipe_slow );
8671 %}
8674 instruct cmovP_cmpP_reg_reg(mRegP dst, mRegP src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8675 match(Set dst (CMoveP (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8676 ins_cost(80);
8677 format %{
8678 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpP_reg_reg\n\t"
8679 "CMOV $dst,$src\t @cmovP_cmpP_reg_reg"
8680 %}
8681 ins_encode %{
8682 Register op1 = $tmp1$$Register;
8683 Register op2 = $tmp2$$Register;
8684 Register dst = $dst$$Register;
8685 Register src = $src$$Register;
8686 int flag = $cop$$cmpcode;
8688 switch(flag)
8689 {
8690 case 0x01: //equal
8691 __ subu(AT, op1, op2);
8692 __ movz(dst, src, AT);
8693 break;
8695 case 0x02: //not_equal
8696 __ subu(AT, op1, op2);
8697 __ movn(dst, src, AT);
8698 break;
8700 case 0x03: //above
8701 __ sltu(AT, op2, op1);
8702 __ movn(dst, src, AT);
8703 break;
8705 case 0x04: //above_equal
8706 __ sltu(AT, op1, op2);
8707 __ movz(dst, src, AT);
8708 break;
8710 case 0x05: //below
8711 __ sltu(AT, op1, op2);
8712 __ movn(dst, src, AT);
8713 break;
8715 case 0x06: //below_equal
8716 __ sltu(AT, op2, op1);
8717 __ movz(dst, src, AT);
8718 break;
8720 default:
8721 Unimplemented();
8722 }
8723 %}
8725 ins_pipe( pipe_slow );
8726 %}
8728 instruct cmovP_cmpI_reg_reg(mRegP dst, mRegP src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8729 match(Set dst (CMoveP (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8730 ins_cost(80);
8731 format %{
8732 "CMP$cop $tmp1,$tmp2\t @cmovP_cmpI_reg_reg\n\t"
8733 "CMOV $dst,$src\t @cmovP_cmpI_reg_reg"
8734 %}
8735 ins_encode %{
8736 Register op1 = $tmp1$$Register;
8737 Register op2 = $tmp2$$Register;
8738 Register dst = $dst$$Register;
8739 Register src = $src$$Register;
8740 int flag = $cop$$cmpcode;
8742 switch(flag)
8743 {
8744 case 0x01: //equal
8745 __ subu32(AT, op1, op2);
8746 __ movz(dst, src, AT);
8747 break;
8749 case 0x02: //not_equal
8750 __ subu32(AT, op1, op2);
8751 __ movn(dst, src, AT);
8752 break;
8754 case 0x03: //above
8755 __ slt(AT, op2, op1);
8756 __ movn(dst, src, AT);
8757 break;
8759 case 0x04: //above_equal
8760 __ slt(AT, op1, op2);
8761 __ movz(dst, src, AT);
8762 break;
8764 case 0x05: //below
8765 __ slt(AT, op1, op2);
8766 __ movn(dst, src, AT);
8767 break;
8769 case 0x06: //below_equal
8770 __ slt(AT, op2, op1);
8771 __ movz(dst, src, AT);
8772 break;
8774 default:
8775 Unimplemented();
8776 }
8777 %}
8779 ins_pipe( pipe_slow );
8780 %}
8782 instruct cmovN_cmpI_reg_reg(mRegN dst, mRegN src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8783 match(Set dst (CMoveN (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8784 ins_cost(80);
8785 format %{
8786 "CMP$cop $tmp1,$tmp2\t @cmovN_cmpI_reg_reg\n\t"
8787 "CMOV $dst,$src\t @cmovN_cmpI_reg_reg"
8788 %}
8789 ins_encode %{
8790 Register op1 = $tmp1$$Register;
8791 Register op2 = $tmp2$$Register;
8792 Register dst = $dst$$Register;
8793 Register src = $src$$Register;
8794 int flag = $cop$$cmpcode;
8796 switch(flag)
8797 {
8798 case 0x01: //equal
8799 __ subu32(AT, op1, op2);
8800 __ movz(dst, src, AT);
8801 break;
8803 case 0x02: //not_equal
8804 __ subu32(AT, op1, op2);
8805 __ movn(dst, src, AT);
8806 break;
8808 case 0x03: //above
8809 __ slt(AT, op2, op1);
8810 __ movn(dst, src, AT);
8811 break;
8813 case 0x04: //above_equal
8814 __ slt(AT, op1, op2);
8815 __ movz(dst, src, AT);
8816 break;
8818 case 0x05: //below
8819 __ slt(AT, op1, op2);
8820 __ movn(dst, src, AT);
8821 break;
8823 case 0x06: //below_equal
8824 __ slt(AT, op2, op1);
8825 __ movz(dst, src, AT);
8826 break;
8828 default:
8829 Unimplemented();
8830 }
8831 %}
8833 ins_pipe( pipe_slow );
8834 %}
8837 instruct cmovL_cmpI_reg_reg(mRegL dst, mRegL src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8838 match(Set dst (CMoveL (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8839 ins_cost(80);
8840 format %{
8841 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpI_reg_reg\n"
8842 "\tCMOV $dst,$src \t @cmovL_cmpI_reg_reg"
8843 %}
8845 ins_encode %{
8846 Register op1 = $tmp1$$Register;
8847 Register op2 = $tmp2$$Register;
8848 Register dst = as_Register($dst$$reg);
8849 Register src = as_Register($src$$reg);
8850 int flag = $cop$$cmpcode;
8852 switch(flag)
8853 {
8854 case 0x01: //equal
8855 __ subu32(AT, op1, op2);
8856 __ movz(dst, src, AT);
8857 break;
8859 case 0x02: //not_equal
8860 __ subu32(AT, op1, op2);
8861 __ movn(dst, src, AT);
8862 break;
8864 case 0x03: //great
8865 __ slt(AT, op2, op1);
8866 __ movn(dst, src, AT);
8867 break;
8869 case 0x04: //great_equal
8870 __ slt(AT, op1, op2);
8871 __ movz(dst, src, AT);
8872 break;
8874 case 0x05: //less
8875 __ slt(AT, op1, op2);
8876 __ movn(dst, src, AT);
8877 break;
8879 case 0x06: //less_equal
8880 __ slt(AT, op2, op1);
8881 __ movz(dst, src, AT);
8882 break;
8884 default:
8885 Unimplemented();
8886 }
8887 %}
8889 ins_pipe( pipe_slow );
8890 %}
8892 instruct cmovL_cmpL_reg_reg(mRegL dst, mRegL src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8893 match(Set dst (CMoveL (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8894 ins_cost(80);
8895 format %{
8896 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpL_reg_reg\n"
8897 "\tCMOV $dst,$src \t @cmovL_cmpL_reg_reg"
8898 %}
8899 ins_encode %{
8900 Register opr1 = as_Register($tmp1$$reg);
8901 Register opr2 = as_Register($tmp2$$reg);
8902 Register dst = as_Register($dst$$reg);
8903 Register src = as_Register($src$$reg);
8904 int flag = $cop$$cmpcode;
8906 switch(flag)
8907 {
8908 case 0x01: //equal
8909 __ subu(AT, opr1, opr2);
8910 __ movz(dst, src, AT);
8911 break;
8913 case 0x02: //not_equal
8914 __ subu(AT, opr1, opr2);
8915 __ movn(dst, src, AT);
8916 break;
8918 case 0x03: //greater
8919 __ slt(AT, opr2, opr1);
8920 __ movn(dst, src, AT);
8921 break;
8923 case 0x04: //greater_equal
8924 __ slt(AT, opr1, opr2);
8925 __ movz(dst, src, AT);
8926 break;
8928 case 0x05: //less
8929 __ slt(AT, opr1, opr2);
8930 __ movn(dst, src, AT);
8931 break;
8933 case 0x06: //less_equal
8934 __ slt(AT, opr2, opr1);
8935 __ movz(dst, src, AT);
8936 break;
8938 default:
8939 Unimplemented();
8940 }
8941 %}
8943 ins_pipe( pipe_slow );
8944 %}
8946 instruct cmovL_cmpN_reg_reg(mRegL dst, mRegL src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8947 match(Set dst (CMoveL (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8948 ins_cost(80);
8949 format %{
8950 "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpN_reg_reg\n\t"
8951 "CMOV $dst,$src\t @cmovL_cmpN_reg_reg"
8952 %}
8953 ins_encode %{
8954 Register op1 = $tmp1$$Register;
8955 Register op2 = $tmp2$$Register;
8956 Register dst = $dst$$Register;
8957 Register src = $src$$Register;
8958 int flag = $cop$$cmpcode;
8960 switch(flag)
8961 {
8962 case 0x01: //equal
8963 __ subu32(AT, op1, op2);
8964 __ movz(dst, src, AT);
8965 break;
8967 case 0x02: //not_equal
8968 __ subu32(AT, op1, op2);
8969 __ movn(dst, src, AT);
8970 break;
8972 case 0x03: //above
8973 __ sltu(AT, op2, op1);
8974 __ movn(dst, src, AT);
8975 break;
8977 case 0x04: //above_equal
8978 __ sltu(AT, op1, op2);
8979 __ movz(dst, src, AT);
8980 break;
8982 case 0x05: //below
8983 __ sltu(AT, op1, op2);
8984 __ movn(dst, src, AT);
8985 break;
8987 case 0x06: //below_equal
8988 __ sltu(AT, op2, op1);
8989 __ movz(dst, src, AT);
8990 break;
8992 default:
8993 Unimplemented();
8994 }
8995 %}
8997 ins_pipe( pipe_slow );
8998 %}
9001 instruct cmovL_cmpD_reg_reg(mRegL dst, mRegL src, regD tmp1, regD tmp2, cmpOp cop ) %{
9002 match(Set dst (CMoveL (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
9003 ins_cost(80);
9004 format %{
9005 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpD_reg_reg\n"
9006 "\tCMOV $dst,$src \t @cmovL_cmpD_reg_reg"
9007 %}
9008 ins_encode %{
9009 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
9010 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
9011 Register dst = as_Register($dst$$reg);
9012 Register src = as_Register($src$$reg);
9014 int flag = $cop$$cmpcode;
9016 switch(flag)
9017 {
9018 case 0x01: //equal
9019 __ c_eq_d(reg_op1, reg_op2);
9020 __ movt(dst, src);
9021 break;
9022 case 0x02: //not_equal
9023 __ c_eq_d(reg_op1, reg_op2);
9024 __ movf(dst, src);
9025 break;
9026 case 0x03: //greater
9027 __ c_ole_d(reg_op1, reg_op2);
9028 __ movf(dst, src);
9029 break;
9030 case 0x04: //greater_equal
9031 __ c_olt_d(reg_op1, reg_op2);
9032 __ movf(dst, src);
9033 break;
9034 case 0x05: //less
9035 __ c_ult_d(reg_op1, reg_op2);
9036 __ movt(dst, src);
9037 break;
9038 case 0x06: //less_equal
9039 __ c_ule_d(reg_op1, reg_op2);
9040 __ movt(dst, src);
9041 break;
9042 default:
9043 Unimplemented();
9044 }
9045 %}
9047 ins_pipe( pipe_slow );
9048 %}
9050 instruct cmovD_cmpD_reg_reg(regD dst, regD src, regD tmp1, regD tmp2, cmpOp cop ) %{
9051 match(Set dst (CMoveD (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
9052 ins_cost(200);
9053 format %{
9054 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpD_reg_reg\n"
9055 "\tCMOV $dst,$src \t @cmovD_cmpD_reg_reg"
9056 %}
9057 ins_encode %{
9058 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
9059 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
9060 FloatRegister dst = as_FloatRegister($dst$$reg);
9061 FloatRegister src = as_FloatRegister($src$$reg);
9063 int flag = $cop$$cmpcode;
9065 Label L;
9067 switch(flag)
9068 {
9069 case 0x01: //equal
9070 __ c_eq_d(reg_op1, reg_op2);
9071 __ bc1f(L);
9072 __ nop();
9073 __ mov_d(dst, src);
9074 __ bind(L);
9075 break;
9076 case 0x02: //not_equal
9077 //2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
9078 __ c_eq_d(reg_op1, reg_op2);
9079 __ bc1t(L);
9080 __ nop();
9081 __ mov_d(dst, src);
9082 __ bind(L);
9083 break;
9084 case 0x03: //greater
9085 __ c_ole_d(reg_op1, reg_op2);
9086 __ bc1t(L);
9087 __ nop();
9088 __ mov_d(dst, src);
9089 __ bind(L);
9090 break;
9091 case 0x04: //greater_equal
9092 __ c_olt_d(reg_op1, reg_op2);
9093 __ bc1t(L);
9094 __ nop();
9095 __ mov_d(dst, src);
9096 __ bind(L);
9097 break;
9098 case 0x05: //less
9099 __ c_ult_d(reg_op1, reg_op2);
9100 __ bc1f(L);
9101 __ nop();
9102 __ mov_d(dst, src);
9103 __ bind(L);
9104 break;
9105 case 0x06: //less_equal
9106 __ c_ule_d(reg_op1, reg_op2);
9107 __ bc1f(L);
9108 __ nop();
9109 __ mov_d(dst, src);
9110 __ bind(L);
9111 break;
9112 default:
9113 Unimplemented();
9114 }
9115 %}
9117 ins_pipe( pipe_slow );
9118 %}
9120 instruct cmovF_cmpI_reg_reg(regF dst, regF src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
9121 match(Set dst (CMoveF (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
9122 ins_cost(200);
9123 format %{
9124 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpI_reg_reg\n"
9125 "\tCMOV $dst, $src \t @cmovF_cmpI_reg_reg"
9126 %}
9128 ins_encode %{
9129 Register op1 = $tmp1$$Register;
9130 Register op2 = $tmp2$$Register;
9131 FloatRegister dst = as_FloatRegister($dst$$reg);
9132 FloatRegister src = as_FloatRegister($src$$reg);
9133 int flag = $cop$$cmpcode;
9134 Label L;
9136 switch(flag)
9137 {
9138 case 0x01: //equal
9139 __ bne(op1, op2, L);
9140 __ nop();
9141 __ mov_s(dst, src);
9142 __ bind(L);
9143 break;
9144 case 0x02: //not_equal
9145 __ beq(op1, op2, L);
9146 __ nop();
9147 __ mov_s(dst, src);
9148 __ bind(L);
9149 break;
9150 case 0x03: //great
9151 __ slt(AT, op2, op1);
9152 __ beq(AT, R0, L);
9153 __ nop();
9154 __ mov_s(dst, src);
9155 __ bind(L);
9156 break;
9157 case 0x04: //great_equal
9158 __ slt(AT, op1, op2);
9159 __ bne(AT, R0, L);
9160 __ nop();
9161 __ mov_s(dst, src);
9162 __ bind(L);
9163 break;
9164 case 0x05: //less
9165 __ slt(AT, op1, op2);
9166 __ beq(AT, R0, L);
9167 __ nop();
9168 __ mov_s(dst, src);
9169 __ bind(L);
9170 break;
9171 case 0x06: //less_equal
9172 __ slt(AT, op2, op1);
9173 __ bne(AT, R0, L);
9174 __ nop();
9175 __ mov_s(dst, src);
9176 __ bind(L);
9177 break;
9178 default:
9179 Unimplemented();
9180 }
9181 %}
9183 ins_pipe( pipe_slow );
9184 %}
9186 instruct cmovD_cmpI_reg_reg(regD dst, regD src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
9187 match(Set dst (CMoveD (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
9188 ins_cost(200);
9189 format %{
9190 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpI_reg_reg\n"
9191 "\tCMOV $dst, $src \t @cmovD_cmpI_reg_reg"
9192 %}
9194 ins_encode %{
9195 Register op1 = $tmp1$$Register;
9196 Register op2 = $tmp2$$Register;
9197 FloatRegister dst = as_FloatRegister($dst$$reg);
9198 FloatRegister src = as_FloatRegister($src$$reg);
9199 int flag = $cop$$cmpcode;
9200 Label L;
9202 switch(flag)
9203 {
9204 case 0x01: //equal
9205 __ bne(op1, op2, L);
9206 __ nop();
9207 __ mov_d(dst, src);
9208 __ bind(L);
9209 break;
9210 case 0x02: //not_equal
9211 __ beq(op1, op2, L);
9212 __ nop();
9213 __ mov_d(dst, src);
9214 __ bind(L);
9215 break;
9216 case 0x03: //great
9217 __ slt(AT, op2, op1);
9218 __ beq(AT, R0, L);
9219 __ nop();
9220 __ mov_d(dst, src);
9221 __ bind(L);
9222 break;
9223 case 0x04: //great_equal
9224 __ slt(AT, op1, op2);
9225 __ bne(AT, R0, L);
9226 __ nop();
9227 __ mov_d(dst, src);
9228 __ bind(L);
9229 break;
9230 case 0x05: //less
9231 __ slt(AT, op1, op2);
9232 __ beq(AT, R0, L);
9233 __ nop();
9234 __ mov_d(dst, src);
9235 __ bind(L);
9236 break;
9237 case 0x06: //less_equal
9238 __ slt(AT, op2, op1);
9239 __ bne(AT, R0, L);
9240 __ nop();
9241 __ mov_d(dst, src);
9242 __ bind(L);
9243 break;
9244 default:
9245 Unimplemented();
9246 }
9247 %}
9249 ins_pipe( pipe_slow );
9250 %}
9252 instruct cmovD_cmpP_reg_reg(regD dst, regD src, mRegP tmp1, mRegP tmp2, cmpOp cop ) %{
9253 match(Set dst (CMoveD (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
9254 ins_cost(200);
9255 format %{
9256 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpP_reg_reg\n"
9257 "\tCMOV $dst, $src \t @cmovD_cmpP_reg_reg"
9258 %}
9260 ins_encode %{
9261 Register op1 = $tmp1$$Register;
9262 Register op2 = $tmp2$$Register;
9263 FloatRegister dst = as_FloatRegister($dst$$reg);
9264 FloatRegister src = as_FloatRegister($src$$reg);
9265 int flag = $cop$$cmpcode;
9266 Label L;
9268 switch(flag)
9269 {
9270 case 0x01: //equal
9271 __ bne(op1, op2, L);
9272 __ nop();
9273 __ mov_d(dst, src);
9274 __ bind(L);
9275 break;
9276 case 0x02: //not_equal
9277 __ beq(op1, op2, L);
9278 __ nop();
9279 __ mov_d(dst, src);
9280 __ bind(L);
9281 break;
9282 case 0x03: //great
9283 __ slt(AT, op2, op1);
9284 __ beq(AT, R0, L);
9285 __ nop();
9286 __ mov_d(dst, src);
9287 __ bind(L);
9288 break;
9289 case 0x04: //great_equal
9290 __ slt(AT, op1, op2);
9291 __ bne(AT, R0, L);
9292 __ nop();
9293 __ mov_d(dst, src);
9294 __ bind(L);
9295 break;
9296 case 0x05: //less
9297 __ slt(AT, op1, op2);
9298 __ beq(AT, R0, L);
9299 __ nop();
9300 __ mov_d(dst, src);
9301 __ bind(L);
9302 break;
9303 case 0x06: //less_equal
9304 __ slt(AT, op2, op1);
9305 __ bne(AT, R0, L);
9306 __ nop();
9307 __ mov_d(dst, src);
9308 __ bind(L);
9309 break;
9310 default:
9311 Unimplemented();
9312 }
9313 %}
9315 ins_pipe( pipe_slow );
9316 %}
9318 //FIXME
9319 instruct cmovI_cmpF_reg_reg(mRegI dst, mRegI src, regF tmp1, regF tmp2, cmpOp cop ) %{
9320 match(Set dst (CMoveI (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
9321 ins_cost(80);
9322 format %{
9323 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpF_reg_reg\n"
9324 "\tCMOV $dst,$src \t @cmovI_cmpF_reg_reg"
9325 %}
9327 ins_encode %{
9328 FloatRegister reg_op1 = $tmp1$$FloatRegister;
9329 FloatRegister reg_op2 = $tmp2$$FloatRegister;
9330 Register dst = $dst$$Register;
9331 Register src = $src$$Register;
9332 int flag = $cop$$cmpcode;
9334 switch(flag)
9335 {
9336 case 0x01: //equal
9337 __ c_eq_s(reg_op1, reg_op2);
9338 __ movt(dst, src);
9339 break;
9340 case 0x02: //not_equal
9341 __ c_eq_s(reg_op1, reg_op2);
9342 __ movf(dst, src);
9343 break;
9344 case 0x03: //greater
9345 __ c_ole_s(reg_op1, reg_op2);
9346 __ movf(dst, src);
9347 break;
9348 case 0x04: //greater_equal
9349 __ c_olt_s(reg_op1, reg_op2);
9350 __ movf(dst, src);
9351 break;
9352 case 0x05: //less
9353 __ c_ult_s(reg_op1, reg_op2);
9354 __ movt(dst, src);
9355 break;
9356 case 0x06: //less_equal
9357 __ c_ule_s(reg_op1, reg_op2);
9358 __ movt(dst, src);
9359 break;
9360 default:
9361 Unimplemented();
9362 }
9363 %}
9364 ins_pipe( pipe_slow );
9365 %}
9367 instruct cmovF_cmpF_reg_reg(regF dst, regF src, regF tmp1, regF tmp2, cmpOp cop ) %{
9368 match(Set dst (CMoveF (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
9369 ins_cost(200);
9370 format %{
9371 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpF_reg_reg\n"
9372 "\tCMOV $dst,$src \t @cmovF_cmpF_reg_reg"
9373 %}
9375 ins_encode %{
9376 FloatRegister reg_op1 = $tmp1$$FloatRegister;
9377 FloatRegister reg_op2 = $tmp2$$FloatRegister;
9378 FloatRegister dst = $dst$$FloatRegister;
9379 FloatRegister src = $src$$FloatRegister;
9380 Label L;
9381 int flag = $cop$$cmpcode;
9383 switch(flag)
9384 {
9385 case 0x01: //equal
9386 __ c_eq_s(reg_op1, reg_op2);
9387 __ bc1f(L);
9388 __ nop();
9389 __ mov_s(dst, src);
9390 __ bind(L);
9391 break;
9392 case 0x02: //not_equal
9393 __ c_eq_s(reg_op1, reg_op2);
9394 __ bc1t(L);
9395 __ nop();
9396 __ mov_s(dst, src);
9397 __ bind(L);
9398 break;
9399 case 0x03: //greater
9400 __ c_ole_s(reg_op1, reg_op2);
9401 __ bc1t(L);
9402 __ nop();
9403 __ mov_s(dst, src);
9404 __ bind(L);
9405 break;
9406 case 0x04: //greater_equal
9407 __ c_olt_s(reg_op1, reg_op2);
9408 __ bc1t(L);
9409 __ nop();
9410 __ mov_s(dst, src);
9411 __ bind(L);
9412 break;
9413 case 0x05: //less
9414 __ c_ult_s(reg_op1, reg_op2);
9415 __ bc1f(L);
9416 __ nop();
9417 __ mov_s(dst, src);
9418 __ bind(L);
9419 break;
9420 case 0x06: //less_equal
9421 __ c_ule_s(reg_op1, reg_op2);
9422 __ bc1f(L);
9423 __ nop();
9424 __ mov_s(dst, src);
9425 __ bind(L);
9426 break;
9427 default:
9428 Unimplemented();
9429 }
9430 %}
9431 ins_pipe( pipe_slow );
9432 %}
9434 // Manifest a CmpL result in an integer register. Very painful.
9435 // This is the test to avoid.
9436 instruct cmpL3_reg_reg(mRegI dst, mRegL src1, mRegL src2) %{
9437 match(Set dst (CmpL3 src1 src2));
9438 ins_cost(1000);
9439 format %{ "cmpL3 $dst, $src1, $src2 @ cmpL3_reg_reg" %}
9440 ins_encode %{
9441 Register opr1 = as_Register($src1$$reg);
9442 Register opr2 = as_Register($src2$$reg);
9443 Register dst = as_Register($dst$$reg);
9445 Label Done;
9447 __ subu(AT, opr1, opr2);
9448 __ bltz(AT, Done);
9449 __ delayed()->daddiu(dst, R0, -1);
9451 __ move(dst, 1);
9452 __ movz(dst, R0, AT);
9454 __ bind(Done);
9455 %}
9456 ins_pipe( pipe_slow );
9457 %}
9459 //
9460 // less_rsult = -1
9461 // greater_result = 1
9462 // equal_result = 0
9463 // nan_result = -1
9464 //
9465 instruct cmpF3_reg_reg(mRegI dst, regF src1, regF src2) %{
9466 match(Set dst (CmpF3 src1 src2));
9467 ins_cost(1000);
9468 format %{ "cmpF3 $dst, $src1, $src2 @ cmpF3_reg_reg" %}
9469 ins_encode %{
9470 FloatRegister src1 = as_FloatRegister($src1$$reg);
9471 FloatRegister src2 = as_FloatRegister($src2$$reg);
9472 Register dst = as_Register($dst$$reg);
9474 Label Done;
9476 __ c_ult_s(src1, src2);
9477 __ bc1t(Done);
9478 __ delayed()->daddiu(dst, R0, -1);
9480 __ c_eq_s(src1, src2);
9481 __ move(dst, 1);
9482 __ movt(dst, R0);
9484 __ bind(Done);
9485 %}
9486 ins_pipe( pipe_slow );
9487 %}
9489 instruct cmpD3_reg_reg(mRegI dst, regD src1, regD src2) %{
9490 match(Set dst (CmpD3 src1 src2));
9491 ins_cost(1000);
9492 format %{ "cmpD3 $dst, $src1, $src2 @ cmpD3_reg_reg" %}
9493 ins_encode %{
9494 FloatRegister src1 = as_FloatRegister($src1$$reg);
9495 FloatRegister src2 = as_FloatRegister($src2$$reg);
9496 Register dst = as_Register($dst$$reg);
9498 Label Done;
9500 __ c_ult_d(src1, src2);
9501 __ bc1t(Done);
9502 __ delayed()->daddiu(dst, R0, -1);
9504 __ c_eq_d(src1, src2);
9505 __ move(dst, 1);
9506 __ movt(dst, R0);
9508 __ bind(Done);
9509 %}
9510 ins_pipe( pipe_slow );
9511 %}
9513 instruct clear_array(mRegL cnt, mRegP base, Universe dummy) %{
9514 match(Set dummy (ClearArray cnt base));
9515 format %{ "CLEAR_ARRAY base = $base, cnt = $cnt # Clear doublewords" %}
9516 ins_encode %{
9517 //Assume cnt is the number of bytes in an array to be cleared,
9518 //and base points to the starting address of the array.
9519 Register base = $base$$Register;
9520 Register num = $cnt$$Register;
9521 Label Loop, done;
9523 /* 2012/9/21 Jin: according to X86, $cnt is caculated by doublewords(8 bytes) */
9524 __ move(T9, num); /* T9 = words */
9525 __ beq(T9, R0, done);
9526 __ nop();
9527 __ move(AT, base);
9529 __ bind(Loop);
9530 __ sd(R0, Address(AT, 0));
9531 __ daddi(AT, AT, wordSize);
9532 __ daddi(T9, T9, -1);
9533 __ bne(T9, R0, Loop);
9534 __ delayed()->nop();
9535 __ bind(done);
9536 %}
9537 ins_pipe( pipe_slow );
9538 %}
9540 instruct string_compare(a4_RegP str1, mA5RegI cnt1, a6_RegP str2, mA7RegI cnt2, no_Ax_mRegI result) %{
9541 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9542 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);
9544 format %{ "String Compare $str1[len: $cnt1], $str2[len: $cnt2] -> $result @ string_compare" %}
9545 ins_encode %{
9546 // Get the first character position in both strings
9547 // [8] char array, [12] offset, [16] count
9548 Register str1 = $str1$$Register;
9549 Register str2 = $str2$$Register;
9550 Register cnt1 = $cnt1$$Register;
9551 Register cnt2 = $cnt2$$Register;
9552 Register result = $result$$Register;
9554 Label L, Loop, haveResult, done;
9556 // compute the and difference of lengths (in result)
9557 __ subu(result, cnt1, cnt2); // result holds the difference of two lengths
9559 // compute the shorter length (in cnt1)
9560 __ slt(AT, cnt2, cnt1);
9561 __ movn(cnt1, cnt2, AT);
9563 // Now the shorter length is in cnt1 and cnt2 can be used as a tmp register
9564 __ bind(Loop); // Loop begin
9565 __ beq(cnt1, R0, done);
9566 __ delayed()->lhu(AT, str1, 0);;
9568 // compare current character
9569 __ lhu(cnt2, str2, 0);
9570 __ bne(AT, cnt2, haveResult);
9571 __ delayed()->addi(str1, str1, 2);
9572 __ addi(str2, str2, 2);
9573 __ b(Loop);
9574 __ delayed()->addi(cnt1, cnt1, -1); // Loop end
9576 __ bind(haveResult);
9577 __ subu(result, AT, cnt2);
9579 __ bind(done);
9580 %}
9582 ins_pipe( pipe_slow );
9583 %}
9585 // intrinsic optimization
9586 instruct string_equals(a4_RegP str1, a5_RegP str2, mA6RegI cnt, mA7RegI temp, no_Ax_mRegI result) %{
9587 match(Set result (StrEquals (Binary str1 str2) cnt));
9588 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL temp);
9590 format %{ "String Equal $str1, $str2, len:$cnt tmp:$temp -> $result @ string_equals" %}
9591 ins_encode %{
9592 // Get the first character position in both strings
9593 // [8] char array, [12] offset, [16] count
9594 Register str1 = $str1$$Register;
9595 Register str2 = $str2$$Register;
9596 Register cnt = $cnt$$Register;
9597 Register tmp = $temp$$Register;
9598 Register result = $result$$Register;
9600 Label Loop, done;
9603 __ beq(str1, str2, done); // same char[] ?
9604 __ daddiu(result, R0, 1);
9606 __ bind(Loop); // Loop begin
9607 __ beq(cnt, R0, done);
9608 __ daddiu(result, R0, 1); // count == 0
9610 // compare current character
9611 __ lhu(AT, str1, 0);;
9612 __ lhu(tmp, str2, 0);
9613 __ bne(AT, tmp, done);
9614 __ delayed()->daddi(result, R0, 0);
9615 __ addi(str1, str1, 2);
9616 __ addi(str2, str2, 2);
9617 __ b(Loop);
9618 __ delayed()->addi(cnt, cnt, -1); // Loop end
9620 __ bind(done);
9621 %}
9623 ins_pipe( pipe_slow );
9624 %}
9626 //----------Arithmetic Instructions-------------------------------------------
9627 //----------Addition Instructions---------------------------------------------
9628 instruct addI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9629 match(Set dst (AddI src1 src2));
9631 format %{ "add $dst, $src1, $src2 #@addI_Reg_Reg" %}
9632 ins_encode %{
9633 Register dst = $dst$$Register;
9634 Register src1 = $src1$$Register;
9635 Register src2 = $src2$$Register;
9636 __ addu32(dst, src1, src2);
9637 %}
9638 ins_pipe( ialu_regI_regI );
9639 %}
9641 instruct addI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{
9642 match(Set dst (AddI src1 src2));
9644 format %{ "add $dst, $src1, $src2 #@addI_Reg_imm" %}
9645 ins_encode %{
9646 Register dst = $dst$$Register;
9647 Register src1 = $src1$$Register;
9648 int imm = $src2$$constant;
9650 if(Assembler::is_simm16(imm)) {
9651 __ addiu32(dst, src1, imm);
9652 } else {
9653 __ move(AT, imm);
9654 __ addu32(dst, src1, AT);
9655 }
9656 %}
9657 ins_pipe( ialu_regI_regI );
9658 %}
9660 instruct addP_reg_reg(mRegP dst, mRegP src1, mRegL src2) %{
9661 match(Set dst (AddP src1 src2));
9663 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg" %}
9665 ins_encode %{
9666 Register dst = $dst$$Register;
9667 Register src1 = $src1$$Register;
9668 Register src2 = $src2$$Register;
9669 __ daddu(dst, src1, src2);
9670 %}
9672 ins_pipe( ialu_regI_regI );
9673 %}
9675 instruct addP_reg_reg_convI2L(mRegP dst, mRegP src1, mRegI src2) %{
9676 match(Set dst (AddP src1 (ConvI2L src2)));
9678 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg_convI2L" %}
9680 ins_encode %{
9681 Register dst = $dst$$Register;
9682 Register src1 = $src1$$Register;
9683 Register src2 = $src2$$Register;
9684 __ daddu(dst, src1, src2);
9685 %}
9687 ins_pipe( ialu_regI_regI );
9688 %}
9690 instruct addP_reg_imm(mRegP dst, mRegP src1, immL src2) %{
9691 match(Set dst (AddP src1 src2));
9693 format %{ "daddi $dst, $src1, $src2 #@addP_reg_imm" %}
9694 ins_encode %{
9695 Register src1 = $src1$$Register;
9696 long src2 = $src2$$constant;
9697 Register dst = $dst$$Register;
9699 if(Assembler::is_simm16(src2)) {
9700 __ daddiu(dst, src1, src2);
9701 } else {
9702 __ set64(AT, src2);
9703 __ daddu(dst, src1, AT);
9704 }
9705 %}
9706 ins_pipe( ialu_regI_imm16 );
9707 %}
9709 // Add Long Register with Register
9710 instruct addL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
9711 match(Set dst (AddL src1 src2));
9712 ins_cost(200);
9713 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_Reg\t" %}
9715 ins_encode %{
9716 Register dst_reg = as_Register($dst$$reg);
9717 Register src1_reg = as_Register($src1$$reg);
9718 Register src2_reg = as_Register($src2$$reg);
9720 __ daddu(dst_reg, src1_reg, src2_reg);
9721 %}
9723 ins_pipe( ialu_regL_regL );
9724 %}
9726 instruct addL_Reg_imm(mRegL dst, mRegL src1, immL16 src2)
9727 %{
9728 match(Set dst (AddL src1 src2));
9730 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_imm " %}
9731 ins_encode %{
9732 Register dst_reg = as_Register($dst$$reg);
9733 Register src1_reg = as_Register($src1$$reg);
9734 int src2_imm = $src2$$constant;
9736 __ daddiu(dst_reg, src1_reg, src2_imm);
9737 %}
9739 ins_pipe( ialu_regL_regL );
9740 %}
9742 instruct addL_RegI2L_imm(mRegL dst, mRegI src1, immL16 src2)
9743 %{
9744 match(Set dst (AddL (ConvI2L src1) src2));
9746 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_imm " %}
9747 ins_encode %{
9748 Register dst_reg = as_Register($dst$$reg);
9749 Register src1_reg = as_Register($src1$$reg);
9750 int src2_imm = $src2$$constant;
9752 __ daddiu(dst_reg, src1_reg, src2_imm);
9753 %}
9755 ins_pipe( ialu_regL_regL );
9756 %}
9758 instruct addL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{
9759 match(Set dst (AddL (ConvI2L src1) src2));
9760 ins_cost(200);
9761 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_Reg\t" %}
9763 ins_encode %{
9764 Register dst_reg = as_Register($dst$$reg);
9765 Register src1_reg = as_Register($src1$$reg);
9766 Register src2_reg = as_Register($src2$$reg);
9768 __ daddu(dst_reg, src1_reg, src2_reg);
9769 %}
9771 ins_pipe( ialu_regL_regL );
9772 %}
9774 instruct addL_RegI2L_RegI2L(mRegL dst, mRegI src1, mRegI src2) %{
9775 match(Set dst (AddL (ConvI2L src1) (ConvI2L src2)));
9776 ins_cost(200);
9777 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_RegI2L\t" %}
9779 ins_encode %{
9780 Register dst_reg = as_Register($dst$$reg);
9781 Register src1_reg = as_Register($src1$$reg);
9782 Register src2_reg = as_Register($src2$$reg);
9784 __ daddu(dst_reg, src1_reg, src2_reg);
9785 %}
9787 ins_pipe( ialu_regL_regL );
9788 %}
9790 instruct addL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{
9791 match(Set dst (AddL src1 (ConvI2L src2)));
9792 ins_cost(200);
9793 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_RegI2L\t" %}
9795 ins_encode %{
9796 Register dst_reg = as_Register($dst$$reg);
9797 Register src1_reg = as_Register($src1$$reg);
9798 Register src2_reg = as_Register($src2$$reg);
9800 __ daddu(dst_reg, src1_reg, src2_reg);
9801 %}
9803 ins_pipe( ialu_regL_regL );
9804 %}
9806 //----------Subtraction Instructions-------------------------------------------
9807 // Integer Subtraction Instructions
9808 instruct subI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9809 match(Set dst (SubI src1 src2));
9810 ins_cost(100);
9812 format %{ "sub $dst, $src1, $src2 #@subI_Reg_Reg" %}
9813 ins_encode %{
9814 Register dst = $dst$$Register;
9815 Register src1 = $src1$$Register;
9816 Register src2 = $src2$$Register;
9817 __ subu32(dst, src1, src2);
9818 %}
9819 ins_pipe( ialu_regI_regI );
9820 %}
9822 instruct subI_Reg_immI16_sub(mRegI dst, mRegI src1, immI16_sub src2) %{
9823 match(Set dst (SubI src1 src2));
9824 ins_cost(80);
9826 format %{ "sub $dst, $src1, $src2 #@subI_Reg_immI16_sub" %}
9827 ins_encode %{
9828 Register dst = $dst$$Register;
9829 Register src1 = $src1$$Register;
9830 __ addiu32(dst, src1, -1 * $src2$$constant);
9831 %}
9832 ins_pipe( ialu_regI_regI );
9833 %}
9835 instruct negI_Reg(mRegI dst, immI0 zero, mRegI src) %{
9836 match(Set dst (SubI zero src));
9837 ins_cost(80);
9839 format %{ "neg $dst, $src #@negI_Reg" %}
9840 ins_encode %{
9841 Register dst = $dst$$Register;
9842 Register src = $src$$Register;
9843 __ subu32(dst, R0, src);
9844 %}
9845 ins_pipe( ialu_regI_regI );
9846 %}
9848 instruct negL_Reg(mRegL dst, immL0 zero, mRegL src) %{
9849 match(Set dst (SubL zero src));
9850 ins_cost(80);
9852 format %{ "neg $dst, $src #@negL_Reg" %}
9853 ins_encode %{
9854 Register dst = $dst$$Register;
9855 Register src = $src$$Register;
9856 __ subu(dst, R0, src);
9857 %}
9858 ins_pipe( ialu_regI_regI );
9859 %}
9861 instruct subL_Reg_immL16_sub(mRegL dst, mRegL src1, immL16_sub src2) %{
9862 match(Set dst (SubL src1 src2));
9863 ins_cost(80);
9865 format %{ "sub $dst, $src1, $src2 #@subL_Reg_immL16_sub" %}
9866 ins_encode %{
9867 Register dst = $dst$$Register;
9868 Register src1 = $src1$$Register;
9869 __ daddiu(dst, src1, -1 * $src2$$constant);
9870 %}
9871 ins_pipe( ialu_regI_regI );
9872 %}
9874 // Subtract Long Register with Register.
9875 instruct subL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
9876 match(Set dst (SubL src1 src2));
9877 ins_cost(100);
9878 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_Reg" %}
9879 ins_encode %{
9880 Register dst = as_Register($dst$$reg);
9881 Register src1 = as_Register($src1$$reg);
9882 Register src2 = as_Register($src2$$reg);
9884 __ subu(dst, src1, src2);
9885 %}
9886 ins_pipe( ialu_regL_regL );
9887 %}
9889 instruct subL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{
9890 match(Set dst (SubL src1 (ConvI2L src2)));
9891 ins_cost(100);
9892 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_RegI2L" %}
9893 ins_encode %{
9894 Register dst = as_Register($dst$$reg);
9895 Register src1 = as_Register($src1$$reg);
9896 Register src2 = as_Register($src2$$reg);
9898 __ subu(dst, src1, src2);
9899 %}
9900 ins_pipe( ialu_regL_regL );
9901 %}
9903 instruct subL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{
9904 match(Set dst (SubL (ConvI2L src1) src2));
9905 ins_cost(200);
9906 format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_Reg" %}
9907 ins_encode %{
9908 Register dst = as_Register($dst$$reg);
9909 Register src1 = as_Register($src1$$reg);
9910 Register src2 = as_Register($src2$$reg);
9912 __ subu(dst, src1, src2);
9913 %}
9914 ins_pipe( ialu_regL_regL );
9915 %}
9917 instruct subL_RegI2L_RegI2L(mRegL dst, mRegI src1, mRegI src2) %{
9918 match(Set dst (SubL (ConvI2L src1) (ConvI2L src2)));
9919 ins_cost(200);
9920 format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_RegI2L" %}
9921 ins_encode %{
9922 Register dst = as_Register($dst$$reg);
9923 Register src1 = as_Register($src1$$reg);
9924 Register src2 = as_Register($src2$$reg);
9926 __ subu(dst, src1, src2);
9927 %}
9928 ins_pipe( ialu_regL_regL );
9929 %}
9931 // Integer MOD with Register
9932 instruct modI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9933 match(Set dst (ModI src1 src2));
9934 ins_cost(300);
9935 format %{ "modi $dst, $src1, $src2 @ modI_Reg_Reg" %}
9936 ins_encode %{
9937 Register dst = $dst$$Register;
9938 Register src1 = $src1$$Register;
9939 Register src2 = $src2$$Register;
9941 //if (UseLoongsonISA) {
9942 if (0) {
9943 // 2016.08.10
9944 // Experiments show that gsmod is slower that div+mfhi.
9945 // So I just disable it here.
9946 __ gsmod(dst, src1, src2);
9947 } else {
9948 __ div(src1, src2);
9949 __ mfhi(dst);
9950 }
9951 %}
9953 //ins_pipe( ialu_mod );
9954 ins_pipe( ialu_regI_regI );
9955 %}
9957 instruct modL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
9958 match(Set dst (ModL src1 src2));
9959 format %{ "modL $dst, $src1, $src2 @modL_reg_reg" %}
9961 ins_encode %{
9962 Register dst = as_Register($dst$$reg);
9963 Register op1 = as_Register($src1$$reg);
9964 Register op2 = as_Register($src2$$reg);
9966 if (UseLoongsonISA) {
9967 __ gsdmod(dst, op1, op2);
9968 } else {
9969 __ ddiv(op1, op2);
9970 __ mfhi(dst);
9971 }
9972 %}
9973 ins_pipe( pipe_slow );
9974 %}
9976 instruct mulI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9977 match(Set dst (MulI src1 src2));
9979 ins_cost(300);
9980 format %{ "mul $dst, $src1, $src2 @ mulI_Reg_Reg" %}
9981 ins_encode %{
9982 Register src1 = $src1$$Register;
9983 Register src2 = $src2$$Register;
9984 Register dst = $dst$$Register;
9986 __ mul(dst, src1, src2);
9987 %}
9988 ins_pipe( ialu_mult );
9989 %}
9991 instruct maddI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mRegI src3) %{
9992 match(Set dst (AddI (MulI src1 src2) src3));
9994 ins_cost(999);
9995 format %{ "madd $dst, $src1 * $src2 + $src3 #@maddI_Reg_Reg" %}
9996 ins_encode %{
9997 Register src1 = $src1$$Register;
9998 Register src2 = $src2$$Register;
9999 Register src3 = $src3$$Register;
10000 Register dst = $dst$$Register;
10002 __ mtlo(src3);
10003 __ madd(src1, src2);
10004 __ mflo(dst);
10005 %}
10006 ins_pipe( ialu_mult );
10007 %}
10009 instruct divI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
10010 match(Set dst (DivI src1 src2));
10012 ins_cost(300);
10013 format %{ "div $dst, $src1, $src2 @ divI_Reg_Reg" %}
10014 ins_encode %{
10015 Register src1 = $src1$$Register;
10016 Register src2 = $src2$$Register;
10017 Register dst = $dst$$Register;
10019 /* 2012/4/21 Jin: In MIPS, div does not cause exception.
10020 We must trap an exception manually. */
10021 __ teq(R0, src2, 0x7);
10023 if (UseLoongsonISA) {
10024 __ gsdiv(dst, src1, src2);
10025 } else {
10026 __ div(src1, src2);
10028 __ nop();
10029 __ nop();
10030 __ mflo(dst);
10031 }
10032 %}
10033 ins_pipe( ialu_mod );
10034 %}
10036 instruct divF_Reg_Reg(regF dst, regF src1, regF src2) %{
10037 match(Set dst (DivF src1 src2));
10039 ins_cost(300);
10040 format %{ "divF $dst, $src1, $src2 @ divF_Reg_Reg" %}
10041 ins_encode %{
10042 FloatRegister src1 = $src1$$FloatRegister;
10043 FloatRegister src2 = $src2$$FloatRegister;
10044 FloatRegister dst = $dst$$FloatRegister;
10046 /* Here do we need to trap an exception manually ? */
10047 __ div_s(dst, src1, src2);
10048 %}
10049 ins_pipe( pipe_slow );
10050 %}
10052 instruct divD_Reg_Reg(regD dst, regD src1, regD src2) %{
10053 match(Set dst (DivD src1 src2));
10055 ins_cost(300);
10056 format %{ "divD $dst, $src1, $src2 @ divD_Reg_Reg" %}
10057 ins_encode %{
10058 FloatRegister src1 = $src1$$FloatRegister;
10059 FloatRegister src2 = $src2$$FloatRegister;
10060 FloatRegister dst = $dst$$FloatRegister;
10062 /* Here do we need to trap an exception manually ? */
10063 __ div_d(dst, src1, src2);
10064 %}
10065 ins_pipe( pipe_slow );
10066 %}
10068 instruct mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
10069 match(Set dst (MulL src1 src2));
10070 format %{ "mulL $dst, $src1, $src2 @mulL_reg_reg" %}
10071 ins_encode %{
10072 Register dst = as_Register($dst$$reg);
10073 Register op1 = as_Register($src1$$reg);
10074 Register op2 = as_Register($src2$$reg);
10076 if (UseLoongsonISA) {
10077 __ gsdmult(dst, op1, op2);
10078 } else {
10079 __ dmult(op1, op2);
10080 __ mflo(dst);
10081 }
10082 %}
10083 ins_pipe( pipe_slow );
10084 %}
10086 instruct mulL_reg_regI2L(mRegL dst, mRegL src1, mRegI src2) %{
10087 match(Set dst (MulL src1 (ConvI2L src2)));
10088 format %{ "mulL $dst, $src1, $src2 @mulL_reg_regI2L" %}
10089 ins_encode %{
10090 Register dst = as_Register($dst$$reg);
10091 Register op1 = as_Register($src1$$reg);
10092 Register op2 = as_Register($src2$$reg);
10094 if (UseLoongsonISA) {
10095 __ gsdmult(dst, op1, op2);
10096 } else {
10097 __ dmult(op1, op2);
10098 __ mflo(dst);
10099 }
10100 %}
10101 ins_pipe( pipe_slow );
10102 %}
10104 instruct divL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
10105 match(Set dst (DivL src1 src2));
10106 format %{ "divL $dst, $src1, $src2 @divL_reg_reg" %}
10108 ins_encode %{
10109 Register dst = as_Register($dst$$reg);
10110 Register op1 = as_Register($src1$$reg);
10111 Register op2 = as_Register($src2$$reg);
10113 if (UseLoongsonISA) {
10114 __ gsddiv(dst, op1, op2);
10115 } else {
10116 __ ddiv(op1, op2);
10117 __ mflo(dst);
10118 }
10119 %}
10120 ins_pipe( pipe_slow );
10121 %}
10123 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
10124 match(Set dst (AddF src1 src2));
10125 format %{ "AddF $dst, $src1, $src2 @addF_reg_reg" %}
10126 ins_encode %{
10127 FloatRegister src1 = as_FloatRegister($src1$$reg);
10128 FloatRegister src2 = as_FloatRegister($src2$$reg);
10129 FloatRegister dst = as_FloatRegister($dst$$reg);
10131 __ add_s(dst, src1, src2);
10132 %}
10133 ins_pipe( fpu_regF_regF );
10134 %}
10136 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
10137 match(Set dst (SubF src1 src2));
10138 format %{ "SubF $dst, $src1, $src2 @subF_reg_reg" %}
10139 ins_encode %{
10140 FloatRegister src1 = as_FloatRegister($src1$$reg);
10141 FloatRegister src2 = as_FloatRegister($src2$$reg);
10142 FloatRegister dst = as_FloatRegister($dst$$reg);
10144 __ sub_s(dst, src1, src2);
10145 %}
10146 ins_pipe( fpu_regF_regF );
10147 %}
10148 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
10149 match(Set dst (AddD src1 src2));
10150 format %{ "AddD $dst, $src1, $src2 @addD_reg_reg" %}
10151 ins_encode %{
10152 FloatRegister src1 = as_FloatRegister($src1$$reg);
10153 FloatRegister src2 = as_FloatRegister($src2$$reg);
10154 FloatRegister dst = as_FloatRegister($dst$$reg);
10156 __ add_d(dst, src1, src2);
10157 %}
10158 ins_pipe( fpu_regF_regF );
10159 %}
10161 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
10162 match(Set dst (SubD src1 src2));
10163 format %{ "SubD $dst, $src1, $src2 @subD_reg_reg" %}
10164 ins_encode %{
10165 FloatRegister src1 = as_FloatRegister($src1$$reg);
10166 FloatRegister src2 = as_FloatRegister($src2$$reg);
10167 FloatRegister dst = as_FloatRegister($dst$$reg);
10169 __ sub_d(dst, src1, src2);
10170 %}
10171 ins_pipe( fpu_regF_regF );
10172 %}
10174 instruct negF_reg(regF dst, regF src) %{
10175 match(Set dst (NegF src));
10176 format %{ "negF $dst, $src @negF_reg" %}
10177 ins_encode %{
10178 FloatRegister src = as_FloatRegister($src$$reg);
10179 FloatRegister dst = as_FloatRegister($dst$$reg);
10181 __ neg_s(dst, src);
10182 %}
10183 ins_pipe( fpu_regF_regF );
10184 %}
10186 instruct negD_reg(regD dst, regD src) %{
10187 match(Set dst (NegD src));
10188 format %{ "negD $dst, $src @negD_reg" %}
10189 ins_encode %{
10190 FloatRegister src = as_FloatRegister($src$$reg);
10191 FloatRegister dst = as_FloatRegister($dst$$reg);
10193 __ neg_d(dst, src);
10194 %}
10195 ins_pipe( fpu_regF_regF );
10196 %}
10199 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
10200 match(Set dst (MulF src1 src2));
10201 format %{ "MULF $dst, $src1, $src2 @mulF_reg_reg" %}
10202 ins_encode %{
10203 FloatRegister src1 = $src1$$FloatRegister;
10204 FloatRegister src2 = $src2$$FloatRegister;
10205 FloatRegister dst = $dst$$FloatRegister;
10207 __ mul_s(dst, src1, src2);
10208 %}
10209 ins_pipe( fpu_regF_regF );
10210 %}
10212 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
10213 match(Set dst (AddF (MulF src1 src2) src3));
10214 // For compatibility reason (e.g. on the Loongson platform), disable this guy.
10215 ins_cost(44444);
10216 format %{ "maddF $dst, $src1, $src2, $src3 @maddF_reg_reg" %}
10217 ins_encode %{
10218 FloatRegister src1 = $src1$$FloatRegister;
10219 FloatRegister src2 = $src2$$FloatRegister;
10220 FloatRegister src3 = $src3$$FloatRegister;
10221 FloatRegister dst = $dst$$FloatRegister;
10223 __ madd_s(dst, src1, src2, src3);
10224 %}
10225 ins_pipe( fpu_regF_regF );
10226 %}
10228 // Mul two double precision floating piont number
10229 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
10230 match(Set dst (MulD src1 src2));
10231 format %{ "MULD $dst, $src1, $src2 @mulD_reg_reg" %}
10232 ins_encode %{
10233 FloatRegister src1 = $src1$$FloatRegister;
10234 FloatRegister src2 = $src2$$FloatRegister;
10235 FloatRegister dst = $dst$$FloatRegister;
10237 __ mul_d(dst, src1, src2);
10238 %}
10239 ins_pipe( fpu_regF_regF );
10240 %}
10242 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
10243 match(Set dst (AddD (MulD src1 src2) src3));
10244 // For compatibility reason (e.g. on the Loongson platform), disable this guy.
10245 ins_cost(44444);
10246 format %{ "maddD $dst, $src1, $src2, $src3 @maddD_reg_reg" %}
10247 ins_encode %{
10248 FloatRegister src1 = $src1$$FloatRegister;
10249 FloatRegister src2 = $src2$$FloatRegister;
10250 FloatRegister src3 = $src3$$FloatRegister;
10251 FloatRegister dst = $dst$$FloatRegister;
10253 __ madd_d(dst, src1, src2, src3);
10254 %}
10255 ins_pipe( fpu_regF_regF );
10256 %}
10258 instruct absF_reg(regF dst, regF src) %{
10259 match(Set dst (AbsF src));
10260 ins_cost(100);
10261 format %{ "absF $dst, $src @absF_reg" %}
10262 ins_encode %{
10263 FloatRegister src = as_FloatRegister($src$$reg);
10264 FloatRegister dst = as_FloatRegister($dst$$reg);
10266 __ abs_s(dst, src);
10267 %}
10268 ins_pipe( fpu_regF_regF );
10269 %}
10272 // intrinsics for math_native.
10273 // AbsD SqrtD CosD SinD TanD LogD Log10D
10275 instruct absD_reg(regD dst, regD src) %{
10276 match(Set dst (AbsD src));
10277 ins_cost(100);
10278 format %{ "absD $dst, $src @absD_reg" %}
10279 ins_encode %{
10280 FloatRegister src = as_FloatRegister($src$$reg);
10281 FloatRegister dst = as_FloatRegister($dst$$reg);
10283 __ abs_d(dst, src);
10284 %}
10285 ins_pipe( fpu_regF_regF );
10286 %}
10288 instruct sqrtD_reg(regD dst, regD src) %{
10289 match(Set dst (SqrtD src));
10290 ins_cost(100);
10291 format %{ "SqrtD $dst, $src @sqrtD_reg" %}
10292 ins_encode %{
10293 FloatRegister src = as_FloatRegister($src$$reg);
10294 FloatRegister dst = as_FloatRegister($dst$$reg);
10296 __ sqrt_d(dst, src);
10297 %}
10298 ins_pipe( fpu_regF_regF );
10299 %}
10301 instruct sqrtF_reg(regF dst, regF src) %{
10302 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10303 ins_cost(100);
10304 format %{ "SqrtF $dst, $src @sqrtF_reg" %}
10305 ins_encode %{
10306 FloatRegister src = as_FloatRegister($src$$reg);
10307 FloatRegister dst = as_FloatRegister($dst$$reg);
10309 __ sqrt_s(dst, src);
10310 %}
10311 ins_pipe( fpu_regF_regF );
10312 %}
10313 //----------------------------------Logical Instructions----------------------
10314 //__________________________________Integer Logical Instructions-------------
10316 //And Instuctions
10317 // And Register with Immediate
10318 instruct andI_Reg_immI(mRegI dst, mRegI src1, immI src2) %{
10319 match(Set dst (AndI src1 src2));
10321 format %{ "and $dst, $src1, $src2 #@andI_Reg_immI" %}
10322 ins_encode %{
10323 Register dst = $dst$$Register;
10324 Register src = $src1$$Register;
10325 int val = $src2$$constant;
10327 __ move(AT, val);
10328 __ andr(dst, src, AT);
10329 %}
10330 ins_pipe( ialu_regI_regI );
10331 %}
10333 instruct andI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
10334 match(Set dst (AndI src1 src2));
10335 ins_cost(60);
10337 format %{ "and $dst, $src1, $src2 #@andI_Reg_imm_0_65535" %}
10338 ins_encode %{
10339 Register dst = $dst$$Register;
10340 Register src = $src1$$Register;
10341 int val = $src2$$constant;
10343 __ andi(dst, src, val);
10344 %}
10345 ins_pipe( ialu_regI_regI );
10346 %}
10348 instruct andI_Reg_immI_nonneg_mask(mRegI dst, mRegI src1, immI_nonneg_mask mask) %{
10349 match(Set dst (AndI src1 mask));
10350 ins_cost(60);
10352 format %{ "and $dst, $src1, $mask #@andI_Reg_immI_nonneg_mask" %}
10353 ins_encode %{
10354 Register dst = $dst$$Register;
10355 Register src = $src1$$Register;
10356 int size = Assembler::is_int_mask($mask$$constant);
10358 __ ext(dst, src, 0, size);
10359 %}
10360 ins_pipe( ialu_regI_regI );
10361 %}
10363 instruct andL_Reg_immL_nonneg_mask(mRegL dst, mRegL src1, immL_nonneg_mask mask) %{
10364 match(Set dst (AndL src1 mask));
10365 ins_cost(60);
10367 format %{ "and $dst, $src1, $mask #@andL_Reg_immL_nonneg_mask" %}
10368 ins_encode %{
10369 Register dst = $dst$$Register;
10370 Register src = $src1$$Register;
10371 int size = Assembler::is_jlong_mask($mask$$constant);
10373 __ dext(dst, src, 0, size);
10374 %}
10375 ins_pipe( ialu_regI_regI );
10376 %}
10378 instruct xorI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
10379 match(Set dst (XorI src1 src2));
10380 ins_cost(60);
10382 format %{ "xori $dst, $src1, $src2 #@xorI_Reg_imm_0_65535" %}
10383 ins_encode %{
10384 Register dst = $dst$$Register;
10385 Register src = $src1$$Register;
10386 int val = $src2$$constant;
10388 __ xori(dst, src, val);
10389 %}
10390 ins_pipe( ialu_regI_regI );
10391 %}
10393 instruct xorI_Reg_immI_M1(mRegI dst, mRegI src1, immI_M1 M1) %{
10394 match(Set dst (XorI src1 M1));
10395 predicate(UseLoongsonISA);
10396 ins_cost(60);
10398 format %{ "xor $dst, $src1, $M1 #@xorI_Reg_immI_M1" %}
10399 ins_encode %{
10400 Register dst = $dst$$Register;
10401 Register src = $src1$$Register;
10403 __ gsorn(dst, R0, src);
10404 %}
10405 ins_pipe( ialu_regI_regI );
10406 %}
10408 instruct xorL_Reg_imm_0_65535(mRegL dst, mRegL src1, immL_0_65535 src2) %{
10409 match(Set dst (XorL src1 src2));
10410 ins_cost(60);
10412 format %{ "xori $dst, $src1, $src2 #@xorL_Reg_imm_0_65535" %}
10413 ins_encode %{
10414 Register dst = $dst$$Register;
10415 Register src = $src1$$Register;
10416 int val = $src2$$constant;
10418 __ xori(dst, src, val);
10419 %}
10420 ins_pipe( ialu_regI_regI );
10421 %}
10423 /*
10424 instruct xorL_Reg_immL_M1(mRegL dst, mRegL src1, immL_M1 M1) %{
10425 match(Set dst (XorL src1 M1));
10426 predicate(UseLoongsonISA);
10427 ins_cost(60);
10429 format %{ "xor $dst, $src1, $M1 #@xorL_Reg_immL_M1" %}
10430 ins_encode %{
10431 Register dst = $dst$$Register;
10432 Register src = $src1$$Register;
10434 __ gsorn(dst, R0, src);
10435 %}
10436 ins_pipe( ialu_regI_regI );
10437 %}
10438 */
10440 instruct lbu_and_lmask(mRegI dst, memory mem, immI_255 mask) %{
10441 match(Set dst (AndI mask (LoadB mem)));
10442 ins_cost(60);
10444 format %{ "lhu $dst, $mem #@lbu_and_lmask" %}
10445 ins_encode(load_UB_enc(dst, mem));
10446 ins_pipe( ialu_loadI );
10447 %}
10449 instruct lbu_and_rmask(mRegI dst, memory mem, immI_255 mask) %{
10450 match(Set dst (AndI (LoadB mem) mask));
10451 ins_cost(60);
10453 format %{ "lhu $dst, $mem #@lbu_and_rmask" %}
10454 ins_encode(load_UB_enc(dst, mem));
10455 ins_pipe( ialu_loadI );
10456 %}
10458 instruct andI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
10459 match(Set dst (AndI src1 src2));
10461 format %{ "and $dst, $src1, $src2 #@andI_Reg_Reg" %}
10462 ins_encode %{
10463 Register dst = $dst$$Register;
10464 Register src1 = $src1$$Register;
10465 Register src2 = $src2$$Register;
10466 __ andr(dst, src1, src2);
10467 %}
10468 ins_pipe( ialu_regI_regI );
10469 %}
10471 instruct andnI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10472 match(Set dst (AndI src1 (XorI src2 M1)));
10473 predicate(UseLoongsonISA);
10475 format %{ "andn $dst, $src1, $src2 #@andnI_Reg_nReg" %}
10476 ins_encode %{
10477 Register dst = $dst$$Register;
10478 Register src1 = $src1$$Register;
10479 Register src2 = $src2$$Register;
10481 __ gsandn(dst, src1, src2);
10482 %}
10483 ins_pipe( ialu_regI_regI );
10484 %}
10486 instruct ornI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10487 match(Set dst (OrI src1 (XorI src2 M1)));
10488 predicate(UseLoongsonISA);
10490 format %{ "orn $dst, $src1, $src2 #@ornI_Reg_nReg" %}
10491 ins_encode %{
10492 Register dst = $dst$$Register;
10493 Register src1 = $src1$$Register;
10494 Register src2 = $src2$$Register;
10496 __ gsorn(dst, src1, src2);
10497 %}
10498 ins_pipe( ialu_regI_regI );
10499 %}
10501 instruct andnI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10502 match(Set dst (AndI (XorI src1 M1) src2));
10503 predicate(UseLoongsonISA);
10505 format %{ "andn $dst, $src2, $src1 #@andnI_nReg_Reg" %}
10506 ins_encode %{
10507 Register dst = $dst$$Register;
10508 Register src1 = $src1$$Register;
10509 Register src2 = $src2$$Register;
10511 __ gsandn(dst, src2, src1);
10512 %}
10513 ins_pipe( ialu_regI_regI );
10514 %}
10516 instruct ornI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10517 match(Set dst (OrI (XorI src1 M1) src2));
10518 predicate(UseLoongsonISA);
10520 format %{ "orn $dst, $src2, $src1 #@ornI_nReg_Reg" %}
10521 ins_encode %{
10522 Register dst = $dst$$Register;
10523 Register src1 = $src1$$Register;
10524 Register src2 = $src2$$Register;
10526 __ gsorn(dst, src2, src1);
10527 %}
10528 ins_pipe( ialu_regI_regI );
10529 %}
10531 // And Long Register with Register
10532 instruct andL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10533 match(Set dst (AndL src1 src2));
10534 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg\n\t" %}
10535 ins_encode %{
10536 Register dst_reg = as_Register($dst$$reg);
10537 Register src1_reg = as_Register($src1$$reg);
10538 Register src2_reg = as_Register($src2$$reg);
10540 __ andr(dst_reg, src1_reg, src2_reg);
10541 %}
10542 ins_pipe( ialu_regL_regL );
10543 %}
10545 instruct andL_Reg_Reg_convI2L(mRegL dst, mRegL src1, mRegI src2) %{
10546 match(Set dst (AndL src1 (ConvI2L src2)));
10547 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg_convI2L\n\t" %}
10548 ins_encode %{
10549 Register dst_reg = as_Register($dst$$reg);
10550 Register src1_reg = as_Register($src1$$reg);
10551 Register src2_reg = as_Register($src2$$reg);
10553 __ andr(dst_reg, src1_reg, src2_reg);
10554 %}
10555 ins_pipe( ialu_regL_regL );
10556 %}
10558 instruct andL_Reg_imm_0_65535(mRegL dst, mRegL src1, immL_0_65535 src2) %{
10559 match(Set dst (AndL src1 src2));
10560 ins_cost(60);
10562 format %{ "and $dst, $src1, $src2 #@andL_Reg_imm_0_65535" %}
10563 ins_encode %{
10564 Register dst = $dst$$Register;
10565 Register src = $src1$$Register;
10566 long val = $src2$$constant;
10568 __ andi(dst, src, val);
10569 %}
10570 ins_pipe( ialu_regI_regI );
10571 %}
10573 /*
10574 instruct andnL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10575 match(Set dst (AndL src1 (XorL src2 M1)));
10576 predicate(UseLoongsonISA);
10578 format %{ "andn $dst, $src1, $src2 #@andnL_Reg_nReg" %}
10579 ins_encode %{
10580 Register dst = $dst$$Register;
10581 Register src1 = $src1$$Register;
10582 Register src2 = $src2$$Register;
10584 __ gsandn(dst, src1, src2);
10585 %}
10586 ins_pipe( ialu_regI_regI );
10587 %}
10588 */
10590 /*
10591 instruct ornL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10592 match(Set dst (OrL src1 (XorL src2 M1)));
10593 predicate(UseLoongsonISA);
10595 format %{ "orn $dst, $src1, $src2 #@ornL_Reg_nReg" %}
10596 ins_encode %{
10597 Register dst = $dst$$Register;
10598 Register src1 = $src1$$Register;
10599 Register src2 = $src2$$Register;
10601 __ gsorn(dst, src1, src2);
10602 %}
10603 ins_pipe( ialu_regI_regI );
10604 %}
10605 */
10607 /*
10608 instruct andnL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10609 match(Set dst (AndL (XorL src1 M1) src2));
10610 predicate(UseLoongsonISA);
10612 format %{ "andn $dst, $src2, $src1 #@andnL_nReg_Reg" %}
10613 ins_encode %{
10614 Register dst = $dst$$Register;
10615 Register src1 = $src1$$Register;
10616 Register src2 = $src2$$Register;
10618 __ gsandn(dst, src2, src1);
10619 %}
10620 ins_pipe( ialu_regI_regI );
10621 %}
10622 */
10624 /*
10625 instruct ornL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10626 match(Set dst (OrL (XorL src1 M1) src2));
10627 predicate(UseLoongsonISA);
10629 format %{ "orn $dst, $src2, $src1 #@ornL_nReg_Reg" %}
10630 ins_encode %{
10631 Register dst = $dst$$Register;
10632 Register src1 = $src1$$Register;
10633 Register src2 = $src2$$Register;
10635 __ gsorn(dst, src2, src1);
10636 %}
10637 ins_pipe( ialu_regI_regI );
10638 %}
10639 */
10641 instruct andL_Reg_immL_M8(mRegL dst, immL_M8 M8) %{
10642 match(Set dst (AndL dst M8));
10643 ins_cost(60);
10645 format %{ "and $dst, $dst, $M8 #@andL_Reg_immL_M8" %}
10646 ins_encode %{
10647 Register dst = $dst$$Register;
10649 __ dins(dst, R0, 0, 3);
10650 %}
10651 ins_pipe( ialu_regI_regI );
10652 %}
10654 instruct andL_Reg_immL_M5(mRegL dst, immL_M5 M5) %{
10655 match(Set dst (AndL dst M5));
10656 ins_cost(60);
10658 format %{ "and $dst, $dst, $M5 #@andL_Reg_immL_M5" %}
10659 ins_encode %{
10660 Register dst = $dst$$Register;
10662 __ dins(dst, R0, 2, 1);
10663 %}
10664 ins_pipe( ialu_regI_regI );
10665 %}
10667 instruct andL_Reg_immL_M7(mRegL dst, immL_M7 M7) %{
10668 match(Set dst (AndL dst M7));
10669 ins_cost(60);
10671 format %{ "and $dst, $dst, $M7 #@andL_Reg_immL_M7" %}
10672 ins_encode %{
10673 Register dst = $dst$$Register;
10675 __ dins(dst, R0, 1, 2);
10676 %}
10677 ins_pipe( ialu_regI_regI );
10678 %}
10680 instruct andL_Reg_immL_M4(mRegL dst, immL_M4 M4) %{
10681 match(Set dst (AndL dst M4));
10682 ins_cost(60);
10684 format %{ "and $dst, $dst, $M4 #@andL_Reg_immL_M4" %}
10685 ins_encode %{
10686 Register dst = $dst$$Register;
10688 __ dins(dst, R0, 0, 2);
10689 %}
10690 ins_pipe( ialu_regI_regI );
10691 %}
10693 instruct andL_Reg_immL_M121(mRegL dst, immL_M121 M121) %{
10694 match(Set dst (AndL dst M121));
10695 ins_cost(60);
10697 format %{ "and $dst, $dst, $M121 #@andL_Reg_immL_M121" %}
10698 ins_encode %{
10699 Register dst = $dst$$Register;
10701 __ dins(dst, R0, 3, 4);
10702 %}
10703 ins_pipe( ialu_regI_regI );
10704 %}
10706 // Or Long Register with Register
10707 instruct orL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10708 match(Set dst (OrL src1 src2));
10709 format %{ "OR $dst, $src1, $src2 @ orL_Reg_Reg\t" %}
10710 ins_encode %{
10711 Register dst_reg = $dst$$Register;
10712 Register src1_reg = $src1$$Register;
10713 Register src2_reg = $src2$$Register;
10715 __ orr(dst_reg, src1_reg, src2_reg);
10716 %}
10717 ins_pipe( ialu_regL_regL );
10718 %}
10720 instruct orL_Reg_P2XReg(mRegL dst, mRegP src1, mRegL src2) %{
10721 match(Set dst (OrL (CastP2X src1) src2));
10722 format %{ "OR $dst, $src1, $src2 @ orL_Reg_P2XReg\t" %}
10723 ins_encode %{
10724 Register dst_reg = $dst$$Register;
10725 Register src1_reg = $src1$$Register;
10726 Register src2_reg = $src2$$Register;
10728 __ orr(dst_reg, src1_reg, src2_reg);
10729 %}
10730 ins_pipe( ialu_regL_regL );
10731 %}
10733 // Xor Long Register with Register
10734 instruct xorL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10735 match(Set dst (XorL src1 src2));
10736 format %{ "XOR $dst, $src1, $src2 @ xorL_Reg_Reg\t" %}
10737 ins_encode %{
10738 Register dst_reg = as_Register($dst$$reg);
10739 Register src1_reg = as_Register($src1$$reg);
10740 Register src2_reg = as_Register($src2$$reg);
10742 __ xorr(dst_reg, src1_reg, src2_reg);
10743 %}
10744 ins_pipe( ialu_regL_regL );
10745 %}
10747 // Shift Left by 8-bit immediate
10748 instruct salI_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
10749 match(Set dst (LShiftI src shift));
10751 format %{ "SHL $dst, $src, $shift #@salI_Reg_imm" %}
10752 ins_encode %{
10753 Register src = $src$$Register;
10754 Register dst = $dst$$Register;
10755 int shamt = $shift$$constant;
10757 /*
10758 094 SHL S0, S0, #-7 #@salI_Reg_imm
10759 static int insn_RRSO(int rt, int rd, int sa, int op) { return (rt<<16) | (rd<<11) | (sa<<6) | op; }
10760 void sll (Register rd, Register rt , int sa) {
10761 emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, sll_op));
10762 }
10763 */
10765 if(0 <= shamt && shamt < 32) __ sll(dst, src, shamt);
10766 else {
10767 __ move(AT, shamt);
10768 __ sllv(dst, src, AT);
10769 }
10770 %}
10771 ins_pipe( ialu_regI_regI );
10772 %}
10774 instruct land7_2_s(mRegI dst, mRegL src, immL7 seven, immI_16 sixteen)
10775 %{
10776 match(Set dst (RShiftI (LShiftI (ConvL2I (AndL src seven)) sixteen) sixteen));
10778 format %{ "andi $dst, $src, 7\t# @land7_2_s" %}
10779 ins_encode %{
10780 Register src = $src$$Register;
10781 Register dst = $dst$$Register;
10783 __ andi(dst, src, 7);
10784 %}
10785 ins_pipe(ialu_regI_regI);
10786 %}
10788 instruct ori2s(mRegI dst, mRegI src1, immI_0_32767 src2, immI_16 sixteen)
10789 %{
10790 match(Set dst (RShiftI (LShiftI (OrI src1 src2) sixteen) sixteen));
10792 format %{ "ori $dst, $src1, $src2\t# @ori2s" %}
10793 ins_encode %{
10794 Register src = $src1$$Register;
10795 int val = $src2$$constant;
10796 Register dst = $dst$$Register;
10798 __ ori(dst, src, val);
10799 %}
10800 ins_pipe(ialu_regI_regI);
10801 %}
10803 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
10804 // This idiom is used by the compiler the i2s bytecode.
10805 instruct i2s(mRegI dst, mRegI src, immI_16 sixteen)
10806 %{
10807 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
10809 format %{ "i2s $dst, $src\t# @i2s" %}
10810 ins_encode %{
10811 Register src = $src$$Register;
10812 Register dst = $dst$$Register;
10814 __ seh(dst, src);
10815 %}
10816 ins_pipe(ialu_regI_regI);
10817 %}
10819 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
10820 // This idiom is used by the compiler for the i2b bytecode.
10821 instruct i2b(mRegI dst, mRegI src, immI_24 twentyfour)
10822 %{
10823 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
10825 format %{ "i2b $dst, $src\t# @i2b" %}
10826 ins_encode %{
10827 Register src = $src$$Register;
10828 Register dst = $dst$$Register;
10830 __ seb(dst, src);
10831 %}
10832 ins_pipe(ialu_regI_regI);
10833 %}
10836 instruct salI_RegL2I_imm(mRegI dst, mRegL src, immI8 shift) %{
10837 match(Set dst (LShiftI (ConvL2I src) shift));
10839 format %{ "SHL $dst, $src, $shift #@salI_RegL2I_imm" %}
10840 ins_encode %{
10841 Register src = $src$$Register;
10842 Register dst = $dst$$Register;
10843 int shamt = $shift$$constant;
10845 if(0 <= shamt && shamt < 32) __ sll(dst, src, shamt);
10846 else {
10847 __ move(AT, shamt);
10848 __ sllv(dst, src, AT);
10849 }
10850 %}
10851 ins_pipe( ialu_regI_regI );
10852 %}
10854 // Shift Left by 8-bit immediate
10855 instruct salI_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
10856 match(Set dst (LShiftI src shift));
10858 format %{ "SHL $dst, $src, $shift #@salI_Reg_Reg" %}
10859 ins_encode %{
10860 Register src = $src$$Register;
10861 Register dst = $dst$$Register;
10862 Register shamt = $shift$$Register;
10863 __ sllv(dst, src, shamt);
10864 %}
10865 ins_pipe( ialu_regI_regI );
10866 %}
10869 // Shift Left Long
10870 instruct salL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
10871 //predicate(UseNewLongLShift);
10872 match(Set dst (LShiftL src shift));
10873 ins_cost(100);
10874 format %{ "salL $dst, $src, $shift @ salL_Reg_imm" %}
10875 ins_encode %{
10876 Register src_reg = as_Register($src$$reg);
10877 Register dst_reg = as_Register($dst$$reg);
10878 int shamt = $shift$$constant;
10880 if (__ is_simm(shamt, 5))
10881 __ dsll(dst_reg, src_reg, shamt);
10882 else
10883 {
10884 __ move(AT, shamt);
10885 __ dsllv(dst_reg, src_reg, AT);
10886 }
10887 %}
10888 ins_pipe( ialu_regL_regL );
10889 %}
10891 instruct salL_RegI2L_imm(mRegL dst, mRegI src, immI8 shift) %{
10892 //predicate(UseNewLongLShift);
10893 match(Set dst (LShiftL (ConvI2L src) shift));
10894 ins_cost(100);
10895 format %{ "salL $dst, $src, $shift @ salL_RegI2L_imm" %}
10896 ins_encode %{
10897 Register src_reg = as_Register($src$$reg);
10898 Register dst_reg = as_Register($dst$$reg);
10899 int shamt = $shift$$constant;
10901 if (__ is_simm(shamt, 5))
10902 __ dsll(dst_reg, src_reg, shamt);
10903 else
10904 {
10905 __ move(AT, shamt);
10906 __ dsllv(dst_reg, src_reg, AT);
10907 }
10908 %}
10909 ins_pipe( ialu_regL_regL );
10910 %}
10912 // Shift Left Long
10913 instruct salL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
10914 //predicate(UseNewLongLShift);
10915 match(Set dst (LShiftL src shift));
10916 ins_cost(100);
10917 format %{ "salL $dst, $src, $shift @ salL_Reg_Reg" %}
10918 ins_encode %{
10919 Register src_reg = as_Register($src$$reg);
10920 Register dst_reg = as_Register($dst$$reg);
10922 __ dsllv(dst_reg, src_reg, $shift$$Register);
10923 %}
10924 ins_pipe( ialu_regL_regL );
10925 %}
10927 instruct salL_convI2L_Reg_imm(mRegL dst, mRegI src, immI8 shift) %{
10928 match(Set dst (LShiftL (ConvI2L src) shift));
10929 ins_cost(100);
10930 format %{ "salL $dst, $src, $shift @ salL_convI2L_Reg_imm" %}
10931 ins_encode %{
10932 Register src_reg = as_Register($src$$reg);
10933 Register dst_reg = as_Register($dst$$reg);
10934 int shamt = $shift$$constant;
10936 if (__ is_simm(shamt, 5)) {
10937 __ dsll(dst_reg, src_reg, shamt);
10938 } else {
10939 __ move(AT, shamt);
10940 __ dsllv(dst_reg, src_reg, AT);
10941 }
10942 %}
10943 ins_pipe( ialu_regL_regL );
10944 %}
10946 // Shift Right Long
10947 instruct sarL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
10948 //predicate(UseNewLongLShift);
10949 match(Set dst (RShiftL src shift));
10950 ins_cost(100);
10951 format %{ "sarL $dst, $src, $shift @ sarL_Reg_imm" %}
10952 ins_encode %{
10953 Register src_reg = as_Register($src$$reg);
10954 Register dst_reg = as_Register($dst$$reg);
10955 int shamt = ($shift$$constant & 0x3f);
10956 if (__ is_simm(shamt, 5))
10957 __ dsra(dst_reg, src_reg, shamt);
10958 else
10959 {
10960 __ move(AT, shamt);
10961 __ dsrav(dst_reg, src_reg, AT);
10962 }
10963 %}
10964 ins_pipe( ialu_regL_regL );
10965 %}
10967 // Shift Right Long arithmetically
10968 instruct sarL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
10969 //predicate(UseNewLongLShift);
10970 match(Set dst (RShiftL src shift));
10971 ins_cost(100);
10972 format %{ "sarL $dst, $src, $shift @ sarL_Reg_Reg" %}
10973 ins_encode %{
10974 Register creg = T9;
10975 Register src_reg = as_Register($src$$reg);
10976 Register dst_reg = as_Register($dst$$reg);
10978 __ move(creg, $shift$$Register);
10979 __ andi(creg, creg, 0x3f);
10980 __ dsrav(dst_reg, src_reg, creg);
10981 %}
10982 ins_pipe( ialu_regL_regL );
10983 %}
10985 // Shift Right Long logically
10986 instruct slrL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
10987 match(Set dst (URShiftL src shift));
10988 ins_cost(100);
10989 format %{ "slrL $dst, $src, $shift @ slrL_Reg_Reg" %}
10990 ins_encode %{
10991 Register creg = T9;
10992 Register src_reg = as_Register($src$$reg);
10993 Register dst_reg = as_Register($dst$$reg);
10995 __ move(creg, $shift$$Register);
10996 __ andi(creg, creg, 0x3f);
10997 __ dsrlv(dst_reg, src_reg, creg);
10998 %}
10999 ins_pipe( ialu_regL_regL );
11000 %}
11002 instruct slrL_Reg_immI_0_31(mRegL dst, mRegL src, immI_0_31 shift) %{
11003 match(Set dst (URShiftL src shift));
11004 ins_cost(80);
11005 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_0_31" %}
11006 ins_encode %{
11007 Register src_reg = as_Register($src$$reg);
11008 Register dst_reg = as_Register($dst$$reg);
11009 int shamt = $shift$$constant;
11011 __ dsrl(dst_reg, src_reg, shamt);
11012 %}
11013 ins_pipe( ialu_regL_regL );
11014 %}
11016 instruct slrL_P2XReg_immI_0_31(mRegL dst, mRegP src, immI_0_31 shift) %{
11017 match(Set dst (URShiftL (CastP2X src) shift));
11018 ins_cost(80);
11019 format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_0_31" %}
11020 ins_encode %{
11021 Register src_reg = as_Register($src$$reg);
11022 Register dst_reg = as_Register($dst$$reg);
11023 int shamt = $shift$$constant;
11025 __ dsrl(dst_reg, src_reg, shamt);
11026 %}
11027 ins_pipe( ialu_regL_regL );
11028 %}
11030 instruct slrL_Reg_immI_32_63(mRegL dst, mRegL src, immI_32_63 shift) %{
11031 match(Set dst (URShiftL src shift));
11032 ins_cost(80);
11033 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_32_63" %}
11034 ins_encode %{
11035 Register src_reg = as_Register($src$$reg);
11036 Register dst_reg = as_Register($dst$$reg);
11037 int shamt = $shift$$constant;
11039 __ dsrl32(dst_reg, src_reg, shamt - 32);
11040 %}
11041 ins_pipe( ialu_regL_regL );
11042 %}
11044 instruct slrL_P2XReg_immI_32_63(mRegL dst, mRegP src, immI_32_63 shift) %{
11045 match(Set dst (URShiftL (CastP2X src) shift));
11046 ins_cost(80);
11047 format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_32_63" %}
11048 ins_encode %{
11049 Register src_reg = as_Register($src$$reg);
11050 Register dst_reg = as_Register($dst$$reg);
11051 int shamt = $shift$$constant;
11053 __ dsrl32(dst_reg, src_reg, shamt - 32);
11054 %}
11055 ins_pipe( ialu_regL_regL );
11056 %}
11058 // Xor Instructions
11059 // Xor Register with Register
11060 instruct xorI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
11061 match(Set dst (XorI src1 src2));
11063 format %{ "XOR $dst, $src1, $src2 #@xorI_Reg_Reg" %}
11065 ins_encode %{
11066 Register dst = $dst$$Register;
11067 Register src1 = $src1$$Register;
11068 Register src2 = $src2$$Register;
11069 __ xorr(dst, src1, src2);
11070 __ sll(dst, dst, 0); /* long -> int */
11071 %}
11073 ins_pipe( ialu_regI_regI );
11074 %}
11076 // Or Instructions
11077 // Or Register with Register
11078 instruct orI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
11079 match(Set dst (OrI src1 src2));
11081 format %{ "OR $dst, $src1, $src2 #@orI_Reg_Reg" %}
11082 ins_encode %{
11083 Register dst = $dst$$Register;
11084 Register src1 = $src1$$Register;
11085 Register src2 = $src2$$Register;
11086 __ orr(dst, src1, src2);
11087 %}
11089 ins_pipe( ialu_regI_regI );
11090 %}
11092 instruct orI_Reg_castP2X(mRegL dst, mRegL src1, mRegP src2) %{
11093 match(Set dst (OrI src1 (CastP2X src2)));
11095 format %{ "OR $dst, $src1, $src2 #@orI_Reg_castP2X" %}
11096 ins_encode %{
11097 Register dst = $dst$$Register;
11098 Register src1 = $src1$$Register;
11099 Register src2 = $src2$$Register;
11100 __ orr(dst, src1, src2);
11101 %}
11103 ins_pipe( ialu_regI_regI );
11104 %}
11106 // Logical Shift Right by 8-bit immediate
11107 instruct shr_logical_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
11108 match(Set dst (URShiftI src shift));
11109 // effect(KILL cr);
11111 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_imm" %}
11112 ins_encode %{
11113 Register src = $src$$Register;
11114 Register dst = $dst$$Register;
11115 int shift = $shift$$constant;
11116 if (shift > 0)
11117 __ srl(dst, src, shift);
11118 else
11119 {
11120 __ move(AT, shift);
11121 __ srlv(dst, src, AT);
11122 }
11123 %}
11124 ins_pipe( ialu_regI_regI );
11125 %}
11127 instruct shr_logical_Reg_imm_nonneg_mask(mRegI dst, mRegI src, immI_0_31 shift, immI_nonneg_mask mask) %{
11128 match(Set dst (AndI (URShiftI src shift) mask));
11130 format %{ "ext $dst, $src, $shift, one-bits($mask) #@shr_logical_Reg_imm_nonneg_mask" %}
11131 ins_encode %{
11132 Register src = $src$$Register;
11133 Register dst = $dst$$Register;
11134 int pos = $shift$$constant;
11135 int size = Assembler::is_int_mask($mask$$constant);
11137 __ ext(dst, src, pos, size);
11138 %}
11139 ins_pipe( ialu_regI_regI );
11140 %}
11142 instruct rolI_Reg_immI_0_31(mRegI dst, immI_0_31 lshift, immI_0_31 rshift)
11143 %{
11144 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
11145 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
11147 ins_cost(100);
11148 format %{ "rotr $dst, $dst, $rshift #@rolI_Reg_immI_0_31" %}
11149 ins_encode %{
11150 Register dst = $dst$$Register;
11151 int sa = $rshift$$constant;
11153 __ rotr(dst, dst, sa);
11154 %}
11155 ins_pipe( ialu_regI_regI );
11156 %}
11158 instruct rorI_Reg_immI_0_31(mRegI dst, immI_0_31 rshift, immI_0_31 lshift)
11159 %{
11160 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
11161 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
11163 ins_cost(100);
11164 format %{ "rotr $dst, $dst, $rshift #@rorI_Reg_immI_0_31" %}
11165 ins_encode %{
11166 Register dst = $dst$$Register;
11167 int sa = $rshift$$constant;
11169 __ rotr(dst, dst, sa);
11170 %}
11171 ins_pipe( ialu_regI_regI );
11172 %}
11174 // Logical Shift Right
11175 instruct shr_logical_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
11176 match(Set dst (URShiftI src shift));
11178 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_Reg" %}
11179 ins_encode %{
11180 Register src = $src$$Register;
11181 Register dst = $dst$$Register;
11182 Register shift = $shift$$Register;
11183 __ srlv(dst, src, shift);
11184 %}
11185 ins_pipe( ialu_regI_regI );
11186 %}
11189 instruct shr_arith_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
11190 match(Set dst (RShiftI src shift));
11191 // effect(KILL cr);
11193 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_imm" %}
11194 ins_encode %{
11195 Register src = $src$$Register;
11196 Register dst = $dst$$Register;
11197 int shift = $shift$$constant;
11198 __ sra(dst, src, shift);
11199 %}
11200 ins_pipe( ialu_regI_regI );
11201 %}
11203 instruct shr_arith_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
11204 match(Set dst (RShiftI src shift));
11205 // effect(KILL cr);
11207 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_Reg" %}
11208 ins_encode %{
11209 Register src = $src$$Register;
11210 Register dst = $dst$$Register;
11211 Register shift = $shift$$Register;
11212 __ srav(dst, src, shift);
11213 %}
11214 ins_pipe( ialu_regI_regI );
11215 %}
11217 //----------Convert Int to Boolean---------------------------------------------
11219 instruct convI2B(mRegI dst, mRegI src) %{
11220 match(Set dst (Conv2B src));
11222 ins_cost(100);
11223 format %{ "convI2B $dst, $src @ convI2B" %}
11224 ins_encode %{
11225 Register dst = as_Register($dst$$reg);
11226 Register src = as_Register($src$$reg);
11228 if (dst != src) {
11229 __ daddiu(dst, R0, 1);
11230 __ movz(dst, R0, src);
11231 } else {
11232 __ move(AT, src);
11233 __ daddiu(dst, R0, 1);
11234 __ movz(dst, R0, AT);
11235 }
11236 %}
11238 ins_pipe( ialu_regL_regL );
11239 %}
11241 instruct convI2L_reg( mRegL dst, mRegI src) %{
11242 match(Set dst (ConvI2L src));
11244 ins_cost(100);
11245 format %{ "SLL $dst, $src @ convI2L_reg\t" %}
11246 ins_encode %{
11247 Register dst = as_Register($dst$$reg);
11248 Register src = as_Register($src$$reg);
11250 if(dst != src) __ sll(dst, src, 0);
11251 %}
11252 ins_pipe( ialu_regL_regL );
11253 %}
11256 instruct convL2I_reg( mRegI dst, mRegL src ) %{
11257 match(Set dst (ConvL2I src));
11259 format %{ "MOV $dst, $src @ convL2I_reg" %}
11260 ins_encode %{
11261 Register dst = as_Register($dst$$reg);
11262 Register src = as_Register($src$$reg);
11264 __ sll(dst, src, 0);
11265 %}
11267 ins_pipe( ialu_regI_regI );
11268 %}
11270 instruct convL2I2L_reg( mRegL dst, mRegL src ) %{
11271 match(Set dst (ConvI2L (ConvL2I src)));
11273 format %{ "sll $dst, $src, 0 @ convL2I2L_reg" %}
11274 ins_encode %{
11275 Register dst = as_Register($dst$$reg);
11276 Register src = as_Register($src$$reg);
11278 __ sll(dst, src, 0);
11279 %}
11281 ins_pipe( ialu_regI_regI );
11282 %}
11284 instruct convL2D_reg( regD dst, mRegL src ) %{
11285 match(Set dst (ConvL2D src));
11286 format %{ "convL2D $dst, $src @ convL2D_reg" %}
11287 ins_encode %{
11288 Register src = as_Register($src$$reg);
11289 FloatRegister dst = as_FloatRegister($dst$$reg);
11291 __ dmtc1(src, dst);
11292 __ cvt_d_l(dst, dst);
11293 %}
11295 ins_pipe( pipe_slow );
11296 %}
11298 instruct convD2L_reg_fast( mRegL dst, regD src ) %{
11299 match(Set dst (ConvD2L src));
11300 ins_cost(150);
11301 format %{ "convD2L $dst, $src @ convD2L_reg_fast" %}
11302 ins_encode %{
11303 Register dst = as_Register($dst$$reg);
11304 FloatRegister src = as_FloatRegister($src$$reg);
11306 Label Done;
11308 __ trunc_l_d(F30, src);
11309 // max_long: 0x7fffffffffffffff
11310 // __ set64(AT, 0x7fffffffffffffff);
11311 __ daddiu(AT, R0, -1);
11312 __ dsrl(AT, AT, 1);
11313 __ dmfc1(dst, F30);
11315 __ bne(dst, AT, Done);
11316 __ delayed()->mtc1(R0, F30);
11318 __ cvt_d_w(F30, F30);
11319 __ c_ult_d(src, F30);
11320 __ bc1f(Done);
11321 __ delayed()->daddiu(T9, R0, -1);
11323 __ c_un_d(src, src); //NaN?
11324 __ subu(dst, T9, AT);
11325 __ movt(dst, R0);
11327 __ bind(Done);
11328 %}
11330 ins_pipe( pipe_slow );
11331 %}
11333 instruct convD2L_reg_slow( mRegL dst, regD src ) %{
11334 match(Set dst (ConvD2L src));
11335 ins_cost(250);
11336 format %{ "convD2L $dst, $src @ convD2L_reg_slow" %}
11337 ins_encode %{
11338 Register dst = as_Register($dst$$reg);
11339 FloatRegister src = as_FloatRegister($src$$reg);
11341 Label L;
11343 __ c_un_d(src, src); //NaN?
11344 __ bc1t(L);
11345 __ delayed();
11346 __ move(dst, R0);
11348 __ trunc_l_d(F30, src);
11349 __ cfc1(AT, 31);
11350 __ li(T9, 0x10000);
11351 __ andr(AT, AT, T9);
11352 __ beq(AT, R0, L);
11353 __ delayed()->dmfc1(dst, F30);
11355 __ mov_d(F12, src);
11356 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l), 1);
11357 __ move(dst, V0);
11358 __ bind(L);
11359 %}
11361 ins_pipe( pipe_slow );
11362 %}
11364 instruct convF2I_reg_fast( mRegI dst, regF src ) %{
11365 match(Set dst (ConvF2I src));
11366 ins_cost(150);
11367 format %{ "convf2i $dst, $src @ convF2I_reg_fast" %}
11368 ins_encode %{
11369 Register dreg = $dst$$Register;
11370 FloatRegister fval = $src$$FloatRegister;
11372 __ trunc_w_s(F30, fval);
11373 __ mfc1(dreg, F30);
11374 __ c_un_s(fval, fval); //NaN?
11375 __ movt(dreg, R0);
11376 %}
11378 ins_pipe( pipe_slow );
11379 %}
11381 instruct convF2I_reg_slow( mRegI dst, regF src ) %{
11382 match(Set dst (ConvF2I src));
11383 ins_cost(250);
11384 format %{ "convf2i $dst, $src @ convF2I_reg_slow" %}
11385 ins_encode %{
11386 Register dreg = $dst$$Register;
11387 FloatRegister fval = $src$$FloatRegister;
11388 Label L;
11390 __ c_un_s(fval, fval); //NaN?
11391 __ bc1t(L);
11392 __ delayed();
11393 __ move(dreg, R0);
11395 __ trunc_w_s(F30, fval);
11397 /* Call SharedRuntime:f2i() to do valid convention */
11398 __ cfc1(AT, 31);
11399 __ li(T9, 0x10000);
11400 __ andr(AT, AT, T9);
11401 __ beq(AT, R0, L);
11402 __ delayed()->mfc1(dreg, F30);
11404 __ mov_s(F12, fval);
11406 /* 2014/01/08 Fu : This bug was found when running ezDS's control-panel.
11407 * J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
11408 *
11409 * An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
11410 * V0 is corrupted during call_VM_leaf(), and should be preserved.
11411 */
11412 if(dreg != V0) {
11413 __ push(V0);
11414 }
11415 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), 1);
11416 if(dreg != V0) {
11417 __ move(dreg, V0);
11418 __ pop(V0);
11419 }
11420 __ bind(L);
11421 %}
11423 ins_pipe( pipe_slow );
11424 %}
11426 instruct convF2L_reg_fast( mRegL dst, regF src ) %{
11427 match(Set dst (ConvF2L src));
11428 ins_cost(150);
11429 format %{ "convf2l $dst, $src @ convF2L_reg_fast" %}
11430 ins_encode %{
11431 Register dreg = $dst$$Register;
11432 FloatRegister fval = $src$$FloatRegister;
11434 __ trunc_l_s(F30, fval);
11435 __ dmfc1(dreg, F30);
11436 __ c_un_s(fval, fval); //NaN?
11437 __ movt(dreg, R0);
11438 %}
11440 ins_pipe( pipe_slow );
11441 %}
11443 instruct convF2L_reg_slow( mRegL dst, regF src ) %{
11444 match(Set dst (ConvF2L src));
11445 ins_cost(250);
11446 format %{ "convf2l $dst, $src @ convF2L_reg_slow" %}
11447 ins_encode %{
11448 Register dst = as_Register($dst$$reg);
11449 FloatRegister fval = $src$$FloatRegister;
11450 Label L;
11452 __ c_un_s(fval, fval); //NaN?
11453 __ bc1t(L);
11454 __ delayed();
11455 __ move(dst, R0);
11457 __ trunc_l_s(F30, fval);
11458 __ cfc1(AT, 31);
11459 __ li(T9, 0x10000);
11460 __ andr(AT, AT, T9);
11461 __ beq(AT, R0, L);
11462 __ delayed()->dmfc1(dst, F30);
11464 __ mov_s(F12, fval);
11465 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l), 1);
11466 __ move(dst, V0);
11467 __ bind(L);
11468 %}
11470 ins_pipe( pipe_slow );
11471 %}
11473 instruct convL2F_reg( regF dst, mRegL src ) %{
11474 match(Set dst (ConvL2F src));
11475 format %{ "convl2f $dst, $src @ convL2F_reg" %}
11476 ins_encode %{
11477 FloatRegister dst = $dst$$FloatRegister;
11478 Register src = as_Register($src$$reg);
11479 Label L;
11481 __ dmtc1(src, dst);
11482 __ cvt_s_l(dst, dst);
11483 %}
11485 ins_pipe( pipe_slow );
11486 %}
11488 instruct convI2F_reg( regF dst, mRegI src ) %{
11489 match(Set dst (ConvI2F src));
11490 format %{ "convi2f $dst, $src @ convI2F_reg" %}
11491 ins_encode %{
11492 Register src = $src$$Register;
11493 FloatRegister dst = $dst$$FloatRegister;
11495 __ mtc1(src, dst);
11496 __ cvt_s_w(dst, dst);
11497 %}
11499 ins_pipe( fpu_regF_regF );
11500 %}
11502 instruct cmpLTMask_immI0( mRegI dst, mRegI p, immI0 zero ) %{
11503 match(Set dst (CmpLTMask p zero));
11504 ins_cost(100);
11506 format %{ "sra $dst, $p, 31 @ cmpLTMask_immI0" %}
11507 ins_encode %{
11508 Register src = $p$$Register;
11509 Register dst = $dst$$Register;
11511 __ sra(dst, src, 31);
11512 %}
11513 ins_pipe( pipe_slow );
11514 %}
11517 instruct cmpLTMask( mRegI dst, mRegI p, mRegI q ) %{
11518 match(Set dst (CmpLTMask p q));
11519 ins_cost(400);
11521 format %{ "cmpLTMask $dst, $p, $q @ cmpLTMask" %}
11522 ins_encode %{
11523 Register p = $p$$Register;
11524 Register q = $q$$Register;
11525 Register dst = $dst$$Register;
11527 __ slt(dst, p, q);
11528 __ subu(dst, R0, dst);
11529 %}
11530 ins_pipe( pipe_slow );
11531 %}
11533 instruct convP2B(mRegI dst, mRegP src) %{
11534 match(Set dst (Conv2B src));
11536 ins_cost(100);
11537 format %{ "convP2B $dst, $src @ convP2B" %}
11538 ins_encode %{
11539 Register dst = as_Register($dst$$reg);
11540 Register src = as_Register($src$$reg);
11542 if (dst != src) {
11543 __ daddiu(dst, R0, 1);
11544 __ movz(dst, R0, src);
11545 } else {
11546 __ move(AT, src);
11547 __ daddiu(dst, R0, 1);
11548 __ movz(dst, R0, AT);
11549 }
11550 %}
11552 ins_pipe( ialu_regL_regL );
11553 %}
11556 instruct convI2D_reg_reg(regD dst, mRegI src) %{
11557 match(Set dst (ConvI2D src));
11558 format %{ "conI2D $dst, $src @convI2D_reg" %}
11559 ins_encode %{
11560 Register src = $src$$Register;
11561 FloatRegister dst = $dst$$FloatRegister;
11562 __ mtc1(src, dst);
11563 __ cvt_d_w(dst, dst);
11564 %}
11565 ins_pipe( fpu_regF_regF );
11566 %}
11568 instruct convF2D_reg_reg(regD dst, regF src) %{
11569 match(Set dst (ConvF2D src));
11570 format %{ "convF2D $dst, $src\t# @convF2D_reg_reg" %}
11571 ins_encode %{
11572 FloatRegister dst = $dst$$FloatRegister;
11573 FloatRegister src = $src$$FloatRegister;
11575 __ cvt_d_s(dst, src);
11576 %}
11577 ins_pipe( fpu_regF_regF );
11578 %}
11580 instruct convD2F_reg_reg(regF dst, regD src) %{
11581 match(Set dst (ConvD2F src));
11582 format %{ "convD2F $dst, $src\t# @convD2F_reg_reg" %}
11583 ins_encode %{
11584 FloatRegister dst = $dst$$FloatRegister;
11585 FloatRegister src = $src$$FloatRegister;
11587 __ cvt_s_d(dst, src);
11588 %}
11589 ins_pipe( fpu_regF_regF );
11590 %}
11592 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11593 instruct convD2I_reg_reg_fast( mRegI dst, regD src ) %{
11594 match(Set dst (ConvD2I src));
11596 ins_cost(150);
11597 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_fast" %}
11599 ins_encode %{
11600 FloatRegister src = $src$$FloatRegister;
11601 Register dst = $dst$$Register;
11603 Label Done;
11605 __ trunc_w_d(F30, src);
11606 // max_int: 2147483647
11607 __ move(AT, 0x7fffffff);
11608 __ mfc1(dst, F30);
11610 __ bne(dst, AT, Done);
11611 __ delayed()->mtc1(R0, F30);
11613 __ cvt_d_w(F30, F30);
11614 __ c_ult_d(src, F30);
11615 __ bc1f(Done);
11616 __ delayed()->addiu(T9, R0, -1);
11618 __ c_un_d(src, src); //NaN?
11619 __ subu32(dst, T9, AT);
11620 __ movt(dst, R0);
11622 __ bind(Done);
11623 %}
11624 ins_pipe( pipe_slow );
11625 %}
11627 instruct convD2I_reg_reg_slow( mRegI dst, regD src ) %{
11628 match(Set dst (ConvD2I src));
11630 ins_cost(250);
11631 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_slow" %}
11633 ins_encode %{
11634 FloatRegister src = $src$$FloatRegister;
11635 Register dst = $dst$$Register;
11636 Label L;
11638 __ trunc_w_d(F30, src);
11639 __ cfc1(AT, 31);
11640 __ li(T9, 0x10000);
11641 __ andr(AT, AT, T9);
11642 __ beq(AT, R0, L);
11643 __ delayed()->mfc1(dst, F30);
11645 __ mov_d(F12, src);
11646 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 1);
11647 __ move(dst, V0);
11648 __ bind(L);
11650 %}
11651 ins_pipe( pipe_slow );
11652 %}
11654 // Convert oop pointer into compressed form
11655 instruct encodeHeapOop(mRegN dst, mRegP src) %{
11656 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
11657 match(Set dst (EncodeP src));
11658 format %{ "encode_heap_oop $dst,$src" %}
11659 ins_encode %{
11660 Register src = $src$$Register;
11661 Register dst = $dst$$Register;
11662 if (src != dst) {
11663 __ move(dst, src);
11664 }
11665 __ encode_heap_oop(dst);
11666 %}
11667 ins_pipe( ialu_regL_regL );
11668 %}
11670 instruct encodeHeapOop_not_null(mRegN dst, mRegP src) %{
11671 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
11672 match(Set dst (EncodeP src));
11673 format %{ "encode_heap_oop_not_null $dst,$src @ encodeHeapOop_not_null" %}
11674 ins_encode %{
11675 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
11676 %}
11677 ins_pipe( ialu_regL_regL );
11678 %}
11680 instruct decodeHeapOop(mRegP dst, mRegN src) %{
11681 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
11682 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
11683 match(Set dst (DecodeN src));
11684 format %{ "decode_heap_oop $dst,$src @ decodeHeapOop" %}
11685 ins_encode %{
11686 Register s = $src$$Register;
11687 Register d = $dst$$Register;
11688 if (s != d) {
11689 __ move(d, s);
11690 }
11691 __ decode_heap_oop(d);
11692 %}
11693 ins_pipe( ialu_regL_regL );
11694 %}
11696 instruct decodeHeapOop_not_null(mRegP dst, mRegN src) %{
11697 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
11698 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
11699 match(Set dst (DecodeN src));
11700 format %{ "decode_heap_oop_not_null $dst,$src @ decodeHeapOop_not_null" %}
11701 ins_encode %{
11702 Register s = $src$$Register;
11703 Register d = $dst$$Register;
11704 if (s != d) {
11705 __ decode_heap_oop_not_null(d, s);
11706 } else {
11707 __ decode_heap_oop_not_null(d);
11708 }
11709 %}
11710 ins_pipe( ialu_regL_regL );
11711 %}
11713 instruct encodeKlass_not_null(mRegN dst, mRegP src) %{
11714 match(Set dst (EncodePKlass src));
11715 format %{ "encode_heap_oop_not_null $dst,$src @ encodeKlass_not_null" %}
11716 ins_encode %{
11717 __ encode_klass_not_null($dst$$Register, $src$$Register);
11718 %}
11719 ins_pipe( ialu_regL_regL );
11720 %}
11722 instruct decodeKlass_not_null(mRegP dst, mRegN src) %{
11723 match(Set dst (DecodeNKlass src));
11724 format %{ "decode_heap_klass_not_null $dst,$src" %}
11725 ins_encode %{
11726 Register s = $src$$Register;
11727 Register d = $dst$$Register;
11728 if (s != d) {
11729 __ decode_klass_not_null(d, s);
11730 } else {
11731 __ decode_klass_not_null(d);
11732 }
11733 %}
11734 ins_pipe( ialu_regL_regL );
11735 %}
11737 //FIXME
11738 instruct tlsLoadP(mRegP dst) %{
11739 match(Set dst (ThreadLocal));
11741 ins_cost(0);
11742 format %{ " get_thread in $dst #@tlsLoadP" %}
11743 ins_encode %{
11744 Register dst = $dst$$Register;
11745 #ifdef OPT_THREAD
11746 __ move(dst, TREG);
11747 #else
11748 __ get_thread(dst);
11749 #endif
11750 %}
11752 ins_pipe( ialu_loadI );
11753 %}
11756 instruct checkCastPP( mRegP dst ) %{
11757 match(Set dst (CheckCastPP dst));
11759 format %{ "#checkcastPP of $dst (empty encoding) #@chekCastPP" %}
11760 ins_encode( /*empty encoding*/ );
11761 ins_pipe( empty );
11762 %}
11764 instruct castPP(mRegP dst)
11765 %{
11766 match(Set dst (CastPP dst));
11768 size(0);
11769 format %{ "# castPP of $dst" %}
11770 ins_encode(/* empty encoding */);
11771 ins_pipe(empty);
11772 %}
11774 instruct castII( mRegI dst ) %{
11775 match(Set dst (CastII dst));
11776 format %{ "#castII of $dst empty encoding" %}
11777 ins_encode( /*empty encoding*/ );
11778 ins_cost(0);
11779 ins_pipe( empty );
11780 %}
11782 // Return Instruction
11783 // Remove the return address & jump to it.
11784 instruct Ret() %{
11785 match(Return);
11786 format %{ "RET #@Ret" %}
11788 ins_encode %{
11789 __ jr(RA);
11790 __ nop();
11791 %}
11793 ins_pipe( pipe_jump );
11794 %}
11796 /*
11797 // For Loongson CPUs, jr seems too slow, so this rule shouldn't be imported.
11798 instruct jumpXtnd(mRegL switch_val) %{
11799 match(Jump switch_val);
11801 ins_cost(350);
11803 format %{ "load T9 <-- [$constanttablebase, $switch_val, $constantoffset] @ jumpXtnd\n\t"
11804 "jr T9\n\t"
11805 "nop" %}
11806 ins_encode %{
11807 Register table_base = $constanttablebase;
11808 int con_offset = $constantoffset;
11809 Register switch_reg = $switch_val$$Register;
11811 if (UseLoongsonISA) {
11812 if (Assembler::is_simm(con_offset, 8)) {
11813 __ gsldx(T9, table_base, switch_reg, con_offset);
11814 } else if (Assembler::is_simm16(con_offset)) {
11815 __ daddu(T9, table_base, switch_reg);
11816 __ ld(T9, T9, con_offset);
11817 } else {
11818 __ move(T9, con_offset);
11819 __ daddu(AT, table_base, switch_reg);
11820 __ gsldx(T9, AT, T9, 0);
11821 }
11822 } else {
11823 if (Assembler::is_simm16(con_offset)) {
11824 __ daddu(T9, table_base, switch_reg);
11825 __ ld(T9, T9, con_offset);
11826 } else {
11827 __ move(T9, con_offset);
11828 __ daddu(AT, table_base, switch_reg);
11829 __ daddu(AT, T9, AT);
11830 __ ld(T9, AT, 0);
11831 }
11832 }
11834 __ jr(T9);
11835 __ nop();
11837 %}
11838 ins_pipe(pipe_jump);
11839 %}
11840 */
11842 // Jump Direct - Label defines a relative address from JMP
11843 instruct jmpDir(label labl) %{
11844 match(Goto);
11845 effect(USE labl);
11847 ins_cost(300);
11848 format %{ "JMP $labl #@jmpDir" %}
11850 ins_encode %{
11851 Label &L = *($labl$$label);
11852 if(&L)
11853 __ b(L);
11854 else
11855 __ b(int(0));
11856 __ nop();
11857 %}
11859 ins_pipe( pipe_jump );
11860 ins_pc_relative(1);
11861 %}
11865 // Tail Jump; remove the return address; jump to target.
11866 // TailCall above leaves the return address around.
11867 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11868 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11869 // "restore" before this instruction (in Epilogue), we need to materialize it
11870 // in %i0.
11871 //FIXME
11872 instruct tailjmpInd(mRegP jump_target,mRegP ex_oop) %{
11873 match( TailJump jump_target ex_oop );
11874 ins_cost(200);
11875 format %{ "Jmp $jump_target ; ex_oop = $ex_oop #@tailjmpInd" %}
11876 ins_encode %{
11877 Register target = $jump_target$$Register;
11879 /* 2012/9/14 Jin: V0, V1 are indicated in:
11880 * [stubGenerator_mips.cpp] generate_forward_exception()
11881 * [runtime_mips.cpp] OptoRuntime::generate_exception_blob()
11882 */
11883 Register oop = $ex_oop$$Register;
11884 Register exception_oop = V0;
11885 Register exception_pc = V1;
11887 __ move(exception_pc, RA);
11888 __ move(exception_oop, oop);
11890 __ jr(target);
11891 __ nop();
11892 %}
11893 ins_pipe( pipe_jump );
11894 %}
11896 // ============================================================================
11897 // Procedure Call/Return Instructions
11898 // Call Java Static Instruction
11899 // Note: If this code changes, the corresponding ret_addr_offset() and
11900 // compute_padding() functions will have to be adjusted.
11901 instruct CallStaticJavaDirect(method meth) %{
11902 match(CallStaticJava);
11903 effect(USE meth);
11905 ins_cost(300);
11906 format %{ "CALL,static #@CallStaticJavaDirect " %}
11907 ins_encode( Java_Static_Call( meth ) );
11908 ins_pipe( pipe_slow );
11909 ins_pc_relative(1);
11910 ins_alignment(16);
11911 %}
11913 // Call Java Dynamic Instruction
11914 // Note: If this code changes, the corresponding ret_addr_offset() and
11915 // compute_padding() functions will have to be adjusted.
11916 instruct CallDynamicJavaDirect(method meth) %{
11917 match(CallDynamicJava);
11918 effect(USE meth);
11920 ins_cost(300);
11921 format %{"MOV IC_Klass, (oop)-1 @ CallDynamicJavaDirect\n\t"
11922 "CallDynamic @ CallDynamicJavaDirect" %}
11923 ins_encode( Java_Dynamic_Call( meth ) );
11924 ins_pipe( pipe_slow );
11925 ins_pc_relative(1);
11926 ins_alignment(16);
11927 %}
11929 instruct CallLeafNoFPDirect(method meth) %{
11930 match(CallLeafNoFP);
11931 effect(USE meth);
11933 ins_cost(300);
11934 format %{ "CALL_LEAF_NOFP,runtime " %}
11935 ins_encode(Java_To_Runtime(meth));
11936 ins_pipe( pipe_slow );
11937 ins_pc_relative(1);
11938 ins_alignment(16);
11939 %}
11941 // Prefetch instructions.
11943 instruct prefetchrNTA( memory mem ) %{
11944 match(PrefetchRead mem);
11945 ins_cost(125);
11947 format %{ "pref $mem\t# Prefetch into non-temporal cache for read @ prefetchrNTA" %}
11948 ins_encode %{
11949 int base = $mem$$base;
11950 int index = $mem$$index;
11951 int scale = $mem$$scale;
11952 int disp = $mem$$disp;
11954 if( index != 0 ) {
11955 if (scale == 0) {
11956 __ daddu(AT, as_Register(base), as_Register(index));
11957 } else {
11958 __ dsll(AT, as_Register(index), scale);
11959 __ daddu(AT, as_Register(base), AT);
11960 }
11961 } else {
11962 __ move(AT, as_Register(base));
11963 }
11964 if( Assembler::is_simm16(disp) ) {
11965 __ daddiu(AT, as_Register(base), disp);
11966 __ daddiu(AT, AT, disp);
11967 } else {
11968 __ move(T9, disp);
11969 __ daddu(AT, as_Register(base), T9);
11970 }
11971 __ pref(0, AT, 0); //hint: 0:load
11972 %}
11973 ins_pipe(pipe_slow);
11974 %}
11976 instruct prefetchwNTA( memory mem ) %{
11977 match(PrefetchWrite mem);
11978 ins_cost(125);
11979 format %{ "pref $mem\t# Prefetch to non-temporal cache for write @ prefetchwNTA" %}
11980 ins_encode %{
11981 int base = $mem$$base;
11982 int index = $mem$$index;
11983 int scale = $mem$$scale;
11984 int disp = $mem$$disp;
11986 if( index != 0 ) {
11987 if (scale == 0) {
11988 __ daddu(AT, as_Register(base), as_Register(index));
11989 } else {
11990 __ dsll(AT, as_Register(index), scale);
11991 __ daddu(AT, as_Register(base), AT);
11992 }
11993 } else {
11994 __ move(AT, as_Register(base));
11995 }
11996 if( Assembler::is_simm16(disp) ) {
11997 __ daddiu(AT, as_Register(base), disp);
11998 __ daddiu(AT, AT, disp);
11999 } else {
12000 __ move(T9, disp);
12001 __ daddu(AT, as_Register(base), T9);
12002 }
12003 __ pref(1, AT, 0); //hint: 1:store
12004 %}
12005 ins_pipe(pipe_slow);
12006 %}
12008 // Prefetch instructions for allocation.
12010 instruct prefetchAllocNTA( memory mem ) %{
12011 match(PrefetchAllocation mem);
12012 ins_cost(125);
12013 format %{ "pref $mem\t# Prefetch allocation @ prefetchAllocNTA" %}
12014 ins_encode %{
12015 int base = $mem$$base;
12016 int index = $mem$$index;
12017 int scale = $mem$$scale;
12018 int disp = $mem$$disp;
12020 Register dst = R0;
12022 if( index != 0 ) {
12023 if( Assembler::is_simm16(disp) ) {
12024 if( UseLoongsonISA ) {
12025 if (scale == 0) {
12026 __ gslbx(dst, as_Register(base), as_Register(index), disp);
12027 } else {
12028 __ dsll(AT, as_Register(index), scale);
12029 __ gslbx(dst, as_Register(base), AT, disp);
12030 }
12031 } else {
12032 if (scale == 0) {
12033 __ addu(AT, as_Register(base), as_Register(index));
12034 } else {
12035 __ dsll(AT, as_Register(index), scale);
12036 __ addu(AT, as_Register(base), AT);
12037 }
12038 __ lb(dst, AT, disp);
12039 }
12040 } else {
12041 if (scale == 0) {
12042 __ addu(AT, as_Register(base), as_Register(index));
12043 } else {
12044 __ dsll(AT, as_Register(index), scale);
12045 __ addu(AT, as_Register(base), AT);
12046 }
12047 __ move(T9, disp);
12048 if( UseLoongsonISA ) {
12049 __ gslbx(dst, AT, T9, 0);
12050 } else {
12051 __ addu(AT, AT, T9);
12052 __ lb(dst, AT, 0);
12053 }
12054 }
12055 } else {
12056 if( Assembler::is_simm16(disp) ) {
12057 __ lb(dst, as_Register(base), disp);
12058 } else {
12059 __ move(T9, disp);
12060 if( UseLoongsonISA ) {
12061 __ gslbx(dst, as_Register(base), T9, 0);
12062 } else {
12063 __ addu(AT, as_Register(base), T9);
12064 __ lb(dst, AT, 0);
12065 }
12066 }
12067 }
12068 %}
12069 ins_pipe(pipe_slow);
12070 %}
12073 // Call runtime without safepoint
12074 instruct CallLeafDirect(method meth) %{
12075 match(CallLeaf);
12076 effect(USE meth);
12078 ins_cost(300);
12079 format %{ "CALL_LEAF,runtime #@CallLeafDirect " %}
12080 ins_encode(Java_To_Runtime(meth));
12081 ins_pipe( pipe_slow );
12082 ins_pc_relative(1);
12083 ins_alignment(16);
12084 %}
12086 // Load Char (16bit unsigned)
12087 instruct loadUS(mRegI dst, memory mem) %{
12088 match(Set dst (LoadUS mem));
12090 ins_cost(125);
12091 format %{ "loadUS $dst,$mem @ loadC" %}
12092 ins_encode(load_C_enc(dst, mem));
12093 ins_pipe( ialu_loadI );
12094 %}
12096 instruct loadUS_convI2L(mRegL dst, memory mem) %{
12097 match(Set dst (ConvI2L (LoadUS mem)));
12099 ins_cost(125);
12100 format %{ "loadUS $dst,$mem @ loadUS_convI2L" %}
12101 ins_encode(load_C_enc(dst, mem));
12102 ins_pipe( ialu_loadI );
12103 %}
12105 // Store Char (16bit unsigned)
12106 instruct storeC(memory mem, mRegI src) %{
12107 match(Set mem (StoreC mem src));
12109 ins_cost(125);
12110 format %{ "storeC $src,$mem @ storeC" %}
12111 ins_encode(store_C_reg_enc(mem, src));
12112 ins_pipe( ialu_loadI );
12113 %}
12116 instruct loadConF0(regF dst, immF0 zero) %{
12117 match(Set dst zero);
12118 ins_cost(100);
12120 format %{ "mov $dst, zero @ loadConF0\n"%}
12121 ins_encode %{
12122 FloatRegister dst = $dst$$FloatRegister;
12124 __ mtc1(R0, dst);
12125 %}
12126 ins_pipe( fpu_loadF );
12127 %}
12130 instruct loadConF(regF dst, immF src) %{
12131 match(Set dst src);
12132 ins_cost(125);
12134 format %{ "lwc1 $dst, $constantoffset[$constanttablebase] # load FLOAT $src from table @ loadConF" %}
12135 ins_encode %{
12136 int con_offset = $constantoffset($src);
12138 if (Assembler::is_simm16(con_offset)) {
12139 __ lwc1($dst$$FloatRegister, $constanttablebase, con_offset);
12140 } else {
12141 __ set64(AT, con_offset);
12142 if (UseLoongsonISA) {
12143 __ gslwxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
12144 } else {
12145 __ daddu(AT, $constanttablebase, AT);
12146 __ lwc1($dst$$FloatRegister, AT, 0);
12147 }
12148 }
12149 %}
12150 ins_pipe( fpu_loadF );
12151 %}
12154 instruct loadConD0(regD dst, immD0 zero) %{
12155 match(Set dst zero);
12156 ins_cost(100);
12158 format %{ "mov $dst, zero @ loadConD0"%}
12159 ins_encode %{
12160 FloatRegister dst = as_FloatRegister($dst$$reg);
12162 __ dmtc1(R0, dst);
12163 %}
12164 ins_pipe( fpu_loadF );
12165 %}
12167 instruct loadConD(regD dst, immD src) %{
12168 match(Set dst src);
12169 ins_cost(125);
12171 format %{ "ldc1 $dst, $constantoffset[$constanttablebase] # load DOUBLE $src from table @ loadConD" %}
12172 ins_encode %{
12173 int con_offset = $constantoffset($src);
12175 if (Assembler::is_simm16(con_offset)) {
12176 __ ldc1($dst$$FloatRegister, $constanttablebase, con_offset);
12177 } else {
12178 __ set64(AT, con_offset);
12179 if (UseLoongsonISA) {
12180 __ gsldxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
12181 } else {
12182 __ daddu(AT, $constanttablebase, AT);
12183 __ ldc1($dst$$FloatRegister, AT, 0);
12184 }
12185 }
12186 %}
12187 ins_pipe( fpu_loadF );
12188 %}
12190 // Store register Float value (it is faster than store from FPU register)
12191 instruct storeF_reg( memory mem, regF src) %{
12192 match(Set mem (StoreF mem src));
12194 ins_cost(50);
12195 format %{ "store $mem, $src\t# store float @ storeF_reg" %}
12196 ins_encode(store_F_reg_enc(mem, src));
12197 ins_pipe( fpu_storeF );
12198 %}
12200 instruct storeF_imm0( memory mem, immF0 zero) %{
12201 match(Set mem (StoreF mem zero));
12203 ins_cost(40);
12204 format %{ "store $mem, zero\t# store float @ storeF_imm0" %}
12205 ins_encode %{
12206 int base = $mem$$base;
12207 int index = $mem$$index;
12208 int scale = $mem$$scale;
12209 int disp = $mem$$disp;
12211 if( index != 0 ) {
12212 if(scale != 0) {
12213 __ dsll(T9, as_Register(index), scale);
12214 __ addu(AT, as_Register(base), T9);
12215 } else {
12216 __ daddu(AT, as_Register(base), as_Register(index));
12217 }
12218 if( Assembler::is_simm16(disp) ) {
12219 __ sw(R0, AT, disp);
12220 } else {
12221 __ move(T9, disp);
12222 __ addu(AT, AT, T9);
12223 __ sw(R0, AT, 0);
12224 }
12226 } else {
12227 if( Assembler::is_simm16(disp) ) {
12228 __ sw(R0, as_Register(base), disp);
12229 } else {
12230 __ move(T9, disp);
12231 __ addu(AT, as_Register(base), T9);
12232 __ sw(R0, AT, 0);
12233 }
12234 }
12235 %}
12236 ins_pipe( ialu_storeI );
12237 %}
12239 // Load Double
12240 instruct loadD(regD dst, memory mem) %{
12241 match(Set dst (LoadD mem));
12243 ins_cost(150);
12244 format %{ "loadD $dst, $mem #@loadD" %}
12245 ins_encode(load_D_enc(dst, mem));
12246 ins_pipe( ialu_loadI );
12247 %}
12249 // Load Double - UNaligned
12250 instruct loadD_unaligned(regD dst, memory mem ) %{
12251 match(Set dst (LoadD_unaligned mem));
12252 ins_cost(250);
12253 // FIXME: Jin: Need more effective ldl/ldr
12254 format %{ "loadD_unaligned $dst, $mem #@loadD_unaligned" %}
12255 ins_encode(load_D_enc(dst, mem));
12256 ins_pipe( ialu_loadI );
12257 %}
12259 instruct storeD_reg( memory mem, regD src) %{
12260 match(Set mem (StoreD mem src));
12262 ins_cost(50);
12263 format %{ "store $mem, $src\t# store float @ storeD_reg" %}
12264 ins_encode(store_D_reg_enc(mem, src));
12265 ins_pipe( fpu_storeF );
12266 %}
12268 instruct storeD_imm0( memory mem, immD0 zero) %{
12269 match(Set mem (StoreD mem zero));
12271 ins_cost(40);
12272 format %{ "store $mem, zero\t# store float @ storeD_imm0" %}
12273 ins_encode %{
12274 int base = $mem$$base;
12275 int index = $mem$$index;
12276 int scale = $mem$$scale;
12277 int disp = $mem$$disp;
12279 __ mtc1(R0, F30);
12280 __ cvt_d_w(F30, F30);
12282 if( index != 0 ) {
12283 if(scale != 0) {
12284 __ dsll(T9, as_Register(index), scale);
12285 __ addu(AT, as_Register(base), T9);
12286 } else {
12287 __ daddu(AT, as_Register(base), as_Register(index));
12288 }
12289 if( Assembler::is_simm16(disp) ) {
12290 __ sdc1(F30, AT, disp);
12291 } else {
12292 __ move(T9, disp);
12293 __ addu(AT, AT, T9);
12294 __ sdc1(F30, AT, 0);
12295 }
12297 } else {
12298 if( Assembler::is_simm16(disp) ) {
12299 __ sdc1(F30, as_Register(base), disp);
12300 } else {
12301 __ move(T9, disp);
12302 __ addu(AT, as_Register(base), T9);
12303 __ sdc1(F30, AT, 0);
12304 }
12305 }
12306 %}
12307 ins_pipe( ialu_storeI );
12308 %}
12310 instruct loadSSI(mRegI dst, stackSlotI src)
12311 %{
12312 match(Set dst src);
12314 ins_cost(125);
12315 format %{ "lw $dst, $src\t# int stk @ loadSSI" %}
12316 ins_encode %{
12317 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSI) !");
12318 __ lw($dst$$Register, SP, $src$$disp);
12319 %}
12320 ins_pipe(ialu_loadI);
12321 %}
12323 instruct storeSSI(stackSlotI dst, mRegI src)
12324 %{
12325 match(Set dst src);
12327 ins_cost(100);
12328 format %{ "sw $dst, $src\t# int stk @ storeSSI" %}
12329 ins_encode %{
12330 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSI) !");
12331 __ sw($src$$Register, SP, $dst$$disp);
12332 %}
12333 ins_pipe(ialu_storeI);
12334 %}
12336 instruct loadSSL(mRegL dst, stackSlotL src)
12337 %{
12338 match(Set dst src);
12340 ins_cost(125);
12341 format %{ "ld $dst, $src\t# long stk @ loadSSL" %}
12342 ins_encode %{
12343 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSL) !");
12344 __ ld($dst$$Register, SP, $src$$disp);
12345 %}
12346 ins_pipe(ialu_loadI);
12347 %}
12349 instruct storeSSL(stackSlotL dst, mRegL src)
12350 %{
12351 match(Set dst src);
12353 ins_cost(100);
12354 format %{ "sd $dst, $src\t# long stk @ storeSSL" %}
12355 ins_encode %{
12356 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSL) !");
12357 __ sd($src$$Register, SP, $dst$$disp);
12358 %}
12359 ins_pipe(ialu_storeI);
12360 %}
12362 instruct loadSSP(mRegP dst, stackSlotP src)
12363 %{
12364 match(Set dst src);
12366 ins_cost(125);
12367 format %{ "ld $dst, $src\t# ptr stk @ loadSSP" %}
12368 ins_encode %{
12369 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSP) !");
12370 __ ld($dst$$Register, SP, $src$$disp);
12371 %}
12372 ins_pipe(ialu_loadI);
12373 %}
12375 instruct storeSSP(stackSlotP dst, mRegP src)
12376 %{
12377 match(Set dst src);
12379 ins_cost(100);
12380 format %{ "sd $dst, $src\t# ptr stk @ storeSSP" %}
12381 ins_encode %{
12382 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSP) !");
12383 __ sd($src$$Register, SP, $dst$$disp);
12384 %}
12385 ins_pipe(ialu_storeI);
12386 %}
12388 instruct loadSSF(regF dst, stackSlotF src)
12389 %{
12390 match(Set dst src);
12392 ins_cost(125);
12393 format %{ "lwc1 $dst, $src\t# float stk @ loadSSF" %}
12394 ins_encode %{
12395 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSF) !");
12396 __ lwc1($dst$$FloatRegister, SP, $src$$disp);
12397 %}
12398 ins_pipe(ialu_loadI);
12399 %}
12401 instruct storeSSF(stackSlotF dst, regF src)
12402 %{
12403 match(Set dst src);
12405 ins_cost(100);
12406 format %{ "swc1 $dst, $src\t# float stk @ storeSSF" %}
12407 ins_encode %{
12408 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSF) !");
12409 __ swc1($src$$FloatRegister, SP, $dst$$disp);
12410 %}
12411 ins_pipe(fpu_storeF);
12412 %}
12414 // Use the same format since predicate() can not be used here.
12415 instruct loadSSD(regD dst, stackSlotD src)
12416 %{
12417 match(Set dst src);
12419 ins_cost(125);
12420 format %{ "ldc1 $dst, $src\t# double stk @ loadSSD" %}
12421 ins_encode %{
12422 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSD) !");
12423 __ ldc1($dst$$FloatRegister, SP, $src$$disp);
12424 %}
12425 ins_pipe(ialu_loadI);
12426 %}
12428 instruct storeSSD(stackSlotD dst, regD src)
12429 %{
12430 match(Set dst src);
12432 ins_cost(100);
12433 format %{ "sdc1 $dst, $src\t# double stk @ storeSSD" %}
12434 ins_encode %{
12435 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSD) !");
12436 __ sdc1($src$$FloatRegister, SP, $dst$$disp);
12437 %}
12438 ins_pipe(fpu_storeF);
12439 %}
12441 instruct cmpFastLock( FlagsReg cr, mRegP object, s0_RegP box, mRegI tmp, mRegP scr) %{
12442 match( Set cr (FastLock object box) );
12443 effect( TEMP tmp, TEMP scr, USE_KILL box );
12444 ins_cost(300);
12445 format %{ "FASTLOCK $cr $object, $box, $tmp #@ cmpFastLock" %}
12446 ins_encode %{
12447 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register);
12448 %}
12450 ins_pipe( pipe_slow );
12451 ins_pc_relative(1);
12452 %}
12454 instruct cmpFastUnlock( FlagsReg cr, mRegP object, s0_RegP box, mRegP tmp ) %{
12455 match( Set cr (FastUnlock object box) );
12456 effect( TEMP tmp, USE_KILL box );
12457 ins_cost(300);
12458 format %{ "FASTUNLOCK $object, $box, $tmp #@cmpFastUnlock" %}
12459 ins_encode %{
12460 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
12461 %}
12463 ins_pipe( pipe_slow );
12464 ins_pc_relative(1);
12465 %}
12467 // Store CMS card-mark Immediate
12468 instruct storeImmCM(memory mem, immI8 src) %{
12469 match(Set mem (StoreCM mem src));
12471 ins_cost(150);
12472 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
12473 // opcode(0xC6);
12474 ins_encode(store_B_immI_enc_sync(mem, src));
12475 ins_pipe( ialu_storeI );
12476 %}
12478 // Die now
12479 instruct ShouldNotReachHere( )
12480 %{
12481 match(Halt);
12482 ins_cost(300);
12484 // Use the following format syntax
12485 format %{ "ILLTRAP ;#@ShouldNotReachHere" %}
12486 ins_encode %{
12487 // Here we should emit illtrap !
12489 __ stop("in ShoudNotReachHere");
12491 %}
12492 ins_pipe( pipe_jump );
12493 %}
12495 instruct leaP8Narrow(mRegP dst, indOffset8Narrow mem)
12496 %{
12497 predicate(Universe::narrow_oop_shift() == 0);
12498 match(Set dst mem);
12500 ins_cost(110);
12501 format %{ "leaq $dst, $mem\t# ptr off8narrow @ leaP8Narrow" %}
12502 ins_encode %{
12503 Register dst = $dst$$Register;
12504 Register base = as_Register($mem$$base);
12505 int disp = $mem$$disp;
12507 __ daddiu(dst, base, disp);
12508 %}
12509 ins_pipe( ialu_regI_imm16 );
12510 %}
12512 instruct leaPPosIdxScaleOff8(mRegP dst, basePosIndexScaleOffset8 mem)
12513 %{
12514 match(Set dst mem);
12516 ins_cost(110);
12517 format %{ "leaq $dst, $mem\t# @ PosIdxScaleOff8" %}
12518 ins_encode %{
12519 Register dst = $dst$$Register;
12520 Register base = as_Register($mem$$base);
12521 Register index = as_Register($mem$$index);
12522 int scale = $mem$$scale;
12523 int disp = $mem$$disp;
12525 if (scale == 0) {
12526 __ daddu(AT, base, index);
12527 __ daddiu(dst, AT, disp);
12528 } else {
12529 __ dsll(AT, index, scale);
12530 __ daddu(AT, base, AT);
12531 __ daddiu(dst, AT, disp);
12532 }
12533 %}
12535 ins_pipe( ialu_regI_imm16 );
12536 %}
12538 instruct leaPIdxScale(mRegP dst, indIndexScale mem)
12539 %{
12540 match(Set dst mem);
12542 ins_cost(110);
12543 format %{ "leaq $dst, $mem\t# @ leaPIdxScale" %}
12544 ins_encode %{
12545 Register dst = $dst$$Register;
12546 Register base = as_Register($mem$$base);
12547 Register index = as_Register($mem$$index);
12548 int scale = $mem$$scale;
12550 if (scale == 0) {
12551 __ daddu(dst, base, index);
12552 } else {
12553 __ dsll(AT, index, scale);
12554 __ daddu(dst, base, AT);
12555 }
12556 %}
12558 ins_pipe( ialu_regI_imm16 );
12559 %}
12561 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12562 instruct jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{
12563 match(CountedLoopEnd cop (CmpI src1 src2));
12564 effect(USE labl);
12566 ins_cost(300);
12567 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd" %}
12568 ins_encode %{
12569 Register op1 = $src1$$Register;
12570 Register op2 = $src2$$Register;
12571 Label &L = *($labl$$label);
12572 int flag = $cop$$cmpcode;
12574 switch(flag)
12575 {
12576 case 0x01: //equal
12577 if (&L)
12578 __ beq(op1, op2, L);
12579 else
12580 __ beq(op1, op2, (int)0);
12581 break;
12582 case 0x02: //not_equal
12583 if (&L)
12584 __ bne(op1, op2, L);
12585 else
12586 __ bne(op1, op2, (int)0);
12587 break;
12588 case 0x03: //above
12589 __ slt(AT, op2, op1);
12590 if(&L)
12591 __ bne(AT, R0, L);
12592 else
12593 __ bne(AT, R0, (int)0);
12594 break;
12595 case 0x04: //above_equal
12596 __ slt(AT, op1, op2);
12597 if(&L)
12598 __ beq(AT, R0, L);
12599 else
12600 __ beq(AT, R0, (int)0);
12601 break;
12602 case 0x05: //below
12603 __ slt(AT, op1, op2);
12604 if(&L)
12605 __ bne(AT, R0, L);
12606 else
12607 __ bne(AT, R0, (int)0);
12608 break;
12609 case 0x06: //below_equal
12610 __ slt(AT, op2, op1);
12611 if(&L)
12612 __ beq(AT, R0, L);
12613 else
12614 __ beq(AT, R0, (int)0);
12615 break;
12616 default:
12617 Unimplemented();
12618 }
12619 __ nop();
12620 %}
12621 ins_pipe( pipe_jump );
12622 ins_pc_relative(1);
12623 %}
12626 instruct jmpLoopEnd_reg_imm16_sub(cmpOp cop, mRegI src1, immI16_sub src2, label labl) %{
12627 match(CountedLoopEnd cop (CmpI src1 src2));
12628 effect(USE labl);
12630 ins_cost(250);
12631 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_imm16_sub" %}
12632 ins_encode %{
12633 Register op1 = $src1$$Register;
12634 int op2 = $src2$$constant;
12635 Label &L = *($labl$$label);
12636 int flag = $cop$$cmpcode;
12638 __ addiu32(AT, op1, -1 * op2);
12640 switch(flag)
12641 {
12642 case 0x01: //equal
12643 if (&L)
12644 __ beq(AT, R0, L);
12645 else
12646 __ beq(AT, R0, (int)0);
12647 break;
12648 case 0x02: //not_equal
12649 if (&L)
12650 __ bne(AT, R0, L);
12651 else
12652 __ bne(AT, R0, (int)0);
12653 break;
12654 case 0x03: //above
12655 if(&L)
12656 __ bgtz(AT, L);
12657 else
12658 __ bgtz(AT, (int)0);
12659 break;
12660 case 0x04: //above_equal
12661 if(&L)
12662 __ bgez(AT, L);
12663 else
12664 __ bgez(AT,(int)0);
12665 break;
12666 case 0x05: //below
12667 if(&L)
12668 __ bltz(AT, L);
12669 else
12670 __ bltz(AT, (int)0);
12671 break;
12672 case 0x06: //below_equal
12673 if(&L)
12674 __ blez(AT, L);
12675 else
12676 __ blez(AT, (int)0);
12677 break;
12678 default:
12679 Unimplemented();
12680 }
12681 __ nop();
12682 %}
12683 ins_pipe( pipe_jump );
12684 ins_pc_relative(1);
12685 %}
12688 /*
12689 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12690 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12691 match(CountedLoopEnd cop cmp);
12692 effect(USE labl);
12694 ins_cost(300);
12695 format %{ "J$cop,u $labl\t# Loop end" %}
12696 size(6);
12697 opcode(0x0F, 0x80);
12698 ins_encode( Jcc( cop, labl) );
12699 ins_pipe( pipe_jump );
12700 ins_pc_relative(1);
12701 %}
12703 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12704 match(CountedLoopEnd cop cmp);
12705 effect(USE labl);
12707 ins_cost(200);
12708 format %{ "J$cop,u $labl\t# Loop end" %}
12709 opcode(0x0F, 0x80);
12710 ins_encode( Jcc( cop, labl) );
12711 ins_pipe( pipe_jump );
12712 ins_pc_relative(1);
12713 %}
12714 */
12716 // This match pattern is created for StoreIConditional since I cannot match IfNode without a RegFlags! fujie 2012/07/17
12717 instruct jmpCon_flags(cmpOp cop, FlagsReg cr, label labl) %{
12718 match(If cop cr);
12719 effect(USE labl);
12721 ins_cost(300);
12722 format %{ "J$cop $labl #mips uses AT as eflag @jmpCon_flags" %}
12724 ins_encode %{
12725 Label &L = *($labl$$label);
12726 switch($cop$$cmpcode)
12727 {
12728 case 0x01: //equal
12729 if (&L)
12730 __ bne(AT, R0, L);
12731 else
12732 __ bne(AT, R0, (int)0);
12733 break;
12734 case 0x02: //not equal
12735 if (&L)
12736 __ beq(AT, R0, L);
12737 else
12738 __ beq(AT, R0, (int)0);
12739 break;
12740 default:
12741 Unimplemented();
12742 }
12743 __ nop();
12744 %}
12746 ins_pipe( pipe_jump );
12747 ins_pc_relative(1);
12748 %}
12751 // ============================================================================
12752 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12753 // array for an instance of the superklass. Set a hidden internal cache on a
12754 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12755 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12756 instruct partialSubtypeCheck( mRegP result, no_T8_mRegP sub, no_T8_mRegP super, mT8RegI tmp ) %{
12757 match(Set result (PartialSubtypeCheck sub super));
12758 effect(KILL tmp);
12759 ins_cost(1100); // slightly larger than the next version
12760 format %{ "partialSubtypeCheck result=$result, sub=$sub, super=$super, tmp=$tmp " %}
12762 ins_encode( enc_PartialSubtypeCheck(result, sub, super, tmp) );
12763 ins_pipe( pipe_slow );
12764 %}
12767 // Conditional-store of an int value.
12768 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
12769 instruct storeIConditional( memory mem, mRegI oldval, mRegI newval, FlagsReg cr ) %{
12770 match(Set cr (StoreIConditional mem (Binary oldval newval)));
12771 // effect(KILL oldval);
12772 format %{ "CMPXCHG $newval, $mem, $oldval \t# @storeIConditional" %}
12774 ins_encode %{
12775 Register oldval = $oldval$$Register;
12776 Register newval = $newval$$Register;
12777 Address addr(as_Register($mem$$base), $mem$$disp);
12778 Label again, failure;
12780 // int base = $mem$$base;
12781 int index = $mem$$index;
12782 int scale = $mem$$scale;
12783 int disp = $mem$$disp;
12785 guarantee(Assembler::is_simm16(disp), "");
12787 if( index != 0 ) {
12788 __ stop("in storeIConditional: index != 0");
12789 } else {
12790 __ bind(again);
12791 __ sync();
12792 __ ll(AT, addr);
12793 __ bne(AT, oldval, failure);
12794 __ delayed()->addu(AT, R0, R0);
12796 __ addu(AT, newval, R0);
12797 __ sc(AT, addr);
12798 __ beq(AT, R0, again);
12799 __ delayed()->addiu(AT, R0, 0xFF);
12800 __ bind(failure);
12801 __ sync();
12802 }
12803 %}
12805 ins_pipe( long_memory_op );
12806 %}
12808 // Conditional-store of a long value.
12809 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
12810 instruct storeLConditional(memory mem, t2RegL oldval, mRegL newval, FlagsReg cr )
12811 %{
12812 match(Set cr (StoreLConditional mem (Binary oldval newval)));
12813 effect(KILL oldval);
12815 format %{ "cmpxchg $mem, $newval\t# If $oldval == $mem then store $newval into $mem" %}
12816 ins_encode%{
12817 Register oldval = $oldval$$Register;
12818 Register newval = $newval$$Register;
12819 Address addr((Register)$mem$$base, $mem$$disp);
12821 int index = $mem$$index;
12822 int scale = $mem$$scale;
12823 int disp = $mem$$disp;
12825 guarantee(Assembler::is_simm16(disp), "");
12827 if( index != 0 ) {
12828 __ stop("in storeIConditional: index != 0");
12829 } else {
12830 __ cmpxchg(newval, addr, oldval);
12831 }
12832 %}
12833 ins_pipe( long_memory_op );
12834 %}
12837 instruct compareAndSwapI( mRegI res, mRegP mem_ptr, mS2RegI oldval, mRegI newval) %{
12838 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
12839 effect(KILL oldval);
12840 // match(CompareAndSwapI mem_ptr (Binary oldval newval));
12841 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapI\n\t"
12842 "MOV $res, 1 @ compareAndSwapI\n\t"
12843 "BNE AT, R0 @ compareAndSwapI\n\t"
12844 "MOV $res, 0 @ compareAndSwapI\n"
12845 "L:" %}
12846 ins_encode %{
12847 Register newval = $newval$$Register;
12848 Register oldval = $oldval$$Register;
12849 Register res = $res$$Register;
12850 Address addr($mem_ptr$$Register, 0);
12851 Label L;
12853 __ cmpxchg32(newval, addr, oldval);
12854 __ move(res, AT);
12855 %}
12856 ins_pipe( long_memory_op );
12857 %}
12859 //FIXME:
12860 instruct compareAndSwapP( mRegI res, mRegP mem_ptr, s2_RegP oldval, mRegP newval) %{
12861 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
12862 effect(KILL oldval);
12863 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapP\n\t"
12864 "MOV $res, AT @ compareAndSwapP\n\t"
12865 "L:" %}
12866 ins_encode %{
12867 Register newval = $newval$$Register;
12868 Register oldval = $oldval$$Register;
12869 Register res = $res$$Register;
12870 Address addr($mem_ptr$$Register, 0);
12871 Label L;
12873 __ cmpxchg(newval, addr, oldval);
12874 __ move(res, AT);
12875 %}
12876 ins_pipe( long_memory_op );
12877 %}
12879 instruct compareAndSwapN( mRegI res, mRegP mem_ptr, t2_RegN oldval, mRegN newval) %{
12880 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
12881 effect(KILL oldval);
12882 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapN\n\t"
12883 "MOV $res, AT @ compareAndSwapN\n\t"
12884 "L:" %}
12885 ins_encode %{
12886 Register newval = $newval$$Register;
12887 Register oldval = $oldval$$Register;
12888 Register res = $res$$Register;
12889 Address addr($mem_ptr$$Register, 0);
12890 Label L;
12892 /* 2013/7/19 Jin: cmpxchg32 is implemented with ll/sc, which will do sign extension.
12893 * Thus, we should extend oldval's sign for correct comparision.
12894 */
12895 __ sll(oldval, oldval, 0);
12897 __ cmpxchg32(newval, addr, oldval);
12898 __ move(res, AT);
12899 %}
12900 ins_pipe( long_memory_op );
12901 %}
12903 //----------Max and Min--------------------------------------------------------
12904 // Min Instructions
12905 ////
12906 // *** Min and Max using the conditional move are slower than the
12907 // *** branch version on a Pentium III.
12908 // // Conditional move for min
12909 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12910 // effect( USE_DEF op2, USE op1, USE cr );
12911 // format %{ "CMOVlt $op2,$op1\t! min" %}
12912 // opcode(0x4C,0x0F);
12913 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12914 // ins_pipe( pipe_cmov_reg );
12915 //%}
12916 //
12917 //// Min Register with Register (P6 version)
12918 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12919 // predicate(VM_Version::supports_cmov() );
12920 // match(Set op2 (MinI op1 op2));
12921 // ins_cost(200);
12922 // expand %{
12923 // eFlagsReg cr;
12924 // compI_eReg(cr,op1,op2);
12925 // cmovI_reg_lt(op2,op1,cr);
12926 // %}
12927 //%}
12929 // Min Register with Register (generic version)
12930 instruct minI_Reg_Reg(mRegI dst, mRegI src) %{
12931 match(Set dst (MinI dst src));
12932 //effect(KILL flags);
12933 ins_cost(80);
12935 format %{ "MIN $dst, $src @minI_Reg_Reg" %}
12936 ins_encode %{
12937 Register dst = $dst$$Register;
12938 Register src = $src$$Register;
12940 __ slt(AT, src, dst);
12941 __ movn(dst, src, AT);
12943 %}
12945 ins_pipe( pipe_slow );
12946 %}
12948 // Max Register with Register
12949 // *** Min and Max using the conditional move are slower than the
12950 // *** branch version on a Pentium III.
12951 // // Conditional move for max
12952 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12953 // effect( USE_DEF op2, USE op1, USE cr );
12954 // format %{ "CMOVgt $op2,$op1\t! max" %}
12955 // opcode(0x4F,0x0F);
12956 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12957 // ins_pipe( pipe_cmov_reg );
12958 //%}
12959 //
12960 // // Max Register with Register (P6 version)
12961 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12962 // predicate(VM_Version::supports_cmov() );
12963 // match(Set op2 (MaxI op1 op2));
12964 // ins_cost(200);
12965 // expand %{
12966 // eFlagsReg cr;
12967 // compI_eReg(cr,op1,op2);
12968 // cmovI_reg_gt(op2,op1,cr);
12969 // %}
12970 //%}
12972 // Max Register with Register (generic version)
12973 instruct maxI_Reg_Reg(mRegI dst, mRegI src) %{
12974 match(Set dst (MaxI dst src));
12975 ins_cost(80);
12977 format %{ "MAX $dst, $src @maxI_Reg_Reg" %}
12979 ins_encode %{
12980 Register dst = $dst$$Register;
12981 Register src = $src$$Register;
12983 __ slt(AT, dst, src);
12984 __ movn(dst, src, AT);
12986 %}
12988 ins_pipe( pipe_slow );
12989 %}
12991 instruct maxI_Reg_zero(mRegI dst, immI0 zero) %{
12992 match(Set dst (MaxI dst zero));
12993 ins_cost(50);
12995 format %{ "MAX $dst, 0 @maxI_Reg_zero" %}
12997 ins_encode %{
12998 Register dst = $dst$$Register;
13000 __ slt(AT, dst, R0);
13001 __ movn(dst, R0, AT);
13003 %}
13005 ins_pipe( pipe_slow );
13006 %}
13008 instruct zerox_long_reg_reg(mRegL dst, mRegL src, immL_32bits mask)
13009 %{
13010 match(Set dst (AndL src mask));
13012 format %{ "movl $dst, $src\t# zero-extend long @ zerox_long_reg_reg" %}
13013 ins_encode %{
13014 Register dst = $dst$$Register;
13015 Register src = $src$$Register;
13017 __ dext(dst, src, 0, 32);
13018 %}
13019 ins_pipe(ialu_regI_regI);
13020 %}
13022 // Zero-extend convert int to long
13023 instruct convI2L_reg_reg_zex(mRegL dst, mRegI src, immL_32bits mask)
13024 %{
13025 match(Set dst (AndL (ConvI2L src) mask));
13027 format %{ "movl $dst, $src\t# i2l zero-extend @ convI2L_reg_reg_zex" %}
13028 ins_encode %{
13029 Register dst = $dst$$Register;
13030 Register src = $src$$Register;
13032 __ dext(dst, src, 0, 32);
13033 %}
13034 ins_pipe(ialu_regI_regI);
13035 %}
13037 instruct convL2I2L_reg_reg_zex(mRegL dst, mRegL src, immL_32bits mask)
13038 %{
13039 match(Set dst (AndL (ConvI2L (ConvL2I src)) mask));
13041 format %{ "movl $dst, $src\t# i2l zero-extend @ convL2I2L_reg_reg_zex" %}
13042 ins_encode %{
13043 Register dst = $dst$$Register;
13044 Register src = $src$$Register;
13046 __ dext(dst, src, 0, 32);
13047 %}
13048 ins_pipe(ialu_regI_regI);
13049 %}
13051 // Match loading integer and casting it to unsigned int in long register.
13052 // LoadI + ConvI2L + AndL 0xffffffff.
13053 instruct loadUI2L_rmask(mRegL dst, memory mem, immL_32bits mask) %{
13054 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
13056 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_rmask" %}
13057 ins_encode (load_N_enc(dst, mem));
13058 ins_pipe(ialu_loadI);
13059 %}
13061 instruct loadUI2L_lmask(mRegL dst, memory mem, immL_32bits mask) %{
13062 match(Set dst (AndL mask (ConvI2L (LoadI mem))));
13064 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_lmask" %}
13065 ins_encode (load_N_enc(dst, mem));
13066 ins_pipe(ialu_loadI);
13067 %}
13070 // ============================================================================
13071 // Safepoint Instruction
13072 instruct safePoint_poll(mRegP poll) %{
13073 match(SafePoint poll);
13074 effect(USE poll);
13076 ins_cost(125);
13077 format %{ "Safepoint @ [$poll] : poll for GC @ safePoint_poll" %}
13079 ins_encode %{
13080 Register poll_reg = $poll$$Register;
13082 __ block_comment("Safepoint:");
13083 __ relocate(relocInfo::poll_type);
13084 __ lw(AT, poll_reg, 0);
13085 %}
13087 ins_pipe( ialu_storeI );
13088 %}
13090 //----------Arithmetic Conversion Instructions---------------------------------
13092 instruct roundFloat_nop(regF dst)
13093 %{
13094 match(Set dst (RoundFloat dst));
13096 ins_cost(0);
13097 ins_encode();
13098 ins_pipe(empty);
13099 %}
13101 instruct roundDouble_nop(regD dst)
13102 %{
13103 match(Set dst (RoundDouble dst));
13105 ins_cost(0);
13106 ins_encode();
13107 ins_pipe(empty);
13108 %}
13110 //---------- Zeros Count Instructions ------------------------------------------
13111 // CountLeadingZerosINode CountTrailingZerosINode
13112 instruct countLeadingZerosI(mRegI dst, mRegI src) %{
13113 predicate(UseCountLeadingZerosInstruction);
13114 match(Set dst (CountLeadingZerosI src));
13116 format %{ "clz $dst, $src\t# count leading zeros (int)" %}
13117 ins_encode %{
13118 __ clz($dst$$Register, $src$$Register);
13119 %}
13120 ins_pipe( ialu_regL_regL );
13121 %}
13123 instruct countLeadingZerosL(mRegI dst, mRegL src) %{
13124 predicate(UseCountLeadingZerosInstruction);
13125 match(Set dst (CountLeadingZerosL src));
13127 format %{ "dclz $dst, $src\t# count leading zeros (long)" %}
13128 ins_encode %{
13129 __ dclz($dst$$Register, $src$$Register);
13130 %}
13131 ins_pipe( ialu_regL_regL );
13132 %}
13134 instruct countTrailingZerosI(mRegI dst, mRegI src) %{
13135 predicate(UseCountTrailingZerosInstruction);
13136 match(Set dst (CountTrailingZerosI src));
13138 format %{ "ctz $dst, $src\t# count trailing zeros (int)" %}
13139 ins_encode %{
13140 // ctz and dctz is gs instructions.
13141 __ ctz($dst$$Register, $src$$Register);
13142 %}
13143 ins_pipe( ialu_regL_regL );
13144 %}
13146 instruct countTrailingZerosL(mRegI dst, mRegL src) %{
13147 predicate(UseCountTrailingZerosInstruction);
13148 match(Set dst (CountTrailingZerosL src));
13150 format %{ "dcto $dst, $src\t# count trailing zeros (long)" %}
13151 ins_encode %{
13152 __ dctz($dst$$Register, $src$$Register);
13153 %}
13154 ins_pipe( ialu_regL_regL );
13155 %}
13157 // ====================VECTOR INSTRUCTIONS=====================================
13159 // Load vectors (8 bytes long)
13160 instruct loadV8(vecD dst, memory mem) %{
13161 predicate(n->as_LoadVector()->memory_size() == 8);
13162 match(Set dst (LoadVector mem));
13163 ins_cost(125);
13164 format %{ "load $dst, $mem\t! load vector (8 bytes)" %}
13165 ins_encode(load_D_enc(dst, mem));
13166 ins_pipe( fpu_loadF );
13167 %}
13169 // Store vectors (8 bytes long)
13170 instruct storeV8(memory mem, vecD src) %{
13171 predicate(n->as_StoreVector()->memory_size() == 8);
13172 match(Set mem (StoreVector mem src));
13173 ins_cost(145);
13174 format %{ "store $mem, $src\t! store vector (8 bytes)" %}
13175 ins_encode(store_D_reg_enc(mem, src));
13176 ins_pipe( fpu_storeF );
13177 %}
13179 instruct Repl8B(vecD dst, mRegI src) %{
13180 predicate(n->as_Vector()->length() == 8);
13181 match(Set dst (ReplicateB src));
13182 format %{ "replv_ob AT, $src\n\t"
13183 "dmtc1 AT, $dst\t! replicate8B" %}
13184 ins_encode %{
13185 __ replv_ob(AT, $src$$Register);
13186 __ dmtc1(AT, $dst$$FloatRegister);
13187 %}
13188 ins_pipe( pipe_mtc1 );
13189 %}
13191 instruct Repl8B_imm(vecD dst, immI con) %{
13192 predicate(n->as_Vector()->length() == 8);
13193 match(Set dst (ReplicateB con));
13194 format %{ "repl_ob AT, [$con]\n\t"
13195 "dmtc1 AT, $dst,0x00\t! replicate8B($con)" %}
13196 ins_encode %{
13197 int val = $con$$constant;
13198 __ repl_ob(AT, val);
13199 __ dmtc1(AT, $dst$$FloatRegister);
13200 %}
13201 ins_pipe( pipe_mtc1 );
13202 %}
13204 instruct Repl8B_zero(vecD dst, immI0 zero) %{
13205 predicate(n->as_Vector()->length() == 8);
13206 match(Set dst (ReplicateB zero));
13207 format %{ "dmtc1 R0, $dst\t! replicate8B zero" %}
13208 ins_encode %{
13209 __ dmtc1(R0, $dst$$FloatRegister);
13210 %}
13211 ins_pipe( pipe_mtc1 );
13212 %}
13214 instruct Repl8B_M1(vecD dst, immI_M1 M1) %{
13215 predicate(n->as_Vector()->length() == 8);
13216 match(Set dst (ReplicateB M1));
13217 format %{ "dmtc1 -1, $dst\t! replicate8B -1" %}
13218 ins_encode %{
13219 __ nor(AT, R0, R0);
13220 __ dmtc1(AT, $dst$$FloatRegister);
13221 %}
13222 ins_pipe( pipe_mtc1 );
13223 %}
13225 instruct Repl4S(vecD dst, mRegI src) %{
13226 predicate(n->as_Vector()->length() == 4);
13227 match(Set dst (ReplicateS src));
13228 format %{ "replv_qh AT, $src\n\t"
13229 "dmtc1 AT, $dst\t! replicate4S" %}
13230 ins_encode %{
13231 __ replv_qh(AT, $src$$Register);
13232 __ dmtc1(AT, $dst$$FloatRegister);
13233 %}
13234 ins_pipe( pipe_mtc1 );
13235 %}
13237 instruct Repl4S_imm(vecD dst, immI con) %{
13238 predicate(n->as_Vector()->length() == 4);
13239 match(Set dst (ReplicateS con));
13240 format %{ "replv_qh AT, [$con]\n\t"
13241 "dmtc1 AT, $dst\t! replicate4S($con)" %}
13242 ins_encode %{
13243 int val = $con$$constant;
13244 if ( Assembler::is_simm(val, 10)) {
13245 //repl_qh supports 10 bits immediate
13246 __ repl_qh(AT, val);
13247 } else {
13248 __ li32(AT, val);
13249 __ replv_qh(AT, AT);
13250 }
13251 __ dmtc1(R0, $dst$$FloatRegister);
13252 %}
13253 ins_pipe( pipe_mtc1 );
13254 %}
13256 instruct Repl4S_zero(vecD dst, immI0 zero) %{
13257 predicate(n->as_Vector()->length() == 4);
13258 match(Set dst (ReplicateS zero));
13259 format %{ "dmtc1 R0, $dst\t! replicate4S zero" %}
13260 ins_encode %{
13261 __ dmtc1(R0, $dst$$FloatRegister);
13262 %}
13263 ins_pipe( pipe_mtc1 );
13264 %}
13266 instruct Repl4S_M1(vecD dst, immI_M1 M1) %{
13267 predicate(n->as_Vector()->length() == 4);
13268 match(Set dst (ReplicateS M1));
13269 format %{ "dmtc1 -1, $dst\t! replicate4S -1" %}
13270 ins_encode %{
13271 __ nor(AT, R0, R0);
13272 __ dmtc1(AT, $dst$$FloatRegister);
13273 %}
13274 ins_pipe( pipe_mtc1 );
13275 %}
13277 // Replicate integer (4 byte) scalar to be vector
13278 instruct Repl2I(vecD dst, mRegI src) %{
13279 predicate(n->as_Vector()->length() == 2);
13280 match(Set dst (ReplicateI src));
13281 format %{ "dins AT, $src, 0, 32\n\t"
13282 "dinsu AT, $src, 32, 32\n\t"
13283 "dmtc1 AT, $dst\t! replicate2I" %}
13284 ins_encode %{
13285 __ dins(AT, $src$$Register, 0, 32);
13286 __ dinsu(AT, $src$$Register, 32, 32);
13287 __ dmtc1(AT, $dst$$FloatRegister);
13288 %}
13289 ins_pipe( pipe_mtc1 );
13290 %}
13292 // Replicate integer (4 byte) scalar immediate to be vector by loading from const table.
13293 instruct Repl2I_imm(vecD dst, immI con, mA7RegI tmp) %{
13294 predicate(n->as_Vector()->length() == 2);
13295 match(Set dst (ReplicateI con));
13296 effect(KILL tmp);
13297 format %{ "li32 AT, [$con], 32\n\t"
13298 "replv_pw AT, AT\n\t"
13299 "dmtc1 AT, $dst\t! replicate2I($con)" %}
13300 ins_encode %{
13301 int val = $con$$constant;
13302 __ li32(AT, val);
13303 __ replv_pw(AT, AT);
13304 __ dmtc1(AT, $dst$$FloatRegister);
13305 %}
13306 ins_pipe( pipe_mtc1 );
13307 %}
13309 // Replicate integer (4 byte) scalar zero to be vector
13310 instruct Repl2I_zero(vecD dst, immI0 zero) %{
13311 predicate(n->as_Vector()->length() == 2);
13312 match(Set dst (ReplicateI zero));
13313 format %{ "dmtc1 R0, $dst\t! replicate2I zero" %}
13314 ins_encode %{
13315 __ dmtc1(R0, $dst$$FloatRegister);
13316 %}
13317 ins_pipe( pipe_mtc1 );
13318 %}
13320 // Replicate integer (4 byte) scalar -1 to be vector
13321 instruct Repl2I_M1(vecD dst, immI_M1 M1) %{
13322 predicate(n->as_Vector()->length() == 2);
13323 match(Set dst (ReplicateI M1));
13324 format %{ "dmtc1 -1, $dst\t! replicate2I -1, use AT" %}
13325 ins_encode %{
13326 __ nor(AT, R0, R0);
13327 __ dmtc1(AT, $dst$$FloatRegister);
13328 %}
13329 ins_pipe( pipe_mtc1 );
13330 %}
13332 // Replicate float (4 byte) scalar to be vector
13333 instruct Repl2F(vecD dst, regF src) %{
13334 predicate(n->as_Vector()->length() == 2);
13335 match(Set dst (ReplicateF src));
13336 format %{ "cvt.ps $dst, $src, $src\t! replicate2F" %}
13337 ins_encode %{
13338 __ cvt_ps_s($dst$$FloatRegister, $src$$FloatRegister, $src$$FloatRegister);
13339 %}
13340 ins_pipe( pipe_slow );
13341 %}
13343 // Replicate float (4 byte) scalar zero to be vector
13344 instruct Repl2F_zero(vecD dst, immF0 zero) %{
13345 predicate(n->as_Vector()->length() == 2);
13346 match(Set dst (ReplicateF zero));
13347 format %{ "dmtc1 R0, $dst\t! replicate2F zero" %}
13348 ins_encode %{
13349 __ dmtc1(R0, $dst$$FloatRegister);
13350 %}
13351 ins_pipe( pipe_mtc1 );
13352 %}
13355 // ====================VECTOR ARITHMETIC=======================================
13357 // --------------------------------- ADD --------------------------------------
13359 // Floats vector add
13360 instruct vadd2F(vecD dst, vecD src) %{
13361 predicate(n->as_Vector()->length() == 2);
13362 match(Set dst (AddVF dst src));
13363 format %{ "add.ps $dst,$src\t! add packed2F" %}
13364 ins_encode %{
13365 __ add_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13366 %}
13367 ins_pipe( pipe_slow );
13368 %}
13370 instruct vadd2F3(vecD dst, vecD src1, vecD src2) %{
13371 predicate(n->as_Vector()->length() == 2);
13372 match(Set dst (AddVF src1 src2));
13373 format %{ "add.ps $dst,$src1,$src2\t! add packed2F" %}
13374 ins_encode %{
13375 __ add_ps($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13376 %}
13377 ins_pipe( fpu_regF_regF );
13378 %}
13380 // --------------------------------- SUB --------------------------------------
13382 // Floats vector sub
13383 instruct vsub2F(vecD dst, vecD src) %{
13384 predicate(n->as_Vector()->length() == 2);
13385 match(Set dst (SubVF dst src));
13386 format %{ "sub.ps $dst,$src\t! sub packed2F" %}
13387 ins_encode %{
13388 __ sub_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13389 %}
13390 ins_pipe( fpu_regF_regF );
13391 %}
13393 // --------------------------------- MUL --------------------------------------
13395 // Floats vector mul
13396 instruct vmul2F(vecD dst, vecD src) %{
13397 predicate(n->as_Vector()->length() == 2);
13398 match(Set dst (MulVF dst src));
13399 format %{ "mul.ps $dst, $src\t! mul packed2F" %}
13400 ins_encode %{
13401 __ mul_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13402 %}
13403 ins_pipe( fpu_regF_regF );
13404 %}
13406 instruct vmul2F3(vecD dst, vecD src1, vecD src2) %{
13407 predicate(n->as_Vector()->length() == 2);
13408 match(Set dst (MulVF src1 src2));
13409 format %{ "mul.ps $dst, $src1, $src2\t! mul packed2F" %}
13410 ins_encode %{
13411 __ mul_ps($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13412 %}
13413 ins_pipe( fpu_regF_regF );
13414 %}
13416 // --------------------------------- DIV --------------------------------------
13417 // MIPS do not have div.ps
13420 //----------PEEPHOLE RULES-----------------------------------------------------
13421 // These must follow all instruction definitions as they use the names
13422 // defined in the instructions definitions.
13423 //
13424 // peepmatch ( root_instr_name [preceeding_instruction]* );
13425 //
13426 // peepconstraint %{
13427 // (instruction_number.operand_name relational_op instruction_number.operand_name
13428 // [, ...] );
13429 // // instruction numbers are zero-based using left to right order in peepmatch
13430 //
13431 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13432 // // provide an instruction_number.operand_name for each operand that appears
13433 // // in the replacement instruction's match rule
13434 //
13435 // ---------VM FLAGS---------------------------------------------------------
13436 //
13437 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13438 //
13439 // Each peephole rule is given an identifying number starting with zero and
13440 // increasing by one in the order seen by the parser. An individual peephole
13441 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13442 // on the command-line.
13443 //
13444 // ---------CURRENT LIMITATIONS----------------------------------------------
13445 //
13446 // Only match adjacent instructions in same basic block
13447 // Only equality constraints
13448 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13449 // Only one replacement instruction
13450 //
13451 // ---------EXAMPLE----------------------------------------------------------
13452 //
13453 // // pertinent parts of existing instructions in architecture description
13454 // instruct movI(eRegI dst, eRegI src) %{
13455 // match(Set dst (CopyI src));
13456 // %}
13457 //
13458 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13459 // match(Set dst (AddI dst src));
13460 // effect(KILL cr);
13461 // %}
13462 //
13463 // // Change (inc mov) to lea
13464 // peephole %{
13465 // // increment preceeded by register-register move
13466 // peepmatch ( incI_eReg movI );
13467 // // require that the destination register of the increment
13468 // // match the destination register of the move
13469 // peepconstraint ( 0.dst == 1.dst );
13470 // // construct a replacement instruction that sets
13471 // // the destination to ( move's source register + one )
13472 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13473 // %}
13474 //
13475 // Implementation no longer uses movX instructions since
13476 // machine-independent system no longer uses CopyX nodes.
13477 //
13478 // peephole %{
13479 // peepmatch ( incI_eReg movI );
13480 // peepconstraint ( 0.dst == 1.dst );
13481 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13482 // %}
13483 //
13484 // peephole %{
13485 // peepmatch ( decI_eReg movI );
13486 // peepconstraint ( 0.dst == 1.dst );
13487 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13488 // %}
13489 //
13490 // peephole %{
13491 // peepmatch ( addI_eReg_imm movI );
13492 // peepconstraint ( 0.dst == 1.dst );
13493 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13494 // %}
13495 //
13496 // peephole %{
13497 // peepmatch ( addP_eReg_imm movP );
13498 // peepconstraint ( 0.dst == 1.dst );
13499 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13500 // %}
13502 // // Change load of spilled value to only a spill
13503 // instruct storeI(memory mem, eRegI src) %{
13504 // match(Set mem (StoreI mem src));
13505 // %}
13506 //
13507 // instruct loadI(eRegI dst, memory mem) %{
13508 // match(Set dst (LoadI mem));
13509 // %}
13510 //
13511 //peephole %{
13512 // peepmatch ( loadI storeI );
13513 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13514 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13515 //%}
13517 //----------SMARTSPILL RULES---------------------------------------------------
13518 // These must follow all instruction definitions as they use the names
13519 // defined in the instructions definitions.
