Mon, 20 Feb 2017 21:35:55 +0800
[Assembler] Redefine the srl instruction for MIPS.
src/cpu/mips/vm/assembler_mips.hpp | file | annotate | diff | comparison | revisions | |
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/assembler_mips.hpp Mon Feb 20 21:27:49 2017 +0800 1.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp Mon Feb 20 21:35:55 2017 +0800 1.3 @@ -1207,7 +1207,7 @@ 1.4 void sltu (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), sltu_op)); } 1.5 void sra (Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, sra_op)); } 1.6 void srav (Register rd, Register rt, Register rs) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), srav_op)); } 1.7 - void srl (Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, srl_op)); } 1.8 + void srl (Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), low(sa, 5), srl_op)); } 1.9 void srlv (Register rd, Register rt, Register rs) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), srlv_op)); } 1.10 1.11 #ifndef _LP64
2.1 --- a/src/cpu/mips/vm/mips_64.ad Mon Feb 20 21:27:49 2017 +0800 2.2 +++ b/src/cpu/mips/vm/mips_64.ad Mon Feb 20 21:35:55 2017 +0800 2.3 @@ -11097,13 +11097,8 @@ 2.4 Register src = $src$$Register; 2.5 Register dst = $dst$$Register; 2.6 int shift = $shift$$constant; 2.7 - if (shift > 0) 2.8 - __ srl(dst, src, shift); 2.9 - else 2.10 - { 2.11 - __ move(AT, shift); 2.12 - __ srlv(dst, src, AT); 2.13 - } 2.14 + 2.15 + __ srl(dst, src, shift); 2.16 %} 2.17 ins_pipe( ialu_regI_regI ); 2.18 %}