| Wed, 04 Dec 2019 18:01:06 +0800 |
#10637: java/util/stream/test/org/openjdk/tests/java/util/stream/SliceOpTest.java fails with -XX:ReservedCodeCacheSize=256m |
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| Mon, 18 Nov 2019 10:41:48 +0800 |
#10052 Backport of #9904 compiler/floatingpoint/TestFloatSyncJNIArgs.java failed |
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| Wed, 28 Aug 2019 15:25:12 +0800 |
#9929 Backport of #9903 compiler/c2/TestMatcherLargeOffset.java crash |
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| Thu, 05 Sep 2019 13:07:31 +0800 |
#9372 Refactor VM_Version, removed UseLoongsonISA and Use3A3000, added UseLEXT1, UseLEXT2, UseLEXT3. |
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| Tue, 05 Mar 2019 17:00:17 +0800 |
#8573 Cleanup: x86 registers in comments; comment style; deadcode |
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| Fri, 22 Feb 2019 18:54:50 +0800 |
#8215 The low 4 bits of off must be 0 in gslq/gssq/gslqc1/gssqc1. |
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| Fri, 18 Jan 2019 16:12:54 +0800 |
#8151 [Assembler] Add gslqc1/gssqc1 for Loongson CPUs. |
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| Fri, 07 Dec 2018 14:53:37 +0800 |
#7987 implements tieredcompilation in mips template interpreter |
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| Thu, 15 Nov 2018 11:52:03 +0800 |
#7877 Follows c22fe8047623, range checking for xori should be regarded as 16-bit unsigned integer |
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| Wed, 14 Nov 2018 10:57:37 +0800 |
#7878 #7879 AT was forbidened in Address constructors and unsupported index register in memory addressing was asserted |
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| Tue, 13 Nov 2018 16:56:02 +0800 |
#7877 range checking was added for the immediate field of mips instructions |
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| Mon, 05 Nov 2018 16:56:18 +0800 |
#7837 fixed assembler of MIPS break instruction |
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| Tue, 17 Jul 2018 20:32:39 +0800 |
#7326 mips generates wrong code for jal/j machine instructions |
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| Tue, 28 Nov 2017 15:31:16 +0800 |
#6313 disable DSP support on Loongson CPUs, added asserts when DSP instructions are generated. |
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| Thu, 23 Nov 2017 14:26:38 +0800 |
fixed assembler, code cleanup and code style fix |
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| Mon, 23 Oct 2017 17:07:19 +0800 |
[G1] Initial porting of MacroAssembler::g1_write_barrier_{pre/post} |
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| Thu, 07 Sep 2017 09:12:16 +0800 |
#5745 [Code Reorganization] code cleanup and code style fix |
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| Tue, 16 May 2017 16:35:16 -0400 |
#5400 Fix shift instructions with negtive parameters. |
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| Mon, 10 Apr 2017 14:48:12 -0400 |
[C2] Remove unnecessary nops for code alignment. |
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| Mon, 10 Apr 2017 15:46:40 +0800 |
[C2] Optimized CMoveF and CMoveD. |
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| Fri, 31 Mar 2017 12:43:02 -0400 |
[C2] Optimize the oop/klass encoding and decoding (Follows a4946a9e94b0). |
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| Sun, 19 Mar 2017 17:04:32 -0400 |
[C2] Add patchable_call for MIPS. |
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| Thu, 16 Mar 2017 21:58:58 +0800 |
[MacroAssembler] Add general_j & general_jal for MIPS. |
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| Wed, 08 Mar 2017 05:42:36 -0500 |
Expand NativeCall::return_address_offset to NativeCall::return_address_offset_short & NativeCall::return_address_offset_long for MIPS. |
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| Thu, 09 Mar 2017 16:31:15 +0800 |
[Code Reorganization] gsandn/gsorn is SPECIAL2 not SPECIAL3. |
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| Thu, 09 Mar 2017 15:11:22 +0800 |
#4784 [interpreter] Use array bounds check instructions to optimize array load and store bytecodes. |
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| Wed, 01 Mar 2017 00:42:08 -0500 |
[C2] Rewrite loadConN & loadConNKlass in mips_64.ad |
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| Tue, 28 Feb 2017 09:53:43 -0500 |
[C2] Remove storeImmN & storeImmNKlass in mips_64.ad |
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| Mon, 20 Feb 2017 21:35:55 +0800 |
[Assembler] Redefine the srl instruction for MIPS. |
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| Mon, 20 Feb 2017 21:27:49 +0800 |
[Assembler] Redefine the sll instruction for MIPS. |
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| Sat, 18 Feb 2017 18:25:01 -0500 |
[Assembler] Add right-rotate instructions for MIPS. |
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| Wed, 15 Feb 2017 10:22:07 -0500 |
[C2] Add instruct andL_Reg_immL_nonneg_mask in mips_64.ad |
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| Tue, 14 Feb 2017 18:51:47 -0500 |
[Assembler] Add gsandn/gsorn for Loongson CPUs. |
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| Tue, 14 Feb 2017 15:44:26 -0500 |
[C2] Enable instruct dins for MIPS CPUs. |
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| Tue, 14 Feb 2017 14:46:37 -0500 |
[C2] Add instruct shr_logical_Reg_imm_nonneg_mask in mips_64.add |
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| Mon, 13 Feb 2017 20:01:12 -0500 |
[C2] Add shr_logical_Reg_imm_mask63 in mips_64.ad |
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| Thu, 09 Feb 2017 04:53:02 -0500 |
[C2] Adjust the loading of long constants for MIPS. |
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| Thu, 09 Feb 2017 01:25:47 -0500 |
[Assembler] set64 & insts_for_set64 for MIPS are ported from sparc. |
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| Tue, 07 Feb 2017 11:22:07 +0800 |
#5022 [Assembler] Fix cvt_ps_s |
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| Wed, 01 Feb 2017 22:24:47 +0800 |
Add seb/seh instructions for MIPS CPUs. |
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| Fri, 09 Jun 2017 20:32:45 +0800 |
Rewrited Assembler, added new opcode and instructions, improved Disassembler. |
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| Fri, 09 Jun 2017 20:26:42 +0800 |
[Assembler] Add madd.fmt instruction for MIPS. |
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| Tue, 11 Oct 2016 08:56:49 +0800 |
Fixed the generation of offset part of some GS instructions. |
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| Sun, 09 Oct 2016 15:36:29 +0800 |
#4536 Added 128-bit memory access to generate_disjoint_short_copy. |
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| Thu, 18 Aug 2016 11:54:02 +0800 |
Fix a bug in the definitions of (gslwxc1/gsldxc1/gsswxc1/gssdxc1): Register --> FloatRegister. |
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| Thu, 18 Aug 2016 11:33:16 +0800 |
Add gsswxc1 and gssdxc1 instructions. |
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| Thu, 18 Aug 2016 11:29:03 +0800 |
Add gslwxc1 and gsldxc1 instruction. |
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| Tue, 16 Aug 2016 15:31:40 +0800 |
Add gslhx/gslbx instructions for Loongson processors. |
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| Tue, 16 Aug 2016 15:25:30 +0800 |
Add gsshx/gssbx instructions for Loongson processors. |
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| Tue, 16 Aug 2016 15:15:02 +0800 |
Add gsswx/gssdx instructions for Loongson processors. |
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| Wed, 10 Aug 2016 10:30:35 +0800 |
Add gsdmod instruction for Loongson processors. |
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| Wed, 10 Aug 2016 10:09:13 +0800 |
Add gsddiv instruction for Loongson processors. |
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| Wed, 10 Aug 2016 09:41:55 +0800 |
Add gsdmult instruction for Loongson processors. |
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| Wed, 10 Aug 2016 09:35:32 +0800 |
Add gsmod instruction for Loongson processors. |
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| Wed, 10 Aug 2016 09:06:24 +0800 |
Add gsdiv instruction for Loongson processors. |
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| Tue, 02 Aug 2016 18:49:44 +0800 |
Add multiply and add/subtract instructions (madd and msub) in MIPS assembler. |
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| Mon, 01 Aug 2016 19:34:35 +0800 |
Add move conditional instructions (movt and movf) in MIPS assembler. |
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| Sat, 30 Jul 2016 01:42:17 +0800 |
Instruction decoding support: add gsldx and gslwx in MIPS disassembler. |
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| Tue, 26 Jul 2016 17:06:17 +0800 |
Add multiply word to GPR instruction (mul) in MIPS assembler. |
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| Mon, 25 Jul 2016 11:37:27 +0800 |
Add move conditional instructions (movz and movn) in MIPS assembler. |
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