Add move conditional instructions (movz and movn) in MIPS assembler.

Mon, 25 Jul 2016 11:37:27 +0800

author
fujie
date
Mon, 25 Jul 2016 11:37:27 +0800
changeset 37
440521e9c713
parent 36
e32766b58924
child 38
f0e26f502a50

Add move conditional instructions (movz and movn) in MIPS assembler.

src/cpu/mips/vm/assembler_mips.hpp file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/assembler_mips.hpp	Fri Jul 15 10:54:18 2016 +0800
     1.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp	Mon Jul 25 11:37:27 2016 +0800
     1.3 @@ -434,6 +434,8 @@
     1.4  		srav_op 		= 0x07,
     1.5  		jr_op				= 0x08,
     1.6  		jalr_op			= 0x09,
     1.7 +		movz_op			= 0x0a,
     1.8 +		movn_op			= 0x0b,
     1.9  		syscall_op	= 0x0c,
    1.10  		break_op		= 0x0d,
    1.11  		sync_op			= 0x0f,
    1.12 @@ -853,6 +855,10 @@
    1.13  	void daddu (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), daddu_op)); }
    1.14  	void ddiv  (Register rs, Register rt)              { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, ddiv_op));	}
    1.15  	void ddivu (Register rs, Register rt)              { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, ddivu_op)); }
    1.16 +
    1.17 +	void movz  (Register rd, Register rs,   Register rt) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), movz_op)); }	
    1.18 +	void movn  (Register rd, Register rs,   Register rt) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), movn_op)); }	
    1.19 +
    1.20  // Do mult and div need both 32-bit and 64-bit version? FIXME aoqi
    1.21  //#ifndef _LP64
    1.22  #if 1

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