1.1 --- a/src/cpu/mips/vm/assembler_mips.hpp Sun Feb 19 17:42:22 2017 +0800
1.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp Sat Feb 18 18:25:01 2017 -0500
1.3 @@ -1092,6 +1092,26 @@
1.4 emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (msbd << 11) | (lsb << 6) | dext_op);
1.5 }
1.6
1.7 + void rotr (Register rd, Register rt, int sa) {
1.8 + emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | srl_op);
1.9 + }
1.10 +
1.11 + void drotr (Register rd, Register rt, int sa) {
1.12 + emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | dsrl_op);
1.13 + }
1.14 +
1.15 + void drotr32 (Register rd, Register rt, int sa) {
1.16 + emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | dsrl32_op);
1.17 + }
1.18 +
1.19 + void rotrv (Register rd, Register rt, Register rs) {
1.20 + emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | srlv_op);
1.21 + }
1.22 +
1.23 + void drotrv (Register rd, Register rt, Register rs) {
1.24 + emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | dsrlv_op);
1.25 + }
1.26 +
1.27 // Do mult and div need both 32-bit and 64-bit version? FIXME aoqi
1.28 //#ifndef _LP64
1.29 #if 1
