Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
[C2] Remove storeImmN & storeImmNKlass in mips_64.ad
Tue, 28 Feb 2017 09:53:43 -0500
- author
- fujie
- date
- Tue, 28 Feb 2017 09:53:43 -0500
- changeset 340
- c0f304ca7c67
- parent 339
- e85176985dae
- child 341
- aa7285c094cd
[C2] Remove storeImmN & storeImmNKlass in mips_64.ad
1.1 --- a/src/cpu/mips/vm/assembler_mips.cpp Mon Feb 27 16:49:02 2017 +0800 1.2 +++ b/src/cpu/mips/vm/assembler_mips.cpp Tue Feb 28 09:53:43 2017 -0500 1.3 @@ -2347,6 +2347,78 @@ 1.4 return count; 1.5 } 1.6 1.7 +void MacroAssembler::patchable_set48(Register d, jlong value) { 1.8 + assert_not_delayed(); 1.9 + 1.10 + int hi = (int)(value >> 32); 1.11 + int lo = (int)(value & ~0); 1.12 + 1.13 + int count = 0; 1.14 + 1.15 + if (value == lo) { // 32-bit integer 1.16 + if (is_simm16(value)) { 1.17 + daddiu(d, R0, value); 1.18 + count += 1; 1.19 + } else { 1.20 + lui(d, split_low(value >> 16)); 1.21 + count += 1; 1.22 + if (split_low(value)) { 1.23 + ori(d, d, split_low(value)); 1.24 + count += 1; 1.25 + } 1.26 + } 1.27 + } else if (hi == 0) { // hardware zero-extends to upper 32 1.28 + ori(d, R0, julong(value) >> 16); 1.29 + dsll(d, d, 16); 1.30 + count += 2; 1.31 + if (split_low(value)) { 1.32 + ori(d, d, split_low(value)); 1.33 + count += 1; 1.34 + } 1.35 + } else if ((value> 0) && is_simm16(value >> 32)) { // li48 1.36 + // 4 insts 1.37 + li48(d, value); 1.38 + count += 4; 1.39 + } else { // li64 1.40 + tty->print_cr("In MacroAssembler::patchable_set48, value = 0x%x", value); 1.41 + guarantee(false, "Not supported yet !"); 1.42 + } 1.43 + 1.44 + for (count; count < 4; count++) { 1.45 + nop(); 1.46 + } 1.47 +} 1.48 + 1.49 +void MacroAssembler::patchable_set32(Register d, jlong value) { 1.50 + assert_not_delayed(); 1.51 + 1.52 + int hi = (int)(value >> 32); 1.53 + int lo = (int)(value & ~0); 1.54 + 1.55 + int count = 0; 1.56 + 1.57 + if (value == lo) { // 32-bit integer 1.58 + if (is_simm16(value)) { 1.59 + daddiu(d, R0, value); 1.60 + count += 1; 1.61 + } else { 1.62 + lui(d, split_low(value >> 16)); 1.63 + count += 1; 1.64 + if (split_low(value)) { 1.65 + ori(d, d, split_low(value)); 1.66 + count += 1; 1.67 + } 1.68 + } 1.69 + } else { 1.70 + tty->print_cr("In MacroAssembler::patchable_set32, value = 0x%x", value); 1.71 + guarantee(false, "Not supported yet !"); 1.72 + } 1.73 + 1.74 + for (count; count < 2; count++) { 1.75 + nop(); 1.76 + } 1.77 +} 1.78 + 1.79 void MacroAssembler::li64(Register rd, long imm) { 1.80 assert_not_delayed(); 1.81 lui(rd, imm >> 48);
2.1 --- a/src/cpu/mips/vm/assembler_mips.hpp Mon Feb 27 16:49:02 2017 +0800 2.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp Tue Feb 28 09:53:43 2017 -0500 2.3 @@ -2335,6 +2335,9 @@ 2.4 void set64(Register d, jlong value); 2.5 static int insts_for_set64(jlong value); 2.6 2.7 + void patchable_set48(Register d, jlong value); 2.8 + void patchable_set32(Register d, jlong value); 2.9 + 2.10 void dli(Register rd, long imm) { li(rd, imm); } 2.11 void li64(Register rd, long imm); 2.12 void li48(Register rd, long imm);
3.1 --- a/src/cpu/mips/vm/mips_64.ad Mon Feb 27 16:49:02 2017 +0800 3.2 +++ b/src/cpu/mips/vm/mips_64.ad Tue Feb 28 09:53:43 2017 -0500 3.3 @@ -2670,168 +2670,6 @@ 3.4 } 3.5 %} 3.6 3.7 -/* 3.8 - * 1d4 storeImmN [S0 + #16 (8-bit)], narrowoop: spec/benchmarks/_213_javac/Identifier:exact * 3.9 - * # compressed ptr ! Field: spec/benchmarks/_213_javac/Identifier.value 3.10 - * 0x00000055648065d4: daddu at, s0, zero 3.11 - * 0x00000055648065d8: lui t9, 0x0 ; {oop(a 'spec/benchmarks/_213_javac/Identifier')} 3.12 - * 0x00000055648065dc: ori t9, t9, 0xfffff610 3.13 - * 0x00000055648065e0: dsll t9, t9, 16 3.14 - * 0x00000055648065e4: ori t9, t9, 0xffffc628 3.15 - * 0x00000055648065e8: sw t9, 0x10(at) 3.16 - */ 3.17 - enc_class storeImmN_enc (memory mem, immN src) %{ 3.18 - MacroAssembler _masm(&cbuf); 3.19 - int base = $mem$$base; 3.20 - int index = $mem$$index; 3.21 - int scale = $mem$$scale; 3.22 - int disp = $mem$$disp; 3.23 - long * value = (long *)$src$$constant; 3.24 - 3.25 - if (value == NULL) { 3.26 - guarantee(Assembler::is_simm16(disp), "FIXME: disp is not simm16!"); 3.27 - if (index == 0) { 3.28 - __ sw(R0, as_Register(base), disp); 3.29 - } else { 3.30 - if (scale == 0) { 3.31 - __ daddu(AT, as_Register(base), as_Register(index)); 3.32 - } else { 3.33 - __ dsll(AT, as_Register(index), scale); 3.34 - __ daddu(AT, as_Register(base), AT); 3.35 - } 3.36 - __ sw(R0, AT, disp); 3.37 - } 3.38 - 3.39 - return; 3.40 - } 3.41 - 3.42 - int oop_index = __ oop_recorder()->find_index((jobject)value); 3.43 - RelocationHolder rspec = oop_Relocation::spec(oop_index); 3.44 - 3.45 - guarantee(scale == 0, "FIXME: scale is not zero !"); 3.46 - guarantee(value != 0, "FIXME: value is zero !"); 3.47 - 3.48 - if (index != 0) { 3.49 - if (scale == 0) { 3.50 - __ daddu(AT, as_Register(base), as_Register(index)); 3.51 - } else { 3.52 - __ dsll(AT, as_Register(index), scale); 3.53 - __ daddu(AT, as_Register(base), AT); 3.54 - } 3.55 - if( Assembler::is_simm16(disp) ) { 3.56 - if(rspec.type() != relocInfo::none) { 3.57 - __ relocate(rspec, Assembler::narrow_oop_operand); 3.58 - __ li48(T9, oop_index); 3.59 - } else { 3.60 - __ set64(T9, oop_index); 3.61 - } 3.62 - __ sw(T9, AT, disp); 3.63 - } else { 3.64 - __ move(T9, disp); 3.65 - __ addu(AT, AT, T9); 3.66 - 3.67 - if(rspec.type() != relocInfo::none) { 3.68 - __ relocate(rspec, Assembler::narrow_oop_operand); 3.69 - __ li48(T9, oop_index); 3.70 - } else { 3.71 - __ set64(T9, oop_index); 3.72 - } 3.73 - __ sw(T9, AT, 0); 3.74 - } 3.75 - } 3.76 - else { 3.77 - if( Assembler::is_simm16(disp) ) { 3.78 - if($src->constant_reloc() != relocInfo::none) { 3.79 - __ relocate(rspec, Assembler::narrow_oop_operand); 3.80 - __ li48(T9, oop_index); 3.81 - } else { 3.82 - __ set64(T9, oop_index); 3.83 - } 3.84 - __ sw(T9, as_Register(base), disp); 3.85 - } else { 3.86 - __ move(T9, disp); 3.87 - __ daddu(AT, as_Register(base), T9); 3.88 - 3.89 - if($src->constant_reloc() != relocInfo::none){ 3.90 - __ relocate(rspec, Assembler::narrow_oop_operand); 3.91 - __ li48(T9, oop_index); 3.92 - } else { 3.93 - __ set64(T9, oop_index); 3.94 - } 3.95 - __ sw(T9, AT, 0); 3.96 - } 3.97 - } 3.98 - %} 3.99 - 3.100 - enc_class storeImmNKlass_enc (memory mem, immNKlass src) %{ 3.101 - MacroAssembler _masm(&cbuf); 3.102 - 3.103 - assert (UseCompressedOops, "should only be used for compressed headers"); 3.104 - assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3.105 - 3.106 - int base = $mem$$base; 3.107 - int index = $mem$$index; 3.108 - int scale = $mem$$scale; 3.109 - int disp = $mem$$disp; 3.110 - long value = $src$$constant; 3.111 - 3.112 - int klass_index = __ oop_recorder()->find_index((Klass*)value); 3.113 - RelocationHolder rspec = metadata_Relocation::spec(klass_index); 3.114 - long narrowp = Klass::encode_klass((Klass*)value); 3.115 - 3.116 - if(index!=0){ 3.117 - if (scale == 0) { 3.118 - __ daddu(AT, as_Register(base), as_Register(index)); 3.119 - } else { 3.120 - __ dsll(AT, as_Register(index), scale); 3.121 - __ daddu(AT, as_Register(base), AT); 3.122 - } 3.123 - 3.124 - if( Assembler::is_simm16(disp) ) { 3.125 - if(rspec.type() != relocInfo::none){ 3.126 - __ relocate(rspec, Assembler::narrow_oop_operand); 3.127 - __ li48(T9, narrowp); 3.128 - } else { 3.129 - __ set64(T9, narrowp); 3.130 - } 3.131 - __ sw(T9, AT, disp); 3.132 - } else { 3.133 - __ move(T9, disp); 3.134 - __ daddu(AT, AT, T9); 3.135 - 3.136 - if(rspec.type() != relocInfo::none){ 3.137 - __ relocate(rspec, Assembler::narrow_oop_operand); 3.138 - __ li48(T9, narrowp); 3.139 - } else { 3.140 - __ set64(T9, narrowp); 3.141 - } 3.142 - 3.143 - __ sw(T9, AT, 0); 3.144 - } 3.145 - } else { 3.146 - if( Assembler::is_simm16(disp) ) { 3.147 - if(rspec.type() != relocInfo::none){ 3.148 - __ relocate(rspec, Assembler::narrow_oop_operand); 3.149 - __ li48(T9, narrowp); 3.150 - } 3.151 - else { 3.152 - __ set64(T9, narrowp); 3.153 - } 3.154 - __ sw(T9, as_Register(base), disp); 3.155 - } else { 3.156 - __ move(T9, disp); 3.157 - __ daddu(AT, as_Register(base), T9); 3.158 - 3.159 - if(rspec.type() != relocInfo::none){ 3.160 - __ relocate(rspec, Assembler::narrow_oop_operand); 3.161 - __ li48(T9, narrowp); 3.162 - } else { 3.163 - __ set64(T9, narrowp); 3.164 - } 3.165 - __ sw(T9, AT, 0); 3.166 - } 3.167 - } 3.168 - %} 3.169 3.170 enc_class storeImmN0_enc(memory mem, ImmN0 src) %{ 3.171 MacroAssembler _masm(&cbuf); 3.172 @@ -6334,26 +6172,6 @@ 3.173 ins_pipe( ialu_storeI ); 3.174 %} 3.175 3.176 -instruct storeImmN(memory mem, immN src) 3.177 -%{ 3.178 - match(Set mem (StoreN mem src)); 3.179 - 3.180 - ins_cost(150); // XXX 3.181 - format %{ "storeImmN $mem, $src\t# compressed ptr @ storeImmN" %} 3.182 - ins_encode(storeImmN_enc(mem, src)); 3.183 - ins_pipe( ialu_storeI ); 3.184 -%} 3.185 - 3.186 -instruct storeImmNKlass(memory mem, immNKlass src) 3.187 -%{ 3.188 - match(Set mem (StoreNKlass mem src)); 3.189 - 3.190 - ins_cost(150); // XXX 3.191 - format %{ "sw $mem, $src\t# compressed klass ptr @ storeImmNKlass" %} 3.192 - ins_encode(storeImmNKlass_enc(mem, src)); 3.193 - ins_pipe( ialu_storeI ); 3.194 -%} 3.195 - 3.196 // Store Byte 3.197 instruct storeB(memory mem, mRegI src) %{ 3.198 match(Set mem (StoreB mem src));
