Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/assembler_mips.hpp	Sun Feb 19 17:42:22 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp	Sat Feb 18 18:25:01 2017 -0500
     1.3 @@ -1092,6 +1092,26 @@
     1.4       emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (msbd << 11) | (lsb << 6) | dext_op); 
     1.5    }
     1.6  
     1.7 +  void rotr (Register rd, Register rt, int sa) { 
     1.8 +     emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | srl_op); 
     1.9 +  }
    1.10 +
    1.11 +  void drotr (Register rd, Register rt, int sa) { 
    1.12 +     emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | dsrl_op); 
    1.13 +  }
    1.14 +
    1.15 +  void drotr32 (Register rd, Register rt, int sa) { 
    1.16 +     emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | dsrl32_op); 
    1.17 +  }
    1.18 +
    1.19 +  void rotrv (Register rd, Register rt, Register rs) { 
    1.20 +     emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | srlv_op); 
    1.21 +  }
    1.22 +
    1.23 +  void drotrv (Register rd, Register rt, Register rs) { 
    1.24 +     emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | dsrlv_op); 
    1.25 +  }
    1.26 +
    1.27  // Do mult and div need both 32-bit and 64-bit version? FIXME aoqi
    1.28  //#ifndef _LP64
    1.29  #if 1

     2.1 --- a/src/cpu/mips/vm/disassembler_mips.cpp	Sun Feb 19 17:42:22 2017 +0800
     2.2 +++ b/src/cpu/mips/vm/disassembler_mips.cpp	Sat Feb 18 18:25:01 2017 -0500
     2.3 @@ -318,13 +318,41 @@
     2.4        special = Assembler::special(insn);
     2.5        switch(special) {
     2.6          case Assembler::sll_op:
     2.7 +          PRINT_ORRS(Assembler::special_name[special]);
     2.8 +          break;
     2.9          case Assembler::srl_op:
    2.10 +          if (insn & (1 << 21)) {
    2.11 +             PRINT_ORRS("rotr");
    2.12 +          } else {
    2.13 +             PRINT_ORRS(Assembler::special_name[special]);
    2.14 +          }
    2.15 +          break;
    2.16          case Assembler::sra_op:
    2.17 +          PRINT_ORRS(Assembler::special_name[special]);
    2.18 +          break;
    2.19          case Assembler::dsll_op:
    2.20 +          PRINT_ORRS(Assembler::special_name[special]);
    2.21 +          break;
    2.22          case Assembler::dsrl_op:
    2.23 +          if (insn & (1 << 21)) {
    2.24 +             PRINT_ORRS("drotr");
    2.25 +          } else {
    2.26 +             PRINT_ORRS(Assembler::special_name[special]);
    2.27 +          }
    2.28 +          break;
    2.29          case Assembler::dsra_op:
    2.30 +          PRINT_ORRS(Assembler::special_name[special]);
    2.31 +          break;
    2.32          case Assembler::dsll32_op:
    2.33 +          PRINT_ORRS(Assembler::special_name[special]);
    2.34 +          break;
    2.35          case Assembler::dsrl32_op:
    2.36 +          if (insn & (1 << 21)) {
    2.37 +             PRINT_ORRS("drotr32");
    2.38 +          } else {
    2.39 +             PRINT_ORRS(Assembler::special_name[special]);
    2.40 +          }
    2.41 +          break;
    2.42          case Assembler::dsra32_op:
    2.43            PRINT_ORRS(Assembler::special_name[special]);
    2.44            break;
    2.45 @@ -339,10 +367,28 @@
    2.46            break;
    2.47  
    2.48          case Assembler::sllv_op:
    2.49 +          PRINT_ORRR_2(Assembler::special_name[special]);
    2.50 +          break;
    2.51          case Assembler::srlv_op:
    2.52 +          if (insn & (1 << 6)) {
    2.53 +             PRINT_ORRR_2("rotrv");
    2.54 +          } else {
    2.55 +             PRINT_ORRR_2(Assembler::special_name[special]);
    2.56 +          }
    2.57 +          break;
    2.58          case Assembler::srav_op:
    2.59 +          PRINT_ORRR_2(Assembler::special_name[special]);
    2.60 +          break;
    2.61          case Assembler::dsllv_op:
    2.62 +          PRINT_ORRR_2(Assembler::special_name[special]);
    2.63 +          break;
    2.64          case Assembler::dsrlv_op:
    2.65 +          if (insn & (1 << 6)) {
    2.66 +             PRINT_ORRR_2("drotrv");
    2.67 +          } else {
    2.68 +             PRINT_ORRR_2(Assembler::special_name[special]);
    2.69 +          }
    2.70 +          break;
    2.71          case Assembler::dsrav_op:
    2.72            PRINT_ORRR_2(Assembler::special_name[special]);
    2.73            break;