1.1 --- a/src/cpu/mips/vm/assembler_mips.hpp Mon Dec 02 16:01:35 2019 +0800
1.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp Wed Dec 04 18:01:06 2019 +0800
1.3 @@ -1265,6 +1265,7 @@
1.4 void sw (Register rt, Register base, int off) { emit_long(insn_ORRI(sw_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1.5 void swl (Register rt, Register base, int off) { emit_long(insn_ORRI(swl_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1.6 void swr (Register rt, Register base, int off) { emit_long(insn_ORRI(swr_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1.7 + void synci(Register base, int off) { emit_long(insn_ORRI(regimm_op, (int)base->encoding(), synci_op, off)); }
1.8 void sync () { emit_long(sync_op); }
1.9 void syscall(int code) { emit_long( (code<<6) | syscall_op ); }
1.10
