Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/assembler_mips.hpp	Thu Apr 06 14:44:34 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp	Mon Apr 10 15:46:40 2017 +0800
     1.3 @@ -1343,8 +1343,12 @@
     1.4    void ceil_w_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, fceilw_op)}
     1.5    void floor_w_s(FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, ffloorw_op)}
     1.6    //null
     1.7 -  //void movf_s(FloatRegister rd, FloatRegister rs, FPConditionCode cc) { unimplemented(" movf_s")}
     1.8 -  //void movt_s(FloatRegister rd, FloatRegister rs, FPConditionCode cc) { unimplemented(" movt_s") }
     1.9 +  void movf_s(FloatRegister fs, FloatRegister fd, int cc = 0) {
    1.10 +    assert(cc >= 0 && cc <= 7, "cc is 3 bits");
    1.11 +    emit_long((cop1_op<<26) | (single_fmt<<21) | (cc<<18) | ((int)fs->encoding()<<11) | ((int)fd->encoding()<<6) | movf_f_op );}
    1.12 +  void movt_s(FloatRegister fs, FloatRegister fd, int cc = 0) {
    1.13 +    assert(cc >= 0 && cc <= 7, "cc is 3 bits");
    1.14 +    emit_long((cop1_op<<26) | (single_fmt<<21) | (cc<<18) | 1<<16 | ((int)fs->encoding()<<11) | ((int)fd->encoding()<<6) | movf_f_op );}
    1.15    void movz_s  (FloatRegister fd, FloatRegister fs, Register rt) {INSN_SINGLE(rt, fs, fd, movz_f_op)}
    1.16    void movn_s  (FloatRegister fd, FloatRegister fs, Register rt) {INSN_SINGLE(rt, fs, fd, movn_f_op)}
    1.17    //null
    1.18 @@ -1398,8 +1402,12 @@
    1.19    void ceil_w_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, fceilw_op)}
    1.20    void floor_w_d(FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, ffloorw_op)}
    1.21    //null
    1.22 -  //void movf_d(Register rd, Register rs, FPConditionCode cc) { unimplemented(" movf_d")}
    1.23 -  //void movt_d(Register rd, Register rs, FPConditionCode cc) { unimplemented(" movt_d") }
    1.24 +  void movf_d(FloatRegister fs, FloatRegister fd, int cc = 0) {
    1.25 +    assert(cc >= 0 && cc <= 7, "cc is 3 bits");
    1.26 +    emit_long((cop1_op<<26) | (double_fmt<<21) | (cc<<18) | ((int)fs->encoding()<<11) | ((int)fd->encoding()<<6) | movf_f_op );}
    1.27 +  void movt_d(FloatRegister fs, FloatRegister fd, int cc = 0) {
    1.28 +    assert(cc >= 0 && cc <= 7, "cc is 3 bits");
    1.29 +    emit_long((cop1_op<<26) | (double_fmt<<21) | (cc<<18) | 1<<16 | ((int)fs->encoding()<<11) | ((int)fd->encoding()<<6) | movf_f_op );}
    1.30    void movz_d  (FloatRegister fd, FloatRegister fs, Register rt) {INSN_DOUBLE(rt, fs, fd, movz_f_op)}
    1.31    void movn_d  (FloatRegister fd, FloatRegister fs, Register rt) {INSN_DOUBLE(rt, fs, fd, movn_f_op)}
    1.32    //null

     2.1 --- a/src/cpu/mips/vm/mips_64.ad	Thu Apr 06 14:44:34 2017 +0800
     2.2 +++ b/src/cpu/mips/vm/mips_64.ad	Mon Apr 10 15:46:40 2017 +0800
     2.3 @@ -9322,56 +9322,35 @@
     2.4  
     2.5      int     flag = $cop$$cmpcode;
     2.6  
     2.7 -    Label L;
     2.8 -
     2.9      switch(flag)
    2.10      {
    2.11        case 0x01: //equal
    2.12          __ c_eq_d(reg_op1, reg_op2);
    2.13 -        __ bc1f(L);
    2.14 -        __ nop();
    2.15 -        __ mov_d(dst, src);
    2.16 -        __ bind(L); 
    2.17 +        __ movt_d(dst, src);
    2.18          break;
    2.19        case 0x02: //not_equal
    2.20 -//2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
    2.21          __ c_eq_d(reg_op1, reg_op2);
    2.22 -        __ bc1t(L);
    2.23 -        __ nop();
    2.24 -        __ mov_d(dst, src);
    2.25 -        __ bind(L); 
    2.26 +        __ movf_d(dst, src);
    2.27          break;
    2.28        case 0x03: //greater
    2.29          __ c_ole_d(reg_op1, reg_op2);
    2.30 -        __ bc1t(L);
    2.31 -        __ nop();
    2.32 -        __ mov_d(dst, src);
    2.33 -        __ bind(L); 
    2.34 +        __ movf_d(dst, src);
    2.35          break;
    2.36        case 0x04: //greater_equal
    2.37          __ c_olt_d(reg_op1, reg_op2);
    2.38 -        __ bc1t(L);
    2.39 -        __ nop();
    2.40 -        __ mov_d(dst, src);
    2.41 -        __ bind(L); 
    2.42 +        __ movf_d(dst, src);
    2.43          break;
    2.44        case 0x05: //less
    2.45          __ c_ult_d(reg_op1, reg_op2);
    2.46 -        __ bc1f(L);
    2.47 -        __ nop();
    2.48 -        __ mov_d(dst, src);
    2.49 -        __ bind(L); 
    2.50 +        __ movt_d(dst, src);
    2.51          break;
    2.52        case 0x06: //less_equal
    2.53          __ c_ule_d(reg_op1, reg_op2);
    2.54 -        __ bc1f(L);
    2.55 -        __ nop();
    2.56 -        __ mov_d(dst, src);
    2.57 -        __ bind(L); 
    2.58 +        __ movt_d(dst, src);
    2.59          break;
    2.60        default:
    2.61            Unimplemented();
    2.62 -    }  
    2.63 +    }
    2.64    %}
    2.65  
    2.66    ins_pipe( pipe_slow );
    2.67 @@ -9637,56 +9616,32 @@
    2.68      FloatRegister reg_op2 = $tmp2$$FloatRegister;
    2.69      FloatRegister dst = $dst$$FloatRegister;
    2.70      FloatRegister src = $src$$FloatRegister;
    2.71 -    Label  L;
    2.72      int    flag = $cop$$cmpcode;
    2.73  
    2.74      switch(flag)
    2.75      {
    2.76        case 0x01: //equal
    2.77          __ c_eq_s(reg_op1, reg_op2);
    2.78 -        __ bc1f(L);
    2.79 -        __ nop();
    2.80 -        __ mov_s(dst, src);
    2.81 -        __ bind(L);
    2.82 +        __ movt_s(dst, src);
    2.83          break;
    2.84        case 0x02: //not_equal
    2.85          __ c_eq_s(reg_op1, reg_op2);
    2.86 -        __ bc1t(L);
    2.87 -        __ nop();
    2.88 -        __ mov_s(dst, src);
    2.89 -        __ bind(L);
    2.90 -        break;
    2.91 +        __ movf_s(dst, src);
    2.92        case 0x03: //greater
    2.93          __ c_ole_s(reg_op1, reg_op2);
    2.94 -        __ bc1t(L);
    2.95 -        __ nop();
    2.96 -        __ mov_s(dst, src);
    2.97 -        __ bind(L);
    2.98 -        break;
    2.99 +        __ movf_s(dst, src);
   2.100        case 0x04: //greater_equal
   2.101          __ c_olt_s(reg_op1, reg_op2);
   2.102 -        __ bc1t(L);
   2.103 -        __ nop();
   2.104 -        __ mov_s(dst, src);
   2.105 -        __ bind(L);
   2.106 -        break;
   2.107 +        __ movf_s(dst, src);
   2.108        case 0x05: //less
   2.109          __ c_ult_s(reg_op1, reg_op2);
   2.110 -        __ bc1f(L);
   2.111 -        __ nop();
   2.112 -        __ mov_s(dst, src);
   2.113 -        __ bind(L);
   2.114 -        break;
   2.115 +        __ movt_s(dst, src);
   2.116        case 0x06: //less_equal
   2.117          __ c_ule_s(reg_op1, reg_op2);
   2.118 -        __ bc1f(L);
   2.119 -        __ nop();
   2.120 -        __ mov_s(dst, src);
   2.121 -        __ bind(L);
   2.122 -       break;
   2.123 +        __ movt_s(dst, src);
   2.124        default:
   2.125            Unimplemented();
   2.126 -    }  
   2.127 +    }
   2.128    %}
   2.129    ins_pipe( pipe_slow );
   2.130  %}