Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/assembler_mips.hpp	Thu Nov 08 20:41:50 2018 +0800
     1.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp	Tue Nov 13 16:56:02 2018 +0800
     1.3 @@ -803,7 +803,6 @@
     1.4  
     1.5    static const char* gs_sdc2_name[];
     1.6  
     1.7 -  /* 2013.10.16 Jin: merge from OpenJDK 8 */
     1.8    enum WhichOperand {
     1.9      // input to locate_operand, and format code for relocations
    1.10      imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
    1.11 @@ -837,7 +836,7 @@
    1.12    //|   opcode   |      rs    |    rt    |            immediat             |
    1.13    //|            |            |          |                                 |
    1.14    //      6              5          5                     16
    1.15 -  static int insn_ORRI(int op, int rs, int rt, int imm) { return (op<<26) | (rs<<21) | (rt<<16) | low16(imm); }
    1.16 +  static int insn_ORRI(int op, int rs, int rt, int imm) { assert(is_simm16(imm), "not a signed 16-bit int"); return (op<<26) | (rs<<21) | (rt<<16) | low16(imm); }
    1.17  
    1.18    // R-Type (Register)
    1.19    // 31         26 25        21 20      16 15      11 10         6 5         0
    1.20 @@ -858,11 +857,6 @@
    1.21      return (cop1x_op<<26) | (fmt<<21) | (ft<<16) | (fs<<11) | (fd<<6) | func;
    1.22    }
    1.23  
    1.24 -
    1.25 -  //static int low  (int x, int l) { return bitfield(x, 0, l); }
    1.26 -  //static int low16(int x)        { return low(x, 16); }
    1.27 -  //static int low26(int x)        { return low(x, 26); }
    1.28 -
    1.29    static int high  (int x, int l) { return bitfield(x, 32-l, l); }
    1.30    static int high16(int x)        { return high(x, 16); }
    1.31    static int high6 (int x)        { return high(x, 6); }
    1.32 @@ -896,6 +890,12 @@
    1.33      return (x & 0xffff);
    1.34    }
    1.35  
    1.36 +  // Convert 16-bit x to a sign-extended 16-bit integer 
    1.37 +  static int simm16(int x) {
    1.38 +    assert(x == (x & 0xFFFF), "must be 16-bit only");
    1.39 +    return (x << 16) >> 16;
    1.40 +  }
    1.41 +
    1.42    static int split_high(int x) {
    1.43      return ( (x >> 16) + ((x & 0x8000) != 0) ) & 0xffff;
    1.44    }
    1.45 @@ -1036,7 +1036,7 @@
    1.46  #endif
    1.47  
    1.48    void andr(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), and_op)); }
    1.49 -  void andi(Register rt, Register rs, int imm)     { emit_long(insn_ORRI(andi_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
    1.50 +  void andi(Register rt, Register rs, int imm)     { emit_long(insn_ORRI(andi_op, (int)rs->encoding(), (int)rt->encoding(), simm16(imm))); }
    1.51  
    1.52    void beq    (Register rs, Register rt, int off)  { emit_long(insn_ORRI(beq_op, (int)rs->encoding(), (int)rt->encoding(), off)); has_delay_slot(); }
    1.53    void beql   (Register rs, Register rt, int off)  { emit_long(insn_ORRI(beql_op, (int)rs->encoding(), (int)rt->encoding(), off)); has_delay_slot(); }
    1.54 @@ -1157,15 +1157,8 @@
    1.55       emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | dsrlv_op);
    1.56    }
    1.57  
    1.58 -// Do mult and div need both 32-bit and 64-bit version? FIXME aoqi
    1.59 -//#ifndef _LP64
    1.60 -#if 1
    1.61    void div   (Register rs, Register rt)              { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, div_op)); }
    1.62    void divu  (Register rs, Register rt)              { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, divu_op)); }
    1.63 -#else
    1.64 -  void div   (Register rs, Register rt)              { ddiv (rs, rt);}
    1.65 -  void divu  (Register rs, Register rt)              { ddivu(rs, rt);}
    1.66 -#endif
    1.67    void dmult (Register rs, Register rt)              { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, dmult_op)); }
    1.68    void dmultu(Register rs, Register rt)              { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, dmultu_op)); }
    1.69    void dsll  (Register rd, Register rt , int sa)     { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), low(sa, 5), dsll_op)); }
    1.70 @@ -1202,7 +1195,7 @@
    1.71    void lhu(Register rt, Register base, int off) { emit_long(insn_ORRI(lhu_op, (int)base->encoding(), (int)rt->encoding(), off)); }
    1.72    void ll (Register rt, Register base, int off) { emit_long(insn_ORRI(ll_op,  (int)base->encoding(), (int)rt->encoding(), off)); }
    1.73    void lld(Register rt, Register base, int off) { emit_long(insn_ORRI(lld_op, (int)base->encoding(), (int)rt->encoding(), off)); }
    1.74 -  void lui(Register rt, int imm)                { emit_long(insn_ORRI(lui_op, 0, (int)rt->encoding(), imm)); }
    1.75 +  void lui(Register rt, int imm)                { emit_long(insn_ORRI(lui_op, 0, (int)rt->encoding(), simm16(imm))); }
    1.76    void lw (Register rt, Register base, int off) { emit_long(insn_ORRI(lw_op,  (int)base->encoding(), (int)rt->encoding(), off)); }
    1.77    void lwl(Register rt, Register base, int off) { emit_long(insn_ORRI(lwl_op, (int)base->encoding(), (int)rt->encoding(), off)); }
    1.78    void lwr(Register rt, Register base, int off) { emit_long(insn_ORRI(lwr_op, (int)base->encoding(), (int)rt->encoding(), off)); }
    1.79 @@ -1235,7 +1228,7 @@
    1.80    void nor(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), nor_op)); }
    1.81  
    1.82    void orr(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), or_op)); }
    1.83 -  void ori(Register rt, Register rs, int imm)     { emit_long(insn_ORRI(ori_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
    1.84 +  void ori(Register rt, Register rs, int imm)     { emit_long(insn_ORRI(ori_op, (int)rs->encoding(), (int)rt->encoding(), simm16(imm))); }
    1.85  
    1.86    void sb   (Register rt, Register base, int off)     { emit_long(insn_ORRI(sb_op,    (int)base->encoding(), (int)rt->encoding(), off)); }
    1.87    void sc   (Register rt, Register base, int off)     { emit_long(insn_ORRI(sc_op,    (int)base->encoding(), (int)rt->encoding(), off)); }

     2.1 --- a/src/cpu/mips/vm/interpreter_mips_64.cpp	Thu Nov 08 20:41:50 2018 +0800
     2.2 +++ b/src/cpu/mips/vm/interpreter_mips_64.cpp	Tue Nov 13 16:56:02 2018 +0800
     2.3 @@ -84,7 +84,8 @@
     2.4      FloatRegister floatreg = as_FloatRegister(i + F12->encoding());
     2.5      Label isfloatordouble, isdouble, next;
     2.6  
     2.7 -    __ andi(AT, T3, 1 << (i*2));      // Float or Double?
     2.8 +    __ set64(AT, 1 << (i*2));         // Float or Double?
     2.9 +    __ andr(AT, T3, AT);
    2.10      __ bne(AT, R0, isfloatordouble);
    2.11      __ delayed()->nop();
    2.12  
    2.13 @@ -94,7 +95,8 @@
    2.14      __ delayed()->nop();
    2.15  
    2.16      __ bind(isfloatordouble);
    2.17 -    __ andi(AT,T3, 1 << ((i*2)+1));     // Double?
    2.18 +    __ set64(AT, 1 << ((i*2)+1));     // Double?
    2.19 +    __ andr(AT, T3, AT);
    2.20      __ bne(AT, R0, isdouble);
    2.21      __ delayed()->nop();
    2.22  

     3.1 --- a/src/cpu/mips/vm/macroAssembler_mips.cpp	Thu Nov 08 20:41:50 2018 +0800
     3.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.cpp	Tue Nov 13 16:56:02 2018 +0800
     3.3 @@ -2322,7 +2322,7 @@
     3.4  
     3.5  void MacroAssembler::li64(Register rd, long imm) {
     3.6    assert_not_delayed();
     3.7 -  lui(rd, imm >> 48);
     3.8 +  lui(rd, split_low(imm >> 48));
     3.9    ori(rd, rd, split_low(imm >> 32));
    3.10    dsll(rd, rd, 16);
    3.11    ori(rd, rd, split_low(imm >> 16));