Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/assembler_mips.cpp	Tue Jul 26 11:33:17 2016 +0800
     1.2 +++ b/src/cpu/mips/vm/assembler_mips.cpp	Tue Jul 26 17:06:17 2016 +0800
     1.3 @@ -207,6 +207,17 @@
     1.4  	"dsll",     "",         "dsrl",     "dsra",     "dsll32",   "",         "dsrl32",   "dsra32"
     1.5  };
     1.6  
     1.7 +const char* Assembler::special2_name[] = {
     1.8 +	"",         "",         "mul",      "",         "",         "",         "",         "",
     1.9 +	"",         "",         "",         "",         "",         "",         "",         "",
    1.10 +	"",         "",         "",         "",         "",         "",         "",         "",
    1.11 +	"",         "",         "",         "",         "",         "",         "",         "",
    1.12 +	"",         "",         "",         "",         "",         "",         "",         "",
    1.13 +	"",         "",         "",         "",         "",         "",         "",         "",
    1.14 +	"",         "",         "",         "",         "",         "",         "",         "",
    1.15 +	"",         "",         "",         "",         "",         "",         "",         ""
    1.16 +};
    1.17 +
    1.18  const char* Assembler::regimm_name[] = {
    1.19  	"bltz",     "bgez",     "bltzl",    "bgezl",    "",         "",         "",         "",
    1.20  	"tgei",     "tgeiu",    "tlti",     "tltiu",    "teqi",     "",         "tnei",     "",

     2.1 --- a/src/cpu/mips/vm/assembler_mips.hpp	Tue Jul 26 11:33:17 2016 +0800
     2.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp	Tue Jul 26 17:06:17 2016 +0800
     2.3 @@ -394,6 +394,7 @@
     2.4  	  daddiu_op   = 0x19,
     2.5  	  ldl_op      = 0x1a,
     2.6  	  ldr_op      = 0x1b,
     2.7 +	  special2_op = 0x1c,
     2.8  	  lb_op       = 0x20,
     2.9  	  lh_op       = 0x21,
    2.10  	  lwl_op      = 0x22,
    2.11 @@ -484,6 +485,13 @@
    2.12  	
    2.13  	static	const char* special_name[]; 
    2.14  	
    2.15 +	//special family, the opcode is in low 6 bits. 
    2.16 +	enum special2_ops {
    2.17 +		mul_op			= 0x02
    2.18 +        };
    2.19 +
    2.20 +	static	const char* special2_name[]; 
    2.21 +
    2.22  	//regimm family, the opcode is in rt[16...20], 5 bits
    2.23  	enum regimm_ops {
    2.24  		bltz_op			= 0x00,
    2.25 @@ -859,6 +867,9 @@
    2.26  	void movz  (Register rd, Register rs,   Register rt) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), movz_op)); }	
    2.27  	void movn  (Register rd, Register rs,   Register rt) { emit_long(insn_RRRO((int)rs->encoding(),  (int)rt->encoding(),   (int)rd->encoding(), movn_op)); }	
    2.28  
    2.29 +	void mul   (Register rd, Register rs,   Register rt) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | mul_op); }	
    2.30 +
    2.31 +
    2.32  // Do mult and div need both 32-bit and 64-bit version? FIXME aoqi
    2.33  //#ifndef _LP64
    2.34  #if 1

     3.1 --- a/src/cpu/mips/vm/disassembler_mips.cpp	Tue Jul 26 11:33:17 2016 +0800
     3.2 +++ b/src/cpu/mips/vm/disassembler_mips.cpp	Tue Jul 26 17:06:17 2016 +0800
     3.3 @@ -307,6 +307,15 @@
     3.4  		}
     3.5  		break;
     3.6  		
     3.7 +	case Assembler::special2_op:
     3.8 +		special = Assembler::special(insn);
     3.9 +		switch(special) {
    3.10 +		case Assembler::mul_op:
    3.11 +			PRINT_ORRR(Assembler::special2_name[special]);
    3.12 +			break;
    3.13 +		}
    3.14 +		break;
    3.15 +
    3.16  	case Assembler::regimm_op:
    3.17  		special	= Assembler::rt(insn);
    3.18