Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
#9372 Refactor VM_Version, removed UseLoongsonISA and Use3A3000, added UseLEXT1, UseLEXT2, UseLEXT3.
Thu, 05 Sep 2019 13:07:31 +0800
- author
- aoqi
- date
- Thu, 05 Sep 2019 13:07:31 +0800
- changeset 9644
- 3089aa0aa0ee
- parent 9643
- 0825e81ce56b
- child 9645
- ac996ba07f9d
#9372 Refactor VM_Version, removed UseLoongsonISA and Use3A3000, added UseLEXT1, UseLEXT2, UseLEXT3.
Summary: used cpucfg to detect cpu features
Reviewed-by: wanghaomin
1.1 --- a/src/cpu/mips/vm/assembler_mips.cpp Mon Jul 22 18:48:55 2019 +0800 1.2 +++ b/src/cpu/mips/vm/assembler_mips.cpp Thu Sep 05 13:07:31 2019 +0800 1.3 @@ -300,9 +300,9 @@ 1.4 int scale = dst.scale(); 1.5 int disp = dst.disp(); 1.6 1.7 - if(index != noreg) { 1.8 - if( Assembler::is_simm16(disp) ) { 1.9 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 1.10 + if (index != noreg) { 1.11 + if (Assembler::is_simm16(disp)) { 1.12 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 1.13 if (scale == 0) { 1.14 gsldx(src, base, index, disp); 1.15 } else { 1.16 @@ -323,7 +323,7 @@ 1.17 lui(AT, split_low(disp >> 16)); 1.18 if (split_low(disp)) ori(AT, AT, split_low(disp)); 1.19 daddu(AT, AT, base); 1.20 - if( UseLoongsonISA ) { 1.21 + if (UseLEXT1) { 1.22 gsldx(src, AT, index, 0); 1.23 } else { 1.24 daddu(AT, AT, index); 1.25 @@ -335,7 +335,7 @@ 1.26 daddu(AT, base, AT); 1.27 lui(src, split_low(disp >> 16)); 1.28 if (split_low(disp)) ori(src, src, split_low(disp)); 1.29 - if( UseLoongsonISA ) { 1.30 + if (UseLEXT1) { 1.31 gsldx(src, AT, src, 0); 1.32 } else { 1.33 daddu(AT, AT, src); 1.34 @@ -344,13 +344,13 @@ 1.35 } 1.36 } 1.37 } else { 1.38 - if( Assembler::is_simm16(disp) ) { 1.39 + if (Assembler::is_simm16(disp)) { 1.40 ld(src, base, disp); 1.41 } else { 1.42 lui(AT, split_low(disp >> 16)); 1.43 if (split_low(disp)) ori(AT, AT, split_low(disp)); 1.44 1.45 - if( UseLoongsonISA ) { 1.46 + if (UseLEXT1) { 1.47 gsldx(src, base, AT, 0); 1.48 } else { 1.49 daddu(AT, base, AT); 1.50 @@ -398,9 +398,9 @@ 1.51 int scale = dst.scale(); 1.52 int disp = dst.disp(); 1.53 1.54 - if(index != noreg) { 1.55 - if( Assembler::is_simm16(disp) ) { 1.56 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 1.57 + if (index != noreg) { 1.58 + if (Assembler::is_simm16(disp)) { 1.59 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 1.60 if (scale == 0) { 1.61 gslwx(src, base, index, disp); 1.62 } else { 1.63 @@ -421,7 +421,7 @@ 1.64 lui(AT, split_low(disp >> 16)); 1.65 if (split_low(disp)) ori(AT, AT, split_low(disp)); 1.66 daddu(AT, AT, base); 1.67 - if( UseLoongsonISA ) { 1.68 + if (UseLEXT1) { 1.69 gslwx(src, AT, index, 0); 1.70 } else { 1.71 daddu(AT, AT, index); 1.72 @@ -433,7 +433,7 @@ 1.73 daddu(AT, base, AT); 1.74 lui(src, split_low(disp >> 16)); 1.75 if (split_low(disp)) ori(src, src, split_low(disp)); 1.76 - if( UseLoongsonISA ) { 1.77 + if (UseLEXT1) { 1.78 gslwx(src, AT, src, 0); 1.79 } else { 1.80 daddu(AT, AT, src); 1.81 @@ -442,13 +442,13 @@ 1.82 } 1.83 } 1.84 } else { 1.85 - if( Assembler::is_simm16(disp) ) { 1.86 + if (Assembler::is_simm16(disp)) { 1.87 lw(src, base, disp); 1.88 } else { 1.89 lui(AT, split_low(disp >> 16)); 1.90 if (split_low(disp)) ori(AT, AT, split_low(disp)); 1.91 1.92 - if( UseLoongsonISA ) { 1.93 + if (UseLEXT1) { 1.94 gslwx(src, base, AT, 0); 1.95 } else { 1.96 daddu(AT, base, AT); 1.97 @@ -539,9 +539,9 @@ 1.98 int scale = dst.scale(); 1.99 int disp = dst.disp(); 1.100 1.101 - if(index != noreg) { 1.102 - if(is_simm16(disp)) { 1.103 - if( UseLoongsonISA && is_simm(disp, 8)) { 1.104 + if (index != noreg) { 1.105 + if (is_simm16(disp)) { 1.106 + if ( UseLEXT1 && is_simm(disp, 8)) { 1.107 if (scale == 0) { 1.108 gssdx(src, base, index, disp); 1.109 } else { 1.110 @@ -565,7 +565,7 @@ 1.111 lui(AT, split_low(disp >> 16)); 1.112 if (split_low(disp)) ori(AT, AT, split_low(disp)); 1.113 daddu(AT, AT, base); 1.114 - if(UseLoongsonISA) { 1.115 + if (UseLEXT1) { 1.116 gssdx(src, AT, index, 0); 1.117 } else { 1.118 daddu(AT, AT, index); 1.119 @@ -579,7 +579,7 @@ 1.120 daddu(AT, base, AT); 1.121 lui(T9, split_low(disp >> 16)); 1.122 if (split_low(disp)) ori(T9, T9, split_low(disp)); 1.123 - if(UseLoongsonISA) { 1.124 + if (UseLEXT1) { 1.125 gssdx(src, AT, T9, 0); 1.126 } else { 1.127 daddu(AT, AT, T9); 1.128 @@ -591,14 +591,14 @@ 1.129 } 1.130 } 1.131 } else { 1.132 - if(is_simm16(disp)) { 1.133 + if (is_simm16(disp)) { 1.134 sd(src, base, disp); 1.135 } else { 1.136 assert_different_registers(rt, AT); 1.137 lui(AT, split_low(disp >> 16)); 1.138 if (split_low(disp)) ori(AT, AT, split_low(disp)); 1.139 1.140 - if(UseLoongsonISA) { 1.141 + if (UseLEXT1) { 1.142 gssdx(src, base, AT, 0); 1.143 } else { 1.144 daddu(AT, base, AT); 1.145 @@ -631,9 +631,9 @@ 1.146 int scale = dst.scale(); 1.147 int disp = dst.disp(); 1.148 1.149 - if(index != noreg) { 1.150 - if( Assembler::is_simm16(disp) ) { 1.151 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 1.152 + if (index != noreg) { 1.153 + if ( Assembler::is_simm16(disp) ) { 1.154 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 1.155 if (scale == 0) { 1.156 gsswx(src, base, index, disp); 1.157 } else { 1.158 @@ -657,7 +657,7 @@ 1.159 lui(AT, split_low(disp >> 16)); 1.160 if (split_low(disp)) ori(AT, AT, split_low(disp)); 1.161 daddu(AT, AT, base); 1.162 - if( UseLoongsonISA ) { 1.163 + if (UseLEXT1) { 1.164 gsswx(src, AT, index, 0); 1.165 } else { 1.166 daddu(AT, AT, index); 1.167 @@ -671,7 +671,7 @@ 1.168 daddu(AT, base, AT); 1.169 lui(T9, split_low(disp >> 16)); 1.170 if (split_low(disp)) ori(T9, T9, split_low(disp)); 1.171 - if( UseLoongsonISA ) { 1.172 + if (UseLEXT1) { 1.173 gsswx(src, AT, T9, 0); 1.174 } else { 1.175 daddu(AT, AT, T9); 1.176 @@ -683,14 +683,14 @@ 1.177 } 1.178 } 1.179 } else { 1.180 - if( Assembler::is_simm16(disp) ) { 1.181 + if (Assembler::is_simm16(disp)) { 1.182 sw(src, base, disp); 1.183 } else { 1.184 assert_different_registers(rt, AT); 1.185 lui(AT, split_low(disp >> 16)); 1.186 if (split_low(disp)) ori(AT, AT, split_low(disp)); 1.187 1.188 - if( UseLoongsonISA ) { 1.189 + if (UseLEXT1) { 1.190 gsswx(src, base, AT, 0); 1.191 } else { 1.192 daddu(AT, base, AT);
2.1 --- a/src/cpu/mips/vm/assembler_mips.hpp Mon Jul 22 18:48:55 2019 +0800 2.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp Thu Sep 05 13:07:31 2019 +0800 2.3 @@ -1741,7 +1741,7 @@ 2.4 //LDC2 & SDC2 2.5 #define INSN(OPS, OP) \ 2.6 assert(is_simm(off, 8), "NAME: off exceeds 8 bits"); \ 2.7 - assert(UseLoongsonISA, "check LoongISA"); \ 2.8 + assert(UseLEXT1, "check UseLEXT1"); \ 2.9 emit_long( (OPS << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | \ 2.10 ((int)index->encoding() << 11) | (low(off, 8) << 3) | OP); 2.11 2.12 @@ -1768,7 +1768,7 @@ 2.13 /* 2.14 void gslbx(Register rt, Register base, Register index, int off) { 2.15 assert(is_simm(off, 8), "gslbx: off exceeds 8 bits"); 2.16 - assert(UseLoongsonISA, "check LoongISA"); 2.17 + assert(UseLEXT1, "check UseLEXT1"); 2.18 emit_long( (gs_ldc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | 2.19 ((int)index->encoding() << 11) | (low(off, 8) << 3) | gslbx_op); 2.20 void gslbx(Register rt, Register base, Register index, int off) {INSN(gs_ldc2_op, gslbx_op);} 2.21 @@ -1807,6 +1807,9 @@ 2.22 #undef INSN_SDC2 2.23 #undef INSN_SDC2_F 2.24 2.25 + // cpucfg on Loongson CPUs above 3A4000 2.26 + void cpucfg(Register rd, Register rs) { emit_long((gs_lwc2_op << 26) | ((int)rs->encoding() << 21) | (0b01000 << 16) | ((int)rd->encoding() << 11) | ( 0b00100 << 6) | 0b011000);} 2.27 + 2.28 2.29 public: 2.30 // Creation
3.1 --- a/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp Mon Jul 22 18:48:55 2019 +0800 3.2 +++ b/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp Thu Sep 05 13:07:31 2019 +0800 3.3 @@ -3991,7 +3991,7 @@ 3.4 if (dest->is_single_cpu()) { 3.5 __ mul(res, lreg, rreg); 3.6 } else { 3.7 - if (UseLoongsonISA) { 3.8 + if (UseLEXT1) { 3.9 __ gsdmult(res, lreg, rreg); 3.10 } else { 3.11 __ dmult(lreg, rreg); 3.12 @@ -4044,7 +4044,7 @@ 3.13 __ mul(res, lreg, AT); 3.14 } else { 3.15 __ set64(AT, c); 3.16 - if (UseLoongsonISA) { 3.17 + if (UseLEXT1) { 3.18 __ gsmult(res, lreg, AT); 3.19 } else { 3.20 __ dmult(lreg, AT); 3.21 @@ -4199,7 +4199,7 @@ 3.22 __ move(dst_lo, R0); 3.23 __ bind(done); 3.24 #else 3.25 - if (UseLoongsonISA) { 3.26 + if (UseLEXT1) { 3.27 __ gsdmult(dst_lo, op2_lo, op1_lo); 3.28 } else { 3.29 __ dmult(op2_lo, op1_lo); 3.30 @@ -4533,7 +4533,7 @@ 3.31 __ div(lreg, rreg); 3.32 __ mfhi(dreg); 3.33 } else if (code == lir_idiv) { 3.34 - if (UseLoongsonISA) { 3.35 + if (UseLEXT1) { 3.36 __ gsdiv(dreg, lreg, rreg); 3.37 } else { 3.38 __ div(lreg, rreg);
4.1 --- a/src/cpu/mips/vm/globals_mips.hpp Mon Jul 22 18:48:55 2019 +0800 4.2 +++ b/src/cpu/mips/vm/globals_mips.hpp Thu Sep 05 13:07:31 2019 +0800 4.3 @@ -87,11 +87,14 @@ 4.4 4.5 #define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \ 4.6 \ 4.7 - product(bool, UseLoongsonISA, false, \ 4.8 - "Use LoongsonISA on Loongson CPUs") \ 4.9 + product(bool, UseLEXT1, false, \ 4.10 + "Use LoongISA general EXTensions 1") \ 4.11 \ 4.12 - product(bool, Use3A2000, false, \ 4.13 - "Use Loongson 3A2000 CPU") \ 4.14 + product(bool, UseLEXT2, false, \ 4.15 + "Use LoongISA general EXTensions 2") \ 4.16 + \ 4.17 + product(bool, UseLEXT3, false, \ 4.18 + "Use LoongISA general EXTensions 3") \ 4.19 \ 4.20 product(bool, UseCodeCacheAllocOpt, true, \ 4.21 "Allocate code cache within 32-bit memory address space") \
5.1 --- a/src/cpu/mips/vm/interp_masm_mips_64.cpp Mon Jul 22 18:48:55 2019 +0800 5.2 +++ b/src/cpu/mips/vm/interp_masm_mips_64.cpp Thu Sep 05 13:07:31 2019 +0800 5.3 @@ -571,14 +571,14 @@ 5.4 // See StubGenerator::generate_call_stub(address& return_address) for the initialization of GP. 5.5 if(table_offset != 0) { 5.6 daddiu(T3, GP, table_offset); 5.7 - if (UseLoongsonISA) { 5.8 + if (UseLEXT1) { 5.9 gsldx(T3, T2, T3, 0); 5.10 } else { 5.11 daddu(T3, T2, T3); 5.12 ld(T3, T3, 0); 5.13 } 5.14 } else { 5.15 - if (UseLoongsonISA) { 5.16 + if (UseLEXT1) { 5.17 gsldx(T3, T2, GP, 0); 5.18 } else { 5.19 daddu(T3, T2, GP); 5.20 @@ -587,7 +587,7 @@ 5.21 } 5.22 } else { 5.23 li(T3, (long)table); 5.24 - if (UseLoongsonISA) { 5.25 + if (UseLEXT1) { 5.26 gsldx(T3, T2, T3, 0); 5.27 } else { 5.28 daddu(T3, T2, T3); 5.29 @@ -1593,7 +1593,7 @@ 5.30 // Build the base (index * per_case_size_in_bytes()) + 5.31 // case_array_offset_in_bytes() 5.32 move(reg2, in_bytes(MultiBranchData::per_case_size())); 5.33 - if (UseLoongsonISA) { 5.34 + if (UseLEXT1) { 5.35 gsdmult(index, index, reg2); 5.36 } else { 5.37 dmult(index, reg2);
6.1 --- a/src/cpu/mips/vm/macroAssembler_mips.cpp Mon Jul 22 18:48:55 2019 +0800 6.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.cpp Thu Sep 05 13:07:31 2019 +0800 6.3 @@ -3935,7 +3935,7 @@ 6.4 if (return_method) { 6.5 // Got a hit. 6.6 lw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 6.7 - if(UseLoongsonISA) { 6.8 + if (UseLEXT1) { 6.9 gsldx(method_result, recv_klass, scan_temp, 0); 6.10 } else { 6.11 daddu(AT, recv_klass, scan_temp);
7.1 --- a/src/cpu/mips/vm/mips_64.ad Mon Jul 22 18:48:55 2019 +0800 7.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Sep 05 13:07:31 2019 +0800 7.3 @@ -1382,7 +1382,7 @@ 7.4 7.5 st->print_cr("daddiu SP, SP, %d # Rlease stack @ MachEpilogNode", framesize); 7.6 st->print("\t"); 7.7 - if (UseLoongsonISA) { 7.8 + if (UseLEXT1) { 7.9 st->print_cr("gslq RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2); 7.10 } else { 7.11 st->print_cr("ld RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize); 7.12 @@ -1406,7 +1406,7 @@ 7.13 7.14 __ daddiu(SP, SP, framesize); 7.15 7.16 - if (UseLoongsonISA) { 7.17 + if (UseLEXT1) { 7.18 __ gslq(RA, FP, SP, -wordSize*2); 7.19 } else { 7.20 __ ld(RA, SP, -wordSize ); 7.21 @@ -1599,7 +1599,7 @@ 7.22 if (C->need_stack_bang(bangsize)) { 7.23 st->print_cr("# stack bang"); st->print("\t"); 7.24 } 7.25 - if (UseLoongsonISA) { 7.26 + if (UseLEXT1) { 7.27 st->print("gssq RA, FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2); 7.28 } else { 7.29 st->print("sd RA, %d(SP) @ MachPrologNode\n\t", -wordSize); 7.30 @@ -1624,7 +1624,7 @@ 7.31 __ generate_stack_overflow_check(bangsize); 7.32 } 7.33 7.34 - if (UseLoongsonISA) { 7.35 + if (UseLEXT1) { 7.36 __ gssq(RA, FP, SP, -wordSize*2); 7.37 } else { 7.38 __ sd(RA, SP, -wordSize); 7.39 @@ -1690,7 +1690,7 @@ 7.40 7.41 if( index != 0 ) { 7.42 if( Assembler::is_simm16(disp) ) { 7.43 - if( UseLoongsonISA ) { 7.44 + if (UseLEXT1) { 7.45 if (scale == 0) { 7.46 __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp); 7.47 } else { 7.48 @@ -1714,7 +1714,7 @@ 7.49 __ addu(AT, as_Register(base), AT); 7.50 } 7.51 __ move(T9, disp); 7.52 - if( UseLoongsonISA ) { 7.53 + if (UseLEXT1) { 7.54 __ gslbx(as_Register(dst), AT, T9, 0); 7.55 } else { 7.56 __ addu(AT, AT, T9); 7.57 @@ -1726,7 +1726,7 @@ 7.58 __ lb(as_Register(dst), as_Register(base), disp); 7.59 } else { 7.60 __ move(T9, disp); 7.61 - if( UseLoongsonISA ) { 7.62 + if (UseLEXT1) { 7.63 __ gslbx(as_Register(dst), as_Register(base), T9, 0); 7.64 } else { 7.65 __ addu(AT, as_Register(base), T9); 7.66 @@ -1781,7 +1781,7 @@ 7.67 if( index != 0 ) { 7.68 if (scale == 0) { 7.69 if( Assembler::is_simm(disp, 8) ) { 7.70 - if (UseLoongsonISA) { 7.71 + if (UseLEXT1) { 7.72 __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp); 7.73 } else { 7.74 __ addu(AT, as_Register(base), as_Register(index)); 7.75 @@ -1793,7 +1793,7 @@ 7.76 } else { 7.77 __ addu(AT, as_Register(base), as_Register(index)); 7.78 __ move(T9, disp); 7.79 - if (UseLoongsonISA) { 7.80 + if (UseLEXT1) { 7.81 __ gssbx(as_Register(src), AT, T9, 0); 7.82 } else { 7.83 __ addu(AT, AT, T9); 7.84 @@ -1803,7 +1803,7 @@ 7.85 } else { 7.86 __ dsll(AT, as_Register(index), scale); 7.87 if( Assembler::is_simm(disp, 8) ) { 7.88 - if (UseLoongsonISA) { 7.89 + if (UseLEXT1) { 7.90 __ gssbx(as_Register(src), AT, as_Register(base), disp); 7.91 } else { 7.92 __ addu(AT, as_Register(base), AT); 7.93 @@ -1815,7 +1815,7 @@ 7.94 } else { 7.95 __ addu(AT, as_Register(base), AT); 7.96 __ move(T9, disp); 7.97 - if (UseLoongsonISA) { 7.98 + if (UseLEXT1) { 7.99 __ gssbx(as_Register(src), AT, T9, 0); 7.100 } else { 7.101 __ addu(AT, AT, T9); 7.102 @@ -1828,7 +1828,7 @@ 7.103 __ sb(as_Register(src), as_Register(base), disp); 7.104 } else { 7.105 __ move(T9, disp); 7.106 - if (UseLoongsonISA) { 7.107 + if (UseLEXT1) { 7.108 __ gssbx(as_Register(src), as_Register(base), T9, 0); 7.109 } else { 7.110 __ addu(AT, as_Register(base), T9); 7.111 @@ -1847,7 +1847,7 @@ 7.112 int value = $src$$constant; 7.113 7.114 if( index != 0 ) { 7.115 - if (!UseLoongsonISA) { 7.116 + if (!UseLEXT1) { 7.117 if (scale == 0) { 7.118 __ daddu(AT, as_Register(base), as_Register(index)); 7.119 } else { 7.120 @@ -1949,7 +1949,7 @@ 7.121 } else { 7.122 if (value == 0) { 7.123 __ move(T9, disp); 7.124 - if (UseLoongsonISA) { 7.125 + if (UseLEXT1) { 7.126 __ gssbx(R0, as_Register(base), T9, 0); 7.127 } else { 7.128 __ daddu(AT, as_Register(base), T9); 7.129 @@ -1957,7 +1957,7 @@ 7.130 } 7.131 } else { 7.132 __ move(T9, disp); 7.133 - if (UseLoongsonISA) { 7.134 + if (UseLEXT1) { 7.135 __ move(AT, value); 7.136 __ gssbx(AT, as_Register(base), T9, 0); 7.137 } else { 7.138 @@ -1980,7 +1980,7 @@ 7.139 int value = $src$$constant; 7.140 7.141 if( index != 0 ) { 7.142 - if ( UseLoongsonISA ) { 7.143 + if (UseLEXT1) { 7.144 if ( Assembler::is_simm(disp,8) ) { 7.145 if ( scale == 0 ) { 7.146 if ( value == 0 ) { 7.147 @@ -2067,7 +2067,7 @@ 7.148 } 7.149 } 7.150 } else { 7.151 - if ( UseLoongsonISA ){ 7.152 + if (UseLEXT1){ 7.153 if ( Assembler::is_simm16(disp) ){ 7.154 if ( value == 0 ) { 7.155 __ sb(R0, as_Register(base), disp); 7.156 @@ -2120,7 +2120,7 @@ 7.157 int disp = $mem$$disp; 7.158 7.159 if( index != 0 ) { 7.160 - if ( UseLoongsonISA ) { 7.161 + if (UseLEXT1) { 7.162 if ( Assembler::is_simm(disp, 8) ) { 7.163 if (scale == 0) { 7.164 __ gslhx(as_Register(dst), as_Register(base), as_Register(index), disp); 7.165 @@ -2165,7 +2165,7 @@ 7.166 } 7.167 } 7.168 } else { // index is 0 7.169 - if ( UseLoongsonISA ) { 7.170 + if (UseLEXT1) { 7.171 if ( Assembler::is_simm16(disp) ) { 7.172 __ lh(as_Register(dst), as_Register(base), disp); 7.173 } else { 7.174 @@ -2229,7 +2229,7 @@ 7.175 7.176 if( index != 0 ) { 7.177 if( Assembler::is_simm16(disp) ) { 7.178 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 7.179 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 7.180 if (scale == 0) { 7.181 __ gsshx(as_Register(src), as_Register(base), as_Register(index), disp); 7.182 } else { 7.183 @@ -2253,7 +2253,7 @@ 7.184 __ addu(AT, as_Register(base), AT); 7.185 } 7.186 __ move(T9, disp); 7.187 - if( UseLoongsonISA ) { 7.188 + if (UseLEXT1) { 7.189 __ gsshx(as_Register(src), AT, T9, 0); 7.190 } else { 7.191 __ addu(AT, AT, T9); 7.192 @@ -2265,7 +2265,7 @@ 7.193 __ sh(as_Register(src), as_Register(base), disp); 7.194 } else { 7.195 __ move(T9, disp); 7.196 - if( UseLoongsonISA ) { 7.197 + if (UseLEXT1) { 7.198 __ gsshx(as_Register(src), as_Register(base), T9, 0); 7.199 } else { 7.200 __ addu(AT, as_Register(base), T9); 7.201 @@ -2283,8 +2283,8 @@ 7.202 int disp = $mem$$disp; 7.203 7.204 if( index != 0 ) { 7.205 - if( Assembler::is_simm16(disp) ) { 7.206 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 7.207 + if ( Assembler::is_simm16(disp) ) { 7.208 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 7.209 if (scale == 0) { 7.210 __ gsshx(R0, as_Register(base), as_Register(index), disp); 7.211 } else { 7.212 @@ -2308,7 +2308,7 @@ 7.213 __ addu(AT, as_Register(base), AT); 7.214 } 7.215 __ move(T9, disp); 7.216 - if( UseLoongsonISA ) { 7.217 + if (UseLEXT1) { 7.218 __ gsshx(R0, AT, T9, 0); 7.219 } else { 7.220 __ addu(AT, AT, T9); 7.221 @@ -2320,7 +2320,7 @@ 7.222 __ sh(R0, as_Register(base), disp); 7.223 } else { 7.224 __ move(T9, disp); 7.225 - if( UseLoongsonISA ) { 7.226 + if (UseLEXT1) { 7.227 __ gsshx(R0, as_Register(base), T9, 0); 7.228 } else { 7.229 __ addu(AT, as_Register(base), T9); 7.230 @@ -2340,7 +2340,7 @@ 7.231 7.232 if( index != 0 ) { 7.233 if( Assembler::is_simm16(disp) ) { 7.234 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 7.235 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 7.236 if (scale == 0) { 7.237 __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp); 7.238 } else { 7.239 @@ -2364,7 +2364,7 @@ 7.240 __ addu(AT, as_Register(base), AT); 7.241 } 7.242 __ move(T9, disp); 7.243 - if( UseLoongsonISA ) { 7.244 + if (UseLEXT1) { 7.245 __ gslwx(as_Register(dst), AT, T9, 0); 7.246 } else { 7.247 __ addu(AT, AT, T9); 7.248 @@ -2376,7 +2376,7 @@ 7.249 __ lw(as_Register(dst), as_Register(base), disp); 7.250 } else { 7.251 __ move(T9, disp); 7.252 - if( UseLoongsonISA ) { 7.253 + if (UseLEXT1) { 7.254 __ gslwx(as_Register(dst), as_Register(base), T9, 0); 7.255 } else { 7.256 __ addu(AT, as_Register(base), T9); 7.257 @@ -2396,7 +2396,7 @@ 7.258 7.259 if( index != 0 ) { 7.260 if( Assembler::is_simm16(disp) ) { 7.261 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 7.262 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 7.263 if (scale == 0) { 7.264 __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp); 7.265 } else { 7.266 @@ -2420,7 +2420,7 @@ 7.267 __ addu(AT, as_Register(base), AT); 7.268 } 7.269 __ move(T9, disp); 7.270 - if( UseLoongsonISA ) { 7.271 + if (UseLEXT1) { 7.272 __ gsswx(as_Register(src), AT, T9, 0); 7.273 } else { 7.274 __ addu(AT, AT, T9); 7.275 @@ -2432,7 +2432,7 @@ 7.276 __ sw(as_Register(src), as_Register(base), disp); 7.277 } else { 7.278 __ move(T9, disp); 7.279 - if( UseLoongsonISA ) { 7.280 + if (UseLEXT1) { 7.281 __ gsswx(as_Register(src), as_Register(base), T9, 0); 7.282 } else { 7.283 __ addu(AT, as_Register(base), T9); 7.284 @@ -2451,7 +2451,7 @@ 7.285 int value = $src$$constant; 7.286 7.287 if( index != 0 ) { 7.288 - if ( UseLoongsonISA ) { 7.289 + if (UseLEXT1) { 7.290 if ( Assembler::is_simm(disp, 8) ) { 7.291 if ( scale == 0 ) { 7.292 if ( value == 0 ) { 7.293 @@ -2538,7 +2538,7 @@ 7.294 } 7.295 } 7.296 } else { 7.297 - if ( UseLoongsonISA ) { 7.298 + if (UseLEXT1) { 7.299 if ( Assembler::is_simm16(disp) ) { 7.300 if ( value == 0 ) { 7.301 __ sw(R0, as_Register(base), disp); 7.302 @@ -2626,7 +2626,7 @@ 7.303 assert(disp_reloc == relocInfo::none, "cannot have disp"); 7.304 7.305 if( index != 0 ) { 7.306 - if ( UseLoongsonISA ) { 7.307 + if (UseLEXT1) { 7.308 if ( Assembler::is_simm(disp, 8) ) { 7.309 if ( scale != 0 ) { 7.310 __ dsll(AT, as_Register(index), scale); 7.311 @@ -2669,7 +2669,7 @@ 7.312 } 7.313 } 7.314 } else { 7.315 - if ( UseLoongsonISA ) { 7.316 + if (UseLEXT1) { 7.317 if ( Assembler::is_simm16(disp) ){ 7.318 __ ld(as_Register(dst), as_Register(base), disp); 7.319 } else { 7.320 @@ -2701,7 +2701,7 @@ 7.321 assert(disp_reloc == relocInfo::none, "cannot have disp"); 7.322 7.323 if( index != 0 ) { 7.324 - if ( UseLoongsonISA ) { 7.325 + if (UseLEXT1) { 7.326 if ( Assembler::is_simm(disp, 8) ) { 7.327 if ( scale != 0 ) { 7.328 __ dsll(AT, as_Register(index), scale); 7.329 @@ -2744,7 +2744,7 @@ 7.330 } 7.331 } 7.332 } else { 7.333 - if ( UseLoongsonISA ) { 7.334 + if (UseLEXT1) { 7.335 if ( Assembler::is_simm16(disp) ){ 7.336 __ ld(as_Register(dst), as_Register(base), disp); 7.337 } else { 7.338 @@ -2773,7 +2773,7 @@ 7.339 int disp = $mem$$disp; 7.340 7.341 if( index != 0 ) { 7.342 - if ( UseLoongsonISA ){ 7.343 + if (UseLEXT1){ 7.344 if ( Assembler::is_simm(disp, 8) ) { 7.345 if ( scale == 0 ) { 7.346 __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp); 7.347 @@ -2816,7 +2816,7 @@ 7.348 } 7.349 } 7.350 } else { 7.351 - if ( UseLoongsonISA ) { 7.352 + if (UseLEXT1) { 7.353 if ( Assembler::is_simm16(disp) ) { 7.354 __ sd(as_Register(src), as_Register(base), disp); 7.355 } else { 7.356 @@ -2844,7 +2844,7 @@ 7.357 int disp = $mem$$disp; 7.358 7.359 if( index != 0 ) { 7.360 - if ( UseLoongsonISA ){ 7.361 + if (UseLEXT1){ 7.362 if ( Assembler::is_simm(disp, 8) ) { 7.363 if ( scale == 0 ) { 7.364 __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp); 7.365 @@ -2887,7 +2887,7 @@ 7.366 } 7.367 } 7.368 } else { 7.369 - if ( UseLoongsonISA ) { 7.370 + if (UseLEXT1) { 7.371 if ( Assembler::is_simm16(disp) ) { 7.372 __ sw(as_Register(src), as_Register(base), disp); 7.373 } else { 7.374 @@ -2915,8 +2915,8 @@ 7.375 7.376 if( index != 0 ) { 7.377 if (scale == 0) { 7.378 - if( Assembler::is_simm16(disp) ) { 7.379 - if (UseLoongsonISA && Assembler::is_simm(disp, 8)) { 7.380 + if ( Assembler::is_simm16(disp) ) { 7.381 + if (UseLEXT1 && Assembler::is_simm(disp, 8)) { 7.382 __ gssdx(R0, as_Register(base), as_Register(index), disp); 7.383 } else { 7.384 __ daddu(AT, as_Register(base), as_Register(index)); 7.385 @@ -2925,7 +2925,7 @@ 7.386 } else { 7.387 __ daddu(AT, as_Register(base), as_Register(index)); 7.388 __ move(T9, disp); 7.389 - if(UseLoongsonISA) { 7.390 + if (UseLEXT1) { 7.391 __ gssdx(R0, AT, T9, 0); 7.392 } else { 7.393 __ daddu(AT, AT, T9); 7.394 @@ -2935,7 +2935,7 @@ 7.395 } else { 7.396 __ dsll(AT, as_Register(index), scale); 7.397 if( Assembler::is_simm16(disp) ) { 7.398 - if (UseLoongsonISA && Assembler::is_simm(disp, 8)) { 7.399 + if (UseLEXT1 && Assembler::is_simm(disp, 8)) { 7.400 __ gssdx(R0, as_Register(base), AT, disp); 7.401 } else { 7.402 __ daddu(AT, as_Register(base), AT); 7.403 @@ -2944,7 +2944,7 @@ 7.404 } else { 7.405 __ daddu(AT, as_Register(base), AT); 7.406 __ move(T9, disp); 7.407 - if (UseLoongsonISA) { 7.408 + if (UseLEXT1) { 7.409 __ gssdx(R0, AT, T9, 0); 7.410 } else { 7.411 __ daddu(AT, AT, T9); 7.412 @@ -2957,7 +2957,7 @@ 7.413 __ sd(R0, as_Register(base), disp); 7.414 } else { 7.415 __ move(T9, disp); 7.416 - if (UseLoongsonISA) { 7.417 + if (UseLEXT1) { 7.418 __ gssdx(R0, as_Register(base), T9, 0); 7.419 } else { 7.420 __ daddu(AT, as_Register(base), T9); 7.421 @@ -3146,7 +3146,7 @@ 7.422 7.423 if( index != 0 ) { 7.424 if( Assembler::is_simm16(disp) ) { 7.425 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 7.426 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 7.427 if (scale == 0) { 7.428 __ gslwxc1(dst, as_Register(base), as_Register(index), disp); 7.429 } else { 7.430 @@ -3170,7 +3170,7 @@ 7.431 __ daddu(AT, as_Register(base), AT); 7.432 } 7.433 __ move(T9, disp); 7.434 - if( UseLoongsonISA ) { 7.435 + if (UseLEXT1) { 7.436 __ gslwxc1(dst, AT, T9, 0); 7.437 } else { 7.438 __ daddu(AT, AT, T9); 7.439 @@ -3182,7 +3182,7 @@ 7.440 __ lwc1(dst, as_Register(base), disp); 7.441 } else { 7.442 __ move(T9, disp); 7.443 - if( UseLoongsonISA ) { 7.444 + if (UseLEXT1) { 7.445 __ gslwxc1(dst, as_Register(base), T9, 0); 7.446 } else { 7.447 __ daddu(AT, as_Register(base), T9); 7.448 @@ -3201,8 +3201,8 @@ 7.449 FloatRegister src = $src$$FloatRegister; 7.450 7.451 if( index != 0 ) { 7.452 - if( Assembler::is_simm16(disp) ) { 7.453 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 7.454 + if ( Assembler::is_simm16(disp) ) { 7.455 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 7.456 if (scale == 0) { 7.457 __ gsswxc1(src, as_Register(base), as_Register(index), disp); 7.458 } else { 7.459 @@ -3226,7 +3226,7 @@ 7.460 __ daddu(AT, as_Register(base), AT); 7.461 } 7.462 __ move(T9, disp); 7.463 - if( UseLoongsonISA ) { 7.464 + if (UseLEXT1) { 7.465 __ gsswxc1(src, AT, T9, 0); 7.466 } else { 7.467 __ daddu(AT, AT, T9); 7.468 @@ -3238,7 +3238,7 @@ 7.469 __ swc1(src, as_Register(base), disp); 7.470 } else { 7.471 __ move(T9, disp); 7.472 - if( UseLoongsonISA ) { 7.473 + if (UseLEXT1) { 7.474 __ gsswxc1(src, as_Register(base), T9, 0); 7.475 } else { 7.476 __ daddu(AT, as_Register(base), T9); 7.477 @@ -3256,9 +3256,9 @@ 7.478 int disp = $mem$$disp; 7.479 FloatRegister dst_reg = as_FloatRegister($dst$$reg); 7.480 7.481 - if( index != 0 ) { 7.482 - if( Assembler::is_simm16(disp) ) { 7.483 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 7.484 + if ( index != 0 ) { 7.485 + if ( Assembler::is_simm16(disp) ) { 7.486 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 7.487 if (scale == 0) { 7.488 __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp); 7.489 } else { 7.490 @@ -3282,7 +3282,7 @@ 7.491 __ daddu(AT, as_Register(base), AT); 7.492 } 7.493 __ move(T9, disp); 7.494 - if( UseLoongsonISA ) { 7.495 + if (UseLEXT1) { 7.496 __ gsldxc1(dst_reg, AT, T9, 0); 7.497 } else { 7.498 __ addu(AT, AT, T9); 7.499 @@ -3294,7 +3294,7 @@ 7.500 __ ldc1(dst_reg, as_Register(base), disp); 7.501 } else { 7.502 __ move(T9, disp); 7.503 - if( UseLoongsonISA ) { 7.504 + if (UseLEXT1) { 7.505 __ gsldxc1(dst_reg, as_Register(base), T9, 0); 7.506 } else { 7.507 __ addu(AT, as_Register(base), T9); 7.508 @@ -3312,9 +3312,9 @@ 7.509 int disp = $mem$$disp; 7.510 FloatRegister src_reg = as_FloatRegister($src$$reg); 7.511 7.512 - if( index != 0 ) { 7.513 - if( Assembler::is_simm16(disp) ) { 7.514 - if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 7.515 + if ( index != 0 ) { 7.516 + if ( Assembler::is_simm16(disp) ) { 7.517 + if ( UseLEXT1 && Assembler::is_simm(disp, 8) ) { 7.518 if (scale == 0) { 7.519 __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp); 7.520 } else { 7.521 @@ -3338,7 +3338,7 @@ 7.522 __ daddu(AT, as_Register(base), AT); 7.523 } 7.524 __ move(T9, disp); 7.525 - if( UseLoongsonISA ) { 7.526 + if (UseLEXT1) { 7.527 __ gssdxc1(src_reg, AT, T9, 0); 7.528 } else { 7.529 __ addu(AT, AT, T9); 7.530 @@ -3346,11 +3346,11 @@ 7.531 } 7.532 } 7.533 } else { 7.534 - if( Assembler::is_simm16(disp) ) { 7.535 + if ( Assembler::is_simm16(disp) ) { 7.536 __ sdc1(src_reg, as_Register(base), disp); 7.537 } else { 7.538 __ move(T9, disp); 7.539 - if( UseLoongsonISA ) { 7.540 + if (UseLEXT1) { 7.541 __ gssdxc1(src_reg, as_Register(base), T9, 0); 7.542 } else { 7.543 __ addu(AT, as_Register(base), T9); 7.544 @@ -6210,7 +6210,7 @@ 7.545 __ ld($dst$$Register, $constanttablebase, con_offset); 7.546 } else { 7.547 __ set64(AT, con_offset); 7.548 - if (UseLoongsonISA) { 7.549 + if (UseLEXT1) { 7.550 __ gsldx($dst$$Register, $constanttablebase, AT, 0); 7.551 } else { 7.552 __ daddu(AT, $constanttablebase, AT); 7.553 @@ -6509,7 +6509,7 @@ 7.554 __ ld($dst$$Register, $constanttablebase, con_offset); 7.555 } else { 7.556 __ set64(AT, con_offset); 7.557 - if (UseLoongsonISA) { 7.558 + if (UseLEXT1) { 7.559 __ gsldx($dst$$Register, $constanttablebase, AT, 0); 7.560 } else { 7.561 __ daddu(AT, $constanttablebase, AT); 7.562 @@ -11237,7 +11237,7 @@ 7.563 Register src1 = $src1$$Register; 7.564 Register src2 = $src2$$Register; 7.565 7.566 - //if (UseLoongsonISA) { 7.567 + //if (UseLEXT1) { 7.568 if (0) { 7.569 // 2016.08.10 7.570 // Experiments show that gsmod is slower that div+mfhi. 7.571 @@ -11262,7 +11262,7 @@ 7.572 Register op1 = as_Register($src1$$reg); 7.573 Register op2 = as_Register($src2$$reg); 7.574 7.575 - if (UseLoongsonISA) { 7.576 + if (UseLEXT1) { 7.577 __ gsdmod(dst, op1, op2); 7.578 } else { 7.579 __ ddiv(op1, op2); 7.580 @@ -11319,7 +11319,7 @@ 7.581 // We must trap an exception manually. 7.582 __ teq(R0, src2, 0x7); 7.583 7.584 - if (UseLoongsonISA) { 7.585 + if (UseLEXT1) { 7.586 __ gsdiv(dst, src1, src2); 7.587 } else { 7.588 __ div(src1, src2); 7.589 @@ -11372,7 +11372,7 @@ 7.590 Register op1 = as_Register($src1$$reg); 7.591 Register op2 = as_Register($src2$$reg); 7.592 7.593 - if (UseLoongsonISA) { 7.594 + if (UseLEXT1) { 7.595 __ gsdmult(dst, op1, op2); 7.596 } else { 7.597 __ dmult(op1, op2); 7.598 @@ -11390,7 +11390,7 @@ 7.599 Register op1 = as_Register($src1$$reg); 7.600 Register op2 = as_Register($src2$$reg); 7.601 7.602 - if (UseLoongsonISA) { 7.603 + if (UseLEXT1) { 7.604 __ gsdmult(dst, op1, op2); 7.605 } else { 7.606 __ dmult(op1, op2); 7.607 @@ -11409,7 +11409,7 @@ 7.608 Register op1 = as_Register($src1$$reg); 7.609 Register op2 = as_Register($src2$$reg); 7.610 7.611 - if (UseLoongsonISA) { 7.612 + if (UseLEXT1) { 7.613 __ gsddiv(dst, op1, op2); 7.614 } else { 7.615 __ ddiv(op1, op2); 7.616 @@ -11691,7 +11691,7 @@ 7.617 7.618 instruct xorI_Reg_immI_M1(mRegI dst, mRegI src1, immI_M1 M1) %{ 7.619 match(Set dst (XorI src1 M1)); 7.620 - predicate(UseLoongsonISA && Use3A2000); 7.621 + predicate(UseLEXT3); 7.622 ins_cost(60); 7.623 7.624 format %{ "xor $dst, $src1, $M1 #@xorI_Reg_immI_M1" %} 7.625 @@ -11706,7 +11706,7 @@ 7.626 7.627 instruct xorL2I_Reg_immI_M1(mRegI dst, mRegL src1, immI_M1 M1) %{ 7.628 match(Set dst (XorI (ConvL2I src1) M1)); 7.629 - predicate(UseLoongsonISA && Use3A2000); 7.630 + predicate(UseLEXT3); 7.631 ins_cost(60); 7.632 7.633 format %{ "xor $dst, $src1, $M1 #@xorL2I_Reg_immI_M1" %} 7.634 @@ -11737,7 +11737,7 @@ 7.635 /* 7.636 instruct xorL_Reg_immL_M1(mRegL dst, mRegL src1, immL_M1 M1) %{ 7.637 match(Set dst (XorL src1 M1)); 7.638 - predicate(UseLoongsonISA); 7.639 + predicate(UseLEXT3); 7.640 ins_cost(60); 7.641 7.642 format %{ "xor $dst, $src1, $M1 #@xorL_Reg_immL_M1" %} 7.643 @@ -11784,7 +11784,7 @@ 7.644 7.645 instruct andnI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{ 7.646 match(Set dst (AndI src1 (XorI src2 M1))); 7.647 - predicate(UseLoongsonISA && Use3A2000); 7.648 + predicate(UseLEXT3); 7.649 7.650 format %{ "andn $dst, $src1, $src2 #@andnI_Reg_nReg" %} 7.651 ins_encode %{ 7.652 @@ -11799,7 +11799,7 @@ 7.653 7.654 instruct ornI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{ 7.655 match(Set dst (OrI src1 (XorI src2 M1))); 7.656 - predicate(UseLoongsonISA && Use3A2000); 7.657 + predicate(UseLEXT3); 7.658 7.659 format %{ "orn $dst, $src1, $src2 #@ornI_Reg_nReg" %} 7.660 ins_encode %{ 7.661 @@ -11814,7 +11814,7 @@ 7.662 7.663 instruct andnI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{ 7.664 match(Set dst (AndI (XorI src1 M1) src2)); 7.665 - predicate(UseLoongsonISA && Use3A2000); 7.666 + predicate(UseLEXT3); 7.667 7.668 format %{ "andn $dst, $src2, $src1 #@andnI_nReg_Reg" %} 7.669 ins_encode %{ 7.670 @@ -11829,7 +11829,7 @@ 7.671 7.672 instruct ornI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{ 7.673 match(Set dst (OrI (XorI src1 M1) src2)); 7.674 - predicate(UseLoongsonISA && Use3A2000); 7.675 + predicate(UseLEXT3); 7.676 7.677 format %{ "orn $dst, $src2, $src1 #@ornI_nReg_Reg" %} 7.678 ins_encode %{ 7.679 @@ -11902,7 +11902,7 @@ 7.680 /* 7.681 instruct andnL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{ 7.682 match(Set dst (AndL src1 (XorL src2 M1))); 7.683 - predicate(UseLoongsonISA); 7.684 + predicate(UseLEXT3); 7.685 7.686 format %{ "andn $dst, $src1, $src2 #@andnL_Reg_nReg" %} 7.687 ins_encode %{ 7.688 @@ -11919,7 +11919,7 @@ 7.689 /* 7.690 instruct ornL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{ 7.691 match(Set dst (OrL src1 (XorL src2 M1))); 7.692 - predicate(UseLoongsonISA); 7.693 + predicate(UseLEXT3); 7.694 7.695 format %{ "orn $dst, $src1, $src2 #@ornL_Reg_nReg" %} 7.696 ins_encode %{ 7.697 @@ -11936,7 +11936,7 @@ 7.698 /* 7.699 instruct andnL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{ 7.700 match(Set dst (AndL (XorL src1 M1) src2)); 7.701 - predicate(UseLoongsonISA); 7.702 + predicate(UseLEXT3); 7.703 7.704 format %{ "andn $dst, $src2, $src1 #@andnL_nReg_Reg" %} 7.705 ins_encode %{ 7.706 @@ -11953,7 +11953,7 @@ 7.707 /* 7.708 instruct ornL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{ 7.709 match(Set dst (OrL (XorL src1 M1) src2)); 7.710 - predicate(UseLoongsonISA); 7.711 + predicate(UseLEXT3); 7.712 7.713 format %{ "orn $dst, $src2, $src1 #@ornL_nReg_Reg" %} 7.714 ins_encode %{ 7.715 @@ -13306,7 +13306,7 @@ 7.716 int con_offset = $constantoffset; 7.717 Register switch_reg = $switch_val$$Register; 7.718 7.719 - if (UseLoongsonISA) { 7.720 + if (UseLEXT1) { 7.721 if (Assembler::is_simm(con_offset, 8)) { 7.722 __ gsldx(T9, table_base, switch_reg, con_offset); 7.723 } else if (Assembler::is_simm16(con_offset)) { 7.724 @@ -13491,9 +13491,9 @@ 7.725 7.726 Register dst = R0; 7.727 7.728 - if( index != 0 ) { 7.729 - if( Assembler::is_simm16(disp) ) { 7.730 - if( UseLoongsonISA ) { 7.731 + if ( index != 0 ) { 7.732 + if ( Assembler::is_simm16(disp) ) { 7.733 + if (UseLEXT1) { 7.734 if (scale == 0) { 7.735 __ gslbx(dst, as_Register(base), as_Register(index), disp); 7.736 } else { 7.737 @@ -13517,7 +13517,7 @@ 7.738 __ addu(AT, as_Register(base), AT); 7.739 } 7.740 __ move(T9, disp); 7.741 - if( UseLoongsonISA ) { 7.742 + if (UseLEXT1) { 7.743 __ gslbx(dst, AT, T9, 0); 7.744 } else { 7.745 __ addu(AT, AT, T9); 7.746 @@ -13525,11 +13525,11 @@ 7.747 } 7.748 } 7.749 } else { 7.750 - if( Assembler::is_simm16(disp) ) { 7.751 + if ( Assembler::is_simm16(disp) ) { 7.752 __ lb(dst, as_Register(base), disp); 7.753 } else { 7.754 __ move(T9, disp); 7.755 - if( UseLoongsonISA ) { 7.756 + if (UseLEXT1) { 7.757 __ gslbx(dst, as_Register(base), T9, 0); 7.758 } else { 7.759 __ addu(AT, as_Register(base), T9); 7.760 @@ -13620,7 +13620,7 @@ 7.761 __ lwc1($dst$$FloatRegister, $constanttablebase, con_offset); 7.762 } else { 7.763 __ set64(AT, con_offset); 7.764 - if (UseLoongsonISA) { 7.765 + if (UseLEXT1) { 7.766 __ gslwxc1($dst$$FloatRegister, $constanttablebase, AT, 0); 7.767 } else { 7.768 __ daddu(AT, $constanttablebase, AT); 7.769 @@ -13657,7 +13657,7 @@ 7.770 __ ldc1($dst$$FloatRegister, $constanttablebase, con_offset); 7.771 } else { 7.772 __ set64(AT, con_offset); 7.773 - if (UseLoongsonISA) { 7.774 + if (UseLEXT1) { 7.775 __ gsldxc1($dst$$FloatRegister, $constanttablebase, AT, 0); 7.776 } else { 7.777 __ daddu(AT, $constanttablebase, AT); 7.778 @@ -13690,7 +13690,7 @@ 7.779 int disp = $mem$$disp; 7.780 7.781 if( index != 0 ) { 7.782 - if ( UseLoongsonISA ) { 7.783 + if (UseLEXT1) { 7.784 if ( Assembler::is_simm(disp, 8) ) { 7.785 if ( scale == 0 ) { 7.786 __ gsswx(R0, as_Register(base), as_Register(index), disp); 7.787 @@ -13734,7 +13734,7 @@ 7.788 } 7.789 } 7.790 } else { //index is 0 7.791 - if ( UseLoongsonISA ) { 7.792 + if (UseLEXT1) { 7.793 if ( Assembler::is_simm16(disp) ) { 7.794 __ sw(R0, as_Register(base), disp); 7.795 } else { 7.796 @@ -13799,7 +13799,7 @@ 7.797 __ cvt_d_w(F30, F30); 7.798 7.799 if( index != 0 ) { 7.800 - if ( UseLoongsonISA ) { 7.801 + if (UseLEXT1) { 7.802 if ( Assembler::is_simm(disp, 8) ) { 7.803 if (scale == 0) { 7.804 __ gssdxc1(F30, as_Register(base), as_Register(index), disp); 7.805 @@ -13844,7 +13844,7 @@ 7.806 } 7.807 } 7.808 } else {// index is 0 7.809 - if ( UseLoongsonISA ) { 7.810 + if (UseLEXT1) { 7.811 if ( Assembler::is_simm16(disp) ) { 7.812 __ sdc1(F30, as_Register(base), disp); 7.813 } else { 7.814 @@ -14647,7 +14647,7 @@ 7.815 %} 7.816 7.817 instruct Repl8B_DSP(vecD dst, mRegI src) %{ 7.818 - predicate(n->as_Vector()->length() == 8 && Use3A2000); 7.819 + predicate(n->as_Vector()->length() == 8 && UseLEXT3); 7.820 match(Set dst (ReplicateB src)); 7.821 ins_cost(100); 7.822 format %{ "replv_ob AT, $src\n\t" 7.823 @@ -14679,7 +14679,7 @@ 7.824 %} 7.825 7.826 instruct Repl8B_imm_DSP(vecD dst, immI con) %{ 7.827 - predicate(n->as_Vector()->length() == 8 && Use3A2000); 7.828 + predicate(n->as_Vector()->length() == 8 && UseLEXT3); 7.829 match(Set dst (ReplicateB con)); 7.830 ins_cost(110); 7.831 format %{ "repl_ob AT, [$con]\n\t" 7.832 @@ -14735,7 +14735,7 @@ 7.833 %} 7.834 7.835 instruct Repl4S_DSP(vecD dst, mRegI src) %{ 7.836 - predicate(n->as_Vector()->length() == 4 && Use3A2000); 7.837 + predicate(n->as_Vector()->length() == 4 && UseLEXT3); 7.838 match(Set dst (ReplicateS src)); 7.839 ins_cost(100); 7.840 format %{ "replv_qh AT, $src\n\t" 7.841 @@ -14765,7 +14765,7 @@ 7.842 %} 7.843 7.844 instruct Repl4S_imm_DSP(vecD dst, immI con) %{ 7.845 - predicate(n->as_Vector()->length() == 4 && Use3A2000); 7.846 + predicate(n->as_Vector()->length() == 4 && UseLEXT3); 7.847 match(Set dst (ReplicateS con)); 7.848 ins_cost(100); 7.849 format %{ "repl_qh AT, [$con]\n\t"
8.1 --- a/src/cpu/mips/vm/nativeInst_mips.cpp Mon Jul 22 18:48:55 2019 +0800 8.2 +++ b/src/cpu/mips/vm/nativeInst_mips.cpp Thu Sep 05 13:07:31 2019 +0800 8.3 @@ -439,7 +439,7 @@ 8.4 static int *buf; 8.5 8.6 static atomic_store128_ptr get_atomic_store128_func() { 8.7 - assert(UseLoongsonISA, "UseLoongsonISA must be true"); 8.8 + assert(UseLEXT1, "UseLEXT1 must be true"); 8.9 static atomic_store128_ptr p = NULL; 8.10 if (p != NULL) 8.11 return p; 8.12 @@ -702,7 +702,7 @@ 8.13 set_int_at(0, (first_word & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 48) & 0xffff)); 8.14 ICache::invalidate_range(addr_at(0), 24); 8.15 } else if (is_op(int_at(16), Assembler::jal_op)) { 8.16 - if (UseLoongsonISA) { 8.17 + if (UseLEXT1) { 8.18 patch_on_jal_gs(dest); 8.19 } else { 8.20 patch_on_jal(dest); 8.21 @@ -710,14 +710,14 @@ 8.22 } else if (is_op(int_at(0), Assembler::jal_op)) { 8.23 patch_on_jal_only(dest); 8.24 } else if (is_special_op(int_at(16), Assembler::jalr_op)) { 8.25 - if (UseLoongsonISA) { 8.26 + if (UseLEXT1) { 8.27 patch_on_jalr(dest); 8.28 } else { 8.29 patch_on_jalr(dest); 8.30 } 8.31 } else if (is_special_op(int_at(8), Assembler::jalr_op)) { 8.32 guarantee(!os::is_MP() || (((long)addr_at(0) % 8) == 0), "destination must be aligned by 8"); 8.33 - if (UseLoongsonISA) { 8.34 + if (UseLEXT1) { 8.35 patch_set32_gs(dest); 8.36 } else { 8.37 patch_set32(dest); 8.38 @@ -1325,7 +1325,7 @@ 8.39 ICache::invalidate_range(addr_at(0), 8); 8.40 #else 8.41 if (is_op(int_at(16), Assembler::j_op)) { 8.42 - if (UseLoongsonISA) { 8.43 + if (UseLEXT1) { 8.44 patch_on_j_gs(dest); 8.45 } else { 8.46 patch_on_j(dest); 8.47 @@ -1333,7 +1333,7 @@ 8.48 } else if (is_op(int_at(0), Assembler::j_op)) { 8.49 patch_on_j_only(dest); 8.50 } else if (is_special_op(int_at(16), Assembler::jr_op)) { 8.51 - if (UseLoongsonISA) { 8.52 + if (UseLEXT1) { 8.53 //guarantee(!os::is_MP() || (((long)addr_at(0) % 16) == 0), "destination must be aligned for GSSD"); 8.54 //patch_on_jr_gs(dest); 8.55 patch_on_jr(dest); 8.56 @@ -1636,7 +1636,7 @@ 8.57 // Destination must be aligned for GSSQ. 8.58 bool is_aligned = !os::is_MP() || (((long)verified_entry % (BytesPerWord * 2)) == 0); 8.59 8.60 - if (UseLoongsonISA && is_aligned) { 8.61 + if (UseLEXT1 && is_aligned) { 8.62 int code_buffer[4]; 8.63 8.64 CodeBuffer cb((address)code_buffer, instruction_size);
9.1 --- a/src/cpu/mips/vm/stubGenerator_mips_64.cpp Mon Jul 22 18:48:55 2019 +0800 9.2 +++ b/src/cpu/mips/vm/stubGenerator_mips_64.cpp Thu Sep 05 13:07:31 2019 +0800 9.3 @@ -561,7 +561,7 @@ 9.4 __ bind(l_0); 9.5 9.6 __ dadd(AT, tmp, T0); 9.7 - if (UseLoongsonISA) { 9.8 + if (UseLEXT1) { 9.9 __ gssbx(R0, AT, T1, 0); 9.10 } else { 9.11 __ dadd(AT, AT, T1); 9.12 @@ -677,7 +677,7 @@ 9.13 __ daddu(start, start, scratch); 9.14 9.15 __ bind(L_loop); 9.16 - if (UseLoongsonISA) { 9.17 + if (UseLEXT1) { 9.18 __ gssbx(R0, start, count, 0); 9.19 } else { 9.20 __ daddu(AT, start, count); 9.21 @@ -1171,7 +1171,7 @@ 9.22 { // FasterArrayCopy 9.23 __ bind(l_11); 9.24 // For loongson the 128-bit memory access instruction is gslq/gssq 9.25 - if (UseLoongsonISA) { 9.26 + if (UseLEXT1) { 9.27 __ gslq(AT, tmp4, tmp1, 0); 9.28 __ gslq(tmp5, tmp6, tmp1, 16); 9.29 __ daddi(tmp1, tmp1, 32);
10.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp Mon Jul 22 18:48:55 2019 +0800 10.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp Thu Sep 05 13:07:31 2019 +0800 10.3 @@ -349,7 +349,7 @@ 10.4 const int tags_offset = Array<u1>::base_offset_in_bytes(); 10.5 10.6 // get type 10.7 - if (UseLoongsonISA && Assembler::is_simm(sizeof(tags_offset), 8)) { 10.8 + if (UseLEXT1 && Assembler::is_simm(sizeof(tags_offset), 8)) { 10.9 __ gslbx(T1, T1, T2, tags_offset); 10.10 } else { 10.11 __ dadd(AT, T1, T2); 10.12 @@ -387,7 +387,7 @@ 10.13 __ bne(AT, R0, notFloat); 10.14 __ delayed()->nop(); 10.15 // ftos 10.16 - if (UseLoongsonISA && Assembler::is_simm(sizeof(base_offset), 8)) { 10.17 + if (UseLEXT1 && Assembler::is_simm(sizeof(base_offset), 8)) { 10.18 __ gslwxc1(FSF, T3, T2, base_offset); 10.19 } else { 10.20 __ dadd(AT, T3, T2); 10.21 @@ -410,7 +410,7 @@ 10.22 } 10.23 #endif 10.24 // itos JVM_CONSTANT_Integer only 10.25 - if (UseLoongsonISA && Assembler::is_simm(sizeof(base_offset), 8)) { 10.26 + if (UseLEXT1 && Assembler::is_simm(sizeof(base_offset), 8)) { 10.27 __ gslwx(FSR, T3, T2, base_offset); 10.28 } else { 10.29 __ dadd(T0, T3, T2); 10.30 @@ -469,7 +469,7 @@ 10.31 const int tags_offset = Array<u1>::base_offset_in_bytes(); 10.32 10.33 // get type in T1 10.34 - if (UseLoongsonISA && Assembler::is_simm(tags_offset, 8)) { 10.35 + if (UseLEXT1 && Assembler::is_simm(tags_offset, 8)) { 10.36 __ gslbx(T1, T1, T2, tags_offset); 10.37 } else { 10.38 __ dadd(AT, T1, T2); 10.39 @@ -481,7 +481,7 @@ 10.40 __ delayed()->dsll(T2, T2, Address::times_8); 10.41 10.42 // dtos 10.43 - if (UseLoongsonISA && Assembler::is_simm(base_offset, 8)) { 10.44 + if (UseLEXT1 && Assembler::is_simm(base_offset, 8)) { 10.45 __ gsldxc1(FSF, T3, T2, base_offset); 10.46 } else { 10.47 __ daddu(AT, T3, T2); 10.48 @@ -493,7 +493,7 @@ 10.49 10.50 // ltos 10.51 __ bind(Long); 10.52 - if (UseLoongsonISA && Assembler::is_simm(base_offset, 8)) { 10.53 + if (UseLEXT1 && Assembler::is_simm(base_offset, 8)) { 10.54 __ gsldx(FSR, T3, T2, base_offset); 10.55 } else { 10.56 __ dadd(AT, T3, T2); 10.57 @@ -709,7 +709,7 @@ 10.58 } else { 10.59 index_check(SSR, FSR); 10.60 __ dsll(FSR, FSR, 2); 10.61 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_INT), 8)) { 10.62 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_INT), 8)) { 10.63 __ gslwx(FSR, FSR, SSR, arrayOopDesc::base_offset_in_bytes(T_INT)); 10.64 } else { 10.65 __ dadd(FSR, SSR, FSR); 10.66 @@ -735,7 +735,7 @@ 10.67 } else { 10.68 index_check(SSR, FSR); 10.69 __ dsll(AT, FSR, Address::times_8); 10.70 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_LONG), 8)) { 10.71 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_LONG), 8)) { 10.72 __ gsldx(FSR, SSR, AT, arrayOopDesc::base_offset_in_bytes(T_LONG)); 10.73 } else { 10.74 __ dadd(AT, SSR, AT); 10.75 @@ -761,7 +761,7 @@ 10.76 } else { 10.77 index_check(SSR, FSR); 10.78 __ shl(FSR, 2); 10.79 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_FLOAT), 8)) { 10.80 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_FLOAT), 8)) { 10.81 __ gslwxc1(FSF, SSR, FSR, arrayOopDesc::base_offset_in_bytes(T_FLOAT)); 10.82 } else { 10.83 __ dadd(FSR, SSR, FSR); 10.84 @@ -787,7 +787,7 @@ 10.85 } else { 10.86 index_check(SSR, FSR); 10.87 __ dsll(AT, FSR, 3); 10.88 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_DOUBLE), 8)) { 10.89 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_DOUBLE), 8)) { 10.90 __ gsldxc1(FSF, SSR, AT, arrayOopDesc::base_offset_in_bytes(T_DOUBLE)); 10.91 } else { 10.92 __ dadd(AT, SSR, AT); 10.93 @@ -819,7 +819,7 @@ 10.94 __ gslble(FSR, FSR, AT); 10.95 } else { 10.96 index_check(SSR, FSR); 10.97 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_BYTE), 8)) { 10.98 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_BYTE), 8)) { 10.99 __ gslbx(FSR, SSR, FSR, arrayOopDesc::base_offset_in_bytes(T_BYTE)); 10.100 } else { 10.101 __ dadd(FSR, SSR, FSR); 10.102 @@ -867,7 +867,7 @@ 10.103 } else { 10.104 index_check(SSR, FSR); 10.105 __ dsll(FSR, FSR, Address::times_2); 10.106 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_SHORT), 8)) { 10.107 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_SHORT), 8)) { 10.108 __ gslhx(FSR, SSR, FSR, arrayOopDesc::base_offset_in_bytes(T_SHORT)); 10.109 } else { 10.110 __ dadd(FSR, SSR, FSR); 10.111 @@ -1062,7 +1062,7 @@ 10.112 } else { 10.113 index_check(T2, SSR); // prefer index in SSR 10.114 __ dsll(SSR, SSR, Address::times_4); 10.115 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_INT), 8)) { 10.116 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_INT), 8)) { 10.117 __ gsswx(FSR, T2, SSR, arrayOopDesc::base_offset_in_bytes(T_INT)); 10.118 } else { 10.119 __ dadd(T2, T2, SSR); 10.120 @@ -1092,7 +1092,7 @@ 10.121 } else { 10.122 index_check(T3, T2); 10.123 __ dsll(T2, T2, Address::times_8); 10.124 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_LONG), 8)) { 10.125 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_LONG), 8)) { 10.126 __ gssdx(FSR, T3, T2, arrayOopDesc::base_offset_in_bytes(T_LONG)); 10.127 } else { 10.128 __ dadd(T3, T3, T2); 10.129 @@ -1120,7 +1120,7 @@ 10.130 } else { 10.131 index_check(T2, SSR); 10.132 __ dsll(SSR, SSR, Address::times_4); 10.133 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_FLOAT), 8)) { 10.134 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_FLOAT), 8)) { 10.135 __ gsswxc1(FSF, T2, SSR, arrayOopDesc::base_offset_in_bytes(T_FLOAT)); 10.136 } else { 10.137 __ dadd(T2, T2, SSR); 10.138 @@ -1148,7 +1148,7 @@ 10.139 } else { 10.140 index_check(T3, T2); 10.141 __ dsll(T2, T2, Address::times_8); 10.142 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_DOUBLE), 8)) { 10.143 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_DOUBLE), 8)) { 10.144 __ gssdxc1(FSF, T3, T2, arrayOopDesc::base_offset_in_bytes(T_DOUBLE)); 10.145 } else { 10.146 __ daddu(T3, T3, T2); 10.147 @@ -1243,7 +1243,7 @@ 10.148 __ andi(FSR, FSR, 0x1); 10.149 __ bind(L_skip); 10.150 10.151 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_BYTE), 8)) { 10.152 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_BYTE), 8)) { 10.153 __ gssbx(FSR, T2, SSR, arrayOopDesc::base_offset_in_bytes(T_BYTE)); 10.154 } else { 10.155 __ dadd(SSR, T2, SSR); 10.156 @@ -1270,7 +1270,7 @@ 10.157 } else { 10.158 index_check(T2, SSR); 10.159 __ dsll(SSR, SSR, Address::times_2); 10.160 - if (UseLoongsonISA && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_CHAR), 8)) { 10.161 + if (UseLEXT1 && Assembler::is_simm(arrayOopDesc::base_offset_in_bytes(T_CHAR), 8)) { 10.162 __ gsshx(FSR, T2, SSR, arrayOopDesc::base_offset_in_bytes(T_CHAR)); 10.163 } else { 10.164 __ dadd(SSR, T2, SSR); 10.165 @@ -1470,7 +1470,7 @@ 10.166 __ bind(not_zero); 10.167 10.168 __ pop_i(SSR); 10.169 - if (UseLoongsonISA) { 10.170 + if (UseLEXT1) { 10.171 __ gsdiv(FSR, SSR, FSR); 10.172 } else { 10.173 __ div(SSR, FSR); 10.174 @@ -1497,7 +1497,7 @@ 10.175 void TemplateTable::lmul() { 10.176 transition(ltos, ltos); 10.177 __ pop_l(T2); 10.178 - if(UseLoongsonISA){ 10.179 + if (UseLEXT1) { 10.180 __ gsdmult(FSR, T2, FSR); 10.181 } else { 10.182 __ dmult(T2, FSR); 10.183 @@ -1519,7 +1519,7 @@ 10.184 10.185 __ bind(normal); 10.186 __ pop_l(A2); 10.187 - if (UseLoongsonISA) { 10.188 + if (UseLEXT1) { 10.189 __ gsddiv(FSR, A2, FSR); 10.190 } else { 10.191 __ ddiv(A2, FSR); 10.192 @@ -1541,7 +1541,7 @@ 10.193 __ bind(normal); 10.194 __ pop_l (A2); 10.195 10.196 - if(UseLoongsonISA){ 10.197 + if (UseLEXT1) { 10.198 __ gsdmod(FSR, A2, FSR); 10.199 } else { 10.200 __ ddiv(A2, FSR); 10.201 @@ -4065,7 +4065,7 @@ 10.202 __ get_cpool_and_tags(A1, T1); 10.203 10.204 __ dsll(AT, A2, Address::times_8); 10.205 - if (UseLoongsonISA && Assembler::is_simm(sizeof(ConstantPool), 8)) { 10.206 + if (UseLEXT1 && Assembler::is_simm(sizeof(ConstantPool), 8)) { 10.207 __ gsldx(T3, A1, AT, sizeof(ConstantPool)); 10.208 } else { 10.209 __ dadd(AT, A1, AT); 10.210 @@ -4075,7 +4075,7 @@ 10.211 // make sure the class we're about to instantiate has been resolved. 10.212 // Note: slow_case does a pop of stack, which is why we loaded class/pushed above 10.213 const int tags_offset = Array<u1>::base_offset_in_bytes(); 10.214 - if (UseLoongsonISA && Assembler::is_simm(tags_offset, 8)) { 10.215 + if (UseLEXT1 && Assembler::is_simm(tags_offset, 8)) { 10.216 __ gslbx(AT, T1, A2, tags_offset); 10.217 } else { 10.218 __ dadd(T1, T1, A2);
11.1 --- a/src/cpu/mips/vm/vm_version_mips.cpp Mon Jul 22 18:48:55 2019 +0800 11.2 +++ b/src/cpu/mips/vm/vm_version_mips.cpp Thu Sep 05 13:07:31 2019 +0800 11.3 @@ -33,25 +33,258 @@ 11.4 #ifdef TARGET_OS_FAMILY_linux 11.5 # include "os_linux.inline.hpp" 11.6 #endif 11.7 -#ifdef TARGET_OS_FAMILY_solaris 11.8 -# include "os_solaris.inline.hpp" 11.9 -#endif 11.10 -#ifdef TARGET_OS_FAMILY_windows 11.11 -# include "os_windows.inline.hpp" 11.12 -#endif 11.13 -#ifdef TARGET_OS_FAMILY_bsd 11.14 -# include "os_bsd.inline.hpp" 11.15 -#endif 11.16 -int VM_Version::_features = VM_Version::unknown_m; 11.17 + 11.18 +int VM_Version::_cpuFeatures; 11.19 const char* VM_Version::_features_str = ""; 11.20 -void VM_Version::initialize() { 11.21 +VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; 11.22 +volatile bool VM_Version::_is_determine_cpucfg_supported_running = false; 11.23 +bool VM_Version::_is_cpucfg_instruction_supported = true; 11.24 +bool VM_Version::_cpu_info_is_initialized = false; 11.25 11.26 - _features = determine_features(); 11.27 - //no need, Abstract_VM_Version already define it as false 11.28 +static BufferBlob* stub_blob; 11.29 +static const int stub_size = 600; 11.30 + 11.31 +extern "C" { 11.32 + typedef void (*get_cpu_info_stub_t)(void*); 11.33 +} 11.34 +static get_cpu_info_stub_t get_cpu_info_stub = NULL; 11.35 + 11.36 + 11.37 +class VM_Version_StubGenerator: public StubCodeGenerator { 11.38 + public: 11.39 + 11.40 + VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} 11.41 + 11.42 + address generate_get_cpu_info() { 11.43 + assert(!VM_Version::cpu_info_is_initialized(), "VM_Version should not be initialized"); 11.44 + StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub"); 11.45 +# define __ _masm-> 11.46 + 11.47 + address start = __ pc(); 11.48 + 11.49 + __ enter(); 11.50 + __ push(AT); 11.51 + __ push(V0); 11.52 + 11.53 + __ li(AT, (long)0); 11.54 + __ cpucfg(V0, AT); 11.55 + __ lw(AT, A0, in_bytes(VM_Version::Loongson_Cpucfg_id0_offset())); 11.56 + __ sw(V0, A0, in_bytes(VM_Version::Loongson_Cpucfg_id0_offset())); 11.57 + 11.58 + __ li(AT, 1); 11.59 + __ cpucfg(V0, AT); 11.60 + __ lw(AT, A0, in_bytes(VM_Version::Loongson_Cpucfg_id1_offset())); 11.61 + __ sw(V0, A0, in_bytes(VM_Version::Loongson_Cpucfg_id1_offset())); 11.62 + 11.63 + __ li(AT, 2); 11.64 + __ cpucfg(V0, AT); 11.65 + __ lw(AT, A0, in_bytes(VM_Version::Loongson_Cpucfg_id2_offset())); 11.66 + __ sw(V0, A0, in_bytes(VM_Version::Loongson_Cpucfg_id2_offset())); 11.67 + 11.68 + __ pop(V0); 11.69 + __ pop(AT); 11.70 + __ leave(); 11.71 + __ jr(RA); 11.72 + __ delayed()->nop(); 11.73 +# undef __ 11.74 + 11.75 + return start; 11.76 + }; 11.77 +}; 11.78 + 11.79 +uint32_t VM_Version::get_feature_flags_by_cpucfg() { 11.80 + uint32_t result = 0; 11.81 + if (_cpuid_info.cpucfg_info_id1.bits.MMI != 0) 11.82 + result |= CPU_MMI; 11.83 + if (_cpuid_info.cpucfg_info_id1.bits.MSA1 != 0) 11.84 + result |= CPU_MSA1_0; 11.85 + if (_cpuid_info.cpucfg_info_id1.bits.MSA2 != 0) 11.86 + result |= CPU_MSA2_0; 11.87 + if (_cpuid_info.cpucfg_info_id1.bits.CGP != 0) 11.88 + result |= CPU_CGP; 11.89 + if (_cpuid_info.cpucfg_info_id1.bits.LSX1 != 0) 11.90 + result |= CPU_LSX1; 11.91 + if (_cpuid_info.cpucfg_info_id1.bits.LSX2 != 0) 11.92 + result |= CPU_LSX2; 11.93 + if (_cpuid_info.cpucfg_info_id1.bits.LASX != 0) 11.94 + result |= CPU_LASX; 11.95 + if (_cpuid_info.cpucfg_info_id1.bits.LLSYNC != 0) 11.96 + result |= CPU_LLSYNC; 11.97 + if (_cpuid_info.cpucfg_info_id1.bits.TGTSYNC != 0) 11.98 + result |= CPU_TGTSYNC; 11.99 + if (_cpuid_info.cpucfg_info_id1.bits.MUALP != 0) 11.100 + result |= CPU_MUALP; 11.101 + if (_cpuid_info.cpucfg_info_id2.bits.LEXT1 != 0) 11.102 + result |= CPU_LEXT1; 11.103 + if (_cpuid_info.cpucfg_info_id2.bits.LEXT2 != 0) 11.104 + result |= CPU_LEXT2; 11.105 + if (_cpuid_info.cpucfg_info_id2.bits.LEXT3 != 0) 11.106 + result |= CPU_LEXT3; 11.107 + if (_cpuid_info.cpucfg_info_id2.bits.LAMO != 0) 11.108 + result |= CPU_LAMO; 11.109 + if (_cpuid_info.cpucfg_info_id2.bits.LPIXU != 0) 11.110 + result |= CPU_LPIXU; 11.111 + 11.112 + result |= CPU_ULSYNC; 11.113 + 11.114 + return result; 11.115 +} 11.116 + 11.117 +void read_cpu_info(const char *path, char *result) { 11.118 + FILE *ptr; 11.119 + char buf[1024]; 11.120 + int i = 0; 11.121 + if((ptr=fopen(path, "r")) != NULL) { 11.122 + while(fgets(buf, 1024, ptr)!=NULL) { 11.123 + strcat(result,buf); 11.124 + i++; 11.125 + if (i == 10) break; 11.126 + } 11.127 + fclose(ptr); 11.128 + } else { 11.129 + warning("Can't detect CPU info - cannot open %s", path); 11.130 + } 11.131 +} 11.132 + 11.133 +void strlwr(char *str) { 11.134 + for (; *str!='\0'; str++) 11.135 + *str = tolower(*str); 11.136 +} 11.137 + 11.138 +int VM_Version::get_feature_flags_by_cpuinfo(int features) { 11.139 + assert(!cpu_info_is_initialized(), "VM_Version should not be initialized"); 11.140 + 11.141 + char res[10240]; 11.142 + int i; 11.143 + memset(res, '\0', 10240 * sizeof(char)); 11.144 + read_cpu_info("/proc/cpuinfo", res); 11.145 + // res is converted to lower case 11.146 + strlwr(res); 11.147 + 11.148 + if (strstr(res, "loongson")) { 11.149 + // Loongson CPU 11.150 + features |= CPU_LOONGSON; 11.151 + 11.152 + const struct Loongson_Cpuinfo loongson_cpuinfo[] = { 11.153 + {L_3A1000, "3a1000"}, 11.154 + {L_3B1500, "3b1500"}, 11.155 + {L_3A2000, "3a2000"}, 11.156 + {L_3B2000, "3b2000"}, 11.157 + {L_3A3000, "3a3000"}, 11.158 + {L_3B3000, "3b3000"}, 11.159 + {L_2K1000, "2k1000"}, 11.160 + {L_UNKNOWN, "unknown"} 11.161 + }; 11.162 + 11.163 + // Loongson Family 11.164 + int detected = 0; 11.165 + for (i = 0; i <= L_UNKNOWN; i++) { 11.166 + switch (i) { 11.167 + // 3A1000 and 3B1500 may use an old kernel and further comparsion is needed 11.168 + // test PRID REV in /proc/cpuinfo 11.169 + // 3A1000: V0.5, model name: ICT Loongson-3A V0.5 FPU V0.1 11.170 + // 3B1500: V0.7, model name: ICT Loongson-3B V0.7 FPU V0.1 11.171 + case L_3A1000: 11.172 + if (strstr(res, loongson_cpuinfo[i].match_str) || strstr(res, "loongson-3a v0.5")) { 11.173 + features |= CPU_LOONGSON_GS464; 11.174 + detected++; 11.175 + //tty->print_cr("3A1000 platform"); 11.176 + } 11.177 + break; 11.178 + case L_3B1500: 11.179 + if (strstr(res, loongson_cpuinfo[i].match_str) || strstr(res, "loongson-3b v0.7")) { 11.180 + features |= CPU_LOONGSON_GS464; 11.181 + detected++; 11.182 + //tty->print_cr("3B1500 platform"); 11.183 + } 11.184 + break; 11.185 + case L_3A2000: 11.186 + case L_3B2000: 11.187 + case L_3A3000: 11.188 + case L_3B3000: 11.189 + if (strstr(res, loongson_cpuinfo[i].match_str)) { 11.190 + features |= CPU_LOONGSON_GS464E; 11.191 + detected++; 11.192 + //tty->print_cr("3A2000/3A3000/3B2000/3B3000 platform"); 11.193 + } 11.194 + break; 11.195 + case L_2K1000: 11.196 + if (strstr(res, loongson_cpuinfo[i].match_str)) { 11.197 + features |= CPU_LOONGSON_GS264; 11.198 + detected++; 11.199 + //tty->print_cr("2K1000 platform"); 11.200 + } 11.201 + break; 11.202 + case L_UNKNOWN: 11.203 + if (detected == 0) { 11.204 + detected++; 11.205 + //tty->print_cr("unknown Loongson platform"); 11.206 + } 11.207 + break; 11.208 + default: 11.209 + ShouldNotReachHere(); 11.210 + } 11.211 + } 11.212 + assert (detected == 1, "one and only one of LOONGSON_CPU_FAMILY should be detected"); 11.213 + } else { // not Loongson 11.214 + // Not Loongson CPU 11.215 + //tty->print_cr("MIPS platform"); 11.216 + } 11.217 + 11.218 + if (features & CPU_LOONGSON_GS264) { 11.219 + features |= CPU_LEXT1; 11.220 + features |= CPU_LEXT2; 11.221 + features |= CPU_TGTSYNC; 11.222 + features |= CPU_ULSYNC; 11.223 + features |= CPU_MSA1_0; 11.224 + features |= CPU_LSX1; 11.225 + } else if (features & CPU_LOONGSON_GS464) { 11.226 + features |= CPU_LEXT1; 11.227 + features |= CPU_LLSYNC; 11.228 + features |= CPU_TGTSYNC; 11.229 + } else if (features & CPU_LOONGSON_GS464E) { 11.230 + features |= CPU_LEXT1; 11.231 + features |= CPU_LEXT2; 11.232 + features |= CPU_LEXT3; 11.233 + features |= CPU_TGTSYNC; 11.234 + features |= CPU_ULSYNC; 11.235 + } else if (features & CPU_LOONGSON) { 11.236 + // unknow loongson 11.237 + features |= CPU_LLSYNC; 11.238 + features |= CPU_TGTSYNC; 11.239 + features |= CPU_ULSYNC; 11.240 + } 11.241 + VM_Version::_cpu_info_is_initialized = true; 11.242 + 11.243 + return features; 11.244 +} 11.245 + 11.246 +void VM_Version::get_processor_features() { 11.247 + 11.248 + clean_cpuFeatures(); 11.249 + 11.250 + // test if cpucfg instruction is supported 11.251 + VM_Version::_is_determine_cpucfg_supported_running = true; 11.252 + __asm__ __volatile__( 11.253 + ".insn \n\t" 11.254 + ".word (0xc8080118)\n\t" // cpucfg zero, zero 11.255 + : 11.256 + : 11.257 + : 11.258 + ); 11.259 + VM_Version::_is_determine_cpucfg_supported_running = false; 11.260 + 11.261 + if (supports_cpucfg()) { 11.262 + get_cpu_info_stub(&_cpuid_info); 11.263 + _cpuFeatures = get_feature_flags_by_cpucfg(); 11.264 + // Only Loongson CPUs support cpucfg 11.265 + _cpuFeatures |= CPU_LOONGSON; 11.266 + } else { 11.267 + _cpuFeatures = get_feature_flags_by_cpuinfo(0); 11.268 + } 11.269 + 11.270 _supports_cx8 = true; 11.271 11.272 - //////////////////////add some other feature here////////////////// 11.273 - 11.274 if (UseG1GC && FLAG_IS_DEFAULT(MaxGCPauseMillis)) { 11.275 FLAG_SET_CMDLINE(uintx, MaxGCPauseMillis, 650); 11.276 } 11.277 @@ -64,6 +297,8 @@ 11.278 } 11.279 if (MaxVectorSize > 0 && supports_ps()) { 11.280 MaxVectorSize = 8; 11.281 + } else { 11.282 + MaxVectorSize = 0; 11.283 } 11.284 } 11.285 // 11.286 @@ -77,49 +312,64 @@ 11.287 MaxVectorSize = 0; 11.288 } 11.289 11.290 - if (is_gs464e()) { 11.291 +#endif 11.292 + 11.293 + if (needs_llsync() && needs_tgtsync() && !needs_ulsync()) { 11.294 + if (FLAG_IS_DEFAULT(UseSyncLevel)) { 11.295 + FLAG_SET_DEFAULT(UseSyncLevel, 1000); 11.296 + } 11.297 + } else if (!needs_llsync() && needs_tgtsync() && needs_ulsync()) { 11.298 + if (FLAG_IS_DEFAULT(UseSyncLevel)) { 11.299 + FLAG_SET_DEFAULT(UseSyncLevel, 2000); 11.300 + } 11.301 + } else if (needs_llsync() && needs_llsync() && needs_ulsync()) { 11.302 + if (FLAG_IS_DEFAULT(UseSyncLevel)) { 11.303 + FLAG_SET_DEFAULT(UseSyncLevel, 3000); 11.304 + } 11.305 + } else if (!needs_llsync() && !needs_llsync() && !needs_ulsync()) { 11.306 + if (FLAG_IS_DEFAULT(UseSyncLevel)) { 11.307 + FLAG_SET_DEFAULT(UseSyncLevel, 0); 11.308 + } 11.309 + } else { 11.310 + assert(false, "Should Not Reach Here, what is the cpu type?"); 11.311 + } 11.312 + 11.313 + if (supports_lext1()) { 11.314 + if (FLAG_IS_DEFAULT(UseLEXT1)) { 11.315 + FLAG_SET_DEFAULT(UseLEXT1, true); 11.316 + } 11.317 + } else if (UseLEXT1) { 11.318 + warning("LEXT1 instructions are not available on this CPU"); 11.319 + FLAG_SET_DEFAULT(UseLEXT1, false); 11.320 + } 11.321 + 11.322 + if (supports_lext2()) { 11.323 + if (FLAG_IS_DEFAULT(UseLEXT2)) { 11.324 + FLAG_SET_DEFAULT(UseLEXT2, true); 11.325 + } 11.326 + } else if (UseLEXT2) { 11.327 + warning("LEXT2 instructions are not available on this CPU"); 11.328 + FLAG_SET_DEFAULT(UseLEXT2, false); 11.329 + } 11.330 + 11.331 + if (supports_lext3()) { 11.332 + if (FLAG_IS_DEFAULT(UseLEXT3)) { 11.333 + FLAG_SET_DEFAULT(UseLEXT3, true); 11.334 + } 11.335 + } else if (UseLEXT3) { 11.336 + warning("LEXT3 instructions are not available on this CPU"); 11.337 + FLAG_SET_DEFAULT(UseLEXT3, false); 11.338 + } 11.339 + 11.340 + if (UseLEXT2) { 11.341 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionMIPS64)) { 11.342 FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionMIPS64, 1); 11.343 } 11.344 } else if (UseCountTrailingZerosInstructionMIPS64) { 11.345 if (!FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionMIPS64)) 11.346 - warning("Only 3A2000/3000 CPUs support UseCountTrailingZerosInstructionMIPS64"); 11.347 + warning("ctz/dctz instructions are not available on this CPU"); 11.348 FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionMIPS64, 0); 11.349 } 11.350 -#endif 11.351 - UseSSE = 0; // Only on x86 and x64 11.352 - 11.353 - if (is_loongson()) { 11.354 - if (FLAG_IS_DEFAULT(UseLoongsonISA)) { 11.355 - FLAG_SET_DEFAULT(UseLoongsonISA, 1); 11.356 - } 11.357 - } else if (UseLoongsonISA) { 11.358 - if (!FLAG_IS_DEFAULT(UseLoongsonISA)) 11.359 - warning("Only Loongson CPUs support LoongISA"); 11.360 - FLAG_SET_DEFAULT(UseLoongsonISA, 0); 11.361 - } 11.362 - 11.363 - if (is_gs464e()) { 11.364 - if (FLAG_IS_DEFAULT(Use3A2000)) { 11.365 - FLAG_SET_DEFAULT(Use3A2000, 1); 11.366 - } 11.367 - } else if (Use3A2000) { 11.368 - if (!FLAG_IS_DEFAULT(Use3A2000)) 11.369 - warning("Only 3A2000/3000 CPUs support this option"); 11.370 - FLAG_SET_DEFAULT(Use3A2000, 0); 11.371 - } 11.372 - 11.373 - if (is_gs464()) { 11.374 - if (FLAG_IS_DEFAULT(UseSyncLevel)) { 11.375 - FLAG_SET_DEFAULT(UseSyncLevel, 1000); 11.376 - } 11.377 - } 11.378 - 11.379 - if (is_gs464e() || is_gs464v()) { 11.380 - if (FLAG_IS_DEFAULT(UseSyncLevel)) { 11.381 - FLAG_SET_DEFAULT(UseSyncLevel, 2000); 11.382 - } 11.383 - } 11.384 11.385 if (TieredCompilation) { 11.386 if (!FLAG_IS_DEFAULT(TieredCompilation)) 11.387 @@ -128,23 +378,35 @@ 11.388 } 11.389 11.390 char buf[256]; 11.391 - bool is_unknown_loongson_cpu = is_loongson() && !is_gs464() && !is_gs464e() && !is_gs464v() && !is_gs264(); 11.392 - jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s, UseSyncLevel:%d", 11.393 - (has_l2_cache() ? ", has_l2_cache" : ""), 11.394 - (has_16k_page() ? ", has_16k_page" : ""), 11.395 - (is_loongson() ? ", MIPS-compatible Loongson CPU" : "MIPS"), 11.396 - (is_gs464() ? ", GS464 (3A1000/3B1500)" : ""), 11.397 - (is_gs464e() ? ", GS464E (3A2000/3A3000/3B2000/3B3000)" : ""), 11.398 - (is_gs464v() ? ", GS464V (3A4000/3B4000)" : ""), 11.399 - (is_gs264() ? ", GS264 (2K1000)" : ""), 11.400 + bool is_unknown_loongson_cpu = is_loongson() && !is_gs464() && !is_gs464e() && !is_gs264() && !supports_cpucfg(); 11.401 + 11.402 + jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s, UseSyncLevel:%d", 11.403 + (is_loongson() ? "MIPS-compatible Loongson CPU" : "MIPS CPU"), 11.404 + (is_gs464() ? ", GS464 (3A1000/3B1500)" : ""), 11.405 + (is_gs464e() ? ", GS464E (3A2000/3A3000/3B2000/3B3000)" : ""), 11.406 + (is_gs264() ? ", GS264 (2K1000)" : ""), 11.407 (is_unknown_loongson_cpu ? ", Unknown Loongson CPU" : ""), 11.408 - (UseLoongsonISA ? ", UseLoongsonISA" : ""), 11.409 - (UseCountTrailingZerosInstructionMIPS64 ? ", UseCountTrailingZerosInstructionMIPS64" : ""), 11.410 - (Use3A2000 ? ", Use3A2000" : ""), 11.411 + (supports_dsp() ? ", dsp" : ""), 11.412 + (supports_ps() ? ", ps" : ""), 11.413 + (supports_3d() ? ", 3d" : ""), 11.414 + (supports_mmi() ? ", mmi" : ""), 11.415 + (supports_msa1_0() ? ", msa1_0" : ""), 11.416 + (supports_msa2_0() ? ", msa2_0" : ""), 11.417 + (supports_lsx1() ? ", lsx1" : ""), 11.418 + (supports_lsx2() ? ", lsx2" : ""), 11.419 + (supports_lasx() ? ", lasx" : ""), 11.420 + (supports_lext1() ? ", lext1" : ""), 11.421 + (supports_lext2() ? ", lext2" : ""), 11.422 + (supports_lext3() ? ", lext3" : ""), 11.423 + (supports_cgp() ? ", aes, crc, sha1, sha256, sha512" : ""), 11.424 + (supports_lamo() ? ", lamo" : ""), 11.425 + (supports_lpixu() ? ", lpixu" : ""), 11.426 + (needs_llsync() ? ", llsync" : ""), 11.427 + (needs_tgtsync() ? ", tgtsync": ""), 11.428 + (needs_ulsync() ? ", ulsync": ""), 11.429 + (supports_mualp() ? ", mualp" : ""), 11.430 UseSyncLevel); 11.431 - 11.432 - // buf is started with ", " or is empty 11.433 - _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); 11.434 + _features_str = strdup(buf); 11.435 11.436 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 11.437 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); 11.438 @@ -178,6 +440,27 @@ 11.439 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 11.440 } 11.441 11.442 + if (UseAES) { 11.443 + if (!FLAG_IS_DEFAULT(UseAES)) { 11.444 + warning("AES instructions are not available on this CPU"); 11.445 + FLAG_SET_DEFAULT(UseAES, false); 11.446 + } 11.447 + } 11.448 + 11.449 + if (UseCRC32Intrinsics) { 11.450 + if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 11.451 + warning("CRC32Intrinsics instructions are not available on this CPU"); 11.452 + FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 11.453 + } 11.454 + } 11.455 + 11.456 + if (UseAESIntrinsics) { 11.457 + if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) { 11.458 + warning("AES intrinsics are not available on this CPU"); 11.459 + FLAG_SET_DEFAULT(UseAESIntrinsics, false); 11.460 + } 11.461 + } 11.462 + 11.463 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 11.464 UseMontgomeryMultiplyIntrinsic = true; 11.465 } 11.466 @@ -185,27 +468,20 @@ 11.467 UseMontgomerySquareIntrinsic = true; 11.468 } 11.469 11.470 - NOT_PRODUCT( if (PrintMiscellaneous && Verbose) print_features(); ); 11.471 } 11.472 11.473 -void VM_Version::print_features() { 11.474 - tty->print_cr("Version: %s", cpu_features()); 11.475 +void VM_Version::initialize() { 11.476 + ResourceMark rm; 11.477 + // Making this stub must be FIRST use of assembler 11.478 + 11.479 + stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); 11.480 + if (stub_blob == NULL) { 11.481 + vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); 11.482 + } 11.483 + CodeBuffer c(stub_blob); 11.484 + VM_Version_StubGenerator g(&c); 11.485 + get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, 11.486 + g.generate_get_cpu_info()); 11.487 + 11.488 + get_processor_features(); 11.489 } 11.490 - 11.491 -int VM_Version::determine_features() { 11.492 - //////////////////////add some other feature here////////////////// 11.493 - int features = platform_features(unknown_m); 11.494 - //spt_16k_page_m; 11.495 - return features; 11.496 -} 11.497 - 11.498 -static int saved_features = 0; 11.499 - 11.500 -void VM_Version::allow_all() { 11.501 - saved_features = _features; 11.502 - _features = all_features_m; 11.503 -} 11.504 - 11.505 -void VM_Version::revert() { 11.506 - _features = saved_features; 11.507 -}
12.1 --- a/src/cpu/mips/vm/vm_version_mips.hpp Mon Jul 22 18:48:55 2019 +0800 12.2 +++ b/src/cpu/mips/vm/vm_version_mips.hpp Thu Sep 05 13:07:31 2019 +0800 12.3 @@ -31,31 +31,98 @@ 12.4 12.5 12.6 class VM_Version: public Abstract_VM_Version { 12.7 -protected: 12.8 - enum Feature_Flag { 12.9 - with_l2_cache = 0, 12.10 - spt_16k_page = 1, 12.11 - gs464v = 2, 12.12 - gs464e = 3, 12.13 - gs464 = 4, 12.14 - gs264 = 5, 12.15 - with_gs_support = 6, 12.16 - //////////////////////add some other feature here////////////////// 12.17 +public: 12.18 + 12.19 + union Loongson_Cpucfg_Id1 { 12.20 + uint32_t value; 12.21 + struct { 12.22 + uint32_t FP : 1, 12.23 + FPREV : 3, 12.24 + MMI : 1, 12.25 + MSA1 : 1, 12.26 + MSA2 : 1, 12.27 + CGP : 1, 12.28 + WRP : 1, 12.29 + LSX1 : 1, 12.30 + LSX2 : 1, 12.31 + LASX : 1, 12.32 + R6FXP : 1, 12.33 + R6CRCP : 1, 12.34 + R6FPP : 1, 12.35 + CNT64 : 1, 12.36 + LSLDR0 : 1, 12.37 + LSPREF : 1, 12.38 + LSPREFX : 1, 12.39 + LSSYNCI : 1, 12.40 + LSUCA : 1, 12.41 + LLSYNC : 1, 12.42 + TGTSYNC : 1, 12.43 + LLEXC : 1, 12.44 + SCRAND : 1, 12.45 + MUALP : 1, 12.46 + KMUALEn : 1, 12.47 + ITLBT : 1, 12.48 + LSUPERF : 1, 12.49 + SFBP : 1, 12.50 + CDMAP : 1, 12.51 + : 1; 12.52 + } bits; 12.53 }; 12.54 12.55 - enum Feature_Flag_Set { 12.56 - unknown_m = 0, 12.57 - all_features_m = -1, 12.58 - with_l2_cache_m = 1 << with_l2_cache, 12.59 - spt_16k_page_m = 1 << spt_16k_page, 12.60 - with_gs_support_m = 1 << with_gs_support, 12.61 - gs464_m = 1 << gs464, 12.62 - gs464v_m = 1 << gs464v, 12.63 - gs464e_m = 1 << gs464e, 12.64 - gs264_m = 1 << gs264, 12.65 + union Loongson_Cpucfg_Id2 { 12.66 + uint32_t value; 12.67 + struct { 12.68 + uint32_t LEXT1 : 1, 12.69 + LEXT2 : 1, 12.70 + LEXT3 : 1, 12.71 + LSPW : 1, 12.72 + LBT1 : 1, 12.73 + LBT2 : 1, 12.74 + LBT3 : 1, 12.75 + LBTMMU : 1, 12.76 + LPMP : 1, 12.77 + LPMRev : 3, 12.78 + LAMO : 1, 12.79 + LPIXU : 1, 12.80 + LPIXNU : 1, 12.81 + LVZP : 1, 12.82 + LVZRev : 3, 12.83 + LGFTP : 1, 12.84 + LGFTRev : 3, 12.85 + LLFTP : 1, 12.86 + LLFTRev : 3, 12.87 + LCSRP : 1, 12.88 + DISBLKLY : 1, 12.89 + : 3; 12.90 + } bits; 12.91 + }; 12.92 + 12.93 +protected: 12.94 + 12.95 + enum { 12.96 + CPU_LOONGSON = (1 << 1), 12.97 + CPU_LOONGSON_GS464 = (1 << 2), 12.98 + CPU_LOONGSON_GS464E = (1 << 3), 12.99 + CPU_LOONGSON_GS264 = (1 << 4), 12.100 + CPU_MMI = (1 << 11), 12.101 + CPU_MSA1_0 = (1 << 12), 12.102 + CPU_MSA2_0 = (1 << 13), 12.103 + CPU_CGP = (1 << 14), 12.104 + CPU_LSX1 = (1 << 15), 12.105 + CPU_LSX2 = (1 << 16), 12.106 + CPU_LASX = (1 << 17), 12.107 + CPU_LEXT1 = (1 << 18), 12.108 + CPU_LEXT2 = (1 << 19), 12.109 + CPU_LEXT3 = (1 << 20), 12.110 + CPU_LAMO = (1 << 21), 12.111 + CPU_LPIXU = (1 << 22), 12.112 + CPU_LLSYNC = (1 << 23), 12.113 + CPU_TGTSYNC = (1 << 24), 12.114 + CPU_ULSYNC = (1 << 25), 12.115 + CPU_MUALP = (1 << 26), 12.116 12.117 //////////////////////add some other feature here////////////////// 12.118 - }; 12.119 + } cpuFeatureFlags; 12.120 12.121 enum Loongson_Family { 12.122 L_3A1000 = 0, 12.123 @@ -65,9 +132,7 @@ 12.124 L_3A3000 = 4, 12.125 L_3B3000 = 5, 12.126 L_2K1000 = 6, 12.127 - L_3A4000 = 7, 12.128 - L_3B4000 = 8, 12.129 - L_UNKNOWN = 9 12.130 + L_UNKNOWN = 7 12.131 }; 12.132 12.133 struct Loongson_Cpuinfo { 12.134 @@ -75,38 +140,82 @@ 12.135 const char* const match_str; 12.136 }; 12.137 12.138 - static int _features; 12.139 + static int _cpuFeatures; 12.140 static const char* _features_str; 12.141 + static volatile bool _is_determine_cpucfg_supported_running; 12.142 + static bool _is_cpucfg_instruction_supported; 12.143 + static bool _cpu_info_is_initialized; 12.144 12.145 - static void print_features(); 12.146 - static int determine_features(); 12.147 - static int platform_features(int features); 12.148 + struct CpuidInfo { 12.149 + uint32_t cpucfg_info_id0; 12.150 + Loongson_Cpucfg_Id1 cpucfg_info_id1; 12.151 + Loongson_Cpucfg_Id2 cpucfg_info_id2; 12.152 + uint32_t cpucfg_info_id3; 12.153 + uint32_t cpucfg_info_id4; 12.154 + uint32_t cpucfg_info_id5; 12.155 + uint32_t cpucfg_info_id6; 12.156 + uint32_t cpucfg_info_id8; 12.157 + }; 12.158 + 12.159 + // The actual cpuid info block 12.160 + static CpuidInfo _cpuid_info; 12.161 + 12.162 + static uint32_t get_feature_flags_by_cpucfg(); 12.163 + static int get_feature_flags_by_cpuinfo(int features); 12.164 + static void get_processor_features(); 12.165 12.166 public: 12.167 + // Offsets for cpuid asm stub 12.168 + static ByteSize Loongson_Cpucfg_id0_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id0); } 12.169 + static ByteSize Loongson_Cpucfg_id1_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id1); } 12.170 + static ByteSize Loongson_Cpucfg_id2_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id2); } 12.171 + static ByteSize Loongson_Cpucfg_id3_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id3); } 12.172 + static ByteSize Loongson_Cpucfg_id4_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id4); } 12.173 + static ByteSize Loongson_Cpucfg_id5_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id5); } 12.174 + static ByteSize Loongson_Cpucfg_id6_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id6); } 12.175 + static ByteSize Loongson_Cpucfg_id8_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id8); } 12.176 + 12.177 + static bool is_determine_features_test_running() { return _is_determine_cpucfg_supported_running; } 12.178 + 12.179 + static void clean_cpuFeatures() { _cpuFeatures = 0; } 12.180 + 12.181 // Initialization 12.182 static void initialize(); 12.183 12.184 + static bool cpu_info_is_initialized() { return _cpu_info_is_initialized; } 12.185 + 12.186 + static bool supports_cpucfg() { return _is_cpucfg_instruction_supported; } 12.187 + static bool set_supports_cpucfg(bool value) { return _is_cpucfg_instruction_supported = value; } 12.188 + 12.189 + static bool is_loongson() { return _cpuFeatures & CPU_LOONGSON; } 12.190 + static bool is_gs264() { return _cpuFeatures & CPU_LOONGSON_GS264; } 12.191 + static bool is_gs464() { return _cpuFeatures & CPU_LOONGSON_GS464; } 12.192 + static bool is_gs464e() { return _cpuFeatures & CPU_LOONGSON_GS464E; } 12.193 + static bool supports_dsp() { return 0; /*not supported yet*/} 12.194 + static bool supports_ps() { return 0; /*not supported yet*/} 12.195 + static bool supports_3d() { return 0; /*not supported yet*/} 12.196 + static bool supports_msa1_0() { return _cpuFeatures & CPU_MSA1_0; } 12.197 + static bool supports_msa2_0() { return _cpuFeatures & CPU_MSA2_0; } 12.198 + static bool supports_cgp() { return _cpuFeatures & CPU_CGP; } 12.199 + static bool supports_mmi() { return _cpuFeatures & CPU_MMI; } 12.200 + static bool supports_lsx1() { return _cpuFeatures & CPU_LSX1; } 12.201 + static bool supports_lsx2() { return _cpuFeatures & CPU_LSX2; } 12.202 + static bool supports_lasx() { return _cpuFeatures & CPU_LASX; } 12.203 + static bool supports_lext1() { return _cpuFeatures & CPU_LEXT1; } 12.204 + static bool supports_lext2() { return _cpuFeatures & CPU_LEXT2; } 12.205 + static bool supports_lext3() { return _cpuFeatures & CPU_LEXT3; } 12.206 + static bool supports_lamo() { return _cpuFeatures & CPU_LAMO; } 12.207 + static bool supports_lpixu() { return _cpuFeatures & CPU_LPIXU; } 12.208 + static bool needs_llsync() { return _cpuFeatures & CPU_LLSYNC; } 12.209 + static bool needs_tgtsync() { return _cpuFeatures & CPU_TGTSYNC; } 12.210 + static bool needs_ulsync() { return _cpuFeatures & CPU_ULSYNC; } 12.211 + static bool supports_mualp() { return _cpuFeatures & CPU_MUALP; } 12.212 + 12.213 //mips has no such instructions, use ll/sc instead 12.214 static bool supports_compare_and_exchange() { return false; } 12.215 12.216 - static bool has_l2_cache() { return _features & with_l2_cache_m; } 12.217 - static bool has_16k_page() { return _features & spt_16k_page_m; } 12.218 - static bool is_gs264() { return _features & gs264_m; } 12.219 - static bool is_gs464() { return _features & gs464_m; } 12.220 - static bool is_gs464v() { return _features & gs464v_m; } 12.221 - static bool is_gs464e() { return _features & gs464e_m; } 12.222 - static bool is_loongson() { return _features & with_gs_support_m; } 12.223 - static bool supports_dsp() { return 0; /*Loongson CPUs do not support DSP instructions well*/} 12.224 - static bool supports_ps() { return 1; /*Loongson CPUs support ps instructions*/} 12.225 - static bool supports_3d() { return 0; /*Loongson CPUs do not support 3d instructions*/} 12.226 + static const char* cpu_features() { return _features_str; } 12.227 12.228 - //////////////////////add some other feature here////////////////// 12.229 - 12.230 - static const char* cpu_features() { return _features_str; } 12.231 - 12.232 - // Assembler testing 12.233 - static void allow_all(); 12.234 - static void revert(); 12.235 }; 12.236 12.237 #endif // CPU_MIPS_VM_VM_VERSION_MIPS_HPP
13.1 --- a/src/os_cpu/linux_mips/vm/os_linux_mips.cpp Mon Jul 22 18:48:55 2019 +0800 13.2 +++ b/src/os_cpu/linux_mips/vm/os_linux_mips.cpp Thu Sep 05 13:07:31 2019 +0800 13.3 @@ -507,6 +507,11 @@ 13.4 } 13.5 } 13.6 } //SIGILL 13.7 + } else if (sig == SIGILL && VM_Version::is_determine_features_test_running()) { 13.8 + // thread->thread_state() != _thread_in_Java 13.9 + // SIGILL must be caused by VM_Version::determine_features(). 13.10 + VM_Version::set_supports_cpucfg(false); 13.11 + stub = pc + 4; // continue with next instruction. 13.12 } else if (thread->thread_state() == _thread_in_vm && 13.13 sig == SIGBUS && /* info->si_code == BUS_OBJERR && */ 13.14 thread->doing_unsafe_access()) {
14.1 --- a/src/os_cpu/linux_mips/vm/vm_version_linux_mips.cpp Mon Jul 22 18:48:55 2019 +0800 14.2 +++ b/src/os_cpu/linux_mips/vm/vm_version_linux_mips.cpp Thu Sep 05 13:07:31 2019 +0800 14.3 @@ -26,117 +26,3 @@ 14.4 #include "precompiled.hpp" 14.5 #include "runtime/os.hpp" 14.6 #include "vm_version_mips.hpp" 14.7 -#include "string.h" 14.8 -#include "ctype.h" 14.9 - 14.10 -void read_cpu_info(const char *path, char *result) { 14.11 - FILE *ptr; 14.12 - char buf[1024]; 14.13 - int i = 0; 14.14 - if((ptr=fopen(path, "r")) != NULL) { 14.15 - while(fgets(buf, 1024, ptr)!=NULL) { 14.16 - strcat(result,buf); 14.17 - i++; 14.18 - if (i == 10) break; 14.19 - } 14.20 - fclose(ptr); 14.21 - } else { 14.22 - warning("Can't detect CPU info - cannot open %s", path); 14.23 - } 14.24 -} 14.25 - 14.26 -void strlwr(char *str) { 14.27 - for (; *str!='\0'; str++) 14.28 - *str = tolower(*str); 14.29 -} 14.30 - 14.31 -int VM_Version::platform_features(int features) { 14.32 - char res[10240]; 14.33 - int i; 14.34 - features = spt_16k_page_m; //default support 14.35 - memset(res, '\0', 10240 * sizeof(char)); 14.36 - read_cpu_info("/proc/cpuinfo", res); 14.37 - // res is converted to lower case 14.38 - strlwr(res); 14.39 - 14.40 - if (strstr(res, "loongson")) { 14.41 - // Loongson CPU 14.42 - features |= with_gs_support_m; 14.43 - 14.44 - const struct Loongson_Cpuinfo loongson_cpuinfo[] = { 14.45 - {L_3A1000, "3a1000"}, 14.46 - {L_3B1500, "3b1500"}, 14.47 - {L_3A2000, "3a2000"}, 14.48 - {L_3B2000, "3b2000"}, 14.49 - {L_3A3000, "3a3000"}, 14.50 - {L_3B3000, "3b3000"}, 14.51 - {L_2K1000, "2k1000"}, 14.52 - {L_3A4000, "3a4000"}, 14.53 - {L_3B4000, "3b4000"}, 14.54 - {L_UNKNOWN, "unknown"} 14.55 - }; 14.56 - 14.57 - // Loongson Family 14.58 - int detected = 0; 14.59 - for (i = 0; i <= L_UNKNOWN; i++) { 14.60 - switch (i) { 14.61 - // 3A1000 and 3B1500 may use an old kernel and further comparsion is needed 14.62 - // test PRID REV in /proc/cpuinfo 14.63 - // 3A1000: V0.5, model name: ICT Loongson-3A V0.5 FPU V0.1 14.64 - // 3B1500: V0.7, model name: ICT Loongson-3B V0.7 FPU V0.1 14.65 - case L_3A1000: 14.66 - if (strstr(res, loongson_cpuinfo[i].match_str) || strstr(res, "loongson-3a v0.5")) { 14.67 - features |= gs464_m; 14.68 - detected++; 14.69 - //tty->print_cr("3A1000 platform"); 14.70 - } 14.71 - break; 14.72 - case L_3B1500: 14.73 - if (strstr(res, loongson_cpuinfo[i].match_str) || strstr(res, "loongson-3b v0.7")) { 14.74 - features |= gs464_m; 14.75 - detected++; 14.76 - //tty->print_cr("3B1500 platform"); 14.77 - } 14.78 - break; 14.79 - case L_3A2000: 14.80 - case L_3B2000: 14.81 - case L_3A3000: 14.82 - case L_3B3000: 14.83 - if (strstr(res, loongson_cpuinfo[i].match_str)) { 14.84 - features |= gs464e_m; 14.85 - detected++; 14.86 - //tty->print_cr("3A2000/3A3000/3B2000/3B3000 platform"); 14.87 - } 14.88 - break; 14.89 - case L_2K1000: 14.90 - if (strstr(res, loongson_cpuinfo[i].match_str)) { 14.91 - features |= gs264_m; 14.92 - detected++; 14.93 - //tty->print_cr("2K1000 platform"); 14.94 - } 14.95 - break; 14.96 - case L_3A4000: 14.97 - case L_3B4000: 14.98 - if (strstr(res, loongson_cpuinfo[i].match_str)) { 14.99 - features |= gs464v_m; 14.100 - detected++; 14.101 - //tty->print_cr("3A4000/3B4000 platform"); 14.102 - } 14.103 - break; 14.104 - case L_UNKNOWN: 14.105 - if (detected == 0) { 14.106 - detected++; 14.107 - //tty->print_cr("unknown Loongson platform"); 14.108 - } 14.109 - break; 14.110 - default: 14.111 - ShouldNotReachHere(); 14.112 - } 14.113 - } 14.114 - assert (detected == 1, "one and only one of LOONGSON_CPU_FAMILY should be detected"); 14.115 - } else { // not Loongson 14.116 - // Not Loongson CPU 14.117 - //tty->print_cr("MIPS platform"); 14.118 - } 14.119 - return features; 14.120 -}
