Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/bytes_mips.hpp	Mon Sep 03 14:27:42 2018 +0800
     1.2 +++ b/src/cpu/mips/vm/bytes_mips.hpp	Tue Sep 04 21:25:12 2018 +0800
     1.3 @@ -111,8 +111,8 @@
     1.4      }
     1.5    }
     1.6    static inline void put_native_u4(address p, u4 x)   {
     1.7 -    /* 2016/5/8 Jin: refer to sparc implementation.
     1.8 -                     Note that sparc is big-endian, while mips is little-endian */
     1.9 +    // refer to sparc implementation.
    1.10 +    // Note that sparc is big-endian, while mips is little-endian
    1.11          switch ( intptr_t(p) & 3 ) {
    1.12          case 0:  *(u4*)p = x;
    1.13              break;
    1.14 @@ -129,8 +129,8 @@
    1.15          }
    1.16     }
    1.17    static inline void put_native_u8(address p, u8 x)   {
    1.18 -  /* 2016/5/8 Jin: refer to sparc implementation.
    1.19 -                   Note that sparc is big-endian, while mips is little-endian */
    1.20 +    // refer to sparc implementation.
    1.21 +    // Note that sparc is big-endian, while mips is little-endian
    1.22      switch ( intptr_t(p) & 7 ) {
    1.23      case 0:  *(u8*)p = x;
    1.24        break;

     2.1 --- a/src/cpu/mips/vm/c1_CodeStubs_mips.cpp	Mon Sep 03 14:27:42 2018 +0800
     2.2 +++ b/src/cpu/mips/vm/c1_CodeStubs_mips.cpp	Tue Sep 04 21:25:12 2018 +0800
     2.3 @@ -66,7 +66,7 @@
     2.4  RangeCheckStub::RangeCheckStub(CodeEmitInfo* info, LIR_Opr index,
     2.5                                 bool throw_index_out_of_bounds_exception)
     2.6    : _throw_index_out_of_bounds_exception(throw_index_out_of_bounds_exception)
     2.7 -    , _index(index)
     2.8 +  , _index(index)
     2.9  {
    2.10    _info = info == NULL ? NULL : new CodeEmitInfo(info);
    2.11  }
    2.12 @@ -150,7 +150,6 @@
    2.13  #ifndef _LP64
    2.14    assert(_klass_reg->as_register() == T4, "klass_reg must in T4");
    2.15  #else
    2.16 -  //FIXME. in A4? aoqi
    2.17    assert(_klass_reg->as_register() == A4, "klass_reg must in A4");
    2.18  #endif
    2.19    __ call(Runtime1::entry_for(_stub_id), relocInfo::runtime_call_type);
    2.20 @@ -181,7 +180,6 @@
    2.21  #ifndef _LP64
    2.22    assert(_klass_reg->as_register() == T4, "klass_reg must in T4");
    2.23  #else
    2.24 -  //FIXME. in A4? aoqi
    2.25    assert(_klass_reg->as_register() == A4, "klass_reg must in A4");
    2.26  #endif
    2.27  
    2.28 @@ -245,7 +243,6 @@
    2.29    } else {
    2.30      enter_id = Runtime1::monitorenter_nofpu_id;
    2.31    }
    2.32 -  //__ call(RuntimeAddress(Runtime1::entry_for(enter_id)));
    2.33    __ call(Runtime1::entry_for(enter_id), relocInfo::runtime_call_type);
    2.34    __ delayed()->nop();
    2.35    ce->add_call_info_here(_info);
    2.36 @@ -269,7 +266,6 @@
    2.37    } else {
    2.38      exit_id = Runtime1::monitorexit_nofpu_id;
    2.39    }
    2.40 -  //__ call(RuntimeAddress(Runtime1::entry_for(exit_id)));
    2.41    __ call(Runtime1::entry_for(exit_id), relocInfo::runtime_call_type);
    2.42    __ delayed()->nop();
    2.43  
    2.44 @@ -350,7 +346,7 @@
    2.45      address start = __ pc();
    2.46      for ( int i = 0; i < _bytes_to_copy; i+=4) {
    2.47        __ emit_int32(*(int*)(_pc_start + i));
    2.48 -      //make the site look like a nop, @jerome
    2.49 +      //make the site look like a nop
    2.50        *(int*)(_pc_start + i)=0;
    2.51      }
    2.52      while ((intx)__ pc() - (intx)start < NativeCall::instruction_size) {

     3.1 --- a/src/cpu/mips/vm/c1_FrameMap_mips.cpp	Mon Sep 03 14:27:42 2018 +0800
     3.2 +++ b/src/cpu/mips/vm/c1_FrameMap_mips.cpp	Tue Sep 04 21:25:12 2018 +0800
     3.3 @@ -224,7 +224,7 @@
     3.4    return is_caller_save_register(reg->as_register());
     3.5  }
     3.6  
     3.7 -//FIXME, why always ture? @jerome
     3.8 +//FIXME, why always ture?
     3.9  bool FrameMap::is_caller_save_register (Register r) {
    3.10    //return (r>=V0 && r<=T7) || (r==T8) || (r==T9);
    3.11    //return ((r>=V0) && (r<=T7));

     4.1 --- a/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp	Mon Sep 03 14:27:42 2018 +0800
     4.2 +++ b/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp	Tue Sep 04 21:25:12 2018 +0800
     4.3 @@ -341,12 +341,10 @@
     4.4    RelocationHolder rspec = oop_Relocation::spec(oop_index);
     4.5    __ relocate(rspec);
     4.6  #ifndef _LP64
     4.7 -//by_css
     4.8    __ lui(reg, Assembler::split_high((int)o));
     4.9    __ addiu(reg, reg, Assembler::split_low((int)o));
    4.10  #else
    4.11 -//li may not pass NativeMovConstReg::verify. see nativeMovConstReg_at(pc_start()); in PatchingStub::install. by aoqi
    4.12 -//  __ li48(reg, (long)o);
    4.13 +//li may not pass NativeMovConstReg::verify. see nativeMovConstReg_at(pc_start()); in PatchingStub::install.
    4.14    __ li48(reg, (long)o);
    4.15  #endif
    4.16    // patching_epilog(patch, LIR_Op1::patch_normal, noreg, info);
    4.17 @@ -530,7 +528,6 @@
    4.18    // Now T3 is the address of the first char in second string(T1)
    4.19  
    4.20  #ifndef _LP64
    4.21 -//by_css
    4.22    // compute minimum length (in T4) and difference of lengths (V0)
    4.23    Label L;
    4.24    __ lw (T4, Address(T0, java_lang_String::count_offset_in_bytes()));
    4.25 @@ -612,7 +609,6 @@
    4.26    // Pop the stack before the safepoint code
    4.27    __ remove_frame(initial_frame_size_in_bytes());
    4.28  #ifndef _LP64
    4.29 -  //by aoqi
    4.30    __ lui(AT, Assembler::split_high((intptr_t)os::get_polling_page()
    4.31    + (SafepointPollOffset % os::vm_page_size())));
    4.32    __ relocate(relocInfo::poll_return_type);
    4.33 @@ -620,7 +616,6 @@
    4.34    + (SafepointPollOffset % os::vm_page_size())));
    4.35  #else
    4.36    #ifndef OPT_SAFEPOINT
    4.37 -  // do not know how to handle relocate yet. do not know li or li64 should be used neither. by aoqi. 20111207 FIXME.
    4.38    __ li48(AT, (intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()));
    4.39    __ relocate(relocInfo::poll_return_type);
    4.40    __ lw(AT, AT, 0);
    4.41 @@ -635,25 +630,21 @@
    4.42    __ delayed()->nop();
    4.43  }
    4.44  
    4.45 -//read protect mem to R0 won't cause the exception only in godson-2e, So I modify R0 to AT .@jerome,11/25,2006
    4.46 +//read protect mem to R0 won't cause the exception only in godson-2e, So I modify R0 to AT.
    4.47  int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
    4.48    assert(info != NULL, "info must not be null for safepoint poll");
    4.49    int offset = __ offset();
    4.50    Register r = tmp->as_register();
    4.51  #ifndef _LP64
    4.52 -//by aoqi
    4.53    __ lui(r, Assembler::split_high((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));
    4.54    add_debug_info_for_branch(info);
    4.55    __ relocate(relocInfo::poll_type);
    4.56    __ lw(AT, r, Assembler::split_low((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));
    4.57  #else
    4.58    #ifndef OPT_SAFEPOINT
    4.59 -  // do not know how to handle relocate yet. do not know li or li64 should be used neither. by aoqi. 20111207 FIXME.
    4.60 -  //__ lui(r, Assembler::split_high((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));
    4.61    __ li48(r, (intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()));
    4.62    add_debug_info_for_branch(info);
    4.63    __ relocate(relocInfo::poll_type);
    4.64 -  //__ lw(AT, r, Assembler::split_low((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));
    4.65    __ lw(AT, r, 0);
    4.66    #else
    4.67    __ lui(r, Assembler::split_high((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));
    4.68 @@ -745,7 +736,6 @@
    4.69        if (dest->is_single_fpu()) {
    4.70          __ relocate(relocInfo::internal_pc_type);
    4.71  #ifndef _LP64
    4.72 -        //by_css
    4.73          __ lui(AT, Assembler::split_high((int)const_addr));
    4.74          __ addiu(AT, AT, Assembler::split_low((int)const_addr));
    4.75  #else
    4.76 @@ -759,7 +749,6 @@
    4.77  
    4.78          __ relocate(relocInfo::internal_pc_type);
    4.79  #ifndef _LP64
    4.80 -        //by_css
    4.81          __ lui(AT, Assembler::split_high((int)const_addr));
    4.82          __ addiu(AT, AT, Assembler::split_low((int)const_addr));
    4.83  #else
    4.84 @@ -777,7 +766,6 @@
    4.85        if (dest->is_double_fpu()) {
    4.86          __ relocate(relocInfo::internal_pc_type);
    4.87  #ifndef _LP64
    4.88 -        //by_css
    4.89          __ lui(AT, Assembler::split_high((int)const_addr));
    4.90          __ addiu(AT, AT, Assembler::split_low((int)const_addr));
    4.91          __ lwc1(dest->as_double_reg(), AT, 0);
    4.92 @@ -792,7 +780,6 @@
    4.93  
    4.94          __ relocate(relocInfo::internal_pc_type);
    4.95  #ifndef _LP64
    4.96 -        //by_css
    4.97          __ lui(AT, Assembler::split_high((int)const_addr));
    4.98          __ addiu(AT, AT, Assembler::split_low((int)const_addr));
    4.99          __ lw(dest->as_register_lo(), AT, 0);
   4.100 @@ -838,7 +825,6 @@
   4.101          RelocationHolder rspec = oop_Relocation::spec(oop_index);
   4.102          __ relocate(rspec);
   4.103  #ifndef _LP64
   4.104 -        //by_css
   4.105          __ lui(AT, Assembler::split_high((int)c->as_jobject()));
   4.106          __ addiu(AT, AT, Assembler::split_low((int)c->as_jobject()));
   4.107  #else
   4.108 @@ -971,7 +957,6 @@
   4.109      // int to int moves
   4.110      if (dest->is_single_cpu()) {
   4.111  #ifdef _LP64
   4.112 -//FIXME aoqi: copy from x86
   4.113        if (src->type() == T_LONG) {
   4.114          // Can do LONG -> OBJECT
   4.115          move_regs(src->as_register_lo(), dest->as_register());
   4.116 @@ -2482,13 +2467,11 @@
   4.117  
   4.118      } else {
   4.119        if (opr2->is_address()) {
   4.120 -        //FIXME. aoqi lw or ld_ptr?
   4.121          if (op->type() == T_INT)
   4.122            __ lw(AT, rebase_Address(opr2->pointer()->as_address()));
   4.123          else
   4.124            __ ld_ptr(AT, rebase_Address(opr2->pointer()->as_address()));
   4.125        } else if (opr2->is_stack()) {
   4.126 -        //FIXME. aoqi
   4.127          __ ld_ptr(AT, frame_map()->address_for_slot(opr2->single_stack_ix()));
   4.128        } else {
   4.129          ShouldNotReachHere();
   4.130 @@ -4017,7 +4000,6 @@
   4.131  
   4.132    case lir_mul:
   4.133  #ifndef _LP64
   4.134 -    //by aoqi
   4.135      __ mult(lreg, rreg);
   4.136  #else
   4.137      __ dmult(lreg, rreg);
   4.138 @@ -4081,7 +4063,6 @@
   4.139    case lir_mul:
   4.140      __ move(AT, c);
   4.141  #ifndef _LP64
   4.142 -    //by aoqi
   4.143      __ mult(lreg, AT);
   4.144  #else
   4.145      __ dmult(lreg, AT);
   4.146 @@ -4184,7 +4165,6 @@
   4.147      switch (code) {
   4.148        case lir_add:
   4.149  #ifndef _LP64
   4.150 -  //by aoqi
   4.151    __ addu(dst_lo, op1_lo, op2_lo);
   4.152    __ sltu(AT, dst_lo, op2_lo);
   4.153    __ addu(dst_hi, op1_hi, op2_hi);
   4.154 @@ -4196,7 +4176,6 @@
   4.155  
   4.156        case lir_sub:
   4.157  #ifndef _LP64
   4.158 -  //by aoqi
   4.159    __ subu(dst_lo, op1_lo, op2_lo);
   4.160    __ sltu(AT, op1_lo, dst_lo);
   4.161    __ subu(dst_hi, op1_hi, op2_hi);
   4.162 @@ -4210,7 +4189,6 @@
   4.163    {
   4.164  
   4.165  #ifndef _LP64
   4.166 -    //by aoqi
   4.167      Label zero, quick, done;
   4.168      //zero?
   4.169      __ orr(AT, op2_lo, op1_lo);
   4.170 @@ -4333,7 +4311,6 @@
   4.171        case lir_mul:
   4.172        case lir_mul_strictfp:
   4.173    // i dont think we need special handling of this. FIXME
   4.174 -  // by yjl 9/13/2005
   4.175    __ mul_d(res, lreg, rreg);
   4.176    break;
   4.177        case lir_div:
   4.178 @@ -4363,7 +4340,6 @@
   4.179        switch (code) {
   4.180    case lir_add:
   4.181  #ifndef _LP64
   4.182 -    //by aoqi
   4.183      __ lw(AT, laddr);
   4.184      __ add(AT, AT, rreg);
   4.185      __ sw(AT, laddr);
   4.186 @@ -4375,7 +4351,6 @@
   4.187      break;
   4.188    case lir_sub:
   4.189  #ifndef _LP64
   4.190 -    //by aoqi
   4.191      __ lw(AT, laddr);
   4.192      __ sub(AT,AT,rreg);
   4.193      __ sw(AT, laddr);
   4.194 @@ -4427,7 +4402,6 @@
   4.195  }
   4.196  
   4.197  void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op *op) {
   4.198 -//FIXME,lir_log, lir_log10,lir_abs,lir_sqrt,so many new lir instruction  @jerome
   4.199  if (value->is_double_fpu()) {
   4.200     // assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
   4.201      switch(code) {
   4.202 @@ -4586,7 +4560,6 @@
   4.203    }
   4.204  }
   4.205  
   4.206 -//done here. aoqi. 12-12 22:25
   4.207  // we assume that eax and edx can be overwritten
   4.208  void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
   4.209  
   4.210 @@ -5254,7 +5227,6 @@
   4.211    RelocationHolder rspec = oop_Relocation::spec(oop_index);
   4.212    __ relocate(rspec);
   4.213  #ifndef _LP64
   4.214 -  //by_css
   4.215    __ lui(AT, Assembler::split_high((int)o));
   4.216    __ addiu(AT, AT, Assembler::split_low((int)o));
   4.217  #else
   4.218 @@ -6021,7 +5993,6 @@
   4.219      // for classes that are not loaded yet, i.e., they will be
   4.220      // never GC'd
   4.221  #ifndef _LP64
   4.222 -//by_css
   4.223      __ lui(reg, Assembler::split_high((int)o));
   4.224      __ addiu(reg, reg, Assembler::split_low((int)o));
   4.225  #else
   4.226 @@ -6033,7 +6004,6 @@
   4.227      RelocationHolder rspec = oop_Relocation::spec(oop_index);
   4.228      __ relocate(rspec);
   4.229  #ifndef _LP64
   4.230 -//by_css
   4.231      __ lui(reg, Assembler::split_high((int)o));
   4.232      __ addiu(reg, reg, Assembler::split_low((int)o));
   4.233  #else

     5.1 --- a/src/cpu/mips/vm/c1_LIRGenerator_mips.cpp	Mon Sep 03 14:27:42 2018 +0800
     5.2 +++ b/src/cpu/mips/vm/c1_LIRGenerator_mips.cpp	Tue Sep 04 21:25:12 2018 +0800
     5.3 @@ -1248,7 +1248,7 @@
     5.4  
     5.5  LIR_Opr LIRGenerator::getThreadPointer() {
     5.6  #ifdef _LP64
     5.7 -  //FIXME, does as_pointer need to be implemented? or 64bit can use one register. by aoqi
     5.8 +  //FIXME, does as_pointer need to be implemented? or 64bit can use one register.
     5.9    //return FrameMap::as_pointer_opr(r15_thread);
    5.10    LIR_Opr result = new_register(T_LONG);
    5.11    __ get_thread(result);

     6.1 --- a/src/cpu/mips/vm/c1_Runtime1_mips.cpp	Mon Sep 03 14:27:42 2018 +0800
     6.2 +++ b/src/cpu/mips/vm/c1_Runtime1_mips.cpp	Tue Sep 04 21:25:12 2018 +0800
     6.3 @@ -119,7 +119,7 @@
     6.4    super_pop(V0);
     6.5  #endif
     6.6    // discard thread and arguments
     6.7 -  ld_ptr(SP, thread, in_bytes(JavaThread::last_Java_sp_offset())); //by yyq
     6.8 +  ld_ptr(SP, thread, in_bytes(JavaThread::last_Java_sp_offset()));
     6.9    reset_last_Java_frame(thread, true);
    6.10    // check for pending exceptions
    6.11    {
    6.12 @@ -329,7 +329,6 @@
    6.13  // expensive.  The deopt blob is the only thing which needs to
    6.14  // describe FPU registers.  In all other cases it should be sufficient
    6.15  // to simply save their current value.
    6.16 -//FIXME, I have no idea which register should be saved . @jerome
    6.17  static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
    6.18                                  bool save_fpu_registers = true, bool describe_fpu_registers = false) {
    6.19  
    6.20 @@ -413,7 +412,6 @@
    6.21    return map;
    6.22  }
    6.23  
    6.24 -//FIXME, Is it enough to save this registers  by yyq
    6.25  static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
    6.26                                     bool save_fpu_registers = true,
    6.27                                     bool describe_fpu_registers = false) {

     7.1 --- a/src/cpu/mips/vm/c2_globals_mips.hpp	Mon Sep 03 14:27:42 2018 +0800
     7.2 +++ b/src/cpu/mips/vm/c2_globals_mips.hpp	Tue Sep 04 21:25:12 2018 +0800
     7.3 @@ -44,7 +44,7 @@
     7.4  #else
     7.5  define_pd_global(bool, ProfileInterpreter,           true);
     7.6  #endif // CC_INTERP
     7.7 -define_pd_global(bool, TieredCompilation,            false);   /* 2013.10.15 Jin: Disable C1 in server JIT */
     7.8 +define_pd_global(bool, TieredCompilation,            false);   // Disable C1 in server JIT
     7.9  define_pd_global(intx, CompileThreshold,             10000);
    7.10  define_pd_global(intx, BackEdgeThreshold,            100000);
    7.11  

     8.1 --- a/src/cpu/mips/vm/interpreter_mips_64.cpp	Mon Sep 03 14:27:42 2018 +0800
     8.2 +++ b/src/cpu/mips/vm/interpreter_mips_64.cpp	Tue Sep 04 21:25:12 2018 +0800
     8.3 @@ -124,7 +124,7 @@
     8.4  
     8.5    // Rmethod: methodOop
     8.6    // V0: scratrch
     8.7 -  // esi: send 's sp, should we use Rsender @jerome
     8.8 +  // esi: send 's sp, should we use Rsender
     8.9  
    8.10    if (!InlineIntrinsics) return NULL; // Generate a vanilla entry
    8.11  
    8.12 @@ -216,7 +216,7 @@
    8.13    // throw exception
    8.14    // adjust stack to what a normal return would do
    8.15  
    8.16 -  __ move(SP,Rsender); //FIXME, why jvm6 add this @jerome
    8.17 +  __ move(SP, Rsender);
    8.18    __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_AbstractMethodError));
    8.19    // the call_VM checks for exception, so we should never return here.
    8.20    __ should_not_reach_here();

     9.1 --- a/src/cpu/mips/vm/macroAssembler_mips.cpp	Mon Sep 03 14:27:42 2018 +0800
     9.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.cpp	Tue Sep 04 21:25:12 2018 +0800
     9.3 @@ -272,7 +272,7 @@
     9.4  void MacroAssembler::beq_far(Register rs, Register rt, address entry) {
     9.5    u_char * cur_pc = pc();
     9.6  
     9.7 -  /* Jin: Near/Far jump */
     9.8 +  // Near/Far jump
     9.9    if(is_simm16((entry - pc() - 4) / 4)) {
    9.10      Assembler::beq(rs, rt, offset(entry));
    9.11    } else {
    9.12 @@ -308,7 +308,7 @@
    9.13  void MacroAssembler::bne_far(Register rs, Register rt, address entry) {
    9.14    u_char * cur_pc = pc();
    9.15  
    9.16 -  /* Jin: Near/Far jump */
    9.17 +  //Near/Far jump
    9.18    if(is_simm16((entry - pc() - 4) / 4)) {
    9.19      Assembler::bne(rs, rt, offset(entry));
    9.20    } else {
    9.21 @@ -417,11 +417,11 @@
    9.22  void MacroAssembler::b_far(address entry) {
    9.23    u_char * cur_pc = pc();
    9.24  
    9.25 -  /* Jin: Near/Far jump */
    9.26 +  // Near/Far jump
    9.27    if(is_simm16((entry - pc() - 4) / 4)) {
    9.28      b(offset(entry));
    9.29    } else {
    9.30 -    /* address must be bounded */
    9.31 +    // address must be bounded
    9.32      move(AT, RA);
    9.33      emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
    9.34      nop();
    9.35 @@ -974,7 +974,7 @@
    9.36  void MacroAssembler::stop(const char* msg) {
    9.37    li(A0, (long)msg);
    9.38  #ifndef _LP64
    9.39 -  //reserver space for argument. added by yjl 7/10/2005
    9.40 +  //reserver space for argument.
    9.41    addiu(SP, SP, - 1 * wordSize);
    9.42  #endif
    9.43    call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
    9.44 @@ -1817,7 +1817,6 @@
    9.45  
    9.46    if (var_size_in_bytes == NOREG) {
    9.47      // i dont think we need move con_size_in_bytes to a register first.
    9.48 -    // by yjl 8/17/2005
    9.49      assert(is_simm16(con_size_in_bytes), "fixme by moving imm to a register first");
    9.50      addi(end, obj, con_size_in_bytes);
    9.51    } else {
    9.52 @@ -1833,11 +1832,6 @@
    9.53    // update the tlab top pointer
    9.54    st_ptr(end, thread, in_bytes(JavaThread::tlab_top_offset()));
    9.55  
    9.56 -  // recover var_size_in_bytes if necessary
    9.57 -  /*if (var_size_in_bytes == end) {
    9.58 -    sub(var_size_in_bytes, end, obj);
    9.59 -    }*/
    9.60 -
    9.61    verify_tlab(t1, t2);
    9.62  }
    9.63  
    9.64 @@ -1845,7 +1839,7 @@
    9.65  void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
    9.66                                     Register t1, Register t2, Label& slow_case) {
    9.67    assert_different_registers(obj, var_size_in_bytes, t1, AT);
    9.68 -  if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { //by yyq
    9.69 +  if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
    9.70      // No allocation in the shared eden.
    9.71      b_far(slow_case);
    9.72      delayed()->nop();
    9.73 @@ -1890,7 +1884,7 @@
    9.74  
    9.75      // if someone beat us on the allocation, try again, otherwise continue
    9.76      cmpxchg(end, heap_top, obj);
    9.77 -    beq_far(AT, R0, retry);    //by yyq
    9.78 +    beq_far(AT, R0, retry);
    9.79      delayed()->nop();
    9.80    }
    9.81  }
    9.82 @@ -1905,7 +1899,7 @@
    9.83    assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ T2, A4);
    9.84    Label do_refill, discard_tlab;
    9.85  
    9.86 -  if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { //by yyq
    9.87 +  if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
    9.88      // No allocation in the shared eden.
    9.89      b(slow_case);
    9.90      delayed()->nop();
    9.91 @@ -2047,11 +2041,9 @@
    9.92  // the x86 version is to clumsy, i dont think we need that fuss. maybe i'm wrong, FIXME
    9.93  // must get argument(a double) in F12/F13
    9.94  //void MacroAssembler::trigfunc(char trig, bool preserve_cpu_regs, int num_fpu_regs_in_use) {
    9.95 -//We need to preseve the register which maybe modified during the Call @Jerome
    9.96 +//We need to preseve the register which maybe modified during the Call
    9.97  void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
    9.98  //save all modified register here
    9.99 -//  if (preserve_cpu_regs) {
   9.100 -//  }
   9.101  //FIXME, in the disassembly of tirgfunc, only used V0,V1,T9, SP,RA,so we ony save V0,V1,T9
   9.102    pushad();
   9.103  //we should preserve the stack space before we call
   9.104 @@ -2076,8 +2068,6 @@
   9.105  
   9.106    addi(SP, SP, wordSize * 2);
   9.107    popad();
   9.108 -//  if (preserve_cpu_regs) {
   9.109 -//  }
   9.110  }
   9.111  
   9.112  #ifdef _LP64
   9.113 @@ -2090,8 +2080,6 @@
   9.114      ori(rd, R0, julong(imm) >> 16);
   9.115      dsll(rd, rd, 16);
   9.116      ori(rd, rd, split_low(imm));
   9.117 -  //aoqi_test
   9.118 -  //} else if ((imm > 0) && ((imm >> 48) == 0)) {
   9.119    } else if ((imm > 0) && is_simm16(imm >> 32)) {
   9.120      /* A 48-bit address */
   9.121      li48(rd, imm);
   9.122 @@ -2107,7 +2095,7 @@
   9.123  
   9.124  void MacroAssembler::li32(Register reg, int imm) {
   9.125    if (is_simm16(imm)) {
   9.126 -    /* Jin: for imm < 0, we should use addi instead of addiu.
   9.127 +    /* for imm < 0, we should use addi instead of addiu.
   9.128       *
   9.129       *  java.lang.StringCoding$StringDecoder.decode(jobject, jint, jint)
   9.130       *
   9.131 @@ -2628,11 +2616,11 @@
   9.132  
   9.133  /* do 32-bit CAS using MIPS64 lld/scd
   9.134  
   9.135 -  Jin: cas_int should only compare 32-bits of the memory value.
   9.136 -       However, lld/scd will do 64-bit operation, which violates the intention of cas_int.
   9.137 -       To simulate a 32-bit atomic operation, the value loaded with LLD should be split into
   9.138 -       tow halves, and only the low-32 bits is compared. If equals, the low-32 bits of newval,
   9.139 -       plus the high-32 bits or memory value, are stored togethor with SCD.
   9.140 +  cas_int should only compare 32-bits of the memory value.
   9.141 +  However, lld/scd will do 64-bit operation, which violates the intention of cas_int.
   9.142 +  To simulate a 32-bit atomic operation, the value loaded with LLD should be split into
   9.143 +  tow halves, and only the low-32 bits is compared. If equals, the low-32 bits of newval,
   9.144 +  plus the high-32 bits or memory value, are stored togethor with SCD.
   9.145  
   9.146  Example:
   9.147  
   9.148 @@ -2673,7 +2661,7 @@
   9.149  */
   9.150  
   9.151  void MacroAssembler::cmpxchg32(Register x_reg, Address dest, Register c_reg) {
   9.152 -  /* 2012/11/11 Jin: MIPS64 can use ll/sc for 32-bit atomic memory access */
   9.153 +  /* MIPS64 can use ll/sc for 32-bit atomic memory access */
   9.154    Label done, again, nequal;
   9.155  
   9.156    bind(again);
   9.157 @@ -3203,7 +3191,7 @@
   9.158  Register caller_saved_registers[] = {AT, V0, V1, A0, A1, A2, A3, A4, A5, A6, A7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
   9.159  Register caller_saved_registers_except_v0[] = {AT, V1, A0, A1, A2, A3, A4, A5, A6, A7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
   9.160  
   9.161 -/* FIXME: Jin: In MIPS64, F0~23 are all caller-saved registers */
   9.162 +//In MIPS64, F0~23 are all caller-saved registers
   9.163  FloatRegister caller_saved_fpu_registers[] = {F0, F12, F13};
   9.164  #else
   9.165  Register caller_saved_registers[] = {AT, V0, V1, A0, A1, A2, A3, T4, T5, T6, T7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
   9.166 @@ -3928,7 +3916,7 @@
   9.167    // not change flags (only scas instruction which is repeated sets flags).
   9.168    // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
   9.169  
   9.170 -  /* 2013/4/3 Jin: OpenJDK8 never compresses klass pointers in secondary-super array. */
   9.171 +  // OpenJDK8 never compresses klass pointers in secondary-super array.
   9.172    Label Loop, subtype;
   9.173    bind(Loop);
   9.174    beq(temp2_reg, R0, *L_failure);
   9.175 @@ -3980,7 +3968,7 @@
   9.176      scale_reg    = arg_slot.as_register();
   9.177      scale_factor = Address::times_8;
   9.178    }
   9.179 -  // 2014/07/31 Fu: We don't push RA on stack in prepare_invoke.
   9.180 +  // We don't push RA on stack in prepare_invoke.
   9.181    //  offset += wordSize;           // return PC is on stack
   9.182    if(scale_reg==NOREG) return Address(SP, offset);
   9.183    else {

    10.1 --- a/src/cpu/mips/vm/mips_64.ad	Mon Sep 03 14:27:42 2018 +0800
    10.2 +++ b/src/cpu/mips/vm/mips_64.ad	Tue Sep 04 21:25:12 2018 +0800
    10.3 @@ -380,8 +380,7 @@
    10.4  
    10.5  
    10.6  // Floating point registers.
    10.7 -// 2012/8/23 Fu: F30/F31 are used as temporary registers in D2I
    10.8 -// 2016/12/1 aoqi: F31 are not used as temporary registers in D2I
    10.9 +// F31 are not used as temporary registers in D2I
   10.10  reg_class flt_reg( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17 F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F31);
   10.11  reg_class dbl_reg( F0, F0_H,
   10.12                     F1, F1_H,
   10.13 @@ -442,7 +441,6 @@
   10.14    // Branches are even more expensive.
   10.15    int_def BRANCH_COST       (    300, DEFAULT_COST * 3);
   10.16    // we use jr instruction to construct call, so more expensive
   10.17 -  // by yjl 2/28/2006
   10.18    int_def CALL_COST         (    500, DEFAULT_COST * 5);
   10.19  /*
   10.20          int_def EQUAL             (   1, 1  );
   10.21 @@ -1383,18 +1381,19 @@
   10.22  
   10.23    assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
   10.24  
   10.25 -  st->print("daddiu   SP, SP, %d # Rlease stack @ MachEpilogNode",framesize);
   10.26 -  st->cr(); st->print("\t");
   10.27 +  st->print_cr("daddiu   SP, SP, %d # Rlease stack @ MachEpilogNode", framesize);
   10.28 +  st->print("\t");
   10.29    if (UseLoongsonISA) {
   10.30 -    st->print("gslq  RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
   10.31 +    st->print_cr("gslq  RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
   10.32    } else {
   10.33 -    st->print("ld    RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
   10.34 -    st->cr(); st->print("\t");
   10.35 -    st->print("ld    FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
   10.36 +    st->print_cr("ld    RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
   10.37 +    st->print("\t");
   10.38 +    st->print_cr("ld    FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
   10.39    }
   10.40  
   10.41    if( do_polling() && C->is_method_compilation() ) {
   10.42 -    st->print("Poll Safepoint # MachEpilogNode");
   10.43 +    st->print("\t");
   10.44 +    st->print_cr("Poll Safepoint # MachEpilogNode");
   10.45    }
   10.46  }
   10.47  #endif
   10.48 @@ -1634,7 +1633,7 @@
   10.49    }
   10.50    __ daddiu(FP, SP, -wordSize*2);
   10.51    __ daddiu(SP, SP, -framesize);
   10.52 -  __ nop(); /* 2013.10.22 Jin: Make enough room for patch_verified_entry() */
   10.53 +  __ nop(); // Make enough room for patch_verified_entry()
   10.54    __ nop();
   10.55  
   10.56    C->set_frame_complete(cbuf.insts_size());
   10.57 @@ -3348,18 +3347,18 @@
   10.58      Register tmp    = T9;
   10.59      Label miss;
   10.60  
   10.61 -    /* 2012/9/28 Jin: result may be the same as sub
   10.62 -     *    47c   B40: #    B21 B41 <- B20  Freq: 0.155379
   10.63 -     *    47c     partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
   10.64 -     *    4bc     mov   S2, NULL #@loadConP
   10.65 -     *    4c0     beq   S1, S2, B21 #@branchConP  P=0.999999 C=-1.000000
   10.66 -     */
   10.67 +    // result may be the same as sub
   10.68 +    //    47c   B40: #    B21 B41 <- B20  Freq: 0.155379
   10.69 +    //    47c     partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
   10.70 +    //    4bc     mov   S2, NULL #@loadConP
   10.71 +    //    4c0     beq   S1, S2, B21 #@branchConP  P=0.999999 C=-1.000000
   10.72 +    //
   10.73      MacroAssembler _masm(&cbuf);
   10.74      Label done;
   10.75      __ check_klass_subtype_slow_path(sub, super, length, tmp,
   10.76          NULL, &miss,
   10.77          /*set_cond_codes:*/ true);
   10.78 -    /* 2013/7/22 Jin: Refer to X86_64's RDI */
   10.79 +    // Refer to X86_64's RDI
   10.80      __ move(result, 0);
   10.81      __ b(done);
   10.82      __ delayed()->nop();
   10.83 @@ -3431,7 +3430,7 @@
   10.84    // These two registers define part of the calling convention
   10.85    // between compiled code and the interpreter.
   10.86    // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention
   10.87 -  // for more information. by yjl 3/16/2006
   10.88 +  // for more information.
   10.89  
   10.90    inline_cache_reg(T1);                // Inline Cache Register
   10.91    interpreter_method_oop_reg(S3);      // Method Oop Register when calling interpreter
   10.92 @@ -3488,7 +3487,7 @@
   10.93  
   10.94  
   10.95    // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing)
   10.96 -  // StartNode::calling_convention call this. by yjl 3/16/2006
   10.97 +  // StartNode::calling_convention call this.
   10.98    calling_convention %{
   10.99      SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
  10.100    %}
  10.101 @@ -3504,7 +3503,7 @@
  10.102    // automatically biased by the preserve_stack_slots field above.
  10.103  
  10.104  
  10.105 -  // SEE CallRuntimeNode::calling_convention for more information. by yjl 3/16/2006
  10.106 +  // SEE CallRuntimeNode::calling_convention for more information.
  10.107    c_calling_convention %{
  10.108     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
  10.109    %}
  10.110 @@ -3512,7 +3511,7 @@
  10.111  
  10.112    // Location of C & interpreter return values
  10.113    // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR.
  10.114 -  // SEE Matcher::match. by yjl 3/16/2006
  10.115 +  // SEE Matcher::match.
  10.116    c_return_value %{
  10.117      assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
  10.118                                 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
  10.119 @@ -3523,7 +3522,7 @@
  10.120  
  10.121    // Location of return values
  10.122    // register(s) contain(s) return value for Op_StartC2I and Op_Start.
  10.123 -  // SEE Matcher::match. by yjl 3/16/2006
  10.124 +  // SEE Matcher::match.
  10.125  
  10.126    return_value %{
  10.127      assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
  10.128 @@ -4597,6 +4596,7 @@
  10.129  operand mRegP() %{
  10.130    constraint(ALLOC_IN_RC(p_reg));
  10.131    match(RegP);
  10.132 +  match(a0_RegP);
  10.133  
  10.134    format %{  %}
  10.135    interface(REG_INTER);
  10.136 @@ -6001,7 +6001,7 @@
  10.137  instruct loadL_unaligned(mRegL dst, memory mem) %{
  10.138    match(Set dst (LoadL_unaligned mem));
  10.139  
  10.140 -  // FIXME: Jin: Need more effective ldl/ldr
  10.141 +  // FIXME: Need more effective ldl/ldr
  10.142    ins_cost(450);
  10.143    format %{ "ld    $dst, $mem   #@loadL_unaligned\n\t" %}
  10.144    ins_encode(load_L_enc(dst, mem));
  10.145 @@ -6540,7 +6540,7 @@
  10.146      Register target = $jump_target$$Register;
  10.147      Register    oop = $method_oop$$Register;
  10.148  
  10.149 -    /* 2012/10/12 Jin: RA will be used in generate_forward_exception() */
  10.150 +    // RA will be used in generate_forward_exception()
  10.151      __ push(RA);
  10.152  
  10.153      __ move(S3, oop);
  10.154 @@ -6561,24 +6561,24 @@
  10.155    // use the following format syntax
  10.156    format %{ "# exception oop is in A0; no code emitted @CreateException" %}
  10.157    ins_encode %{
  10.158 -    /* Jin: X86 leaves this function empty */
  10.159 -    __ block_comment("CreateException is empty in X86/MIPS");
  10.160 +    // X86 leaves this function empty
  10.161 +    __ block_comment("CreateException is empty in MIPS");
  10.162    %}
  10.163    ins_pipe( empty );
  10.164  //  ins_pipe( pipe_jump );
  10.165  %}
  10.166  
  10.167  
  10.168 -/* 2012/9/14 Jin: The mechanism of exception handling is clear now.
  10.169 +/* The mechanism of exception handling is clear now.
  10.170  
  10.171  - Common try/catch:
  10.172 - 2012/9/14 Jin: [stubGenerator_mips.cpp] generate_forward_exception()
  10.173 -                    |- V0, V1 are created
  10.174 -                    |- T9 <= SharedRuntime::exception_handler_for_return_address
  10.175 -                    `- jr T9
  10.176 -                         `- the caller's exception_handler
  10.177 -                               `- jr OptoRuntime::exception_blob
  10.178 -                                      `- here
  10.179 +  [stubGenerator_mips.cpp] generate_forward_exception()
  10.180 +      |- V0, V1 are created
  10.181 +      |- T9 <= SharedRuntime::exception_handler_for_return_address
  10.182 +      `- jr T9
  10.183 +           `- the caller's exception_handler
  10.184 +                 `- jr OptoRuntime::exception_blob
  10.185 +                        `- here
  10.186  - Rethrow(e.g. 'unwind'):
  10.187    * The callee:
  10.188       |- an exception is triggered during execution
  10.189 @@ -7536,7 +7536,7 @@
  10.190          __ bc1t_long(*L);
  10.191          break;
  10.192        case 0x02: //not_equal
  10.193 -        //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
  10.194 +        // c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
  10.195          __ c_eq_d(reg_op1, reg_op2);
  10.196          __ bc1f_long(*L);
  10.197          break;
  10.198 @@ -8751,7 +8751,7 @@
  10.199            __ bc1t((int)0);
  10.200          break;
  10.201        case 0x02: //not_equal
  10.202 -        //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
  10.203 +        // c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
  10.204          __ c_eq_d(reg_op1, reg_op2);
  10.205          if (&L)
  10.206            __ bc1f(L);
  10.207 @@ -9659,7 +9659,7 @@
  10.208          __ movt(dst, src);
  10.209          break;
  10.210        case 0x02: //not_equal
  10.211 -//2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
  10.212 +      // See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
  10.213          __ c_eq_d(reg_op1, reg_op2);
  10.214          __ movf(dst, src);
  10.215          break;
  10.216 @@ -11132,8 +11132,8 @@
  10.217       Register src2 = $src2$$Register;
  10.218       Register dst  = $dst$$Register;
  10.219  
  10.220 -    /* 2012/4/21 Jin: In MIPS, div does not cause exception.
  10.221 -       We must trap an exception manually. */
  10.222 +    // In MIPS, div does not cause exception.
  10.223 +    //   We must trap an exception manually.
  10.224      __ teq(R0, src2, 0x7);
  10.225  
  10.226      if (UseLoongsonISA) {
  10.227 @@ -12706,12 +12706,12 @@
  10.228  
  10.229      __ mov_s(F12, fval);
  10.230  
  10.231 -    /* 2014/01/08 Fu : This bug was found when running ezDS's control-panel.
  10.232 -     *    J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
  10.233 -     *
  10.234 -     * An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
  10.235 -     * V0 is corrupted during call_VM_leaf(), and should be preserved.
  10.236 -     */
  10.237 +    //This bug was found when running ezDS's control-panel.
  10.238 +    //    J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
  10.239 +    //
  10.240 +    // An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
  10.241 +    // V0 is corrupted during call_VM_leaf(), and should be preserved.
  10.242 +    //
  10.243      __ push(fval);
  10.244      if(dreg != V0) {
  10.245        __ push(V0);
  10.246 @@ -13173,10 +13173,10 @@
  10.247    ins_encode %{
  10.248      Register target = $jump_target$$Register;
  10.249  
  10.250 -    /* 2012/9/14 Jin: V0, V1 are indicated in:
  10.251 -     *      [stubGenerator_mips.cpp] generate_forward_exception()
  10.252 -     *      [runtime_mips.cpp] OptoRuntime::generate_exception_blob()
  10.253 -     */
  10.254 +    // V0, V1 are indicated in:
  10.255 +    //     [stubGenerator_mips.cpp] generate_forward_exception()
  10.256 +    //     [runtime_mips.cpp] OptoRuntime::generate_exception_blob()
  10.257 +    //
  10.258      Register oop  = $ex_oop$$Register;
  10.259      Register exception_oop = V0;
  10.260      Register exception_pc = V1;
  10.261 @@ -13214,7 +13214,7 @@
  10.262    effect(USE meth);
  10.263  
  10.264    ins_cost(300);
  10.265 -  format %{"MOV IC_Klass, (oop)-1\n\t"
  10.266 +  format %{"MOV IC_Klass, #Universe::non_oop_word()\n\t"
  10.267             "CallDynamic @ CallDynamicJavaDirect" %}
  10.268    ins_encode( Java_Dynamic_Call( meth ) );
  10.269    ins_pipe( pipe_slow );
  10.270 @@ -13592,7 +13592,7 @@
  10.271  instruct loadD_unaligned(regD dst, memory mem ) %{
  10.272    match(Set dst (LoadD_unaligned mem));
  10.273    ins_cost(250);
  10.274 -  // FIXME: Jin: Need more effective ldl/ldr
  10.275 +  // FIXME: Need more effective ldl/ldr
  10.276    format %{ "loadD_unaligned   $dst, $mem #@loadD_unaligned" %}
  10.277    ins_encode(load_D_enc(dst, mem));
  10.278    ins_pipe( ialu_loadI );
  10.279 @@ -14102,9 +14102,9 @@
  10.280      Address  addr($mem_ptr$$Register, 0);
  10.281      Label L;
  10.282  
  10.283 -    /* 2013/7/19 Jin: cmpxchg32 is implemented with ll/sc, which will do sign extension.
  10.284 -     *      Thus, we should extend oldval's sign for correct comparision.
  10.285 -     */
  10.286 +    // cmpxchg32 is implemented with ll/sc, which will do sign extension.
  10.287 +    //      Thus, we should extend oldval's sign for correct comparision.
  10.288 +    //
  10.289      __ sll(oldval, oldval, 0);
  10.290  
  10.291      __ cmpxchg32(newval, addr, oldval);

    11.1 --- a/src/cpu/mips/vm/register_mips.hpp	Mon Sep 03 14:27:42 2018 +0800
    11.2 +++ b/src/cpu/mips/vm/register_mips.hpp	Tue Sep 04 21:25:12 2018 +0800
    11.3 @@ -241,7 +241,7 @@
    11.4  // be sure to save and restore its value in call_stub
    11.5  #define TSR            S2
    11.6  
    11.7 -/* 2013/7/10 Jin: OPT_SAFEPOINT not supported yet */
    11.8 +//OPT_SAFEPOINT not supported yet
    11.9  #define OPT_SAFEPOINT 1
   11.10  
   11.11  #define OPT_THREAD 1

    12.1 --- a/src/cpu/mips/vm/runtime_mips_64.cpp	Mon Sep 03 14:27:42 2018 +0800
    12.2 +++ b/src/cpu/mips/vm/runtime_mips_64.cpp	Tue Sep 04 21:25:12 2018 +0800
    12.3 @@ -65,13 +65,13 @@
    12.4  //
    12.5  // Note: the exception pc MUST be at a call (precise debug information)
    12.6  //
    12.7 -// 2012/9/14 Jin: [stubGenerator_mips.cpp] generate_forward_exception()
    12.8 -//                    |- V0, V1 are created
    12.9 -//                    |- T9 <= SharedRuntime::exception_handler_for_return_address
   12.10 -//                    `- jr T9
   12.11 -//                         `- the caller's exception_handler
   12.12 -//                               `- jr OptoRuntime::exception_blob
   12.13 -//                                      `- here
   12.14 +//  [stubGenerator_mips.cpp] generate_forward_exception()
   12.15 +//      |- V0, V1 are created
   12.16 +//      |- T9 <= SharedRuntime::exception_handler_for_return_address
   12.17 +//      `- jr T9
   12.18 +//           `- the caller's exception_handler
   12.19 +//                 `- jr OptoRuntime::exception_blob
   12.20 +//                        `- here
   12.21  //
   12.22  void OptoRuntime::generate_exception_blob() {
   12.23    // Capture info about frame layout
   12.24 @@ -92,10 +92,9 @@
   12.25  
   12.26    __ daddiu(SP, SP, -1 * framesize * wordSize);   // Prolog!
   12.27  
   12.28 -  /* 2012/9.27 Jin: this frame will be treated as the original caller method.
   12.29 -   * So, the return pc should be filled with the original exception pc.
   12.30 -   *   ref: X86's implementation
   12.31 -   */
   12.32 +  // this frame will be treated as the original caller method.
   12.33 +  // So, the return pc should be filled with the original exception pc.
   12.34 +  //   ref: X86's implementation
   12.35    __ sd(V1, SP, return_off  *wordSize);  // return address
   12.36    __ sd(FP, SP, fp_off  *wordSize);  // EBP
   12.37  
   12.38 @@ -172,12 +171,12 @@
   12.39    // Clear the exception oop so GC no longer processes it as a root.
   12.40    __ sd(R0, Address(thread, JavaThread::exception_oop_offset()));
   12.41  
   12.42 -  /* 2014/5/12 Jin: Fix seg fault when running:
   12.43 -   *    Eclipse + Plugin + Debug As
   12.44 -   *  This is the only condition where C2 calls SharedRuntime::generate_deopt_blob()
   12.45 -   *
   12.46 -   *  Ref:  http://10.2.5.21:8000/projects/java/wiki/Jgj-log-2014-5-12_
   12.47 -   */
   12.48 +  // Fix seg fault when running:
   12.49 +  //    Eclipse + Plugin + Debug As
   12.50 +  //  This is the only condition where C2 calls SharedRuntime::generate_deopt_blob()
   12.51 +  //
   12.52 +  //  Ref:  http://10.2.5.21:8000/projects/java/wiki/Jgj-log-2014-5-12_
   12.53 +  //
   12.54    __ move(V0, A0);
   12.55    __ move(V1, A1);
   12.56  

    13.1 --- a/src/cpu/mips/vm/sharedRuntime_mips_64.cpp	Mon Sep 03 14:27:42 2018 +0800
    13.2 +++ b/src/cpu/mips/vm/sharedRuntime_mips_64.cpp	Tue Sep 04 21:25:12 2018 +0800
    13.3 @@ -687,11 +687,11 @@
    13.4      } else if (r_1->is_Register()) {
    13.5        Register r = r_1->as_Register();
    13.6        if (!r_2->is_valid()) {
    13.7 -          __ sd(r,SP, st_off); //aoqi_test FIXME
    13.8 +          __ sd(r,SP, st_off);
    13.9        } else {
   13.10          //FIXME, mips will not enter here
   13.11          // long/double in gpr
   13.12 -          __ sd(r,SP, st_off); //aoqi_test FIXME
   13.13 +          __ sd(r,SP, st_off);
   13.14  /* Jin: In [java/util/zip/ZipFile.java]
   13.15  
   13.16      private static native long open(String name, int mode, long lastModified);
   13.17 @@ -893,10 +893,7 @@
   13.18          //  assert(r_2->as_Register() != eax, "need another temporary register");
   13.19          // Remember r_1 is low address (and LSB on mips)
   13.20          // So r_2 gets loaded from high address regardless of the platform
   13.21 -        //aoqi
   13.22          assert(r_2->as_Register() == r_1->as_Register(), "");
   13.23 -        //__ ld(r_2->as_Register(), saved_sp, ld_off);
   13.24 -        //__ ld(r, saved_sp, next_off);
   13.25          __ ld(r, saved_sp, ld_off);
   13.26  
   13.27        /* Jin:
   13.28 @@ -3105,8 +3102,8 @@
   13.29    int   exception_offset = __ pc() - start;
   13.30    // Prolog for exception case
   13.31  
   13.32 -  // all registers are dead at this entry point, except for eax and
   13.33 -  // edx which contain the exception oop and exception pc
   13.34 +  // all registers are dead at this entry point, except for V0 and
   13.35 +  // V1 which contain the exception oop and exception pc
   13.36    // respectively.  Set them in TLS and fall thru to the
   13.37    // unpack_with_exception_in_tls entry point.
   13.38  

    14.1 --- a/src/cpu/mips/vm/stubGenerator_mips_64.cpp	Mon Sep 03 14:27:42 2018 +0800
    14.2 +++ b/src/cpu/mips/vm/stubGenerator_mips_64.cpp	Tue Sep 04 21:25:12 2018 +0800
    14.3 @@ -327,7 +327,7 @@
    14.4    // not the case if the callee is compiled code => need to setup the
    14.5    // rsp.
    14.6    //
    14.7 -  // rax: exception oop
    14.8 +  // V0: exception oop
    14.9  
   14.10    address generate_catch_exception() {
   14.11      StubCodeMark mark(this, "StubRoutines", "catch_exception");

    15.1 --- a/src/cpu/mips/vm/templateInterpreter_mips_64.cpp	Mon Sep 03 14:27:42 2018 +0800
    15.2 +++ b/src/cpu/mips/vm/templateInterpreter_mips_64.cpp	Tue Sep 04 21:25:12 2018 +0800
    15.3 @@ -128,10 +128,6 @@
    15.4  address TemplateInterpreterGenerator::generate_ClassCastException_handler() {
    15.5    address entry = __ pc();
    15.6  
    15.7 -  // object is at TOS
    15.8 -  //FIXME, I am not sure if the object is at TOS as x86 do now @jerome, 04/20,2007
    15.9 -  //__ pop(c_rarg1);
   15.10 -
   15.11    // expression stack must be empty before entering the VM if an
   15.12    // exception happened
   15.13    __ empty_expression_stack();
   15.14 @@ -261,8 +257,6 @@
   15.15  }
   15.16  
   15.17  
   15.18 -// why do not consider float and double , @jerome, 12/27,06, @jerome
   15.19 -//FIXME, aoqi
   15.20  address TemplateInterpreterGenerator::generate_result_handler_for(
   15.21          BasicType type) {
   15.22    address entry = __ pc();
   15.23 @@ -451,7 +445,6 @@
   15.24  #endif
   15.25  
   15.26    // locals + overhead, in bytes
   15.27 -  //FIXME aoqi
   15.28    __ dsll(T3, T2, Interpreter::stackElementScale());
   15.29    __ daddiu(T3, T3, overhead_size);   // locals * 4 + overhead_size --> T3
   15.30  
   15.31 @@ -557,7 +550,7 @@
   15.32    __ sd(FP, SP, (-2) * wordSize);  // save sender's fp
   15.33    __ daddiu(FP, SP, (-2) * wordSize);
   15.34    __ sd(Rsender, FP, (-++i) * wordSize);  // save sender's sp
   15.35 -  __ sd(R0, FP,(-++i)*wordSize);       //save last_sp as null, FIXME aoqi
   15.36 +  __ sd(R0, FP,(-++i)*wordSize);       //save last_sp as null
   15.37    __ sd(LVP, FP, (-++i) * wordSize);  // save locals offset
   15.38    __ ld(BCP, Rmethod, in_bytes(Method::const_offset())); // get constMethodOop
   15.39    __ daddiu(BCP, BCP, in_bytes(ConstMethod::codes_offset())); // get codebase
   15.40 @@ -1046,9 +1039,8 @@
   15.41    {
   15.42      Label L, Lstatic;
   15.43      __ ld(t,method,in_bytes(Method::const_offset()));
   15.44 -    __ lhu(t, t, in_bytes(ConstMethod::size_of_parameters_offset()));  // Fu: 20130814
   15.45 +    __ lhu(t, t, in_bytes(ConstMethod::size_of_parameters_offset()));
   15.46      // MIPS n64 ABI: caller does not reserve space for the register auguments.
   15.47 -    //FIXME, aoqi: A1?
   15.48      // A0 and A1(if needed)
   15.49      __ lw(AT, Rmethod, in_bytes(Method::access_flags_offset()));
   15.50      __ andi(AT, AT, JVM_ACC_STATIC);
   15.51 @@ -1198,7 +1190,6 @@
   15.52    __ get_thread(thread);
   15.53  #endif
   15.54    __ daddi(t, thread, in_bytes(JavaThread::jni_environment_offset()));
   15.55 -  // stack,but I think it won't work when pass float,double etc @jerome,10/17,2006
   15.56    __ move(A0, t);
   15.57    // [ jni environment          ] <--- sp
   15.58    // [ mthd holder mirror ptr   ] ---------------------------->| (only for static method)
   15.59 @@ -2184,7 +2175,7 @@
   15.60    // prepare expression stack
   15.61    __ push(state);       // save tosca
   15.62  
   15.63 -  // tos & tos2, added by yjl 7/15/2005
   15.64 +  // tos & tos2
   15.65    // trace_bytecode need actually 4 args, the last two is tos&tos2
   15.66    // this work fine for x86. but mips o32 call convention will store A2-A3
   15.67    // to the stack position it think is the tos&tos2

    16.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp	Mon Sep 03 14:27:42 2018 +0800
    16.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp	Tue Sep 04 21:25:12 2018 +0800
    16.3 @@ -2572,7 +2572,7 @@
    16.4      __ load_klass(LVP, T1);
    16.5      __ lw(LVP, LVP, in_bytes(Klass::access_flags_offset()));
    16.6      __ move(AT, JVM_ACC_HAS_FINALIZER);
    16.7 -    __ andr(AT, AT, LVP);//by_css
    16.8 +    __ andr(AT, AT, LVP);
    16.9      Label skip_register_finalizer;
   16.10      __ beq(AT, R0, skip_register_finalizer);
   16.11      __ delayed()->nop();

    17.1 --- a/src/os/linux/vm/os_linux.cpp	Mon Sep 03 14:27:42 2018 +0800
    17.2 +++ b/src/os/linux/vm/os_linux.cpp	Tue Sep 04 21:25:12 2018 +0800
    17.3 @@ -981,7 +981,7 @@
    17.4    sync_with_child->notify();
    17.5  
    17.6  #ifdef MIPS64
    17.7 -  /* 2013/11/5 Jin: To be accessed in NativeGeneralJump::patch_verified_entry() */
    17.8 +  //To be accessed in NativeGeneralJump::patch_verified_entry()
    17.9    if (thread->is_Java_thread())
   17.10    {
   17.11      ((JavaThread*)thread)->set_handle_wrong_method_stub(SharedRuntime::get_handle_wrong_method_stub());

    18.1 --- a/src/os_cpu/linux_mips/vm/os_linux_mips.cpp	Mon Sep 03 14:27:42 2018 +0800
    18.2 +++ b/src/os_cpu/linux_mips/vm/os_linux_mips.cpp	Tue Sep 04 21:25:12 2018 +0800
    18.3 @@ -98,7 +98,7 @@
    18.4  
    18.5  address os::Linux::ucontext_get_pc(ucontext_t * uc) {
    18.6    //return (address)uc->uc_mcontext.gregs[REG_PC];
    18.7 -  return (address)uc->uc_mcontext.pc;//aoqi:what is gregs?
    18.8 +  return (address)uc->uc_mcontext.pc;
    18.9  }
   18.10  
   18.11  intptr_t* os::Linux::ucontext_get_sp(ucontext_t * uc) {
   18.12 @@ -566,7 +566,6 @@
   18.13      ) &&
   18.14        //(uc->uc_mcontext.cause == 2 || uc->uc_mcontext.cause == 3)) {
   18.15        (uc->uc_mcontext.hi1 == 2 || uc->uc_mcontext.hi1 == 3)) {
   18.16 -        //aoqi: copy from jdk1.5, dont understand the struct mcontext_t.
   18.17  #ifdef PRINT_SIGNAL_HANDLE
   18.18      tty->print_cr("execution protection violation\n");
   18.19  #endif

    19.1 --- a/src/share/vm/c1/c1_LIR.hpp	Mon Sep 03 14:27:42 2018 +0800
    19.2 +++ b/src/share/vm/c1/c1_LIR.hpp	Tue Sep 04 21:25:12 2018 +0800
    19.3 @@ -27,7 +27,6 @@
    19.4   * modifications are Copyright (c) 2018 Loongson Technology, and are made
    19.5   * available on the same license terms set forth above.
    19.6   */
    19.7 -
    19.8  #ifndef SHARE_VM_C1_C1_LIR_HPP
    19.9  #define SHARE_VM_C1_C1_LIR_HPP
   19.10  
   19.11 @@ -388,7 +387,6 @@
   19.12  #ifdef MIPS
   19.13    bool has_common_register(LIR_Opr opr) const;
   19.14  #endif
   19.15 -
   19.16    // semantic for fpu- and xmm-registers:
   19.17    // * is_float and is_double return true for xmm_registers
   19.18    //   (so is_single_fpu and is_single_xmm are true)
   19.19 @@ -1954,11 +1952,8 @@
   19.20     void          negate_cond();
   19.21  
   19.22  
   19.23 -  // 12/21,06,jerome
   19.24 -  //virtual void emit_code(LIR_AbstractAssembler* masm);
   19.25    virtual void emit_code(LIR_Assembler* masm);
   19.26    virtual LIR_OpBranch* as_OpBranch() { return this; }
   19.27 -  //virtual void print_instr() const PRODUCT_RETURN;
   19.28    virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
   19.29  
   19.30   };
   19.31 @@ -2125,7 +2120,6 @@
   19.32    virtual void emit_code(LIR_Assembler* masm);
   19.33    virtual LIR_Op4* as_Op4() { return this; }
   19.34  
   19.35 -  // virtual void print_instr() const PRODUCT_RETURN;
   19.36    virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
   19.37  };
   19.38  #endif
   19.39 @@ -2585,7 +2579,6 @@
   19.40  #ifdef MIPS
   19.41    void frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info = NULL);
   19.42  #endif
   19.43 -
   19.44    void idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info);
   19.45    void idiv(LIR_Opr left, int   right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info);
   19.46    void irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info);

    20.1 --- a/src/share/vm/c1/c1_LIRGenerator.cpp	Mon Sep 03 14:27:42 2018 +0800
    20.2 +++ b/src/share/vm/c1/c1_LIRGenerator.cpp	Tue Sep 04 21:25:12 2018 +0800
    20.3 @@ -316,7 +316,6 @@
    20.4    CardTableModRefBS* ct = (CardTableModRefBS*)_bs;
    20.5    assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
    20.6    //_card_table_base = new LIR_Const((intptr_t)ct->byte_map_base);
    20.7 -  //        //FIXME, untested in 32bit. by aoqi
    20.8    _card_table_base = new LIR_Const(ct->byte_map_base);
    20.9  #endif
   20.10  }