1.1 --- a/src/cpu/mips/vm/mips_64.ad Mon Sep 03 14:27:42 2018 +0800
1.2 +++ b/src/cpu/mips/vm/mips_64.ad Tue Sep 04 21:25:12 2018 +0800
1.3 @@ -380,8 +380,7 @@
1.4
1.5
1.6 // Floating point registers.
1.7 -// 2012/8/23 Fu: F30/F31 are used as temporary registers in D2I
1.8 -// 2016/12/1 aoqi: F31 are not used as temporary registers in D2I
1.9 +// F31 are not used as temporary registers in D2I
1.10 reg_class flt_reg( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17 F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F31);
1.11 reg_class dbl_reg( F0, F0_H,
1.12 F1, F1_H,
1.13 @@ -442,7 +441,6 @@
1.14 // Branches are even more expensive.
1.15 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
1.16 // we use jr instruction to construct call, so more expensive
1.17 - // by yjl 2/28/2006
1.18 int_def CALL_COST ( 500, DEFAULT_COST * 5);
1.19 /*
1.20 int_def EQUAL ( 1, 1 );
1.21 @@ -1383,18 +1381,19 @@
1.22
1.23 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1.24
1.25 - st->print("daddiu SP, SP, %d # Rlease stack @ MachEpilogNode",framesize);
1.26 - st->cr(); st->print("\t");
1.27 + st->print_cr("daddiu SP, SP, %d # Rlease stack @ MachEpilogNode", framesize);
1.28 + st->print("\t");
1.29 if (UseLoongsonISA) {
1.30 - st->print("gslq RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
1.31 + st->print_cr("gslq RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
1.32 } else {
1.33 - st->print("ld RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
1.34 - st->cr(); st->print("\t");
1.35 - st->print("ld FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
1.36 + st->print_cr("ld RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
1.37 + st->print("\t");
1.38 + st->print_cr("ld FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
1.39 }
1.40
1.41 if( do_polling() && C->is_method_compilation() ) {
1.42 - st->print("Poll Safepoint # MachEpilogNode");
1.43 + st->print("\t");
1.44 + st->print_cr("Poll Safepoint # MachEpilogNode");
1.45 }
1.46 }
1.47 #endif
1.48 @@ -1634,7 +1633,7 @@
1.49 }
1.50 __ daddiu(FP, SP, -wordSize*2);
1.51 __ daddiu(SP, SP, -framesize);
1.52 - __ nop(); /* 2013.10.22 Jin: Make enough room for patch_verified_entry() */
1.53 + __ nop(); // Make enough room for patch_verified_entry()
1.54 __ nop();
1.55
1.56 C->set_frame_complete(cbuf.insts_size());
1.57 @@ -3348,18 +3347,18 @@
1.58 Register tmp = T9;
1.59 Label miss;
1.60
1.61 - /* 2012/9/28 Jin: result may be the same as sub
1.62 - * 47c B40: # B21 B41 <- B20 Freq: 0.155379
1.63 - * 47c partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
1.64 - * 4bc mov S2, NULL #@loadConP
1.65 - * 4c0 beq S1, S2, B21 #@branchConP P=0.999999 C=-1.000000
1.66 - */
1.67 + // result may be the same as sub
1.68 + // 47c B40: # B21 B41 <- B20 Freq: 0.155379
1.69 + // 47c partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
1.70 + // 4bc mov S2, NULL #@loadConP
1.71 + // 4c0 beq S1, S2, B21 #@branchConP P=0.999999 C=-1.000000
1.72 + //
1.73 MacroAssembler _masm(&cbuf);
1.74 Label done;
1.75 __ check_klass_subtype_slow_path(sub, super, length, tmp,
1.76 NULL, &miss,
1.77 /*set_cond_codes:*/ true);
1.78 - /* 2013/7/22 Jin: Refer to X86_64's RDI */
1.79 + // Refer to X86_64's RDI
1.80 __ move(result, 0);
1.81 __ b(done);
1.82 __ delayed()->nop();
1.83 @@ -3431,7 +3430,7 @@
1.84 // These two registers define part of the calling convention
1.85 // between compiled code and the interpreter.
1.86 // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention
1.87 - // for more information. by yjl 3/16/2006
1.88 + // for more information.
1.89
1.90 inline_cache_reg(T1); // Inline Cache Register
1.91 interpreter_method_oop_reg(S3); // Method Oop Register when calling interpreter
1.92 @@ -3488,7 +3487,7 @@
1.93
1.94
1.95 // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing)
1.96 - // StartNode::calling_convention call this. by yjl 3/16/2006
1.97 + // StartNode::calling_convention call this.
1.98 calling_convention %{
1.99 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
1.100 %}
1.101 @@ -3504,7 +3503,7 @@
1.102 // automatically biased by the preserve_stack_slots field above.
1.103
1.104
1.105 - // SEE CallRuntimeNode::calling_convention for more information. by yjl 3/16/2006
1.106 + // SEE CallRuntimeNode::calling_convention for more information.
1.107 c_calling_convention %{
1.108 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
1.109 %}
1.110 @@ -3512,7 +3511,7 @@
1.111
1.112 // Location of C & interpreter return values
1.113 // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR.
1.114 - // SEE Matcher::match. by yjl 3/16/2006
1.115 + // SEE Matcher::match.
1.116 c_return_value %{
1.117 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
1.118 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
1.119 @@ -3523,7 +3522,7 @@
1.120
1.121 // Location of return values
1.122 // register(s) contain(s) return value for Op_StartC2I and Op_Start.
1.123 - // SEE Matcher::match. by yjl 3/16/2006
1.124 + // SEE Matcher::match.
1.125
1.126 return_value %{
1.127 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
1.128 @@ -4597,6 +4596,7 @@
1.129 operand mRegP() %{
1.130 constraint(ALLOC_IN_RC(p_reg));
1.131 match(RegP);
1.132 + match(a0_RegP);
1.133
1.134 format %{ %}
1.135 interface(REG_INTER);
1.136 @@ -6001,7 +6001,7 @@
1.137 instruct loadL_unaligned(mRegL dst, memory mem) %{
1.138 match(Set dst (LoadL_unaligned mem));
1.139
1.140 - // FIXME: Jin: Need more effective ldl/ldr
1.141 + // FIXME: Need more effective ldl/ldr
1.142 ins_cost(450);
1.143 format %{ "ld $dst, $mem #@loadL_unaligned\n\t" %}
1.144 ins_encode(load_L_enc(dst, mem));
1.145 @@ -6540,7 +6540,7 @@
1.146 Register target = $jump_target$$Register;
1.147 Register oop = $method_oop$$Register;
1.148
1.149 - /* 2012/10/12 Jin: RA will be used in generate_forward_exception() */
1.150 + // RA will be used in generate_forward_exception()
1.151 __ push(RA);
1.152
1.153 __ move(S3, oop);
1.154 @@ -6561,24 +6561,24 @@
1.155 // use the following format syntax
1.156 format %{ "# exception oop is in A0; no code emitted @CreateException" %}
1.157 ins_encode %{
1.158 - /* Jin: X86 leaves this function empty */
1.159 - __ block_comment("CreateException is empty in X86/MIPS");
1.160 + // X86 leaves this function empty
1.161 + __ block_comment("CreateException is empty in MIPS");
1.162 %}
1.163 ins_pipe( empty );
1.164 // ins_pipe( pipe_jump );
1.165 %}
1.166
1.167
1.168 -/* 2012/9/14 Jin: The mechanism of exception handling is clear now.
1.169 +/* The mechanism of exception handling is clear now.
1.170
1.171 - Common try/catch:
1.172 - 2012/9/14 Jin: [stubGenerator_mips.cpp] generate_forward_exception()
1.173 - |- V0, V1 are created
1.174 - |- T9 <= SharedRuntime::exception_handler_for_return_address
1.175 - `- jr T9
1.176 - `- the caller's exception_handler
1.177 - `- jr OptoRuntime::exception_blob
1.178 - `- here
1.179 + [stubGenerator_mips.cpp] generate_forward_exception()
1.180 + |- V0, V1 are created
1.181 + |- T9 <= SharedRuntime::exception_handler_for_return_address
1.182 + `- jr T9
1.183 + `- the caller's exception_handler
1.184 + `- jr OptoRuntime::exception_blob
1.185 + `- here
1.186 - Rethrow(e.g. 'unwind'):
1.187 * The callee:
1.188 |- an exception is triggered during execution
1.189 @@ -7536,7 +7536,7 @@
1.190 __ bc1t_long(*L);
1.191 break;
1.192 case 0x02: //not_equal
1.193 - //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
1.194 + // c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
1.195 __ c_eq_d(reg_op1, reg_op2);
1.196 __ bc1f_long(*L);
1.197 break;
1.198 @@ -8751,7 +8751,7 @@
1.199 __ bc1t((int)0);
1.200 break;
1.201 case 0x02: //not_equal
1.202 - //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
1.203 + // c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
1.204 __ c_eq_d(reg_op1, reg_op2);
1.205 if (&L)
1.206 __ bc1f(L);
1.207 @@ -9659,7 +9659,7 @@
1.208 __ movt(dst, src);
1.209 break;
1.210 case 0x02: //not_equal
1.211 -//2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
1.212 + // See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
1.213 __ c_eq_d(reg_op1, reg_op2);
1.214 __ movf(dst, src);
1.215 break;
1.216 @@ -11132,8 +11132,8 @@
1.217 Register src2 = $src2$$Register;
1.218 Register dst = $dst$$Register;
1.219
1.220 - /* 2012/4/21 Jin: In MIPS, div does not cause exception.
1.221 - We must trap an exception manually. */
1.222 + // In MIPS, div does not cause exception.
1.223 + // We must trap an exception manually.
1.224 __ teq(R0, src2, 0x7);
1.225
1.226 if (UseLoongsonISA) {
1.227 @@ -12706,12 +12706,12 @@
1.228
1.229 __ mov_s(F12, fval);
1.230
1.231 - /* 2014/01/08 Fu : This bug was found when running ezDS's control-panel.
1.232 - * J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
1.233 - *
1.234 - * An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
1.235 - * V0 is corrupted during call_VM_leaf(), and should be preserved.
1.236 - */
1.237 + //This bug was found when running ezDS's control-panel.
1.238 + // J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
1.239 + //
1.240 + // An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
1.241 + // V0 is corrupted during call_VM_leaf(), and should be preserved.
1.242 + //
1.243 __ push(fval);
1.244 if(dreg != V0) {
1.245 __ push(V0);
1.246 @@ -13173,10 +13173,10 @@
1.247 ins_encode %{
1.248 Register target = $jump_target$$Register;
1.249
1.250 - /* 2012/9/14 Jin: V0, V1 are indicated in:
1.251 - * [stubGenerator_mips.cpp] generate_forward_exception()
1.252 - * [runtime_mips.cpp] OptoRuntime::generate_exception_blob()
1.253 - */
1.254 + // V0, V1 are indicated in:
1.255 + // [stubGenerator_mips.cpp] generate_forward_exception()
1.256 + // [runtime_mips.cpp] OptoRuntime::generate_exception_blob()
1.257 + //
1.258 Register oop = $ex_oop$$Register;
1.259 Register exception_oop = V0;
1.260 Register exception_pc = V1;
1.261 @@ -13214,7 +13214,7 @@
1.262 effect(USE meth);
1.263
1.264 ins_cost(300);
1.265 - format %{"MOV IC_Klass, (oop)-1\n\t"
1.266 + format %{"MOV IC_Klass, #Universe::non_oop_word()\n\t"
1.267 "CallDynamic @ CallDynamicJavaDirect" %}
1.268 ins_encode( Java_Dynamic_Call( meth ) );
1.269 ins_pipe( pipe_slow );
1.270 @@ -13592,7 +13592,7 @@
1.271 instruct loadD_unaligned(regD dst, memory mem ) %{
1.272 match(Set dst (LoadD_unaligned mem));
1.273 ins_cost(250);
1.274 - // FIXME: Jin: Need more effective ldl/ldr
1.275 + // FIXME: Need more effective ldl/ldr
1.276 format %{ "loadD_unaligned $dst, $mem #@loadD_unaligned" %}
1.277 ins_encode(load_D_enc(dst, mem));
1.278 ins_pipe( ialu_loadI );
1.279 @@ -14102,9 +14102,9 @@
1.280 Address addr($mem_ptr$$Register, 0);
1.281 Label L;
1.282
1.283 - /* 2013/7/19 Jin: cmpxchg32 is implemented with ll/sc, which will do sign extension.
1.284 - * Thus, we should extend oldval's sign for correct comparision.
1.285 - */
1.286 + // cmpxchg32 is implemented with ll/sc, which will do sign extension.
1.287 + // Thus, we should extend oldval's sign for correct comparision.
1.288 + //
1.289 __ sll(oldval, oldval, 0);
1.290
1.291 __ cmpxchg32(newval, addr, oldval);
