jdk8-mips64-public/hotspot: comparison src/cpu/mips/vm/macroAssembler

-:f1560009a081
+:617b86d17edb
 }
 void MacroAssembler::beq_far(Register rs, Register rt, address entry) {
 u_char * cur_pc = pc();
-/* Jin: Near/Far jump */
+// Near/Far jump
 if(is_simm16((entry - pc() - 4) / 4)) {
 Assembler::beq(rs, rt, offset(entry));
 } else {
 Label not_jump;
 bne(rs, rt, not_jump);
 }
 void MacroAssembler::bne_far(Register rs, Register rt, address entry) {
 u_char * cur_pc = pc();
-/* Jin: Near/Far jump */
+//Near/Far jump
 if(is_simm16((entry - pc() - 4) / 4)) {
 Assembler::bne(rs, rt, offset(entry));
 } else {
 Label not_jump;
 beq(rs, rt, not_jump);
 }
 void MacroAssembler::b_far(address entry) {
 u_char * cur_pc = pc();
-/* Jin: Near/Far jump */
+// Near/Far jump
 if(is_simm16((entry - pc() - 4) / 4)) {
 b(offset(entry));
 } else {
-/* address must be bounded */
+// address must be bounded
 move(AT, RA);
 emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
 nop();
 li32(T9, entry - pc());
 daddu(T9, T9, RA);
 void MacroAssembler::stop(const char* msg) {
 li(A0, (long)msg);
 #ifndef _LP64
-//reserver space for argument. added by yjl 7/10/2005
+//reserver space for argument.
 addiu(SP, SP, - 1 * wordSize);
 #endif
 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
 delayed()->nop();
 #ifndef _LP64
 ld_ptr(obj, thread, in_bytes(JavaThread::tlab_top_offset()));
 if (var_size_in_bytes == NOREG) {
 // i dont think we need move con_size_in_bytes to a register first.
-// by yjl 8/17/2005
 assert(is_simm16(con_size_in_bytes), "fixme by moving imm to a register first");
 addi(end, obj, con_size_in_bytes);
 } else {
 add(end, obj, var_size_in_bytes);
 }
 delayed()->nop();
 // update the tlab top pointer
 st_ptr(end, thread, in_bytes(JavaThread::tlab_top_offset()));
-// recover var_size_in_bytes if necessary
-/*if (var_size_in_bytes == end) {
-sub(var_size_in_bytes, end, obj);
-}*/
 verify_tlab(t1, t2);
 }
 // Defines obj, preserves var_size_in_bytes
 void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
 Register t1, Register t2, Label& slow_case) {
 assert_different_registers(obj, var_size_in_bytes, t1, AT);
-if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { //by yyq
+if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
 // No allocation in the shared eden.
 b_far(slow_case);
 delayed()->nop();
 } else {
 //  sync();
 //}
 // if someone beat us on the allocation, try again, otherwise continue
 cmpxchg(end, heap_top, obj);
-beq_far(AT, R0, retry);    //by yyq
+beq_far(AT, R0, retry);
 delayed()->nop();
 }
 }
 // C2 doesn't invoke this one.
 Register t3  = T3;
 Register thread_reg = T8;
 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ T2, A4);
 Label do_refill, discard_tlab;
-if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { //by yyq
+if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
 // No allocation in the shared eden.
 b(slow_case);
 delayed()->nop();
 }
 static const double     pi_4 =  0.7853981633974483;
 // the x86 version is to clumsy, i dont think we need that fuss. maybe i'm wrong, FIXME
 // must get argument(a double) in F12/F13
 //void MacroAssembler::trigfunc(char trig, bool preserve_cpu_regs, int num_fpu_regs_in_use) {
-//We need to preseve the register which maybe modified during the Call @Jerome
+//We need to preseve the register which maybe modified during the Call
 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
 //save all modified register here
-//  if (preserve_cpu_regs) {
-//  }
 //FIXME, in the disassembly of tirgfunc, only used V0,V1,T9, SP,RA,so we ony save V0,V1,T9
 pushad();
 //we should preserve the stack space before we call
 addi(SP, SP, -wordSize * 2);
 switch (trig){
 }
 addi(SP, SP, wordSize * 2);
 popad();
-//  if (preserve_cpu_regs) {
-//  }
 }
 #ifdef _LP64
 void MacroAssembler::li(Register rd, long imm) {
 if (imm <= max_jint && imm >= min_jint) {
 assert_not_delayed();
 // lui sign-extends, so we can't use that.
 ori(rd, R0, julong(imm) >> 16);
 dsll(rd, rd, 16);
 ori(rd, rd, split_low(imm));
-//aoqi_test
-//} else if ((imm > 0) && ((imm >> 48) == 0)) {
 } else if ((imm > 0) && is_simm16(imm >> 32)) {
 /* A 48-bit address */
 li48(rd, imm);
 } else {
 li64(rd, imm);
 }
 #endif
 void MacroAssembler::li32(Register reg, int imm) {
 if (is_simm16(imm)) {
-/* Jin: for imm < 0, we should use addi instead of addiu.
+/* for imm < 0, we should use addi instead of addiu.
 *
 *  java.lang.StringCoding$StringDecoder.decode(jobject, jint, jint)
 *
 *  78 move [int:-1|I] [a0|I]
 *    : daddi a0, zero, 0xffffffff  (correct)
 #ifdef _LP64
 /* do 32-bit CAS using MIPS64 lld/scd
-Jin: cas_int should only compare 32-bits of the memory value.
+cas_int should only compare 32-bits of the memory value.
 However, lld/scd will do 64-bit operation, which violates the intention of cas_int.
 To simulate a 32-bit atomic operation, the value loaded with LLD should be split into
 tow halves, and only the low-32 bits is compared. If equals, the low-32 bits of newval,
 plus the high-32 bits or memory value, are stored togethor with SCD.
 Example:
 double d = 3.1415926;
 System.err.println("hello" + d);
 0x00000055647f45a8: dadd at, zero, zero
 done:
 */
 void MacroAssembler::cmpxchg32(Register x_reg, Address dest, Register c_reg) {
-/* 2012/11/11 Jin: MIPS64 can use ll/sc for 32-bit atomic memory access */
+/* MIPS64 can use ll/sc for 32-bit atomic memory access */
 Label done, again, nequal;
 bind(again);
 if(UseSyncLevel >= 3000 || UseSyncLevel < 2000) sync();
 #ifdef _LP64
 Register caller_saved_registers[] = {AT, V0, V1, A0, A1, A2, A3, A4, A5, A6, A7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
 Register caller_saved_registers_except_v0[] = {AT, V1, A0, A1, A2, A3, A4, A5, A6, A7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
-/* FIXME: Jin: In MIPS64, F0~23 are all caller-saved registers */
+//In MIPS64, F0~23 are all caller-saved registers
 FloatRegister caller_saved_fpu_registers[] = {F0, F12, F13};
 #else
 Register caller_saved_registers[] = {AT, V0, V1, A0, A1, A2, A3, T4, T5, T6, T7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
 Register caller_saved_registers_except_v0[] = {AT, V1, A0, A1, A2, A3, T4, T5, T6, T7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
 // Set NZ/Z based on last compare.
 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
 // not change flags (only scas instruction which is repeated sets flags).
 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
-/* 2013/4/3 Jin: OpenJDK8 never compresses klass pointers in secondary-super array. */
+// OpenJDK8 never compresses klass pointers in secondary-super array.
 Label Loop, subtype;
 bind(Loop);
 beq(temp2_reg, R0, *L_failure);
 delayed()->nop();
 ld(AT, temp_reg, 0);
 offset += arg_slot.as_constant() * stackElementSize;
 } else {
 scale_reg    = arg_slot.as_register();
 scale_factor = Address::times_8;
 }
-// 2014/07/31 Fu: We don't push RA on stack in prepare_invoke.
+// We don't push RA on stack in prepare_invoke.
 //  offset += wordSize;           // return PC is on stack
 if(scale_reg==NOREG) return Address(SP, offset);
 else {
 dsll(scale_reg, scale_reg, scale_factor);
 daddu(scale_reg, SP, scale_reg);

comparison: src/cpu/mips/vm/macroAssembler_mips.cpp

src/cpu/mips/vm/macroAssembler_mips.cpp

Mercurial > jdk8-mips64-public > hotspot / file comparison

comparison: src/cpu/mips/vm/macroAssembler_mips.cpp

src/cpu/mips/vm/macroAssembler_mips.cpp