src/cpu/mips/vm/register_mips.hpp

changeset 9228
617b86d17edb
parent 6880
52ea28d233d2
child 9251
1ccc5a3b3671
equal deleted inserted replaced
9227:f1560009a081 9228:617b86d17edb
239 #define LVP S7 239 #define LVP S7
240 // temperary callee saved register, we use this register to save the register maybe blowed cross call_VM 240 // temperary callee saved register, we use this register to save the register maybe blowed cross call_VM
241 // be sure to save and restore its value in call_stub 241 // be sure to save and restore its value in call_stub
242 #define TSR S2 242 #define TSR S2
243 243
244 /* 2013/7/10 Jin: OPT_SAFEPOINT not supported yet */ 244 //OPT_SAFEPOINT not supported yet
245 #define OPT_SAFEPOINT 1 245 #define OPT_SAFEPOINT 1
246 246
247 #define OPT_THREAD 1 247 #define OPT_THREAD 1
248 248
249 #define TREG S6 249 #define TREG S6

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