src/cpu/mips/vm/sharedRuntime_mips_64.cpp

changeset 9228
617b86d17edb
parent 9171
c67c94f5b85d
child 9459
814e9e335067
equal deleted inserted replaced
9227:f1560009a081 9228:617b86d17edb
685 __ st_ptr(AT,SP,st_off - 8); 685 __ st_ptr(AT,SP,st_off - 8);
686 } 686 }
687 } else if (r_1->is_Register()) { 687 } else if (r_1->is_Register()) {
688 Register r = r_1->as_Register(); 688 Register r = r_1->as_Register();
689 if (!r_2->is_valid()) { 689 if (!r_2->is_valid()) {
690 __ sd(r,SP, st_off); //aoqi_test FIXME 690 __ sd(r,SP, st_off);
691 } else { 691 } else {
692 //FIXME, mips will not enter here 692 //FIXME, mips will not enter here
693 // long/double in gpr 693 // long/double in gpr
694 __ sd(r,SP, st_off); //aoqi_test FIXME 694 __ sd(r,SP, st_off);
695 /* Jin: In [java/util/zip/ZipFile.java] 695 /* Jin: In [java/util/zip/ZipFile.java]
696 696
697 private static native long open(String name, int mode, long lastModified); 697 private static native long open(String name, int mode, long lastModified);
698 private static native int getTotal(long jzfile); 698 private static native int getTotal(long jzfile);
699 * 699 *
891 // assert(r != eax, "must be different"); 891 // assert(r != eax, "must be different");
892 if (r_2->is_valid()) { 892 if (r_2->is_valid()) {
893 // assert(r_2->as_Register() != eax, "need another temporary register"); 893 // assert(r_2->as_Register() != eax, "need another temporary register");
894 // Remember r_1 is low address (and LSB on mips) 894 // Remember r_1 is low address (and LSB on mips)
895 // So r_2 gets loaded from high address regardless of the platform 895 // So r_2 gets loaded from high address regardless of the platform
896 //aoqi
897 assert(r_2->as_Register() == r_1->as_Register(), ""); 896 assert(r_2->as_Register() == r_1->as_Register(), "");
898 //__ ld(r_2->as_Register(), saved_sp, ld_off);
899 //__ ld(r, saved_sp, next_off);
900 __ ld(r, saved_sp, ld_off); 897 __ ld(r, saved_sp, ld_off);
901 898
902 /* Jin: 899 /* Jin:
903 * 900 *
904 * For T_LONG type, the real layout is as below: 901 * For T_LONG type, the real layout is as below:
3103 __ delayed()->nop(); 3100 __ delayed()->nop();
3104 3101
3105 int exception_offset = __ pc() - start; 3102 int exception_offset = __ pc() - start;
3106 // Prolog for exception case 3103 // Prolog for exception case
3107 3104
3108 // all registers are dead at this entry point, except for eax and 3105 // all registers are dead at this entry point, except for V0 and
3109 // edx which contain the exception oop and exception pc 3106 // V1 which contain the exception oop and exception pc
3110 // respectively. Set them in TLS and fall thru to the 3107 // respectively. Set them in TLS and fall thru to the
3111 // unpack_with_exception_in_tls entry point. 3108 // unpack_with_exception_in_tls entry point.
3112 3109
3113 __ get_thread(thread); 3110 __ get_thread(thread);
3114 __ st_ptr(V1, thread, in_bytes(JavaThread::exception_pc_offset())); 3111 __ st_ptr(V1, thread, in_bytes(JavaThread::exception_pc_offset()));

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