1.1 --- a/src/share/vm/c1/c1_LIR.hpp Mon Sep 03 14:27:42 2018 +0800 1.2 +++ b/src/share/vm/c1/c1_LIR.hpp Tue Sep 04 21:25:12 2018 +0800 1.3 @@ -27,7 +27,6 @@ 1.4 * modifications are Copyright (c) 2018 Loongson Technology, and are made 1.5 * available on the same license terms set forth above. 1.6 */ 1.7 - 1.8 #ifndef SHARE_VM_C1_C1_LIR_HPP 1.9 #define SHARE_VM_C1_C1_LIR_HPP 1.10 1.11 @@ -388,7 +387,6 @@ 1.12 #ifdef MIPS 1.13 bool has_common_register(LIR_Opr opr) const; 1.14 #endif 1.15 - 1.16 // semantic for fpu- and xmm-registers: 1.17 // * is_float and is_double return true for xmm_registers 1.18 // (so is_single_fpu and is_single_xmm are true) 1.19 @@ -1954,11 +1952,8 @@ 1.20 void negate_cond(); 1.21 1.22 1.23 - // 12/21,06,jerome 1.24 - //virtual void emit_code(LIR_AbstractAssembler* masm); 1.25 virtual void emit_code(LIR_Assembler* masm); 1.26 virtual LIR_OpBranch* as_OpBranch() { return this; } 1.27 - //virtual void print_instr() const PRODUCT_RETURN; 1.28 virtual void print_instr(outputStream* out) const PRODUCT_RETURN; 1.29 1.30 }; 1.31 @@ -2125,7 +2120,6 @@ 1.32 virtual void emit_code(LIR_Assembler* masm); 1.33 virtual LIR_Op4* as_Op4() { return this; } 1.34 1.35 - // virtual void print_instr() const PRODUCT_RETURN; 1.36 virtual void print_instr(outputStream* out) const PRODUCT_RETURN; 1.37 }; 1.38 #endif 1.39 @@ -2585,7 +2579,6 @@ 1.40 #ifdef MIPS 1.41 void frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info = NULL); 1.42 #endif 1.43 - 1.44 void idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info); 1.45 void idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info); 1.46 void irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info);