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src/cpu/mips/vm/c1_Runtime1_mips.cpp@617b86d17edb
src/cpu/mips/vm/c1_Runtime1_mips.cpp
Tue, 04 Sep 2018 21:25:12 +0800
- author
- aoqi
- date
- Tue, 04 Sep 2018 21:25:12 +0800
- changeset 9228
- 617b86d17edb
- parent 9207
- 874b8588c4ae
- child 9248
- 610b27224729
- permissions
- -rw-r--r--
#7517 mRegP match a0_RegP
1 /*
2 * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_Defs.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "nativeInst_mips.hpp"
33 #include "oops/compiledICHolder.hpp"
34 #include "oops/oop.inline.hpp"
35 #include "prims/jvmtiExport.hpp"
36 #include "register_mips.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/signature.hpp"
39 #include "runtime/vframeArray.hpp"
40 #include "utilities/macros.hpp"
41 #include "vmreg_mips.inline.hpp"
42 #if INCLUDE_ALL_GCS
43 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
44 #endif
47 // Implementation of StubAssembler
48 // this method will preserve the stack space for arguments as indicated by args_size
49 // for stack alignment consideration, you cannot call this with argument in stack.
50 // if you need >3 arguments, you must implement this method yourself.
51 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
52 // i use S7 for edi.
53 // setup registers
54 const Register thread = TREG; // is callee-saved register (Visual C++ calling conventions)
55 assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result, "registers must be different");
56 assert(oop_result1 != thread && metadata_result != thread, "registers must be different");
57 assert(args_size >= 0, "illegal args_size");
58 bool align_stack = false;
59 #ifdef _LP64
60 // At a method handle call, the stack may not be properly aligned
61 // when returning with an exception.
62 align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id);
63 #endif
65 set_num_rt_args(1 + args_size);
68 // push java thread (becomes first argument of C function)
69 get_thread(thread);
70 move(A0, thread);
72 if(!align_stack) {
73 set_last_Java_frame(thread, NOREG, FP, NULL);
74 } else {
75 address the_pc = pc();
76 set_last_Java_frame(thread, NOREG, FP, the_pc);
77 move(AT, -(StackAlignmentInBytes));
78 andr(SP, SP, AT);
79 }
81 relocate(relocInfo::internal_pc_type);
82 {
83 #ifndef _LP64
84 int save_pc = (int)pc() + 12 + NativeCall::return_address_offset;
85 lui(AT, Assembler::split_high(save_pc));
86 addiu(AT, AT, Assembler::split_low(save_pc));
87 #else
88 uintptr_t save_pc = (uintptr_t)pc() + NativeMovConstReg::instruction_size + 1 * BytesPerInstWord + NativeCall::return_address_offset_long;
89 li48(AT, save_pc);
90 #endif
91 }
92 st_ptr(AT, thread, in_bytes(JavaThread::last_Java_pc_offset()));
94 // do the call
95 #ifndef _LP64
96 lui(T9, Assembler::split_high((int)entry));
97 addiu(T9, T9, Assembler::split_low((int)entry));
98 #else
99 li48(T9, (intptr_t)entry);
100 #endif
101 jalr(T9);
102 delayed()->nop();
104 int call_offset = offset();
106 // verify callee-saved register
107 #ifdef ASSERT
108 guarantee(thread != V0, "change this code");
109 push(V0);
110 {
111 Label L;
112 get_thread(V0);
113 beq(thread, V0, L);
114 delayed()->nop();
115 int3();
116 stop("StubAssembler::call_RT: edi not callee saved?");
117 bind(L);
118 }
119 super_pop(V0);
120 #endif
121 // discard thread and arguments
122 ld_ptr(SP, thread, in_bytes(JavaThread::last_Java_sp_offset()));
123 reset_last_Java_frame(thread, true);
124 // check for pending exceptions
125 {
126 Label L;
127 ld_ptr(AT, thread, in_bytes(Thread::pending_exception_offset()));
128 beq(AT, R0, L);
129 delayed()->nop();
130 // exception pending => remove activation and forward to exception handler
131 // make sure that the vm_results are cleared
132 if (oop_result1->is_valid()) {
133 st_ptr(R0, thread, in_bytes(JavaThread::vm_result_offset()));
134 }
135 if (metadata_result->is_valid()) {
136 st_ptr(R0, thread, in_bytes(JavaThread::vm_result_2_offset()));
137 }
138 // the leave() in x86 just pops ebp and remains the return address on the top
139 // of stack
140 // the return address will be needed by forward_exception_entry()
141 if (frame_size() == no_frame_size) {
142 addiu(SP, FP, wordSize);
143 ld_ptr(FP, SP, (-1) * wordSize);
144 jmp(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
145 delayed()->nop();
146 } else if (_stub_id == Runtime1::forward_exception_id) {
147 should_not_reach_here();
148 } else {
149 jmp(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type);
150 delayed()->nop();
151 }
152 bind(L);
153 }
154 // get oop results if there are any and reset the values in the thread
155 if (oop_result1->is_valid()) {
156 ld_ptr(oop_result1, thread, in_bytes(JavaThread::vm_result_offset()));
157 st_ptr(R0, thread, in_bytes(JavaThread::vm_result_offset()));
158 verify_oop(oop_result1);
159 }
160 if (metadata_result->is_valid()) {
161 ld_ptr(metadata_result, thread, in_bytes(JavaThread::vm_result_2_offset()));
162 st_ptr(R0, thread, in_bytes(JavaThread::vm_result_2_offset()));
163 verify_oop(metadata_result);
164 }
165 return call_offset;
166 }
169 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
170 if (arg1 != A1) move(A1, arg1);
171 return call_RT(oop_result1, metadata_result, entry, 1);
172 }
175 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
176 if (arg1!=A1) move(A1, arg1);
177 if (arg2!=A2) move(A2, arg2); assert(arg2 != A1, "smashed argument");
178 return call_RT(oop_result1, metadata_result, entry, 2);
179 }
182 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
183 if (arg1!=A1) move(A1, arg1);
184 if (arg2!=A2) move(A2, arg2); assert(arg2 != A1, "smashed argument");
185 if (arg3!=A3) move(A3, arg3); assert(arg3 != A1 && arg3 != A2, "smashed argument");
186 return call_RT(oop_result1, metadata_result, entry, 3);
187 }
190 // Implementation of StubFrame
192 class StubFrame: public StackObj {
193 private:
194 StubAssembler* _sasm;
196 public:
197 StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments);
198 void load_argument(int offset_in_words, Register reg);
200 ~StubFrame();
201 };
204 #define __ _sasm->
206 StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) {
207 _sasm = sasm;
208 __ set_info(name, must_gc_arguments);
209 __ enter();
210 }
213 //FIXME, I have no idea the frame architecture of mips
214 // load parameters that were stored with LIR_Assembler::store_parameter
215 // Note: offsets for store_parameter and load_argument must match
216 void StubFrame::load_argument(int offset_in_words, Register reg) {
217 //ebp + 0: link
218 // + 1: return address
219 // + 2: argument with offset 0
220 // + 3: argument with offset 1
221 // + 4: ...
222 __ ld_ptr(reg, Address(FP, (offset_in_words + 2) * BytesPerWord));
223 }
226 StubFrame::~StubFrame() {
227 __ leave();
228 __ jr(RA);
229 __ delayed()->nop();
230 }
232 #undef __
235 // Implementation of Runtime1
237 #define __ sasm->
239 //static OopMap* save_live_registers(MacroAssembler* sasm, int num_rt_args);
240 //static void restore_live_registers(MacroAssembler* sasm);
241 //DeoptimizationBlob* SharedRuntime::_deopt_blob = NULL;
242 /*
243 const int fpu_stack_as_doubles_size_in_words = 16;
244 const int fpu_stack_as_doubles_size = 64;
245 */
246 const int float_regs_as_doubles_size_in_words = 16;
248 //FIXME,
249 // Stack layout for saving/restoring all the registers needed during a runtime
250 // call (this includes deoptimization)
251 // Note: note that users of this frame may well have arguments to some runtime
252 // while these values are on the stack. These positions neglect those arguments
253 // but the code in save_live_registers will take the argument count into
254 // account.
255 //
256 #ifdef _LP64
257 #define SLOT2(x) x,
258 #define SLOT_PER_WORD 2
259 #else
260 #define SLOT2(x)
261 #define SLOT_PER_WORD 1
262 #endif // _LP64
264 enum reg_save_layout {
265 #ifndef _LP64
266 T0_off = 0,
267 S0_off = T0_off + SLOT_PER_WORD * 8,
268 #else
269 A4_off = 0,
270 S0_off = A4_off + SLOT_PER_WORD * 8,
271 #endif
272 FP_off = S0_off + SLOT_PER_WORD * 8, SLOT2(FPH_off)
273 T8_off, SLOT2(T8H_off)
274 T9_off, SLOT2(T9H_off)
275 SP_off, SLOT2(SPH_off)
276 V0_off, SLOT2(V0H_off)
277 V1_off, SLOT2(V1H_off)
278 A0_off, SLOT2(A0H_off)
279 A1_off, SLOT2(A1H_off)
280 A2_off, SLOT2(A2H_off)
281 A3_off, SLOT2(A3H_off)
283 // Float registers
284 /* FIXME: Jin: In MIPS64, F0~23 are all caller-saved registers */
285 F0_off, SLOT2( F0H_off)
286 F1_off, SLOT2( F1H_off)
287 F2_off, SLOT2( F2H_off)
288 F3_off, SLOT2( F3H_off)
289 F4_off, SLOT2( F4H_off)
290 F5_off, SLOT2( F5H_off)
291 F6_off, SLOT2( F6H_off)
292 F7_off, SLOT2( F7H_off)
293 F8_off, SLOT2( F8H_off)
294 F9_off, SLOT2( F9H_off)
295 F10_off, SLOT2( F10H_off)
296 F11_off, SLOT2( F11H_off)
297 F12_off, SLOT2( F12H_off)
298 F13_off, SLOT2( F13H_off)
299 F14_off, SLOT2( F14H_off)
300 F15_off, SLOT2( F15H_off)
301 F16_off, SLOT2( F16H_off)
302 F17_off, SLOT2( F17H_off)
303 F18_off, SLOT2( F18H_off)
304 F19_off, SLOT2( F19H_off)
306 GP_off, SLOT2( GPH_off)
307 //temp_2_off,
308 temp_1_off, SLOT2(temp_1H_off)
309 saved_fp_off, SLOT2(saved_fpH_off)
310 return_off, SLOT2(returnH_off)
312 reg_save_frame_size,
314 // illegal instruction handler
315 continue_dest_off = temp_1_off,
317 // deoptimization equates
318 //deopt_type = temp_2_off, // slot for type of deopt in progress
319 ret_type = temp_1_off // slot for return type
320 };
324 // Save off registers which might be killed by calls into the runtime.
325 // Tries to smart of about FP registers. In particular we separate
326 // saving and describing the FPU registers for deoptimization since we
327 // have to save the FPU registers twice if we describe them and on P4
328 // saving FPU registers which don't contain anything appears
329 // expensive. The deopt blob is the only thing which needs to
330 // describe FPU registers. In all other cases it should be sufficient
331 // to simply save their current value.
332 static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
333 bool save_fpu_registers = true, bool describe_fpu_registers = false) {
335 LP64_ONLY(num_rt_args = 0);
336 LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
337 int frame_size_in_slots = reg_save_frame_size + num_rt_args * wordSize / VMRegImpl::slots_per_word; // args + thread
338 sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word);
340 // record saved value locations in an OopMap
341 // locations are offsets from sp after runtime call; num_rt_args is number of arguments
342 // in call, including thread
343 OopMap* map = new OopMap(reg_save_frame_size, 0);
345 map->set_callee_saved(VMRegImpl::stack2reg(V0_off + num_rt_args), V0->as_VMReg());
346 map->set_callee_saved(VMRegImpl::stack2reg(V1_off + num_rt_args), V1->as_VMReg());
347 #ifdef _LP64
348 map->set_callee_saved(VMRegImpl::stack2reg(V0H_off + num_rt_args), V0->as_VMReg()->next());
349 map->set_callee_saved(VMRegImpl::stack2reg(V1H_off + num_rt_args), V1->as_VMReg()->next());
350 #endif
352 int i = 0;
353 #ifndef _LP64
354 for (Register r = T0; r != T7->successor(); r = r->successor() ) {
355 map->set_callee_saved(VMRegImpl::stack2reg(T0_off + num_rt_args + i++), r->as_VMReg());
356 }
357 #else
358 for (Register r = A4; r != T3->successor(); r = r->successor() ) {
359 map->set_callee_saved(VMRegImpl::stack2reg(A4_off + num_rt_args + i++), r->as_VMReg());
360 map->set_callee_saved(VMRegImpl::stack2reg(A4_off + num_rt_args + i++), r->as_VMReg()->next());
361 }
362 #endif
364 i = 0;
365 for (Register r = S0; r != S7->successor(); r = r->successor() ) {
366 map->set_callee_saved(VMRegImpl::stack2reg(S0_off + num_rt_args + i++), r->as_VMReg());
367 #ifdef _LP64
368 map->set_callee_saved(VMRegImpl::stack2reg(S0_off + num_rt_args + i++), r->as_VMReg()->next());
369 #endif
370 }
372 map->set_callee_saved(VMRegImpl::stack2reg(FP_off + num_rt_args), FP->as_VMReg());
373 map->set_callee_saved(VMRegImpl::stack2reg(GP_off + num_rt_args), GP->as_VMReg());
374 map->set_callee_saved(VMRegImpl::stack2reg(T8_off + num_rt_args), T8->as_VMReg());
375 map->set_callee_saved(VMRegImpl::stack2reg(T9_off + num_rt_args), T9->as_VMReg());
376 map->set_callee_saved(VMRegImpl::stack2reg(A0_off + num_rt_args), A0->as_VMReg());
377 map->set_callee_saved(VMRegImpl::stack2reg(A1_off + num_rt_args), A1->as_VMReg());
378 map->set_callee_saved(VMRegImpl::stack2reg(A2_off + num_rt_args), A2->as_VMReg());
379 map->set_callee_saved(VMRegImpl::stack2reg(A3_off + num_rt_args), A3->as_VMReg());
381 map->set_callee_saved(VMRegImpl::stack2reg(F0_off + num_rt_args), F0->as_VMReg());
382 map->set_callee_saved(VMRegImpl::stack2reg(F1_off + num_rt_args), F1->as_VMReg());
383 map->set_callee_saved(VMRegImpl::stack2reg(F2_off + num_rt_args), F2->as_VMReg());
384 map->set_callee_saved(VMRegImpl::stack2reg(F3_off + num_rt_args), F1->as_VMReg());
385 map->set_callee_saved(VMRegImpl::stack2reg(F4_off + num_rt_args), F4->as_VMReg());
386 map->set_callee_saved(VMRegImpl::stack2reg(F5_off + num_rt_args), F4->as_VMReg());
387 map->set_callee_saved(VMRegImpl::stack2reg(F6_off + num_rt_args), F4->as_VMReg());
388 map->set_callee_saved(VMRegImpl::stack2reg(F7_off + num_rt_args), F4->as_VMReg());
389 map->set_callee_saved(VMRegImpl::stack2reg(F8_off + num_rt_args), F4->as_VMReg());
390 map->set_callee_saved(VMRegImpl::stack2reg(F9_off + num_rt_args), F4->as_VMReg());
391 map->set_callee_saved(VMRegImpl::stack2reg(F10_off + num_rt_args), F4->as_VMReg());
392 map->set_callee_saved(VMRegImpl::stack2reg(F11_off + num_rt_args), F4->as_VMReg());
393 map->set_callee_saved(VMRegImpl::stack2reg(F12_off + num_rt_args), F12->as_VMReg());
394 map->set_callee_saved(VMRegImpl::stack2reg(F13_off + num_rt_args), F13->as_VMReg());
395 map->set_callee_saved(VMRegImpl::stack2reg(F14_off + num_rt_args), F14->as_VMReg());
396 map->set_callee_saved(VMRegImpl::stack2reg(F15_off + num_rt_args), F15->as_VMReg());
397 map->set_callee_saved(VMRegImpl::stack2reg(F16_off + num_rt_args), F16->as_VMReg());
398 map->set_callee_saved(VMRegImpl::stack2reg(F17_off + num_rt_args), F17->as_VMReg());
399 map->set_callee_saved(VMRegImpl::stack2reg(F18_off + num_rt_args), F18->as_VMReg());
400 map->set_callee_saved(VMRegImpl::stack2reg(F19_off + num_rt_args), F19->as_VMReg());
402 #ifdef _LP64
403 map->set_callee_saved(VMRegImpl::stack2reg(FPH_off + num_rt_args), FP->as_VMReg()->next());
404 map->set_callee_saved(VMRegImpl::stack2reg(GPH_off + num_rt_args), GP->as_VMReg()->next());
405 map->set_callee_saved(VMRegImpl::stack2reg(T8H_off + num_rt_args), T8->as_VMReg()->next());
406 map->set_callee_saved(VMRegImpl::stack2reg(T9H_off + num_rt_args), T9->as_VMReg()->next());
407 map->set_callee_saved(VMRegImpl::stack2reg(A0H_off + num_rt_args), A0->as_VMReg()->next());
408 map->set_callee_saved(VMRegImpl::stack2reg(A1H_off + num_rt_args), A1->as_VMReg()->next());
409 map->set_callee_saved(VMRegImpl::stack2reg(A2H_off + num_rt_args), A2->as_VMReg()->next());
410 map->set_callee_saved(VMRegImpl::stack2reg(A3H_off + num_rt_args), A3->as_VMReg()->next());
411 #endif
412 return map;
413 }
415 static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
416 bool save_fpu_registers = true,
417 bool describe_fpu_registers = false) {
418 //const int reg_save_frame_size = return_off + 1 + num_rt_args;
419 __ block_comment("save_live_registers");
421 // save all register state - int, fpu
422 __ addi(SP, SP, -(reg_save_frame_size / SLOT_PER_WORD - 2)* wordSize);
424 #ifndef _LP64
425 for (Register r = T0; r != T7->successor(); r = r->successor() ) {
426 __ sw(r, SP, (r->encoding() - T0->encoding() + T0_off / SLOT_PER_WORD) * wordSize);
427 #else
428 for (Register r = A4; r != T3->successor(); r = r->successor() ) {
429 __ sd(r, SP, (r->encoding() - A4->encoding() + A4_off / SLOT_PER_WORD) * wordSize);
430 #endif
431 }
432 for (Register r = S0; r != S7->successor(); r = r->successor() ) {
433 __ st_ptr(r, SP, (r->encoding() - S0->encoding() + S0_off / SLOT_PER_WORD) * wordSize);
434 }
435 __ st_ptr(FP, SP, FP_off * wordSize / SLOT_PER_WORD);
436 __ st_ptr(GP, SP, GP_off * wordSize / SLOT_PER_WORD);
437 __ st_ptr(T8, SP, T8_off * wordSize / SLOT_PER_WORD);
438 __ st_ptr(T9, SP, T9_off * wordSize / SLOT_PER_WORD);
439 __ st_ptr(A0, SP, A0_off * wordSize / SLOT_PER_WORD);
440 __ st_ptr(A1, SP, A1_off * wordSize / SLOT_PER_WORD);
441 __ st_ptr(A2, SP, A2_off * wordSize / SLOT_PER_WORD);
442 __ st_ptr(A3, SP, A3_off * wordSize / SLOT_PER_WORD);
443 __ st_ptr(V0, SP, V0_off * wordSize / SLOT_PER_WORD);
444 __ st_ptr(V1, SP, V1_off * wordSize / SLOT_PER_WORD);
446 __ sdc1(F0, SP, F0_off * wordSize / SLOT_PER_WORD);
447 __ sdc1(F1, SP, F1_off * wordSize / SLOT_PER_WORD);
448 __ sdc1(F2, SP, F2_off * wordSize / SLOT_PER_WORD);
449 __ sdc1(F3, SP, F3_off * wordSize / SLOT_PER_WORD);
450 __ sdc1(F4, SP, F4_off * wordSize / SLOT_PER_WORD);
451 __ sdc1(F5, SP, F5_off * wordSize / SLOT_PER_WORD);
452 __ sdc1(F6, SP, F6_off * wordSize / SLOT_PER_WORD);
453 __ sdc1(F7, SP, F7_off * wordSize / SLOT_PER_WORD);
454 __ sdc1(F8, SP, F8_off * wordSize / SLOT_PER_WORD);
455 __ sdc1(F9, SP, F9_off * wordSize / SLOT_PER_WORD);
456 __ sdc1(F10, SP, F10_off * wordSize / SLOT_PER_WORD);
457 __ sdc1(F11, SP, F11_off * wordSize / SLOT_PER_WORD);
458 __ sdc1(F12, SP, F12_off * wordSize / SLOT_PER_WORD);
459 __ sdc1(F13, SP, F13_off * wordSize / SLOT_PER_WORD);
460 __ sdc1(F14, SP, F14_off * wordSize / SLOT_PER_WORD);
461 __ sdc1(F15, SP, F15_off * wordSize / SLOT_PER_WORD);
462 __ sdc1(F16, SP, F16_off * wordSize / SLOT_PER_WORD);
463 __ sdc1(F17, SP, F17_off * wordSize / SLOT_PER_WORD);
464 __ sdc1(F18, SP, F18_off * wordSize / SLOT_PER_WORD);
465 __ sdc1(F19, SP, F19_off * wordSize / SLOT_PER_WORD);
467 return generate_oop_map(sasm, num_rt_args, save_fpu_registers, describe_fpu_registers);
468 }
470 static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true) {
471 //static void restore_live_registers(MacroAssembler* sasm) {
472 #ifndef _LP64
473 for (Register r = T0; r != T7->successor(); r = r->successor() ) {
474 __ lw(r, SP, (r->encoding() - T0->encoding() + T0_off / SLOT_PER_WORD) * wordSize);
475 #else
476 for (Register r = A4; r != T3->successor(); r = r->successor() ) {
477 __ ld(r, SP, (r->encoding() - A4->encoding() + A4_off / SLOT_PER_WORD) * wordSize);
478 #endif
479 }
480 for (Register r = S0; r != S7->successor(); r = r->successor() ) {
481 __ ld_ptr(r, SP, (r->encoding() - S0->encoding() + S0_off / SLOT_PER_WORD) * wordSize);
482 }
483 __ ld_ptr(FP, SP, FP_off * wordSize / SLOT_PER_WORD);
484 __ ld_ptr(GP, SP, GP_off * wordSize / SLOT_PER_WORD);
486 __ ld_ptr(T8, SP, T8_off * wordSize / SLOT_PER_WORD);
487 __ ld_ptr(T9, SP, T9_off * wordSize / SLOT_PER_WORD);
488 __ ld_ptr(A0, SP, A0_off * wordSize / SLOT_PER_WORD);
489 __ ld_ptr(A1, SP, A1_off * wordSize / SLOT_PER_WORD);
490 __ ld_ptr(A2, SP, A2_off * wordSize / SLOT_PER_WORD);
491 __ ld_ptr(A3, SP, A3_off * wordSize / SLOT_PER_WORD);
493 __ ld_ptr(V0, SP, V0_off * wordSize / SLOT_PER_WORD);
494 __ ld_ptr(V1, SP, V1_off * wordSize / SLOT_PER_WORD);
496 __ ldc1(F0, SP, F0_off * wordSize / SLOT_PER_WORD);
497 __ ldc1(F1, SP, F1_off * wordSize / SLOT_PER_WORD);
498 __ ldc1(F2, SP, F2_off * wordSize / SLOT_PER_WORD);
499 __ ldc1(F3, SP, F3_off * wordSize / SLOT_PER_WORD);
500 __ ldc1(F4, SP, F4_off * wordSize / SLOT_PER_WORD);
501 __ ldc1(F5, SP, F5_off * wordSize / SLOT_PER_WORD);
502 __ ldc1(F6, SP, F6_off * wordSize / SLOT_PER_WORD);
503 __ ldc1(F7, SP, F7_off * wordSize / SLOT_PER_WORD);
504 __ ldc1(F8, SP, F8_off * wordSize / SLOT_PER_WORD);
505 __ ldc1(F9, SP, F9_off * wordSize / SLOT_PER_WORD);
506 __ ldc1(F10, SP, F10_off * wordSize / SLOT_PER_WORD);
507 __ ldc1(F11, SP, F11_off * wordSize / SLOT_PER_WORD);
508 __ ldc1(F12, SP, F12_off * wordSize / SLOT_PER_WORD);
509 __ ldc1(F13, SP, F13_off * wordSize / SLOT_PER_WORD);
510 __ ldc1(F14, SP, F14_off * wordSize / SLOT_PER_WORD);
511 __ ldc1(F15, SP, F15_off * wordSize / SLOT_PER_WORD);
512 __ ldc1(F16, SP, F16_off * wordSize / SLOT_PER_WORD);
513 __ ldc1(F17, SP, F17_off * wordSize / SLOT_PER_WORD);
514 __ ldc1(F18, SP, F18_off * wordSize / SLOT_PER_WORD);
515 __ ldc1(F19, SP, F19_off * wordSize / SLOT_PER_WORD);
517 __ addiu(SP, SP, (reg_save_frame_size / SLOT_PER_WORD - 2) * wordSize);
518 }
520 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) {
521 __ block_comment("restore_live_registers");
522 restore_fpu(sasm, restore_fpu_registers);
523 }
525 static void restore_live_registers_except_V0(StubAssembler* sasm, bool restore_fpu_registers = true) {
526 //static void restore_live_registers(MacroAssembler* sasm) {
527 //FIXME , maybe V1 need to be saved too
528 __ block_comment("restore_live_registers except V0");
529 #ifndef _LP64
530 for (Register r = T0; r != T7->successor(); r = r->successor() ) {
531 __ lw(r, SP, (r->encoding() - T0->encoding() + T0_off / SLOT_PER_WORD) * wordSize);
532 #else
533 for (Register r = A4; r != T3->successor(); r = r->successor() ) {
534 __ ld(r, SP, (r->encoding() - A4->encoding() + A4_off / SLOT_PER_WORD) * wordSize);
535 #endif
536 }
537 for (Register r = S0; r != S7->successor(); r = r->successor() ) {
538 __ ld_ptr(r, SP, (r->encoding() - S0->encoding() + S0_off / SLOT_PER_WORD) * wordSize);
539 }
540 __ ld_ptr(FP, SP, FP_off * wordSize / SLOT_PER_WORD);
541 __ ld_ptr(GP, SP, GP_off * wordSize / SLOT_PER_WORD);
543 __ ld_ptr(T8, SP, T8_off * wordSize / SLOT_PER_WORD);
544 __ ld_ptr(T9, SP, T9_off * wordSize / SLOT_PER_WORD);
545 __ ld_ptr(A0, SP, A0_off * wordSize / SLOT_PER_WORD);
546 __ ld_ptr(A1, SP, A1_off * wordSize / SLOT_PER_WORD);
547 __ ld_ptr(A2, SP, A2_off * wordSize / SLOT_PER_WORD);
548 __ ld_ptr(A3, SP, A3_off * wordSize / SLOT_PER_WORD);
550 #if 1
551 __ ldc1(F0, SP, F0_off * wordSize / SLOT_PER_WORD);
552 __ ldc1(F1, SP, F1_off * wordSize / SLOT_PER_WORD);
553 __ ldc1(F2, SP, F2_off * wordSize / SLOT_PER_WORD);
554 __ ldc1(F3, SP, F3_off * wordSize / SLOT_PER_WORD);
555 __ ldc1(F4, SP, F4_off * wordSize / SLOT_PER_WORD);
556 __ ldc1(F5, SP, F5_off * wordSize / SLOT_PER_WORD);
557 __ ldc1(F6, SP, F6_off * wordSize / SLOT_PER_WORD);
558 __ ldc1(F7, SP, F7_off * wordSize / SLOT_PER_WORD);
559 __ ldc1(F8, SP, F8_off * wordSize / SLOT_PER_WORD);
560 __ ldc1(F9, SP, F9_off * wordSize / SLOT_PER_WORD);
561 __ ldc1(F10, SP, F10_off * wordSize / SLOT_PER_WORD);
562 __ ldc1(F11, SP, F11_off * wordSize / SLOT_PER_WORD);
563 __ ldc1(F12, SP, F12_off * wordSize / SLOT_PER_WORD);
564 __ ldc1(F13, SP, F13_off * wordSize / SLOT_PER_WORD);
565 __ ldc1(F14, SP, F14_off * wordSize / SLOT_PER_WORD);
566 __ ldc1(F15, SP, F15_off * wordSize / SLOT_PER_WORD);
567 __ ldc1(F16, SP, F16_off * wordSize / SLOT_PER_WORD);
568 __ ldc1(F17, SP, F17_off * wordSize / SLOT_PER_WORD);
569 __ ldc1(F18, SP, F18_off * wordSize / SLOT_PER_WORD);
570 __ ldc1(F19, SP, F19_off * wordSize / SLOT_PER_WORD);
571 #endif
573 __ ld_ptr(V1, SP, V1_off * wordSize / SLOT_PER_WORD);
575 __ addiu(SP, SP, (reg_save_frame_size / SLOT_PER_WORD - 2) * wordSize);
576 }
578 void Runtime1::initialize_pd() {
579 // nothing to do
580 }
582 // target: the entry point of the method that creates and posts the exception oop
583 // has_argument: true if the exception needs an argument (passed on stack because registers must be preserved)
584 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
585 // preserve all registers
586 OopMap* oop_map = save_live_registers(sasm, 0);
588 // now all registers are saved and can be used freely
589 // verify that no old value is used accidentally
590 //all reigster are saved , I think mips do not need this
592 // registers used by this stub
593 const Register temp_reg = T3;
594 // load argument for exception that is passed as an argument into the stub
595 if (has_argument) {
596 __ ld_ptr(temp_reg, Address(FP, 2*BytesPerWord));
597 }
598 int call_offset;
599 if (has_argument)
600 call_offset = __ call_RT(noreg, noreg, target, temp_reg);
601 else
602 call_offset = __ call_RT(noreg, noreg, target);
604 OopMapSet* oop_maps = new OopMapSet();
605 oop_maps->add_gc_map(call_offset, oop_map);
607 __ stop("should not reach here");
609 return oop_maps;
610 }
612 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
613 __ block_comment("generate_handle_exception");
615 // incoming parameters
616 const Register exception_oop = V0;
617 const Register exception_pc = V1;
618 // other registers used in this stub
619 const Register thread = TREG;
620 #ifndef OPT_THREAD
621 __ get_thread(thread);
622 #endif
623 // Save registers, if required.
624 OopMapSet* oop_maps = new OopMapSet();
625 OopMap* oop_map = NULL;
626 switch (id) {
627 case forward_exception_id:
628 // We're handling an exception in the context of a compiled frame.
629 // The registers have been saved in the standard places. Perform
630 // an exception lookup in the caller and dispatch to the handler
631 // if found. Otherwise unwind and dispatch to the callers
632 // exception handler.
633 oop_map = generate_oop_map(sasm, 1 /*thread*/);
635 // load and clear pending exception oop into RAX
636 __ ld_ptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
637 __ st_ptr(R0, Address(thread, Thread::pending_exception_offset()));
639 // load issuing PC (the return address for this stub) into rdx
640 __ ld_ptr(exception_pc, Address(FP, 1*BytesPerWord));
642 // make sure that the vm_results are cleared (may be unnecessary)
643 __ st_ptr(R0, Address(thread, JavaThread::vm_result_offset()));
644 __ st_ptr(R0, Address(thread, JavaThread::vm_result_2_offset()));
645 break;
646 case handle_exception_nofpu_id:
647 case handle_exception_id:
648 // At this point all registers MAY be live.
649 oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id);
650 break;
651 case handle_exception_from_callee_id: {
652 // At this point all registers except exception oop (RAX) and
653 // exception pc (RDX) are dead.
654 const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/);
655 oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0);
656 sasm->set_frame_size(frame_size);
657 break;
658 }
659 default: ShouldNotReachHere();
660 }
662 #ifdef TIERED
663 // C2 can leave the fpu stack dirty
664 __ empty_FPU_stack();
665 #endif // TIERED
667 // verify that only V0 and V1 is valid at this time
668 // verify that V0 contains a valid exception
669 __ verify_not_null_oop(exception_oop);
671 // load address of JavaThread object for thread-local data
672 __ get_thread(thread);
674 #ifdef ASSERT
675 // check that fields in JavaThread for exception oop and issuing pc are
676 // empty before writing to them
677 Label oop_empty;
678 __ ld_ptr(AT, Address(thread, in_bytes(JavaThread::exception_oop_offset())));
679 __ beq(AT, R0, oop_empty);
680 __ delayed()->nop();
681 __ stop("exception oop already set");
682 __ bind(oop_empty);
684 Label pc_empty;
685 __ ld_ptr(AT, Address(thread, in_bytes(JavaThread::exception_pc_offset())));
686 __ beq(AT, R0, pc_empty);
687 __ delayed()->nop();
688 __ stop("exception pc already set");
689 __ bind(pc_empty);
690 #endif
692 // save exception oop and issuing pc into JavaThread
693 // (exception handler will load it from here)
694 __ st_ptr(exception_oop, Address(thread, in_bytes(JavaThread::exception_oop_offset())));
695 __ st_ptr(exception_pc, Address(thread, in_bytes(JavaThread::exception_pc_offset())));
697 // patch throwing pc into return address (has bci & oop map)
698 __ st_ptr(exception_pc, Address(FP, 1*BytesPerWord));
700 // compute the exception handler.
701 // the exception oop and the throwing pc are read from the fields in JavaThread
702 __ block_comment(";; will call_RT exception_handler_for_pc");
703 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
704 oop_maps->add_gc_map(call_offset, oop_map);
705 __ block_comment(";; end of call_RT exception_handler_for_pc");
707 // V0: handler address or NULL if no handler exists
708 // will be the deopt blob if nmethod was deoptimized while we looked up
709 // handler regardless of whether handler existed in the nmethod.
711 // only V0 is valid at this time, all other registers have been destroyed by the
712 // runtime call
714 // patch the return address -> the stub will directly return to the exception handler
715 __ st_ptr(V0, Address(FP, 1 * BytesPerWord));
717 switch (id) {
718 case forward_exception_id:
719 case handle_exception_nofpu_id:
720 case handle_exception_id:
721 // Restore the registers that were saved at the beginning.
722 restore_live_registers(sasm, id != handle_exception_nofpu_id);
723 break;
724 case handle_exception_from_callee_id:
725 // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP
726 // since we do a leave anyway.
728 // Pop the return address since we are possibly changing SP (restoring from BP).
729 __ move(SP, FP);
730 __ pop(FP);
731 __ pop(RA);
732 __ jr(RA); // jump to exception handler
733 __ delayed()->nop();
734 break;
735 default: ShouldNotReachHere();
736 }
738 return oop_maps;
739 }
745 void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
746 // incoming parameters
747 const Register exception_oop = V0;
748 // callee-saved copy of exception_oop during runtime call
749 const Register exception_oop_callee_saved = S0;
750 // other registers used in this stub
751 const Register exception_pc = V1;
752 const Register handler_addr = T3;
753 const Register thread = TREG;
755 // verify that only eax is valid at this time
756 // __ invalidate_registers(false, true, true, true, true, true);
758 #ifdef ASSERT
759 // check that fields in JavaThread for exception oop and issuing pc are empty
760 __ get_thread(thread);
761 Label oop_empty;
762 __ ld_ptr(AT, thread, in_bytes(JavaThread::exception_oop_offset()));
763 __ beq(AT, R0, oop_empty);
764 __ delayed()->nop();
765 __ stop("exception oop must be empty");
766 __ bind(oop_empty);
768 Label pc_empty;
769 __ ld_ptr(AT, thread, in_bytes(JavaThread::exception_pc_offset()));
770 __ beq(AT, R0, pc_empty);
771 __ delayed()->nop();
772 __ stop("exception pc must be empty");
773 __ bind(pc_empty);
774 #endif
775 // clear the FPU stack in case any FPU results are left behind
776 __ empty_FPU_stack();
778 // save exception_oop in callee-saved register to preserve it during runtime calls
779 __ verify_not_null_oop(exception_oop);
780 __ move(exception_oop_callee_saved, exception_oop);
782 #ifndef OPT_THREAD
783 __ get_thread(thread);
784 #endif
785 // Get return address (is in RA after leave).
787 __ move(exception_pc, RA);
788 __ push(RA);
790 // search the exception handler address of the caller (using the return address)
791 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
792 // V0: exception handler address of the caller
794 // only eax is valid at this time, all other registers have been destroyed by the call
796 // move result of call into correct register
797 __ move(handler_addr, V0);
799 // Restore exception oop to V0 (required convention of exception handler).
800 __ move(exception_oop, exception_oop_callee_saved);
802 // verify that there is really a valid exception in V0
803 __ verify_oop(exception_oop);
805 // get throwing pc (= return address).
806 // V1 has been destroyed by the call, so it must be set again
807 // the pop is also necessary to simulate the effect of a ret(0)
808 __ super_pop(exception_pc);
810 // continue at exception handler (return address removed)
811 // note: do *not* remove arguments when unwinding the
812 // activation since the caller assumes having
813 // all arguments on the stack when entering the
814 // runtime to determine the exception handler
815 // (GC happens at call site with arguments!)
816 // V0: exception oop
817 // V1: throwing pc
818 // T3: exception handler
819 __ jr(handler_addr);
820 __ delayed()->nop();
821 }
826 //static address deopt_with_exception_entry_for_patch = NULL;
828 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
830 // use the maximum number of runtime-arguments here because it is difficult to
831 // distinguish each RT-Call.
832 // Note: This number affects also the RT-Call in generate_handle_exception because
833 // the oop-map is shared for all calls.
835 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
836 assert(deopt_blob != NULL, "deoptimization blob must have been created");
837 // assert(deopt_with_exception_entry_for_patch != NULL,
838 // "deoptimization blob must have been created");
840 //OopMap* oop_map = save_live_registers(sasm, num_rt_args);
841 OopMap* oop_map = save_live_registers(sasm, 0);
842 const Register thread = T8;
843 // push java thread (becomes first argument of C function)
844 __ get_thread(thread);
845 __ move(A0, thread);
848 /*
849 * NOTE: this frame should be compiled frame, but at this point, the pc in frame-anchor
850 * is contained in interpreter. It should be wrong, and should be cleared but is not.
851 * even if we cleared the wrong pc in anchor, the default way to get caller pc in class frame
852 * is not right. It depends on that the caller pc is stored in *(sp - 1) but it's not the case
853 */
854 __ set_last_Java_frame(thread, NOREG, FP, NULL);
855 NOT_LP64(__ addiu(SP, SP, (-1) * wordSize));
856 __ move(AT, -(StackAlignmentInBytes));
857 __ andr(SP, SP, AT);
858 __ relocate(relocInfo::internal_pc_type);
859 {
860 #ifndef _LP64
861 int save_pc = (int)__ pc() + 12 + NativeCall::return_address_offset;
862 __ lui(AT, Assembler::split_high(save_pc));
863 __ addiu(AT, AT, Assembler::split_low(save_pc));
864 #else
865 uintptr_t save_pc = (uintptr_t)__ pc() + NativeMovConstReg::instruction_size + 1 * BytesPerInstWord + NativeCall::return_address_offset_long;
866 __ li48(AT, save_pc);
867 #endif
868 }
869 __ st_ptr(AT, thread, in_bytes(JavaThread::last_Java_pc_offset()));
871 // do the call
872 #ifndef _LP64
873 __ lui(T9, Assembler::split_high((int)target));
874 __ addiu(T9, T9, Assembler::split_low((int)target));
875 #else
876 __ li48(T9, (intptr_t)target);
877 #endif
878 __ jalr(T9);
879 __ delayed()->nop();
880 OopMapSet* oop_maps = new OopMapSet();
881 oop_maps->add_gc_map(__ offset(), oop_map);
883 __ get_thread(thread);
885 __ ld_ptr (SP, thread, in_bytes(JavaThread::last_Java_sp_offset()));
886 __ reset_last_Java_frame(thread, true);
887 // discard thread arg
888 // check for pending exceptions
889 {
890 Label L, skip;
891 //Label no_deopt;
892 __ ld_ptr(AT, thread, in_bytes(Thread::pending_exception_offset()));
893 __ beq(AT, R0, L);
894 __ delayed()->nop();
895 // exception pending => remove activation and forward to exception handler
897 __ bne(V0, R0, skip);
898 __ delayed()->nop();
899 __ jmp(Runtime1::entry_for(Runtime1::forward_exception_id),
900 relocInfo::runtime_call_type);
901 __ delayed()->nop();
902 __ bind(skip);
904 // the deopt blob expects exceptions in the special fields of
905 // JavaThread, so copy and clear pending exception.
907 // load and clear pending exception
908 __ ld_ptr(V0, Address(thread,in_bytes(Thread::pending_exception_offset())));
909 __ st_ptr(R0, Address(thread, in_bytes(Thread::pending_exception_offset())));
911 // check that there is really a valid exception
912 __ verify_not_null_oop(V0);
914 // load throwing pc: this is the return address of the stub
915 __ ld_ptr(V1, Address(SP, return_off * BytesPerWord));
918 #ifdef ASSERT
919 // check that fields in JavaThread for exception oop and issuing pc are empty
920 Label oop_empty;
921 __ ld_ptr(AT, Address(thread, in_bytes(JavaThread::exception_oop_offset())));
922 __ beq(AT,R0,oop_empty);
923 __ delayed()->nop();
924 __ stop("exception oop must be empty");
925 __ bind(oop_empty);
927 Label pc_empty;
928 __ ld_ptr(AT, Address(thread, in_bytes(JavaThread::exception_pc_offset())));
929 __ beq(AT,R0,pc_empty);
930 __ delayed()->nop();
931 __ stop("exception pc must be empty");
932 __ bind(pc_empty);
933 #endif
935 // store exception oop and throwing pc to JavaThread
936 __ st_ptr(V0,Address(thread, in_bytes(JavaThread::exception_oop_offset())));
937 __ st_ptr(V1,Address(thread, in_bytes(JavaThread::exception_pc_offset())));
939 restore_live_registers(sasm);
941 __ leave();
943 // Forward the exception directly to deopt blob. We can blow no
944 // registers and must leave throwing pc on the stack. A patch may
945 // have values live in registers so the entry point with the
946 // exception in tls.
947 __ jmp(deopt_blob->unpack_with_exception_in_tls(), relocInfo::runtime_call_type);
948 __ delayed()->nop();
950 __ bind(L);
951 }
953 // Runtime will return true if the nmethod has been deoptimized during
954 // the patching process. In that case we must do a deopt reexecute instead.
956 Label reexecuteEntry, cont;
958 __ beq(V0, R0, cont); // have we deoptimized?
959 __ delayed()->nop();
961 // Will reexecute. Proper return address is already on the stack we just restore
962 // registers, pop all of our frame but the return address and jump to the deopt blob
963 restore_live_registers(sasm);
965 __ leave();
966 __ jmp(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type);
967 __ delayed()->nop();
969 __ bind(cont);
970 restore_live_registers(sasm);
972 __ leave();
973 __ jr(RA);
974 __ delayed()->nop();
976 return oop_maps;
977 }
980 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
981 // for better readability
982 const bool must_gc_arguments = true;
983 const bool dont_gc_arguments = false;
986 // default value; overwritten for some optimized stubs that are called
987 // from methods that do not use the fpu
988 bool save_fpu_registers = true;
991 // stub code & info for the different stubs
992 OopMapSet* oop_maps = NULL;
994 switch (id) {
995 case forward_exception_id:
996 {
997 oop_maps = generate_handle_exception(id, sasm);
998 __ leave();
999 __ jr(RA);
1000 __ delayed()->nop();
1001 }
1002 break;
1004 case new_instance_id:
1005 case fast_new_instance_id:
1006 case fast_new_instance_init_check_id:
1007 {
1008 Register klass = A4; // Incoming
1009 Register obj = V0; // Result
1011 if (id == new_instance_id) {
1012 __ set_info("new_instance", dont_gc_arguments);
1013 } else if (id == fast_new_instance_id) {
1014 __ set_info("fast new_instance", dont_gc_arguments);
1015 } else {
1016 assert(id == fast_new_instance_init_check_id, "bad StubID");
1017 __ set_info("fast new_instance init check", dont_gc_arguments);
1018 }
1020 if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id)
1021 && UseTLAB && FastTLABRefill) {
1022 Label slow_path;
1023 Register obj_size = T0;
1024 Register t1 = T2;
1025 Register t2 = T3;
1026 assert_different_registers(klass, obj, obj_size, t1, t2);
1027 if (id == fast_new_instance_init_check_id) {
1028 // make sure the klass is initialized
1029 __ ld_ptr(AT, Address(klass, in_bytes(InstanceKlass::init_state_offset())));
1030 __ move(t1, InstanceKlass::fully_initialized);
1031 __ bne(AT, t1, slow_path);
1032 __ delayed()->nop();
1033 }
1034 #ifdef ASSERT
1035 // assert object can be fast path allocated
1036 {
1037 Label ok, not_ok;
1038 __ lw(obj_size, klass, in_bytes(Klass::layout_helper_offset()));
1039 __ blez(obj_size, not_ok);
1040 __ delayed()->nop();
1041 __ andi(t1 , obj_size, Klass::_lh_instance_slow_path_bit);
1042 __ beq(t1, R0, ok);
1043 __ delayed()->nop();
1044 __ bind(not_ok);
1045 __ stop("assert(can be fast path allocated)");
1046 __ should_not_reach_here();
1047 __ bind(ok);
1048 }
1049 #endif // ASSERT
1050 // if we got here then the TLAB allocation failed, so try
1051 // refilling the TLAB or allocating directly from eden.
1053 Label retry_tlab, try_eden;
1054 __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy edx (klass)
1056 __ bind(retry_tlab);
1058 // get the instance size
1059 __ lw(obj_size, klass, in_bytes(Klass::layout_helper_offset()));
1060 __ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path);
1061 __ initialize_object(obj, klass, obj_size, 0, t1, t2);
1062 __ verify_oop(obj);
1063 __ jr(RA);
1064 __ delayed()->nop();
1066 #ifndef OPT_THREAD
1067 const Register thread = T8;
1068 __ get_thread(thread);
1069 #else
1070 const Register thread = TREG;
1071 #endif
1073 __ bind(try_eden);
1075 // get the instance size
1076 __ lw(obj_size, klass, in_bytes(Klass::layout_helper_offset()));
1077 __ eden_allocate(obj, obj_size, 0, t1, t2, slow_path);
1078 __ incr_allocated_bytes(thread, obj_size, 0);
1080 __ initialize_object(obj, klass, obj_size, 0, t1, t2);
1081 __ verify_oop(obj);
1082 __ jr(RA);
1083 __ delayed()->nop();
1085 __ bind(slow_path);
1086 }
1087 __ enter();
1088 OopMap* map = save_live_registers(sasm, 0);
1089 int call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
1090 oop_maps = new OopMapSet();
1091 oop_maps->add_gc_map(call_offset, map);
1092 restore_live_registers_except_V0(sasm);
1093 __ verify_oop(obj);
1094 __ leave();
1095 __ jr(RA);
1096 __ delayed()->nop();
1098 // V0: new instance
1099 }
1100 break;
1103 #ifdef TIERED
1104 //FIXME, I hava no idea which register to use
1105 case counter_overflow_id:
1106 {
1107 #ifndef _LP64
1108 Register bci = T5;
1109 #else
1110 Register bci = A5;
1111 #endif
1112 Register method = AT;
1113 __ enter();
1114 OopMap* map = save_live_registers(sasm, 0);
1115 // Retrieve bci
1116 __ lw(bci, Address(FP, 2*BytesPerWord));// FIXME:wuhui.ebp==??
1117 __ ld(method, Address(FP, 3*BytesPerWord));
1118 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method);
1119 oop_maps = new OopMapSet();
1120 oop_maps->add_gc_map(call_offset, map);
1121 restore_live_registers(sasm);
1122 __ leave();
1123 __ jr(RA);
1124 __ delayed()->nop();
1125 }
1126 break;
1127 #endif // TIERED
1131 case new_type_array_id:
1132 case new_object_array_id:
1133 {
1134 // i use T2 as length register, T4 as klass register, V0 as result register.
1135 // MUST accord with NewTypeArrayStub::emit_code, NewObjectArrayStub::emit_code
1136 Register length = T2; // Incoming
1137 #ifndef _LP64
1138 Register klass = T4; // Incoming
1139 #else
1140 Register klass = A4; // Incoming
1141 #endif
1142 Register obj = V0; // Result
1144 if (id == new_type_array_id) {
1145 __ set_info("new_type_array", dont_gc_arguments);
1146 } else {
1147 __ set_info("new_object_array", dont_gc_arguments);
1148 }
1150 if (UseTLAB && FastTLABRefill) {
1151 Register arr_size = T0;
1152 Register t1 = T1;
1153 Register t2 = T3;
1154 Label slow_path;
1155 assert_different_registers(length, klass, obj, arr_size, t1, t2);
1157 // check that array length is small enough for fast path
1158 __ move(AT, C1_MacroAssembler::max_array_allocation_length);
1159 __ sltu(AT, AT, length);
1160 __ bne(AT, R0, slow_path);
1161 __ delayed()->nop();
1163 // if we got here then the TLAB allocation failed, so try
1164 // refilling the TLAB or allocating directly from eden.
1165 Label retry_tlab, try_eden;
1166 //T0,T1,T5,T8 have changed!
1167 __ tlab_refill(retry_tlab, try_eden, slow_path); // preserves T2 & T4
1169 __ bind(retry_tlab);
1171 // get the allocation size: (length << (layout_helper & 0x1F)) + header_size
1172 __ lw(t1, klass, in_bytes(Klass::layout_helper_offset()));
1173 __ andi(AT, t1, 0x1f);
1174 __ sllv(arr_size, length, AT);
1175 __ srl(t1, t1, Klass::_lh_header_size_shift);
1176 __ andi(t1, t1, Klass::_lh_header_size_mask);
1177 __ add(arr_size, t1, arr_size);
1178 __ addi(arr_size, arr_size, MinObjAlignmentInBytesMask); // align up
1179 __ move(AT, ~MinObjAlignmentInBytesMask);
1180 __ andr(arr_size, arr_size, AT);
1183 __ tlab_allocate(obj, arr_size, 0, t1, t2, slow_path); // preserves arr_size
1184 __ initialize_header(obj, klass, length,t1,t2);
1185 __ lbu(t1, Address(klass, in_bytes(Klass::layout_helper_offset())
1186 + (Klass::_lh_header_size_shift / BitsPerByte)));
1187 assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
1188 assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
1189 __ andi(t1, t1, Klass::_lh_header_size_mask);
1190 __ sub(arr_size, arr_size, t1); // body length
1191 __ add(t1, t1, obj); // body start
1192 __ initialize_body(t1, arr_size, 0, t2);
1193 __ verify_oop(obj);
1194 __ jr(RA);
1195 __ delayed()->nop();
1197 #ifndef OPT_THREAD
1198 const Register thread = T8;
1199 __ get_thread(thread);
1200 #else
1201 const Register thread = TREG;
1202 #endif
1204 __ bind(try_eden);
1205 // get the allocation size: (length << (layout_helper & 0x1F)) + header_size
1206 __ lw(t1, klass, in_bytes(Klass::layout_helper_offset()));
1207 __ andi(AT, t1, 0x1f);
1208 __ sllv(arr_size, length, AT);
1209 __ srl(t1, t1, Klass::_lh_header_size_shift);
1210 __ andi(t1, t1, Klass::_lh_header_size_mask);
1211 __ add(arr_size, t1, arr_size);
1212 __ addi(arr_size, arr_size, MinObjAlignmentInBytesMask); // align up
1213 __ move(AT, ~MinObjAlignmentInBytesMask);
1214 __ andr(arr_size, arr_size, AT);
1215 __ eden_allocate(obj, arr_size, 0, t1, t2, slow_path); // preserves arr_size
1216 __ incr_allocated_bytes(thread, arr_size, 0);
1218 __ initialize_header(obj, klass, length,t1,t2);
1219 __ lbu(t1, Address(klass, in_bytes(Klass::layout_helper_offset())
1220 + (Klass::_lh_header_size_shift / BitsPerByte)));
1221 __ andi(t1, t1, Klass::_lh_header_size_mask);
1222 __ sub(arr_size, arr_size, t1); // body length
1223 __ add(t1, t1, obj); // body start
1225 __ initialize_body(t1, arr_size, 0, t2);
1226 __ verify_oop(obj);
1227 __ jr(RA);
1228 __ delayed()->nop();
1229 __ bind(slow_path);
1230 }
1233 __ enter();
1234 OopMap* map = save_live_registers(sasm, 0);
1235 int call_offset;
1236 if (id == new_type_array_id) {
1237 call_offset = __ call_RT(obj, noreg,
1238 CAST_FROM_FN_PTR(address, new_type_array), klass, length);
1239 } else {
1240 call_offset = __ call_RT(obj, noreg,
1241 CAST_FROM_FN_PTR(address, new_object_array), klass, length);
1242 }
1244 oop_maps = new OopMapSet();
1245 oop_maps->add_gc_map(call_offset, map);
1246 restore_live_registers_except_V0(sasm);
1247 __ verify_oop(obj);
1248 __ leave();
1249 __ jr(RA);
1250 __ delayed()->nop();
1251 }
1252 break;
1254 case new_multi_array_id:
1255 {
1256 StubFrame f(sasm, "new_multi_array", dont_gc_arguments);
1257 //refer to c1_LIRGenerate_mips.cpp:do_NewmultiArray
1258 // V0: klass
1259 // T2: rank
1260 // T0: address of 1st dimension
1261 //__ call_RT(V0, noreg, CAST_FROM_FN_PTR(address, new_multi_array), A1, A2, A3);
1262 //OopMap* map = save_live_registers(sasm, 4);
1263 OopMap* map = save_live_registers(sasm, 0);
1264 int call_offset = __ call_RT(V0, noreg, CAST_FROM_FN_PTR(address, new_multi_array),
1265 V0,T2,T0);
1266 oop_maps = new OopMapSet();
1267 oop_maps->add_gc_map(call_offset, map);
1268 //FIXME
1269 restore_live_registers_except_V0(sasm);
1270 // V0: new multi array
1271 __ verify_oop(V0);
1272 }
1273 break;
1276 case register_finalizer_id:
1277 {
1278 __ set_info("register_finalizer", dont_gc_arguments);
1280 // The object is passed on the stack and we haven't pushed a
1281 // frame yet so it's one work away from top of stack.
1282 //reference to LIRGenerator::do_RegisterFinalizer, call_runtime
1283 __ move(V0, A0);
1284 __ verify_oop(V0);
1285 // load the klass and check the has finalizer flag
1286 Label register_finalizer;
1287 #ifndef _LP64
1288 Register t = T5;
1289 #else
1290 Register t = A5;
1291 #endif
1292 //__ ld_ptr(t, Address(V0, oopDesc::klass_offset_in_bytes()));
1293 __ load_klass(t, V0);
1294 __ lw(t, Address(t, Klass::access_flags_offset()));
1295 __ move(AT, JVM_ACC_HAS_FINALIZER);
1296 __ andr(AT, AT, t);
1298 __ bne(AT, R0, register_finalizer);
1299 __ delayed()->nop();
1300 __ jr(RA);
1301 __ delayed()->nop();
1302 __ bind(register_finalizer);
1303 __ enter();
1304 OopMap* map = save_live_registers(sasm, 0 /*num_rt_args */);
1306 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address,
1307 SharedRuntime::register_finalizer), V0);
1308 oop_maps = new OopMapSet();
1309 oop_maps->add_gc_map(call_offset, map);
1311 // Now restore all the live registers
1312 restore_live_registers(sasm);
1314 __ leave();
1315 __ jr(RA);
1316 __ delayed()->nop();
1317 }
1318 break;
1320 // case range_check_failed_id:
1321 case throw_range_check_failed_id:
1322 {
1323 StubFrame f(sasm, "range_check_failed", dont_gc_arguments);
1324 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
1325 throw_range_check_exception),true);
1326 }
1327 break;
1329 case throw_index_exception_id:
1330 {
1331 // i use A1 as the index register, for this will be the first argument, see call_RT
1332 StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments);
1333 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
1334 throw_index_exception), true);
1335 }
1336 break;
1338 case throw_div0_exception_id:
1339 { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments);
1340 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
1341 throw_div0_exception), false);
1342 }
1343 break;
1345 case throw_null_pointer_exception_id:
1346 {
1347 StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments);
1348 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
1349 throw_null_pointer_exception),false);
1350 }
1351 break;
1353 case handle_exception_nofpu_id:
1354 save_fpu_registers = false;
1355 // fall through
1356 case handle_exception_id:
1357 {
1358 StubFrame f(sasm, "handle_exception", dont_gc_arguments);
1359 //OopMap* oop_map = save_live_registers(sasm, 1, save_fpu_registers);
1360 oop_maps = generate_handle_exception(id, sasm);
1361 }
1362 break;
1363 case handle_exception_from_callee_id:
1364 {
1365 StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments);
1366 oop_maps = generate_handle_exception(id, sasm);
1367 }
1368 break;
1369 case unwind_exception_id:
1370 {
1371 __ set_info("unwind_exception", dont_gc_arguments);
1372 generate_unwind_exception(sasm);
1373 }
1374 break;
1377 case throw_array_store_exception_id:
1378 {
1379 StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments);
1380 // tos + 0: link
1381 // + 1: return address
1382 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
1383 throw_array_store_exception), false);
1384 }
1385 break;
1387 case throw_class_cast_exception_id:
1388 {
1389 StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments);
1390 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
1391 throw_class_cast_exception), true);
1392 }
1393 break;
1395 case throw_incompatible_class_change_error_id:
1396 {
1397 StubFrame f(sasm, "throw_incompatible_class_cast_exception", dont_gc_arguments);
1398 oop_maps = generate_exception_throw(sasm,
1399 CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
1400 }
1401 break;
1403 case slow_subtype_check_id:
1404 {
1405 //actually , We do not use it
1406 // A0:klass_RInfo sub
1407 // A1:k->encoding() super
1408 __ set_info("slow_subtype_check", dont_gc_arguments);
1409 __ st_ptr(T0, SP, (-1) * wordSize);
1410 __ st_ptr(T1, SP, (-2) * wordSize);
1411 __ addiu(SP, SP, (-2) * wordSize);
1413 Label miss;
1414 __ check_klass_subtype_slow_path(A0, A1, T0, T1, NULL, &miss);
1416 __ addiu(V0, R0, 1);
1417 __ addiu(SP, SP, 2 * wordSize);
1418 __ ld_ptr(T0, SP, (-1) * wordSize);
1419 __ ld_ptr(T1, SP, (-2) * wordSize);
1420 __ jr(RA);
1421 __ delayed()->nop();
1424 __ bind(miss);
1425 __ move(V0, R0);
1426 __ addiu(SP, SP, 2 * wordSize);
1427 __ ld_ptr(T0, SP, (-1) * wordSize);
1428 __ ld_ptr(T1, SP, (-2) * wordSize);
1429 __ jr(RA);
1430 __ delayed()->nop();
1431 }
1432 break;
1434 case monitorenter_nofpu_id:
1435 save_fpu_registers = false;// fall through
1437 case monitorenter_id:
1438 {
1439 StubFrame f(sasm, "monitorenter", dont_gc_arguments);
1440 OopMap* map = save_live_registers(sasm, 0, save_fpu_registers);
1442 f.load_argument(1, V0); // V0: object
1443 #ifndef _LP64
1444 f.load_argument(0, T6); // T6: lock address
1445 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address,
1446 monitorenter), V0, T6);
1447 #else
1448 f.load_argument(0, A6); // A6: lock address
1449 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address,
1450 monitorenter), V0, A6);
1451 #endif
1453 oop_maps = new OopMapSet();
1454 oop_maps->add_gc_map(call_offset, map);
1455 restore_live_registers(sasm, save_fpu_registers);
1456 }
1457 break;
1459 case monitorexit_nofpu_id:
1460 save_fpu_registers = false;
1461 // fall through
1462 case monitorexit_id:
1463 {
1464 StubFrame f(sasm, "monitorexit", dont_gc_arguments);
1465 OopMap* map = save_live_registers(sasm, 0, save_fpu_registers);
1467 #ifndef _LP64
1468 f.load_argument(0, T6); // eax: lock address
1469 #else
1470 f.load_argument(0, A6); // A6: lock address
1471 #endif
1472 // note: really a leaf routine but must setup last java sp
1473 // => use call_RT for now (speed can be improved by
1474 // doing last java sp setup manually)
1475 #ifndef _LP64
1476 int call_offset = __ call_RT(noreg, noreg,
1477 CAST_FROM_FN_PTR(address, monitorexit), T6);
1478 #else
1479 int call_offset = __ call_RT(noreg, noreg,
1480 CAST_FROM_FN_PTR(address, monitorexit), A6);
1481 #endif
1482 oop_maps = new OopMapSet();
1483 oop_maps->add_gc_map(call_offset, map);
1484 restore_live_registers(sasm, save_fpu_registers);
1486 }
1487 break;
1488 // case init_check_patching_id:
1489 case access_field_patching_id:
1490 {
1491 StubFrame f(sasm, "access_field_patching", dont_gc_arguments);
1492 // we should set up register map
1493 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1495 }
1496 break;
1498 case load_klass_patching_id:
1499 {
1500 StubFrame f(sasm, "load_klass_patching", dont_gc_arguments);
1501 // we should set up register map
1502 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address,
1503 move_klass_patching));
1504 }
1505 break;
1506 /* case jvmti_exception_throw_id:
1507 {
1508 // V0: exception oop
1509 // V1: exception pc
1510 StubFrame f(sasm, "jvmti_exception_throw", dont_gc_arguments);
1511 // Preserve all registers across this potentially blocking call
1512 const int num_rt_args = 2; // thread, exception oop
1513 //OopMap* map = save_live_registers(sasm, num_rt_args);
1514 OopMap* map = save_live_registers(sasm, 0);
1515 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address,
1516 Runtime1::post_jvmti_exception_throw), V0);
1517 oop_maps = new OopMapSet();
1518 oop_maps->add_gc_map(call_offset, map);
1519 restore_live_registers(sasm);
1520 }*/
1521 case load_mirror_patching_id:
1522 {
1523 StubFrame f(sasm, "load_mirror_patching" , dont_gc_arguments);
1524 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1525 }
1526 break;
1528 case load_appendix_patching_id:
1529 {
1530 StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments);
1531 // we should set up register map
1532 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1533 }
1534 break;
1536 case dtrace_object_alloc_id:
1537 {
1538 // V0:object
1539 StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments);
1540 // we can't gc here so skip the oopmap but make sure that all
1541 // the live registers get saved.
1542 save_live_registers(sasm, 0);
1544 __ push_reg(V0);
1545 __ move(A0, V0);
1546 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc),
1547 relocInfo::runtime_call_type);
1548 __ delayed()->nop();
1549 __ super_pop(V0);
1551 restore_live_registers(sasm);
1552 }
1553 break;
1555 case fpu2long_stub_id:
1556 {
1557 //FIXME, I hava no idea how to port this
1558 //tty->print_cr("fpu2long_stub_id unimplemented yet!");
1559 }
1560 break;
1562 case deoptimize_id:
1563 {
1564 StubFrame f(sasm, "deoptimize", dont_gc_arguments);
1565 const int num_rt_args = 1; // thread
1566 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
1567 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize));
1568 oop_maps = new OopMapSet();
1569 oop_maps->add_gc_map(call_offset, oop_map);
1570 restore_live_registers(sasm);
1571 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1572 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1573 __ leave();
1574 __ jmp(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type);
1575 __ delayed()->nop();
1576 }
1577 break;
1579 case predicate_failed_trap_id:
1580 {
1581 StubFrame f(sasm, "predicate_failed_trap", dont_gc_arguments);
1583 OopMap* map = save_live_registers(sasm, 1);
1585 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1586 oop_maps = new OopMapSet();
1587 oop_maps->add_gc_map(call_offset, map);
1588 restore_live_registers(sasm);
1589 __ leave();
1590 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1591 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1593 __ jmp(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type);
1594 __ delayed()->nop();
1595 }
1596 break;
1598 default:
1599 {
1600 StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
1601 __ move(A1, (int)id);
1602 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), A1);
1603 __ should_not_reach_here();
1604 }
1605 break;
1606 }
1607 return oop_maps;
1608 }
1610 #undef __
1612 const char *Runtime1::pd_name_for_address(address entry) {
1613 return "<unknown function>";
1614 }
