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src/cpu/mips/vm/disassembler_mips.cpp@8ac5b6ff8466
src/cpu/mips/vm/disassembler_mips.cpp
Sat, 18 Feb 2017 18:25:01 -0500
- author
- fujie
- date
- Sat, 18 Feb 2017 18:25:01 -0500
- changeset 315
- 8ac5b6ff8466
- parent 301
- d585b6706dc2
- child 335
- e6f2f90635ab
- permissions
- -rw-r--r--
[Assembler] Add right-rotate instructions for MIPS.
1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifdef USE_PRAGMA_IDENT_SRC
27 #pragma ident "@(#)disassembler_mips.cpp 1.35 03/12/23 16:36:14 JVM"
28 #endif
29 # include "precompiled.hpp"
30 # include "depChecker_mips.hpp"
31 # include "runtime/fprofiler.hpp"
34 class mips32_env : public DisassemblerEnv {
35 private:
36 nmethod* code;
37 outputStream* output;
38 public:
39 mips32_env(nmethod* rcode, outputStream* routput) {
40 code = rcode;
41 output = routput;
42 }
43 void print_label(intptr_t value);
44 void print_raw(const char* str) { output->print_raw(str); }
45 void print(const char* format, ...);
46 char* string_for_offset(intptr_t value);
47 char* string_for_constant(unsigned char* pc, intptr_t value, int is_decimal);
48 };
51 void mips32_env::print_label(intptr_t value) {
52 if (!Universe::is_fully_initialized()) {
53 output->print(INTPTR_FORMAT, value);
54 return;
55 }
56 address adr = (address) value;
57 if (StubRoutines::contains(adr)) {
58 StubCodeDesc* desc = StubCodeDesc::desc_for(adr);
59 const char * desc_name = "unknown stub";
60 if (desc != NULL) {
61 desc_name = desc->name();
62 }
63 output->print("Stub::%s", desc_name);
64 if (WizardMode) output->print(" " INTPTR_FORMAT, value);
65 } else {
66 output->print(INTPTR_FORMAT, value);
67 }
68 }
70 void mips32_env::print(const char* format, ...) {
71 va_list ap;
72 va_start(ap, format);
73 output->vprint(format, ap);
74 va_end(ap);
75 }
77 char* mips32_env::string_for_offset(intptr_t value) {
78 stringStream st;
79 if (!Universe::is_fully_initialized()) {
80 st.print("%d", value);
81 return st.as_string();
82 }
83 BarrierSet* bs = Universe::heap()->barrier_set();
84 BarrierSet::Name bsn = bs->kind();
86 if (bs->kind() == BarrierSet::CardTableModRef && (jbyte*) value == ((CardTableModRefBS*)(bs))->byte_map_base) {
87 st.print("word_map_base");
88 } else {
89 st.print("%d", value);
90 }
91 return st.as_string();
92 }
94 char* mips32_env::string_for_constant(unsigned char* pc, intptr_t value, int is_decimal) {
95 stringStream st;
96 oop obj = NULL;
97 #ifndef CORE
98 if (code && (obj = code->embeddedOop_at(pc))!=NULL) {
99 obj->print_value_on(&st);
100 } else
101 #endif
102 {
103 if (is_decimal == 1) {
104 st.print("%d", value);
105 } else {
106 st.print("0x%lx", value);
107 }
108 }
109 return st.as_string();
110 }
112 #define PRINT_NOP() \
113 env->print("nop");
115 #define PRINT_ORRI(OP) \
116 env->print("%s %s, %s, 0x%x", OP, as_Register(Assembler::rt(insn))->name(), \
117 as_Register(Assembler::rs(insn))->name(), \
118 (short)Assembler::low16(insn) )
120 #define PRINT_ORRL(OP) \
121 env->print("%s %s, %s, ", OP, as_Register(Assembler::rs(insn))->name(), \
122 as_Register(Assembler::rt(insn))->name()); \
123 env->print_label( (intptr_t)start + 4 + ((short)Assembler::low16(insn)<<2) )
125 #define PRINT_J(OP) \
126 env->print((char*)OP); \
127 env->print_label( ( ( (intptr_t)start + 4 ) & 0xc0000000 ) | ( Assembler::low26(insn) << 2 ) ); \
128 env->print("");
130 #define PRINT_ORSL(OP) \
131 env->print("%s %s, ", OP, as_Register(Assembler::rs(insn))->name()); \
132 env->print_label( (intptr_t)start + 4 + (short)Assembler::low16(insn) ); \
133 env->print("");
135 #define PRINT_OROB(OP) \
136 env->print("%s %s, 0x%x(%s)", OP, as_Register(Assembler::rt(insn))->name(), \
137 (short)Assembler::low16(insn), \
138 as_Register(Assembler::rs(insn))->name() )
140 #define PRINT_OFOB(OP) \
141 env->print("%s %s, 0x%x(%s)", OP, as_FloatRegister(Assembler::rt(insn))->name(), \
142 (short)Assembler::low16(insn), \
143 as_Register(Assembler::rs(insn))->name() )
146 #define PRINT_ORRS(OP) \
147 env->print("%s %s, %s, %d", OP, as_Register(Assembler::rd(insn))->name(), \
148 as_Register(Assembler::rt(insn))->name(), \
149 Assembler::sa(insn) )
151 #define PRINT_ORRR(OP) \
152 env->print("%s %s, %s, %s", OP, as_Register(Assembler::rd(insn))->name(), \
153 as_Register(Assembler::rs(insn))->name(), \
154 as_Register(Assembler::rt(insn))->name() )
156 #define PRINT_ORRII(OP) \
157 env->print("%s %s, %s, %s, 0x%x", OP,as_Register(Assembler::rt(insn))->name(), \
158 as_Register(Assembler::rs(insn))->name(), \
159 ((short)Assembler::low(insn, 11)), \
160 ((short)Assembler::low(insn, 6)) )
162 #define PRINT_ORRRI_GSLDC2(OP) \
163 env->print("%s %s, %s, %s, 0x%x", OP,as_Register(Assembler::rt(insn))->name(), \
164 as_Register(Assembler::rs(insn))->name(), \
165 as_Register(Assembler::rd(insn))->name(), \
166 ((short)Assembler::low(insn, 11) >> 3) )
168 #define PRINT_COP1X(OP) \
169 env->print("%s %s, %s, %s, %s", OP, as_FloatRegister(Assembler::sa(insn))->name(), \
170 as_FloatRegister(Assembler::rt(insn))->name(), \
171 as_FloatRegister(Assembler::rd(insn))->name(), \
172 as_FloatRegister(Assembler::rs(insn))->name())
174 /*
175 * "<< 17 >> 23 << 4" is short for "<< 17 >> 17 >> 6 << 4". vAddr = sign_extend(offset << 4 ) + GPR[base]
176 * "<< 17 >> 17": sign-extending
177 * ">> 6": offset pos
178 * "<< 4": offset << 4
179 */
180 #define PRINT_ORRRI_GSLQ(OP) \
181 env->print("%s %s, %s, %d(%s)", OP, as_Register((insn)&0x1f)->name(), \
182 as_Register(Assembler::rt(insn))->name(), (Assembler::low(insn, 15) << 17 >> 23 << 4), \
183 as_Register(Assembler::rs(insn))->name())
185 #define PRINT_ORRR_2(OP) \
186 env->print("%s %s, %s, %s", OP, as_Register(Assembler::rd(insn))->name(), \
187 as_Register(Assembler::rt(insn))->name(), \
188 as_Register(Assembler::rs(insn))->name() )
190 #define PRINT_ORS(OP) \
191 env->print("%s %s", OP, as_Register(Assembler::rs(insn))->name())
193 #define PRINT_ORD(OP) \
194 env->print("%s %s", OP, as_Register(Assembler::rd(insn))->name())
196 #define PRINT_ORR(OP) \
197 env->print("%s %s, %s", OP, as_Register(Assembler::rs(insn))->name(), \
198 as_Register(Assembler::rt(insn))->name())
200 #define PRINT_ORR_2(OP) \
201 env->print("%s %s, %s", OP, as_Register(Assembler::rt(insn))->name(), \
202 as_Register(Assembler::rd(insn))->name())
204 #define PRINT_FLOAT(OP) \
205 env->print("%s.%s %s, %s, %s", OP, fmt, as_FloatRegister(Assembler::sa(insn))->name(), \
206 as_FloatRegister(Assembler::rd(insn))->name(), \
207 as_FloatRegister(Assembler::rt(insn))->name() )
209 #define PRINT_CVT(OP) \
210 env->print("%s.%s %s, %s", OP, fmt, as_FloatRegister(Assembler::sa(insn))->name(), \
211 as_FloatRegister(Assembler::rd(insn))->name() )
213 static const char* fmt_str(int fmt) {
214 switch(fmt) {
215 case Assembler::single_fmt:
216 return "s";
217 case Assembler::double_fmt:
218 return "d";
219 case Assembler::word_fmt:
220 return "w";
221 case Assembler::long_fmt:
222 return "l";
223 }
225 return "";
226 }
228 address Disassembler::decode_instruction(address start, DisassemblerEnv* env) {
229 int insn = *(int*)start;
230 int opcode = Assembler::opcode(insn);
231 int special;
232 const char *fmt;
233 int flag = 0;
235 if (insn == 0)
236 {
237 PRINT_NOP();
238 return start+4;
239 }
241 switch(opcode) {
242 // case op
243 // case special_op
244 // case regimm_op
245 // case cop0_op not
246 // case cop1_op
247 // case cop2_op not
248 // case cop1x_op
249 // case special2_op
250 // case special3_op
251 // case gs_lwc2_op
252 // case gs_ldc2_op
253 // case gs_swc2_op
254 // case gs_sdc2_op
255 case Assembler::j_op:
256 case Assembler::jal_op:
257 PRINT_J(Assembler::ops_name[opcode]);
258 break;
259 case Assembler::beq_op:
260 case Assembler::bne_op:
261 case Assembler::blez_op:
262 case Assembler::bgtz_op:
263 PRINT_ORRL(Assembler::ops_name[opcode]);
264 break;
265 case Assembler::addi_op:
266 case Assembler::addiu_op:
267 case Assembler::slti_op:
268 case Assembler::sltiu_op:
269 case Assembler::ori_op:
270 case Assembler::andi_op:
271 case Assembler::xori_op:
272 case Assembler::daddi_op:
273 case Assembler::daddiu_op:
274 PRINT_ORRI(Assembler::ops_name[opcode]);
275 break;
276 case Assembler::lui_op:
277 env->print("lui %s, 0x%x", as_Register(Assembler::rt(insn))->name(), (short)Assembler::low16(insn) ); \
278 break;
279 case Assembler::beql_op:
280 case Assembler::bnel_op:
281 case Assembler::blezl_op:
282 case Assembler::bgtzl_op:
283 PRINT_ORRL(Assembler::ops_name[opcode]);
284 break;
285 case Assembler::ldl_op:
286 case Assembler::ldr_op:
287 case Assembler::lb_op:
288 case Assembler::lh_op:
289 case Assembler::lwl_op:
290 case Assembler::lw_op:
291 case Assembler::lbu_op:
292 case Assembler::lhu_op:
293 case Assembler::lwr_op:
294 case Assembler::lwu_op:
295 case Assembler::sb_op:
296 case Assembler::sh_op:
297 case Assembler::swl_op:
298 case Assembler::sw_op:
299 case Assembler::sdl_op:
300 case Assembler::sdr_op:
301 case Assembler::swr_op:
302 case Assembler::ll_op:
303 case Assembler::lld_op:
304 case Assembler::ld_op:
305 case Assembler::sc_op:
306 case Assembler::scd_op:
307 case Assembler::sd_op:
308 PRINT_OROB(Assembler::ops_name[opcode]);
309 break;
310 case Assembler::sdc1_op:
311 case Assembler::ldc1_op:
312 case Assembler::lwc1_op:
313 case Assembler::swc1_op:
314 PRINT_OFOB(Assembler::ops_name[opcode]);
315 break;
317 case Assembler::special_op: {
318 special = Assembler::special(insn);
319 switch(special) {
320 case Assembler::sll_op:
321 PRINT_ORRS(Assembler::special_name[special]);
322 break;
323 case Assembler::srl_op:
324 if (insn & (1 << 21)) {
325 PRINT_ORRS("rotr");
326 } else {
327 PRINT_ORRS(Assembler::special_name[special]);
328 }
329 break;
330 case Assembler::sra_op:
331 PRINT_ORRS(Assembler::special_name[special]);
332 break;
333 case Assembler::dsll_op:
334 PRINT_ORRS(Assembler::special_name[special]);
335 break;
336 case Assembler::dsrl_op:
337 if (insn & (1 << 21)) {
338 PRINT_ORRS("drotr");
339 } else {
340 PRINT_ORRS(Assembler::special_name[special]);
341 }
342 break;
343 case Assembler::dsra_op:
344 PRINT_ORRS(Assembler::special_name[special]);
345 break;
346 case Assembler::dsll32_op:
347 PRINT_ORRS(Assembler::special_name[special]);
348 break;
349 case Assembler::dsrl32_op:
350 if (insn & (1 << 21)) {
351 PRINT_ORRS("drotr32");
352 } else {
353 PRINT_ORRS(Assembler::special_name[special]);
354 }
355 break;
356 case Assembler::dsra32_op:
357 PRINT_ORRS(Assembler::special_name[special]);
358 break;
360 case Assembler::movci_op:
361 flag = insn & (1 << 16);
362 if (flag) {
363 env->print("movt %s, %s", as_Register(Assembler::rd(insn))->name(), as_Register(Assembler::rs(insn))->name());
364 } else {
365 env->print("movf %s, %s", as_Register(Assembler::rd(insn))->name(), as_Register(Assembler::rs(insn))->name());
366 }
367 break;
369 case Assembler::sllv_op:
370 PRINT_ORRR_2(Assembler::special_name[special]);
371 break;
372 case Assembler::srlv_op:
373 if (insn & (1 << 6)) {
374 PRINT_ORRR_2("rotrv");
375 } else {
376 PRINT_ORRR_2(Assembler::special_name[special]);
377 }
378 break;
379 case Assembler::srav_op:
380 PRINT_ORRR_2(Assembler::special_name[special]);
381 break;
382 case Assembler::dsllv_op:
383 PRINT_ORRR_2(Assembler::special_name[special]);
384 break;
385 case Assembler::dsrlv_op:
386 if (insn & (1 << 6)) {
387 PRINT_ORRR_2("drotrv");
388 } else {
389 PRINT_ORRR_2(Assembler::special_name[special]);
390 }
391 break;
392 case Assembler::dsrav_op:
393 PRINT_ORRR_2(Assembler::special_name[special]);
394 break;
396 case Assembler::jr_op:
397 case Assembler::jalr_op:
398 case Assembler::mthi_op:
399 case Assembler::mtlo_op:
400 PRINT_ORS(Assembler::special_name[special]);
401 break;
403 case Assembler::syscall_op:
404 case Assembler::break_op:
405 env->print("%s 0x%x\n", Assembler::special_name[special], bitfield(insn, 6, 20)>>10);
406 break;
408 case Assembler::sync_op:
409 env->print("sync\n");
410 break;
412 case Assembler::mfhi_op:
413 case Assembler::mflo_op:
414 PRINT_ORD(Assembler::special_name[special]);
415 break;
417 case Assembler::mult_op:
418 case Assembler::multu_op:
419 case Assembler::div_op:
420 case Assembler::divu_op:
421 case Assembler::dmult_op:
422 case Assembler::dmultu_op:
423 case Assembler::ddiv_op:
424 case Assembler::ddivu_op:
425 PRINT_ORR(Assembler::special_name[special]);
426 break;
428 case Assembler::add_op:
429 case Assembler::addu_op:
430 case Assembler::sub_op:
431 case Assembler::subu_op:
432 case Assembler::and_op:
433 case Assembler::or_op:
434 case Assembler::xor_op:
435 case Assembler::nor_op:
436 case Assembler::slt_op:
437 case Assembler::sltu_op:
438 case Assembler::movz_op:
439 case Assembler::movn_op:
440 case Assembler::dadd_op:
441 case Assembler::daddu_op:
442 case Assembler::dsub_op:
443 case Assembler::dsubu_op:
444 PRINT_ORRR(Assembler::special_name[special]);
445 break;
447 case Assembler::tge_op:
448 case Assembler::tgeu_op:
449 case Assembler::tlt_op:
450 case Assembler::tltu_op:
451 case Assembler::teq_op:
452 case Assembler::tne_op:
453 env->print("%s 0x%x, %s, %s\n", Assembler::special_name[special], bitfield(insn, 6, 10),
454 as_Register(Assembler::rs(insn))->name(),
455 as_Register(Assembler::rt(insn))->name() );
456 break;
458 default:
459 //Unimplemented();
460 env->print("0x%x\n", insn);
461 }
462 break;
463 } //special_op
465 case Assembler::regimm_op: {
466 special = Assembler::rt(insn);
467 switch(special) {
468 case Assembler::bltz_op:
469 case Assembler::bgez_op:
470 case Assembler::bltzl_op:
471 case Assembler::bgezl_op:
472 case Assembler::bltzal_op:
473 case Assembler::bgezal_op:
474 case Assembler::bltzall_op:
475 case Assembler::bgezall_op:
476 env->print("[%lx]%s %s, ", *(int *)start, Assembler::regimm_name[special], as_Register(Assembler::rs(insn))->name());
477 env->print_label( (intptr_t)start + 4 + 4 * (short)Assembler::low16(insn) );
478 env->print("\n");
479 break;
481 case Assembler::tgei_op:
482 case Assembler::tgeiu_op:
483 case Assembler::tlti_op:
484 case Assembler::tltiu_op:
485 case Assembler::teqi_op:
486 case Assembler::tnei_op:
487 env->print("%s %s, %d\n", Assembler::regimm_name[special],
488 as_Register(Assembler::rs(insn))->name(),
489 (short)Assembler::low16(insn));
490 break;
492 default:
493 //Unimplemented();
494 env->print("0x%x\n", insn);
495 }
496 break;
497 } //regimm_op
499 case Assembler::cop0_op: {
500 //Unimplemented();
501 break;
502 } //cop0_op
504 case Assembler::cop1_op: {
505 special = Assembler::rs(insn);
506 switch(special) {
507 case Assembler::mfc1_op:
508 PRINT_ORR_2("mfc1");
509 break;
510 case Assembler::mtc1_op:
511 PRINT_ORR_2("mtc1");
512 break;
513 case Assembler::cfc1_op:
514 PRINT_ORR_2("cfc1");
515 break;
516 case Assembler::ctc1_op:
517 PRINT_ORR_2("ctc1");
518 break;
519 case Assembler::dmfc1_op:
520 PRINT_ORR_2("dmfc1");
521 break;
522 case Assembler::dmtc1_op:
523 PRINT_ORR_2("dmtc1");
524 break;
526 case Assembler::bc1f_op:
527 special = Assembler::rt(insn);
528 switch(special) {
529 case Assembler::bcf_op:
530 env->print("bc1f ");
531 env->print_label( (intptr_t)start + 4 + (short)Assembler::low16(insn) );
532 env->print("\n");
533 break;
534 case Assembler::bcfl_op:
535 env->print("bc1fl ");
536 env->print_label( (intptr_t)start + 4 + (short)Assembler::low16(insn) );
537 env->print("\n");
538 break;
539 case Assembler::bct_op:
540 env->print("bc1t ");
541 env->print_label( (intptr_t)start + 4 + (short)Assembler::low16(insn) );
542 env->print("\n");
543 break;
544 case Assembler::bctl_op:
545 env->print("bc1tl ");
546 env->print_label( (intptr_t)start + 4 + (short)Assembler::low16(insn) );
547 env->print("\n");
548 break;
549 default:
550 //Unimplemented();
551 env->print("0x%x\n", insn);
552 }
553 break;
554 case Assembler::single_fmt:
555 case Assembler::double_fmt:
556 case Assembler::word_fmt:
557 case Assembler::long_fmt:
558 fmt = fmt_str(special);
559 special = Assembler::special(insn);
560 switch(special) {
561 case Assembler::fadd_op:
562 case Assembler::fsub_op:
563 case Assembler::fmul_op:
564 case Assembler::fdiv_op:
565 case Assembler::fsqrt_op:
566 case Assembler::fabs_op:
567 case Assembler::fmov_op:
568 case Assembler::fneg_op:
569 case Assembler::froundl_op:
570 case Assembler::ftruncl_op:
571 case Assembler::fceill_op:
572 case Assembler::ffloorl_op:
573 case Assembler::froundw_op:
574 case Assembler::ftruncw_op:
575 case Assembler::fceilw_op:
576 case Assembler::ffloorw_op:
577 PRINT_FLOAT(Assembler::cop1_name[special]);
578 break;
580 case Assembler::fcvts_op:
581 PRINT_CVT("cvt.s");
582 break;
583 case Assembler::fcvtd_op:
584 PRINT_CVT("cvt.d");
585 break;
586 case Assembler::fcvtw_op:
587 PRINT_CVT("cvt.w");
588 break;
589 case Assembler::fcvtl_op:
590 PRINT_CVT("cvt.l");
591 break;
592 default:
593 //tty->print_cr("0x%x(%x)", insn, opcode);
594 //Unimplemented();
595 env->print("0x%x\n", insn);
596 }
597 }
598 break;
599 } //cop1_op
601 case Assembler::gs_cop2_op: {
602 //Unimplemented();
603 break;
604 } //gs_cop2_op
606 case Assembler::cop1x_op: {
607 special = Assembler::special(insn);
608 switch(special) {
609 case Assembler::madd_s_op:
610 case Assembler::madd_d_op:
611 case Assembler::madd_ps_op:
612 case Assembler::msub_s_op:
613 case Assembler::msub_d_op:
614 case Assembler::msub_ps_op:
615 case Assembler::nmadd_s_op:
616 case Assembler::nmadd_d_op:
617 case Assembler::nmadd_ps_op:
618 case Assembler::nmsub_s_op:
619 case Assembler::nmsub_d_op:
620 case Assembler::nmsub_ps_op:
621 PRINT_COP1X(Assembler::cop1x_name[Assembler::special(insn)]);
622 break;
623 }
624 break;
625 } //cop1x_op
627 case Assembler::special2_op: {
628 special = Assembler::special(insn);
629 switch(special) {
630 case Assembler::mul_op:
631 case Assembler::gsdiv_op:
632 case Assembler::gsddiv_op:
633 case Assembler::gsmod_op:
634 case Assembler::gsdmod_op:
635 case Assembler::gsdmult_op:
636 PRINT_ORRR(Assembler::special2_name[special]);
637 break;
638 case Assembler::madd_op:
639 case Assembler::msub_op:
640 PRINT_ORR(Assembler::special2_name[special]);
641 break;
642 case Assembler::gs0x03_op:
643 if ( (insn & (0x1f << 6)) == (18 << 6) ) {
644 PRINT_ORR("gsandn");
645 }
646 break;
647 case Assembler::gs0x06_op:
648 if ( (insn & (0x1f << 6)) == (18 << 6) ) {
649 PRINT_ORR("gsorn");
650 }
651 break;
652 }
653 break;
654 } //special2_op
656 case Assembler::special3_op: {
657 special = Assembler::special(insn);
658 switch(special) {
659 case Assembler::ext_op:
660 case Assembler::dext_op:
661 case Assembler::ins_op:
662 case Assembler::dinsm_op:
663 case Assembler::dinsu_op:
664 case Assembler::dins_op:
665 PRINT_ORRII(Assembler::special3_name[special]);
666 break;
667 case Assembler::bshfl_op:
668 if ( (insn & (0x1f << 6)) == (Assembler::seb_op << 6) ) {
669 env->print("seb, %s, %s", as_Register(Assembler::rd(insn))->name(), as_Register(Assembler::rt(insn))->name());
670 } else if ( (insn & (0x1f << 6)) == (Assembler::seh_op << 6) ) {
671 env->print("seh, %s, %s", as_Register(Assembler::rd(insn))->name(), as_Register(Assembler::rt(insn))->name());
672 } else {
673 env->print("Invalid instruction");
674 }
675 break;
676 }
677 break;
678 } //special3_op
680 case Assembler::gs_lwc2_op: {
681 if ((Assembler::special(insn) & 0x20) != 0 ) {
682 //gslq rq, rt, offset(base)
683 if ( (insn & (1 << 15)) == 0) {
684 special = Assembler::gslq_op;
685 PRINT_ORRRI_GSLQ(Assembler::gs_lwc2_name[special]);
686 } else {
687 //gsLQC1
688 env->print("gs_lwc2_op 0x%x\n", insn);
689 }
690 } else {
691 env->print("gs_lwc2_op 0x%x\n", insn);
692 }
693 break;
694 } //gs_lwc2_op
696 case Assembler::gs_ldc2_op: {
697 special = Assembler::special(insn) & 0x7;
698 PRINT_ORRRI_GSLDC2(Assembler::gs_ldc2_name[special]);
699 break;
700 } //gs_ldc2_op
702 case Assembler::gs_swc2_op: {
703 if ((Assembler::special(insn) & 0x20) != 0 ) {
704 //gssq rq, rt, offset(base)
705 if ( (insn & (1 << 15)) == 0) {
706 //gsSQ
707 special = Assembler::gssq_op;
708 PRINT_ORRRI_GSLQ(Assembler::gs_swc2_name[special]);
709 } else {
710 //gsSQC1
711 env->print("0x%x\n", insn);
712 }
713 } else {
714 env->print("0x%x\n", insn);
715 }
716 break;
717 } //gs_swc2_op
719 case Assembler::gs_sdc2_op: {
720 special = Assembler::special(insn) & 0x7;
721 PRINT_ORRRI_GSLDC2(Assembler::gs_sdc2_name[special]);
722 break;
723 } //gs_sdc2_op
725 default:
726 //tty->print_cr("0x%x(%x)", insn, opcode);
727 //Unimplemented();
728 env->print("0x%x\n", insn);
729 }
731 return start+4;
732 }
734 /*
735 void Disassembler::decode(address start, address end, outputStream* st, CodeComments c) {
736 if (!load_library()) return;
737 decode_env env(CodeCache::find_blob_unsafe(start), st, c);
738 env.decode_instructions(start, end);
739 }
740 */
742 void Disassembler::decode(CodeBlob* cb, outputStream* st) {
743 #ifndef CORE
744 st = st ? st : tty;
745 st->print_cr("Decoding CodeBlob " INTPTR_FORMAT, cb);
746 decode(cb->content_begin(), cb->content_end(), st);
747 #endif
748 }
751 void Disassembler::decode(u_char* begin, u_char* end, outputStream* st) {
752 st = st ? st : tty;
754 const int show_bytes = false; // for disassembler debugging
756 mips32_env env(NULL, st);
757 unsigned char* p = (unsigned char*) begin;
758 CodeBlob* cb = CodeCache::find_blob_unsafe(begin);
759 while (p < (unsigned char*) end) {
760 if (cb != NULL) {
761 cb->print_block_comment(st, (unsigned char*)(p - cb->content_begin()));
762 }
764 unsigned char* p0 = p;
765 st->print(" "INTPTR_FORMAT ": ", p);
766 p = decode_instruction(p, &env);
767 if (show_bytes) {
768 st->print("\t\t\t");
769 while (p0 < p) st->print("%x ", *p0++);
770 }
771 st->cr();
772 }
773 }
776 void Disassembler::decode(nmethod* nm, outputStream* st) {
777 #ifndef CORE
778 st = st ? st : tty;
780 st->print_cr("Decoding compiled method " INTPTR_FORMAT ":", nm);
781 st->print("Code:");
782 st->cr();
784 mips32_env env(nm, st);
786 // Print constant table.
787 if (nm->consts_size() > 0) {
788 nm->print_nmethod_labels(st, nm->consts_begin());
789 int offset = 0;
790 for (address p = nm->consts_begin(); p < nm->consts_end(); p += 4, offset += 4) {
791 if ((offset % 8) == 0) {
792 st->print_cr(" " PTR_FORMAT " (offset: %4d): " PTR32_FORMAT " " PTR64_FORMAT, p, offset, *((int32_t*) p), *((int64_t*) p));
793 } else {
794 st->print_cr(" " PTR_FORMAT " (offset: %4d): " PTR32_FORMAT, p, offset, *((int32_t*) p));
795 }
796 }
797 }
799 #ifdef COMPILER1
800 unsigned char* p = nm->code_begin();
801 #else
802 unsigned char* p = nm->content_begin();
803 #endif
804 unsigned char* end = nm->content_end();
805 while (p < end) {
806 if (p == nm->entry_point()) st->print_cr("[Entry Point]");
807 if (p == nm->verified_entry_point()) st->print_cr("[Verified Entry Point]");
808 if (p == nm->exception_begin()) st->print_cr("[Exception Handler]");
809 if (p == nm->stub_begin()) st->print_cr("[Stub Code]");
810 if (p == nm->consts_begin()) st->print_cr("[Constants]");
811 nm->print_block_comment(st, (unsigned char*)(p - nm->content_begin()));
812 unsigned char* p0 = p;
813 st->print(" " INTPTR_FORMAT ": ", p);
814 p = decode_instruction(p, &env);
815 nm->print_code_comment_on(st, 40, p0, p);
816 st->cr();
817 // Output pc bucket ticks if we have any
818 address bucket_pc = FlatProfiler::bucket_start_for(p);
819 if (bucket_pc != NULL && bucket_pc > p0 && bucket_pc <= p) {
820 int bucket_count = FlatProfiler::bucket_count_for(bucket_pc);
821 tty->print_cr("[%d]", bucket_count);
822 }
823 }
824 #endif
825 }
