# HG changeset patch
# User fujie
# Date 1487460301 18000
# Node ID 8ac5b6ff8466c28a0b6e62f5ea003303ba90db14
# Parent  5682475ccb5df006a8f76b78d909e3e1aee0e400
[Assembler] Add right-rotate instructions for MIPS.

diff -r 5682475ccb5d -r 8ac5b6ff8466 src/cpu/mips/vm/assembler_mips.hpp
--- a/src/cpu/mips/vm/assembler_mips.hpp	Sun Feb 19 17:42:22 2017 +0800
+++ b/src/cpu/mips/vm/assembler_mips.hpp	Sat Feb 18 18:25:01 2017 -0500
@@ -1092,6 +1092,26 @@
      emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (msbd << 11) | (lsb << 6) | dext_op); 
   }
 
+  void rotr (Register rd, Register rt, int sa) { 
+     emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | srl_op); 
+  }
+
+  void drotr (Register rd, Register rt, int sa) { 
+     emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | dsrl_op); 
+  }
+
+  void drotr32 (Register rd, Register rt, int sa) { 
+     emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | dsrl32_op); 
+  }
+
+  void rotrv (Register rd, Register rt, Register rs) { 
+     emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | srlv_op); 
+  }
+
+  void drotrv (Register rd, Register rt, Register rs) { 
+     emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | dsrlv_op); 
+  }
+
 // Do mult and div need both 32-bit and 64-bit version? FIXME aoqi
 //#ifndef _LP64
 #if 1
diff -r 5682475ccb5d -r 8ac5b6ff8466 src/cpu/mips/vm/disassembler_mips.cpp
--- a/src/cpu/mips/vm/disassembler_mips.cpp	Sun Feb 19 17:42:22 2017 +0800
+++ b/src/cpu/mips/vm/disassembler_mips.cpp	Sat Feb 18 18:25:01 2017 -0500
@@ -318,13 +318,41 @@
       special = Assembler::special(insn);
       switch(special) {
         case Assembler::sll_op:
+          PRINT_ORRS(Assembler::special_name[special]);
+          break;
         case Assembler::srl_op:
+          if (insn & (1 << 21)) {
+             PRINT_ORRS("rotr");
+          } else {
+             PRINT_ORRS(Assembler::special_name[special]);
+          }
+          break;
         case Assembler::sra_op:
+          PRINT_ORRS(Assembler::special_name[special]);
+          break;
         case Assembler::dsll_op:
+          PRINT_ORRS(Assembler::special_name[special]);
+          break;
         case Assembler::dsrl_op:
+          if (insn & (1 << 21)) {
+             PRINT_ORRS("drotr");
+          } else {
+             PRINT_ORRS(Assembler::special_name[special]);
+          }
+          break;
         case Assembler::dsra_op:
+          PRINT_ORRS(Assembler::special_name[special]);
+          break;
         case Assembler::dsll32_op:
+          PRINT_ORRS(Assembler::special_name[special]);
+          break;
         case Assembler::dsrl32_op:
+          if (insn & (1 << 21)) {
+             PRINT_ORRS("drotr32");
+          } else {
+             PRINT_ORRS(Assembler::special_name[special]);
+          }
+          break;
         case Assembler::dsra32_op:
           PRINT_ORRS(Assembler::special_name[special]);
           break;
@@ -339,10 +367,28 @@
           break;
 
         case Assembler::sllv_op:
+          PRINT_ORRR_2(Assembler::special_name[special]);
+          break;
         case Assembler::srlv_op:
+          if (insn & (1 << 6)) {
+             PRINT_ORRR_2("rotrv");
+          } else {
+             PRINT_ORRR_2(Assembler::special_name[special]);
+          }
+          break;
         case Assembler::srav_op:
+          PRINT_ORRR_2(Assembler::special_name[special]);
+          break;
         case Assembler::dsllv_op:
+          PRINT_ORRR_2(Assembler::special_name[special]);
+          break;
         case Assembler::dsrlv_op:
+          if (insn & (1 << 6)) {
+             PRINT_ORRR_2("drotrv");
+          } else {
+             PRINT_ORRR_2(Assembler::special_name[special]);
+          }
+          break;
         case Assembler::dsrav_op:
           PRINT_ORRR_2(Assembler::special_name[special]);
           break;