Mercurial > jdk8-mips64-public > hotspot / file comparison
comparison: src/cpu/mips/vm/assembler_mips.hpp
src/cpu/mips/vm/assembler_mips.hpp
- changeset 315
- 8ac5b6ff8466
- parent 301
- d585b6706dc2
- child 318
- b7127982c97c
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| 314:5682475ccb5d | 315:8ac5b6ff8466 |
|---|---|
| 1090 int msbd = size - 1; | 1090 int msbd = size - 1; |
| 1091 | 1091 |
| 1092 emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (msbd << 11) | (lsb << 6) | dext_op); | 1092 emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (msbd << 11) | (lsb << 6) | dext_op); |
| 1093 } | 1093 } |
| 1094 | 1094 |
| 1095 void rotr (Register rd, Register rt, int sa) { | |
| 1096 emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | srl_op); | |
| 1097 } | |
| 1098 | |
| 1099 void drotr (Register rd, Register rt, int sa) { | |
| 1100 emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | dsrl_op); | |
| 1101 } | |
| 1102 | |
| 1103 void drotr32 (Register rd, Register rt, int sa) { | |
| 1104 emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | dsrl32_op); | |
| 1105 } | |
| 1106 | |
| 1107 void rotrv (Register rd, Register rt, Register rs) { | |
| 1108 emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | srlv_op); | |
| 1109 } | |
| 1110 | |
| 1111 void drotrv (Register rd, Register rt, Register rs) { | |
| 1112 emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | dsrlv_op); | |
| 1113 } | |
| 1114 | |
| 1095 // Do mult and div need both 32-bit and 64-bit version? FIXME aoqi | 1115 // Do mult and div need both 32-bit and 64-bit version? FIXME aoqi |
| 1096 //#ifndef _LP64 | 1116 //#ifndef _LP64 |
| 1097 #if 1 | 1117 #if 1 |
| 1098 void div (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, div_op)); } | 1118 void div (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, div_op)); } |
| 1099 void divu (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, divu_op)); } | 1119 void divu (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, divu_op)); } |
