Thu, 19 Jan 2012 10:56:51 -0800
7131288: COMPILE SKIPPED: deopt handler overflow (retry at different tier)
Summary: Fix exception handler stub size, enable guarantees to check for the correct deopt and exception stub sizes in the future
Reviewed-by: kvn, never, twisti
duke@435 | 1 | /* |
iveresov@2432 | 2 | * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
twisti@2697 | 26 | #include "asm/assembler.hpp" |
stefank@2314 | 27 | #include "c1/c1_Compilation.hpp" |
stefank@2314 | 28 | #include "c1/c1_LIRAssembler.hpp" |
stefank@2314 | 29 | #include "c1/c1_MacroAssembler.hpp" |
stefank@2314 | 30 | #include "c1/c1_Runtime1.hpp" |
stefank@2314 | 31 | #include "c1/c1_ValueStack.hpp" |
stefank@2314 | 32 | #include "ci/ciArrayKlass.hpp" |
stefank@2314 | 33 | #include "ci/ciInstance.hpp" |
stefank@2314 | 34 | #include "gc_interface/collectedHeap.hpp" |
stefank@2314 | 35 | #include "memory/barrierSet.hpp" |
stefank@2314 | 36 | #include "memory/cardTableModRefBS.hpp" |
stefank@2314 | 37 | #include "nativeInst_x86.hpp" |
stefank@2314 | 38 | #include "oops/objArrayKlass.hpp" |
stefank@2314 | 39 | #include "runtime/sharedRuntime.hpp" |
duke@435 | 40 | |
duke@435 | 41 | |
duke@435 | 42 | // These masks are used to provide 128-bit aligned bitmasks to the XMM |
duke@435 | 43 | // instructions, to allow sign-masking or sign-bit flipping. They allow |
duke@435 | 44 | // fast versions of NegF/NegD and AbsF/AbsD. |
duke@435 | 45 | |
duke@435 | 46 | // Note: 'double' and 'long long' have 32-bits alignment on x86. |
duke@435 | 47 | static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { |
duke@435 | 48 | // Use the expression (adr)&(~0xF) to provide 128-bits aligned address |
duke@435 | 49 | // of 128-bits operands for SSE instructions. |
iveresov@2932 | 50 | jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); |
duke@435 | 51 | // Store the value to a 128-bits operand. |
duke@435 | 52 | operand[0] = lo; |
duke@435 | 53 | operand[1] = hi; |
duke@435 | 54 | return operand; |
duke@435 | 55 | } |
duke@435 | 56 | |
duke@435 | 57 | // Buffer for 128-bits masks used by SSE instructions. |
duke@435 | 58 | static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) |
duke@435 | 59 | |
duke@435 | 60 | // Static initialization during VM startup. |
duke@435 | 61 | static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); |
duke@435 | 62 | static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); |
duke@435 | 63 | static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); |
duke@435 | 64 | static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); |
duke@435 | 65 | |
duke@435 | 66 | |
duke@435 | 67 | |
duke@435 | 68 | NEEDS_CLEANUP // remove this definitions ? |
duke@435 | 69 | const Register IC_Klass = rax; // where the IC klass is cached |
duke@435 | 70 | const Register SYNC_header = rax; // synchronization header |
duke@435 | 71 | const Register SHIFT_count = rcx; // where count for shift operations must be |
duke@435 | 72 | |
duke@435 | 73 | #define __ _masm-> |
duke@435 | 74 | |
duke@435 | 75 | |
duke@435 | 76 | static void select_different_registers(Register preserve, |
duke@435 | 77 | Register extra, |
duke@435 | 78 | Register &tmp1, |
duke@435 | 79 | Register &tmp2) { |
duke@435 | 80 | if (tmp1 == preserve) { |
duke@435 | 81 | assert_different_registers(tmp1, tmp2, extra); |
duke@435 | 82 | tmp1 = extra; |
duke@435 | 83 | } else if (tmp2 == preserve) { |
duke@435 | 84 | assert_different_registers(tmp1, tmp2, extra); |
duke@435 | 85 | tmp2 = extra; |
duke@435 | 86 | } |
duke@435 | 87 | assert_different_registers(preserve, tmp1, tmp2); |
duke@435 | 88 | } |
duke@435 | 89 | |
duke@435 | 90 | |
duke@435 | 91 | |
duke@435 | 92 | static void select_different_registers(Register preserve, |
duke@435 | 93 | Register extra, |
duke@435 | 94 | Register &tmp1, |
duke@435 | 95 | Register &tmp2, |
duke@435 | 96 | Register &tmp3) { |
duke@435 | 97 | if (tmp1 == preserve) { |
duke@435 | 98 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 99 | tmp1 = extra; |
duke@435 | 100 | } else if (tmp2 == preserve) { |
duke@435 | 101 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 102 | tmp2 = extra; |
duke@435 | 103 | } else if (tmp3 == preserve) { |
duke@435 | 104 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 105 | tmp3 = extra; |
duke@435 | 106 | } |
duke@435 | 107 | assert_different_registers(preserve, tmp1, tmp2, tmp3); |
duke@435 | 108 | } |
duke@435 | 109 | |
duke@435 | 110 | |
duke@435 | 111 | |
duke@435 | 112 | bool LIR_Assembler::is_small_constant(LIR_Opr opr) { |
duke@435 | 113 | if (opr->is_constant()) { |
duke@435 | 114 | LIR_Const* constant = opr->as_constant_ptr(); |
duke@435 | 115 | switch (constant->type()) { |
duke@435 | 116 | case T_INT: { |
duke@435 | 117 | return true; |
duke@435 | 118 | } |
duke@435 | 119 | |
duke@435 | 120 | default: |
duke@435 | 121 | return false; |
duke@435 | 122 | } |
duke@435 | 123 | } |
duke@435 | 124 | return false; |
duke@435 | 125 | } |
duke@435 | 126 | |
duke@435 | 127 | |
duke@435 | 128 | LIR_Opr LIR_Assembler::receiverOpr() { |
never@739 | 129 | return FrameMap::receiver_opr; |
duke@435 | 130 | } |
duke@435 | 131 | |
duke@435 | 132 | LIR_Opr LIR_Assembler::osrBufferPointer() { |
never@739 | 133 | return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
duke@435 | 134 | } |
duke@435 | 135 | |
duke@435 | 136 | //--------------fpu register translations----------------------- |
duke@435 | 137 | |
duke@435 | 138 | |
duke@435 | 139 | address LIR_Assembler::float_constant(float f) { |
duke@435 | 140 | address const_addr = __ float_constant(f); |
duke@435 | 141 | if (const_addr == NULL) { |
duke@435 | 142 | bailout("const section overflow"); |
duke@435 | 143 | return __ code()->consts()->start(); |
duke@435 | 144 | } else { |
duke@435 | 145 | return const_addr; |
duke@435 | 146 | } |
duke@435 | 147 | } |
duke@435 | 148 | |
duke@435 | 149 | |
duke@435 | 150 | address LIR_Assembler::double_constant(double d) { |
duke@435 | 151 | address const_addr = __ double_constant(d); |
duke@435 | 152 | if (const_addr == NULL) { |
duke@435 | 153 | bailout("const section overflow"); |
duke@435 | 154 | return __ code()->consts()->start(); |
duke@435 | 155 | } else { |
duke@435 | 156 | return const_addr; |
duke@435 | 157 | } |
duke@435 | 158 | } |
duke@435 | 159 | |
duke@435 | 160 | |
duke@435 | 161 | void LIR_Assembler::set_24bit_FPU() { |
duke@435 | 162 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); |
duke@435 | 163 | } |
duke@435 | 164 | |
duke@435 | 165 | void LIR_Assembler::reset_FPU() { |
duke@435 | 166 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
duke@435 | 167 | } |
duke@435 | 168 | |
duke@435 | 169 | void LIR_Assembler::fpop() { |
duke@435 | 170 | __ fpop(); |
duke@435 | 171 | } |
duke@435 | 172 | |
duke@435 | 173 | void LIR_Assembler::fxch(int i) { |
duke@435 | 174 | __ fxch(i); |
duke@435 | 175 | } |
duke@435 | 176 | |
duke@435 | 177 | void LIR_Assembler::fld(int i) { |
duke@435 | 178 | __ fld_s(i); |
duke@435 | 179 | } |
duke@435 | 180 | |
duke@435 | 181 | void LIR_Assembler::ffree(int i) { |
duke@435 | 182 | __ ffree(i); |
duke@435 | 183 | } |
duke@435 | 184 | |
duke@435 | 185 | void LIR_Assembler::breakpoint() { |
duke@435 | 186 | __ int3(); |
duke@435 | 187 | } |
duke@435 | 188 | |
duke@435 | 189 | void LIR_Assembler::push(LIR_Opr opr) { |
duke@435 | 190 | if (opr->is_single_cpu()) { |
duke@435 | 191 | __ push_reg(opr->as_register()); |
duke@435 | 192 | } else if (opr->is_double_cpu()) { |
never@739 | 193 | NOT_LP64(__ push_reg(opr->as_register_hi())); |
duke@435 | 194 | __ push_reg(opr->as_register_lo()); |
duke@435 | 195 | } else if (opr->is_stack()) { |
duke@435 | 196 | __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); |
duke@435 | 197 | } else if (opr->is_constant()) { |
duke@435 | 198 | LIR_Const* const_opr = opr->as_constant_ptr(); |
duke@435 | 199 | if (const_opr->type() == T_OBJECT) { |
duke@435 | 200 | __ push_oop(const_opr->as_jobject()); |
duke@435 | 201 | } else if (const_opr->type() == T_INT) { |
duke@435 | 202 | __ push_jint(const_opr->as_jint()); |
duke@435 | 203 | } else { |
duke@435 | 204 | ShouldNotReachHere(); |
duke@435 | 205 | } |
duke@435 | 206 | |
duke@435 | 207 | } else { |
duke@435 | 208 | ShouldNotReachHere(); |
duke@435 | 209 | } |
duke@435 | 210 | } |
duke@435 | 211 | |
duke@435 | 212 | void LIR_Assembler::pop(LIR_Opr opr) { |
duke@435 | 213 | if (opr->is_single_cpu()) { |
never@739 | 214 | __ pop_reg(opr->as_register()); |
duke@435 | 215 | } else { |
duke@435 | 216 | ShouldNotReachHere(); |
duke@435 | 217 | } |
duke@435 | 218 | } |
duke@435 | 219 | |
never@739 | 220 | bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
never@739 | 221 | return addr->base()->is_illegal() && addr->index()->is_illegal(); |
never@739 | 222 | } |
never@739 | 223 | |
duke@435 | 224 | //------------------------------------------- |
never@739 | 225 | |
duke@435 | 226 | Address LIR_Assembler::as_Address(LIR_Address* addr) { |
never@739 | 227 | return as_Address(addr, rscratch1); |
never@739 | 228 | } |
never@739 | 229 | |
never@739 | 230 | Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { |
duke@435 | 231 | if (addr->base()->is_illegal()) { |
duke@435 | 232 | assert(addr->index()->is_illegal(), "must be illegal too"); |
never@739 | 233 | AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
never@739 | 234 | if (! __ reachable(laddr)) { |
never@739 | 235 | __ movptr(tmp, laddr.addr()); |
never@739 | 236 | Address res(tmp, 0); |
never@739 | 237 | return res; |
never@739 | 238 | } else { |
never@739 | 239 | return __ as_Address(laddr); |
never@739 | 240 | } |
duke@435 | 241 | } |
duke@435 | 242 | |
never@739 | 243 | Register base = addr->base()->as_pointer_register(); |
duke@435 | 244 | |
duke@435 | 245 | if (addr->index()->is_illegal()) { |
duke@435 | 246 | return Address( base, addr->disp()); |
never@739 | 247 | } else if (addr->index()->is_cpu_register()) { |
never@739 | 248 | Register index = addr->index()->as_pointer_register(); |
duke@435 | 249 | return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
duke@435 | 250 | } else if (addr->index()->is_constant()) { |
never@739 | 251 | intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
never@739 | 252 | assert(Assembler::is_simm32(addr_offset), "must be"); |
duke@435 | 253 | |
duke@435 | 254 | return Address(base, addr_offset); |
duke@435 | 255 | } else { |
duke@435 | 256 | Unimplemented(); |
duke@435 | 257 | return Address(); |
duke@435 | 258 | } |
duke@435 | 259 | } |
duke@435 | 260 | |
duke@435 | 261 | |
duke@435 | 262 | Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { |
duke@435 | 263 | Address base = as_Address(addr); |
duke@435 | 264 | return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); |
duke@435 | 265 | } |
duke@435 | 266 | |
duke@435 | 267 | |
duke@435 | 268 | Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { |
duke@435 | 269 | return as_Address(addr); |
duke@435 | 270 | } |
duke@435 | 271 | |
duke@435 | 272 | |
duke@435 | 273 | void LIR_Assembler::osr_entry() { |
duke@435 | 274 | offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); |
duke@435 | 275 | BlockBegin* osr_entry = compilation()->hir()->osr_entry(); |
duke@435 | 276 | ValueStack* entry_state = osr_entry->state(); |
duke@435 | 277 | int number_of_locks = entry_state->locks_size(); |
duke@435 | 278 | |
duke@435 | 279 | // we jump here if osr happens with the interpreter |
duke@435 | 280 | // state set up to continue at the beginning of the |
duke@435 | 281 | // loop that triggered osr - in particular, we have |
duke@435 | 282 | // the following registers setup: |
duke@435 | 283 | // |
duke@435 | 284 | // rcx: osr buffer |
duke@435 | 285 | // |
duke@435 | 286 | |
duke@435 | 287 | // build frame |
duke@435 | 288 | ciMethod* m = compilation()->method(); |
duke@435 | 289 | __ build_frame(initial_frame_size_in_bytes()); |
duke@435 | 290 | |
duke@435 | 291 | // OSR buffer is |
duke@435 | 292 | // |
duke@435 | 293 | // locals[nlocals-1..0] |
duke@435 | 294 | // monitors[0..number_of_locks] |
duke@435 | 295 | // |
duke@435 | 296 | // locals is a direct copy of the interpreter frame so in the osr buffer |
duke@435 | 297 | // so first slot in the local array is the last local from the interpreter |
duke@435 | 298 | // and last slot is local[0] (receiver) from the interpreter |
duke@435 | 299 | // |
duke@435 | 300 | // Similarly with locks. The first lock slot in the osr buffer is the nth lock |
duke@435 | 301 | // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock |
duke@435 | 302 | // in the interpreter frame (the method lock if a sync method) |
duke@435 | 303 | |
duke@435 | 304 | // Initialize monitors in the compiled activation. |
duke@435 | 305 | // rcx: pointer to osr buffer |
duke@435 | 306 | // |
duke@435 | 307 | // All other registers are dead at this point and the locals will be |
duke@435 | 308 | // copied into place by code emitted in the IR. |
duke@435 | 309 | |
never@739 | 310 | Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
duke@435 | 311 | { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
duke@435 | 312 | int monitor_offset = BytesPerWord * method()->max_locals() + |
roland@1495 | 313 | (2 * BytesPerWord) * (number_of_locks - 1); |
roland@1495 | 314 | // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in |
roland@1495 | 315 | // the OSR buffer using 2 word entries: first the lock and then |
roland@1495 | 316 | // the oop. |
duke@435 | 317 | for (int i = 0; i < number_of_locks; i++) { |
roland@1495 | 318 | int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
duke@435 | 319 | #ifdef ASSERT |
duke@435 | 320 | // verify the interpreter's monitor has a non-null object |
duke@435 | 321 | { |
duke@435 | 322 | Label L; |
roland@1495 | 323 | __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); |
duke@435 | 324 | __ jcc(Assembler::notZero, L); |
duke@435 | 325 | __ stop("locked object is NULL"); |
duke@435 | 326 | __ bind(L); |
duke@435 | 327 | } |
duke@435 | 328 | #endif |
roland@1495 | 329 | __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); |
never@739 | 330 | __ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
roland@1495 | 331 | __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); |
never@739 | 332 | __ movptr(frame_map()->address_for_monitor_object(i), rbx); |
duke@435 | 333 | } |
duke@435 | 334 | } |
duke@435 | 335 | } |
duke@435 | 336 | |
duke@435 | 337 | |
duke@435 | 338 | // inline cache check; done before the frame is built. |
duke@435 | 339 | int LIR_Assembler::check_icache() { |
duke@435 | 340 | Register receiver = FrameMap::receiver_opr->as_register(); |
duke@435 | 341 | Register ic_klass = IC_Klass; |
never@739 | 342 | const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
iveresov@2344 | 343 | const bool do_post_padding = VerifyOops || UseCompressedOops; |
iveresov@2344 | 344 | if (!do_post_padding) { |
duke@435 | 345 | // insert some nops so that the verified entry point is aligned on CodeEntryAlignment |
never@739 | 346 | while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
duke@435 | 347 | __ nop(); |
duke@435 | 348 | } |
duke@435 | 349 | } |
duke@435 | 350 | int offset = __ offset(); |
duke@435 | 351 | __ inline_cache_check(receiver, IC_Klass); |
iveresov@2344 | 352 | assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); |
iveresov@2344 | 353 | if (do_post_padding) { |
duke@435 | 354 | // force alignment after the cache check. |
duke@435 | 355 | // It's been verified to be aligned if !VerifyOops |
duke@435 | 356 | __ align(CodeEntryAlignment); |
duke@435 | 357 | } |
duke@435 | 358 | return offset; |
duke@435 | 359 | } |
duke@435 | 360 | |
duke@435 | 361 | |
duke@435 | 362 | void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { |
duke@435 | 363 | jobject o = NULL; |
duke@435 | 364 | PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); |
duke@435 | 365 | __ movoop(reg, o); |
duke@435 | 366 | patching_epilog(patch, lir_patch_normal, reg, info); |
duke@435 | 367 | } |
duke@435 | 368 | |
duke@435 | 369 | |
duke@435 | 370 | // This specifies the rsp decrement needed to build the frame |
duke@435 | 371 | int LIR_Assembler::initial_frame_size_in_bytes() { |
duke@435 | 372 | // if rounding, must let FrameMap know! |
never@739 | 373 | |
never@739 | 374 | // The frame_map records size in slots (32bit word) |
never@739 | 375 | |
never@739 | 376 | // subtract two words to account for return address and link |
never@739 | 377 | return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; |
duke@435 | 378 | } |
duke@435 | 379 | |
duke@435 | 380 | |
twisti@1639 | 381 | int LIR_Assembler::emit_exception_handler() { |
duke@435 | 382 | // if the last instruction is a call (typically to do a throw which |
duke@435 | 383 | // is coming at the end after block reordering) the return address |
duke@435 | 384 | // must still point into the code area in order to avoid assertion |
duke@435 | 385 | // failures when searching for the corresponding bci => add a nop |
duke@435 | 386 | // (was bug 5/14/1999 - gri) |
duke@435 | 387 | __ nop(); |
duke@435 | 388 | |
duke@435 | 389 | // generate code for exception handler |
duke@435 | 390 | address handler_base = __ start_a_stub(exception_handler_size); |
duke@435 | 391 | if (handler_base == NULL) { |
duke@435 | 392 | // not enough space left for the handler |
duke@435 | 393 | bailout("exception handler overflow"); |
twisti@1639 | 394 | return -1; |
duke@435 | 395 | } |
twisti@1639 | 396 | |
duke@435 | 397 | int offset = code_offset(); |
duke@435 | 398 | |
twisti@1730 | 399 | // the exception oop and pc are in rax, and rdx |
duke@435 | 400 | // no other registers need to be preserved, so invalidate them |
twisti@1730 | 401 | __ invalidate_registers(false, true, true, false, true, true); |
duke@435 | 402 | |
duke@435 | 403 | // check that there is really an exception |
duke@435 | 404 | __ verify_not_null_oop(rax); |
duke@435 | 405 | |
twisti@1730 | 406 | // search an exception handler (rax: exception oop, rdx: throwing pc) |
twisti@2603 | 407 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); |
twisti@2603 | 408 | __ should_not_reach_here(); |
iveresov@3435 | 409 | guarantee(code_offset() - offset <= exception_handler_size, "overflow"); |
duke@435 | 410 | __ end_a_stub(); |
twisti@1639 | 411 | |
twisti@1639 | 412 | return offset; |
duke@435 | 413 | } |
duke@435 | 414 | |
twisti@1639 | 415 | |
never@1813 | 416 | // Emit the code to remove the frame from the stack in the exception |
never@1813 | 417 | // unwind path. |
never@1813 | 418 | int LIR_Assembler::emit_unwind_handler() { |
never@1813 | 419 | #ifndef PRODUCT |
never@1813 | 420 | if (CommentedAssembly) { |
never@1813 | 421 | _masm->block_comment("Unwind handler"); |
never@1813 | 422 | } |
never@1813 | 423 | #endif |
never@1813 | 424 | |
never@1813 | 425 | int offset = code_offset(); |
never@1813 | 426 | |
never@1813 | 427 | // Fetch the exception from TLS and clear out exception related thread state |
never@1813 | 428 | __ get_thread(rsi); |
never@1813 | 429 | __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); |
never@3156 | 430 | __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); |
never@3156 | 431 | __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); |
never@1813 | 432 | |
never@1813 | 433 | __ bind(_unwind_handler_entry); |
never@1813 | 434 | __ verify_not_null_oop(rax); |
never@1813 | 435 | if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
never@1813 | 436 | __ mov(rsi, rax); // Preserve the exception |
never@1813 | 437 | } |
never@1813 | 438 | |
never@1813 | 439 | // Preform needed unlocking |
never@1813 | 440 | MonitorExitStub* stub = NULL; |
never@1813 | 441 | if (method()->is_synchronized()) { |
never@1813 | 442 | monitor_address(0, FrameMap::rax_opr); |
never@1813 | 443 | stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); |
never@1813 | 444 | __ unlock_object(rdi, rbx, rax, *stub->entry()); |
never@1813 | 445 | __ bind(*stub->continuation()); |
never@1813 | 446 | } |
never@1813 | 447 | |
never@1813 | 448 | if (compilation()->env()->dtrace_method_probes()) { |
never@2185 | 449 | __ get_thread(rax); |
never@2185 | 450 | __ movptr(Address(rsp, 0), rax); |
never@2185 | 451 | __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding()); |
never@1813 | 452 | __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); |
never@1813 | 453 | } |
never@1813 | 454 | |
never@1813 | 455 | if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
never@1813 | 456 | __ mov(rax, rsi); // Restore the exception |
never@1813 | 457 | } |
never@1813 | 458 | |
never@1813 | 459 | // remove the activation and dispatch to the unwind handler |
never@1813 | 460 | __ remove_frame(initial_frame_size_in_bytes()); |
never@1813 | 461 | __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
never@1813 | 462 | |
never@1813 | 463 | // Emit the slow path assembly |
never@1813 | 464 | if (stub != NULL) { |
never@1813 | 465 | stub->emit_code(this); |
never@1813 | 466 | } |
never@1813 | 467 | |
never@1813 | 468 | return offset; |
never@1813 | 469 | } |
never@1813 | 470 | |
never@1813 | 471 | |
twisti@1639 | 472 | int LIR_Assembler::emit_deopt_handler() { |
duke@435 | 473 | // if the last instruction is a call (typically to do a throw which |
duke@435 | 474 | // is coming at the end after block reordering) the return address |
duke@435 | 475 | // must still point into the code area in order to avoid assertion |
duke@435 | 476 | // failures when searching for the corresponding bci => add a nop |
duke@435 | 477 | // (was bug 5/14/1999 - gri) |
duke@435 | 478 | __ nop(); |
duke@435 | 479 | |
duke@435 | 480 | // generate code for exception handler |
duke@435 | 481 | address handler_base = __ start_a_stub(deopt_handler_size); |
duke@435 | 482 | if (handler_base == NULL) { |
duke@435 | 483 | // not enough space left for the handler |
duke@435 | 484 | bailout("deopt handler overflow"); |
twisti@1639 | 485 | return -1; |
duke@435 | 486 | } |
twisti@1639 | 487 | |
duke@435 | 488 | int offset = code_offset(); |
duke@435 | 489 | InternalAddress here(__ pc()); |
twisti@1730 | 490 | |
duke@435 | 491 | __ pushptr(here.addr()); |
duke@435 | 492 | __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
iveresov@3435 | 493 | guarantee(code_offset() - offset <= deopt_handler_size, "overflow"); |
duke@435 | 494 | __ end_a_stub(); |
duke@435 | 495 | |
twisti@1639 | 496 | return offset; |
duke@435 | 497 | } |
duke@435 | 498 | |
duke@435 | 499 | |
duke@435 | 500 | // This is the fast version of java.lang.String.compare; it has not |
duke@435 | 501 | // OSR-entry and therefore, we generate a slow version for OSR's |
duke@435 | 502 | void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { |
never@739 | 503 | __ movptr (rbx, rcx); // receiver is in rcx |
never@739 | 504 | __ movptr (rax, arg1->as_register()); |
duke@435 | 505 | |
duke@435 | 506 | // Get addresses of first characters from both Strings |
iveresov@2344 | 507 | __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
iveresov@2344 | 508 | __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); |
iveresov@2344 | 509 | __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); |
duke@435 | 510 | |
duke@435 | 511 | |
duke@435 | 512 | // rbx, may be NULL |
duke@435 | 513 | add_debug_info_for_null_check_here(info); |
iveresov@2344 | 514 | __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
iveresov@2344 | 515 | __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); |
iveresov@2344 | 516 | __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); |
duke@435 | 517 | |
duke@435 | 518 | // compute minimum length (in rax) and difference of lengths (on top of stack) |
twisti@2697 | 519 | __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
twisti@2697 | 520 | __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); |
twisti@2697 | 521 | __ mov (rcx, rbx); |
twisti@2697 | 522 | __ subptr(rbx, rax); // subtract lengths |
twisti@2697 | 523 | __ push (rbx); // result |
twisti@2697 | 524 | __ cmov (Assembler::lessEqual, rax, rcx); |
twisti@2697 | 525 | |
duke@435 | 526 | // is minimum length 0? |
duke@435 | 527 | Label noLoop, haveResult; |
never@739 | 528 | __ testptr (rax, rax); |
duke@435 | 529 | __ jcc (Assembler::zero, noLoop); |
duke@435 | 530 | |
duke@435 | 531 | // compare first characters |
jrose@1057 | 532 | __ load_unsigned_short(rcx, Address(rdi, 0)); |
jrose@1057 | 533 | __ load_unsigned_short(rbx, Address(rsi, 0)); |
duke@435 | 534 | __ subl(rcx, rbx); |
duke@435 | 535 | __ jcc(Assembler::notZero, haveResult); |
duke@435 | 536 | // starting loop |
duke@435 | 537 | __ decrement(rax); // we already tested index: skip one |
duke@435 | 538 | __ jcc(Assembler::zero, noLoop); |
duke@435 | 539 | |
duke@435 | 540 | // set rsi.edi to the end of the arrays (arrays have same length) |
duke@435 | 541 | // negate the index |
duke@435 | 542 | |
never@739 | 543 | __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
never@739 | 544 | __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
never@739 | 545 | __ negptr(rax); |
duke@435 | 546 | |
duke@435 | 547 | // compare the strings in a loop |
duke@435 | 548 | |
duke@435 | 549 | Label loop; |
duke@435 | 550 | __ align(wordSize); |
duke@435 | 551 | __ bind(loop); |
jrose@1057 | 552 | __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
jrose@1057 | 553 | __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
duke@435 | 554 | __ subl(rcx, rbx); |
duke@435 | 555 | __ jcc(Assembler::notZero, haveResult); |
duke@435 | 556 | __ increment(rax); |
duke@435 | 557 | __ jcc(Assembler::notZero, loop); |
duke@435 | 558 | |
duke@435 | 559 | // strings are equal up to min length |
duke@435 | 560 | |
duke@435 | 561 | __ bind(noLoop); |
never@739 | 562 | __ pop(rax); |
duke@435 | 563 | return_op(LIR_OprFact::illegalOpr); |
duke@435 | 564 | |
duke@435 | 565 | __ bind(haveResult); |
duke@435 | 566 | // leave instruction is going to discard the TOS value |
never@739 | 567 | __ mov (rax, rcx); // result of call is in rax, |
duke@435 | 568 | } |
duke@435 | 569 | |
duke@435 | 570 | |
duke@435 | 571 | void LIR_Assembler::return_op(LIR_Opr result) { |
duke@435 | 572 | assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); |
duke@435 | 573 | if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { |
duke@435 | 574 | assert(result->fpu() == 0, "result must already be on TOS"); |
duke@435 | 575 | } |
duke@435 | 576 | |
duke@435 | 577 | // Pop the stack before the safepoint code |
twisti@1730 | 578 | __ remove_frame(initial_frame_size_in_bytes()); |
duke@435 | 579 | |
duke@435 | 580 | bool result_is_oop = result->is_valid() ? result->is_oop() : false; |
duke@435 | 581 | |
duke@435 | 582 | // Note: we do not need to round double result; float result has the right precision |
duke@435 | 583 | // the poll sets the condition code, but no data registers |
duke@435 | 584 | AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), |
duke@435 | 585 | relocInfo::poll_return_type); |
never@739 | 586 | |
iveresov@2686 | 587 | if (Assembler::is_polling_page_far()) { |
iveresov@2686 | 588 | __ lea(rscratch1, polling_page); |
iveresov@2686 | 589 | __ relocate(relocInfo::poll_return_type); |
iveresov@2686 | 590 | __ testl(rax, Address(rscratch1, 0)); |
iveresov@2686 | 591 | } else { |
iveresov@2686 | 592 | __ testl(rax, polling_page); |
iveresov@2686 | 593 | } |
duke@435 | 594 | __ ret(0); |
duke@435 | 595 | } |
duke@435 | 596 | |
duke@435 | 597 | |
duke@435 | 598 | int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { |
duke@435 | 599 | AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), |
duke@435 | 600 | relocInfo::poll_type); |
iveresov@2686 | 601 | guarantee(info != NULL, "Shouldn't be NULL"); |
iveresov@2686 | 602 | int offset = __ offset(); |
iveresov@2686 | 603 | if (Assembler::is_polling_page_far()) { |
iveresov@2686 | 604 | __ lea(rscratch1, polling_page); |
iveresov@2686 | 605 | offset = __ offset(); |
duke@435 | 606 | add_debug_info_for_branch(info); |
iveresov@2686 | 607 | __ testl(rax, Address(rscratch1, 0)); |
duke@435 | 608 | } else { |
iveresov@2686 | 609 | add_debug_info_for_branch(info); |
iveresov@2686 | 610 | __ testl(rax, polling_page); |
duke@435 | 611 | } |
duke@435 | 612 | return offset; |
duke@435 | 613 | } |
duke@435 | 614 | |
duke@435 | 615 | |
duke@435 | 616 | void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { |
never@739 | 617 | if (from_reg != to_reg) __ mov(to_reg, from_reg); |
duke@435 | 618 | } |
duke@435 | 619 | |
duke@435 | 620 | void LIR_Assembler::swap_reg(Register a, Register b) { |
never@739 | 621 | __ xchgptr(a, b); |
duke@435 | 622 | } |
duke@435 | 623 | |
duke@435 | 624 | |
duke@435 | 625 | void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { |
duke@435 | 626 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 627 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 628 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 629 | |
duke@435 | 630 | switch (c->type()) { |
iveresov@2344 | 631 | case T_INT: { |
iveresov@2344 | 632 | assert(patch_code == lir_patch_none, "no patching handled here"); |
iveresov@2344 | 633 | __ movl(dest->as_register(), c->as_jint()); |
iveresov@2344 | 634 | break; |
iveresov@2344 | 635 | } |
iveresov@2344 | 636 | |
roland@1732 | 637 | case T_ADDRESS: { |
duke@435 | 638 | assert(patch_code == lir_patch_none, "no patching handled here"); |
iveresov@2344 | 639 | __ movptr(dest->as_register(), c->as_jint()); |
duke@435 | 640 | break; |
duke@435 | 641 | } |
duke@435 | 642 | |
duke@435 | 643 | case T_LONG: { |
duke@435 | 644 | assert(patch_code == lir_patch_none, "no patching handled here"); |
never@739 | 645 | #ifdef _LP64 |
never@739 | 646 | __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); |
never@739 | 647 | #else |
never@739 | 648 | __ movptr(dest->as_register_lo(), c->as_jint_lo()); |
never@739 | 649 | __ movptr(dest->as_register_hi(), c->as_jint_hi()); |
never@739 | 650 | #endif // _LP64 |
duke@435 | 651 | break; |
duke@435 | 652 | } |
duke@435 | 653 | |
duke@435 | 654 | case T_OBJECT: { |
duke@435 | 655 | if (patch_code != lir_patch_none) { |
duke@435 | 656 | jobject2reg_with_patching(dest->as_register(), info); |
duke@435 | 657 | } else { |
duke@435 | 658 | __ movoop(dest->as_register(), c->as_jobject()); |
duke@435 | 659 | } |
duke@435 | 660 | break; |
duke@435 | 661 | } |
duke@435 | 662 | |
duke@435 | 663 | case T_FLOAT: { |
duke@435 | 664 | if (dest->is_single_xmm()) { |
duke@435 | 665 | if (c->is_zero_float()) { |
duke@435 | 666 | __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); |
duke@435 | 667 | } else { |
duke@435 | 668 | __ movflt(dest->as_xmm_float_reg(), |
duke@435 | 669 | InternalAddress(float_constant(c->as_jfloat()))); |
duke@435 | 670 | } |
duke@435 | 671 | } else { |
duke@435 | 672 | assert(dest->is_single_fpu(), "must be"); |
duke@435 | 673 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 674 | if (c->is_zero_float()) { |
duke@435 | 675 | __ fldz(); |
duke@435 | 676 | } else if (c->is_one_float()) { |
duke@435 | 677 | __ fld1(); |
duke@435 | 678 | } else { |
duke@435 | 679 | __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); |
duke@435 | 680 | } |
duke@435 | 681 | } |
duke@435 | 682 | break; |
duke@435 | 683 | } |
duke@435 | 684 | |
duke@435 | 685 | case T_DOUBLE: { |
duke@435 | 686 | if (dest->is_double_xmm()) { |
duke@435 | 687 | if (c->is_zero_double()) { |
duke@435 | 688 | __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); |
duke@435 | 689 | } else { |
duke@435 | 690 | __ movdbl(dest->as_xmm_double_reg(), |
duke@435 | 691 | InternalAddress(double_constant(c->as_jdouble()))); |
duke@435 | 692 | } |
duke@435 | 693 | } else { |
duke@435 | 694 | assert(dest->is_double_fpu(), "must be"); |
duke@435 | 695 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 696 | if (c->is_zero_double()) { |
duke@435 | 697 | __ fldz(); |
duke@435 | 698 | } else if (c->is_one_double()) { |
duke@435 | 699 | __ fld1(); |
duke@435 | 700 | } else { |
duke@435 | 701 | __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); |
duke@435 | 702 | } |
duke@435 | 703 | } |
duke@435 | 704 | break; |
duke@435 | 705 | } |
duke@435 | 706 | |
duke@435 | 707 | default: |
duke@435 | 708 | ShouldNotReachHere(); |
duke@435 | 709 | } |
duke@435 | 710 | } |
duke@435 | 711 | |
duke@435 | 712 | void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { |
duke@435 | 713 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 714 | assert(dest->is_stack(), "should not call otherwise"); |
duke@435 | 715 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 716 | |
duke@435 | 717 | switch (c->type()) { |
duke@435 | 718 | case T_INT: // fall through |
duke@435 | 719 | case T_FLOAT: |
iveresov@2344 | 720 | __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
iveresov@2344 | 721 | break; |
iveresov@2344 | 722 | |
roland@1732 | 723 | case T_ADDRESS: |
iveresov@2344 | 724 | __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
duke@435 | 725 | break; |
duke@435 | 726 | |
duke@435 | 727 | case T_OBJECT: |
duke@435 | 728 | __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); |
duke@435 | 729 | break; |
duke@435 | 730 | |
duke@435 | 731 | case T_LONG: // fall through |
duke@435 | 732 | case T_DOUBLE: |
never@739 | 733 | #ifdef _LP64 |
never@739 | 734 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 735 | lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); |
never@739 | 736 | #else |
never@739 | 737 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 738 | lo_word_offset_in_bytes), c->as_jint_lo_bits()); |
never@739 | 739 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 740 | hi_word_offset_in_bytes), c->as_jint_hi_bits()); |
never@739 | 741 | #endif // _LP64 |
duke@435 | 742 | break; |
duke@435 | 743 | |
duke@435 | 744 | default: |
duke@435 | 745 | ShouldNotReachHere(); |
duke@435 | 746 | } |
duke@435 | 747 | } |
duke@435 | 748 | |
iveresov@2344 | 749 | void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { |
duke@435 | 750 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 751 | assert(dest->is_address(), "should not call otherwise"); |
duke@435 | 752 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 753 | LIR_Address* addr = dest->as_address_ptr(); |
duke@435 | 754 | |
never@739 | 755 | int null_check_here = code_offset(); |
duke@435 | 756 | switch (type) { |
duke@435 | 757 | case T_INT: // fall through |
duke@435 | 758 | case T_FLOAT: |
iveresov@2344 | 759 | __ movl(as_Address(addr), c->as_jint_bits()); |
iveresov@2344 | 760 | break; |
iveresov@2344 | 761 | |
roland@1732 | 762 | case T_ADDRESS: |
iveresov@2344 | 763 | __ movptr(as_Address(addr), c->as_jint_bits()); |
duke@435 | 764 | break; |
duke@435 | 765 | |
duke@435 | 766 | case T_OBJECT: // fall through |
duke@435 | 767 | case T_ARRAY: |
duke@435 | 768 | if (c->as_jobject() == NULL) { |
iveresov@2344 | 769 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 770 | __ movl(as_Address(addr), (int32_t)NULL_WORD); |
iveresov@2344 | 771 | } else { |
iveresov@2344 | 772 | __ movptr(as_Address(addr), NULL_WORD); |
iveresov@2344 | 773 | } |
duke@435 | 774 | } else { |
never@739 | 775 | if (is_literal_address(addr)) { |
never@739 | 776 | ShouldNotReachHere(); |
never@739 | 777 | __ movoop(as_Address(addr, noreg), c->as_jobject()); |
never@739 | 778 | } else { |
roland@1495 | 779 | #ifdef _LP64 |
roland@1495 | 780 | __ movoop(rscratch1, c->as_jobject()); |
iveresov@2344 | 781 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 782 | __ encode_heap_oop(rscratch1); |
iveresov@2344 | 783 | null_check_here = code_offset(); |
iveresov@2344 | 784 | __ movl(as_Address_lo(addr), rscratch1); |
iveresov@2344 | 785 | } else { |
iveresov@2344 | 786 | null_check_here = code_offset(); |
iveresov@2344 | 787 | __ movptr(as_Address_lo(addr), rscratch1); |
iveresov@2344 | 788 | } |
roland@1495 | 789 | #else |
never@739 | 790 | __ movoop(as_Address(addr), c->as_jobject()); |
roland@1495 | 791 | #endif |
never@739 | 792 | } |
duke@435 | 793 | } |
duke@435 | 794 | break; |
duke@435 | 795 | |
duke@435 | 796 | case T_LONG: // fall through |
duke@435 | 797 | case T_DOUBLE: |
never@739 | 798 | #ifdef _LP64 |
never@739 | 799 | if (is_literal_address(addr)) { |
never@739 | 800 | ShouldNotReachHere(); |
never@739 | 801 | __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); |
never@739 | 802 | } else { |
never@739 | 803 | __ movptr(r10, (intptr_t)c->as_jlong_bits()); |
never@739 | 804 | null_check_here = code_offset(); |
never@739 | 805 | __ movptr(as_Address_lo(addr), r10); |
never@739 | 806 | } |
never@739 | 807 | #else |
never@739 | 808 | // Always reachable in 32bit so this doesn't produce useless move literal |
never@739 | 809 | __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); |
never@739 | 810 | __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); |
never@739 | 811 | #endif // _LP64 |
duke@435 | 812 | break; |
duke@435 | 813 | |
duke@435 | 814 | case T_BOOLEAN: // fall through |
duke@435 | 815 | case T_BYTE: |
duke@435 | 816 | __ movb(as_Address(addr), c->as_jint() & 0xFF); |
duke@435 | 817 | break; |
duke@435 | 818 | |
duke@435 | 819 | case T_CHAR: // fall through |
duke@435 | 820 | case T_SHORT: |
duke@435 | 821 | __ movw(as_Address(addr), c->as_jint() & 0xFFFF); |
duke@435 | 822 | break; |
duke@435 | 823 | |
duke@435 | 824 | default: |
duke@435 | 825 | ShouldNotReachHere(); |
duke@435 | 826 | }; |
never@739 | 827 | |
never@739 | 828 | if (info != NULL) { |
never@739 | 829 | add_debug_info_for_null_check(null_check_here, info); |
never@739 | 830 | } |
duke@435 | 831 | } |
duke@435 | 832 | |
duke@435 | 833 | |
duke@435 | 834 | void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { |
duke@435 | 835 | assert(src->is_register(), "should not call otherwise"); |
duke@435 | 836 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 837 | |
duke@435 | 838 | // move between cpu-registers |
duke@435 | 839 | if (dest->is_single_cpu()) { |
never@739 | 840 | #ifdef _LP64 |
never@739 | 841 | if (src->type() == T_LONG) { |
never@739 | 842 | // Can do LONG -> OBJECT |
never@739 | 843 | move_regs(src->as_register_lo(), dest->as_register()); |
never@739 | 844 | return; |
never@739 | 845 | } |
never@739 | 846 | #endif |
duke@435 | 847 | assert(src->is_single_cpu(), "must match"); |
duke@435 | 848 | if (src->type() == T_OBJECT) { |
duke@435 | 849 | __ verify_oop(src->as_register()); |
duke@435 | 850 | } |
duke@435 | 851 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 852 | |
duke@435 | 853 | } else if (dest->is_double_cpu()) { |
never@739 | 854 | #ifdef _LP64 |
never@739 | 855 | if (src->type() == T_OBJECT || src->type() == T_ARRAY) { |
never@739 | 856 | // Surprising to me but we can see move of a long to t_object |
never@739 | 857 | __ verify_oop(src->as_register()); |
never@739 | 858 | move_regs(src->as_register(), dest->as_register_lo()); |
never@739 | 859 | return; |
never@739 | 860 | } |
never@739 | 861 | #endif |
duke@435 | 862 | assert(src->is_double_cpu(), "must match"); |
duke@435 | 863 | Register f_lo = src->as_register_lo(); |
duke@435 | 864 | Register f_hi = src->as_register_hi(); |
duke@435 | 865 | Register t_lo = dest->as_register_lo(); |
duke@435 | 866 | Register t_hi = dest->as_register_hi(); |
never@739 | 867 | #ifdef _LP64 |
never@739 | 868 | assert(f_hi == f_lo, "must be same"); |
never@739 | 869 | assert(t_hi == t_lo, "must be same"); |
never@739 | 870 | move_regs(f_lo, t_lo); |
never@739 | 871 | #else |
duke@435 | 872 | assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
duke@435 | 873 | |
never@739 | 874 | |
duke@435 | 875 | if (f_lo == t_hi && f_hi == t_lo) { |
duke@435 | 876 | swap_reg(f_lo, f_hi); |
duke@435 | 877 | } else if (f_hi == t_lo) { |
duke@435 | 878 | assert(f_lo != t_hi, "overwriting register"); |
duke@435 | 879 | move_regs(f_hi, t_hi); |
duke@435 | 880 | move_regs(f_lo, t_lo); |
duke@435 | 881 | } else { |
duke@435 | 882 | assert(f_hi != t_lo, "overwriting register"); |
duke@435 | 883 | move_regs(f_lo, t_lo); |
duke@435 | 884 | move_regs(f_hi, t_hi); |
duke@435 | 885 | } |
never@739 | 886 | #endif // LP64 |
duke@435 | 887 | |
duke@435 | 888 | // special moves from fpu-register to xmm-register |
duke@435 | 889 | // necessary for method results |
duke@435 | 890 | } else if (src->is_single_xmm() && !dest->is_single_xmm()) { |
duke@435 | 891 | __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); |
duke@435 | 892 | __ fld_s(Address(rsp, 0)); |
duke@435 | 893 | } else if (src->is_double_xmm() && !dest->is_double_xmm()) { |
duke@435 | 894 | __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); |
duke@435 | 895 | __ fld_d(Address(rsp, 0)); |
duke@435 | 896 | } else if (dest->is_single_xmm() && !src->is_single_xmm()) { |
duke@435 | 897 | __ fstp_s(Address(rsp, 0)); |
duke@435 | 898 | __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); |
duke@435 | 899 | } else if (dest->is_double_xmm() && !src->is_double_xmm()) { |
duke@435 | 900 | __ fstp_d(Address(rsp, 0)); |
duke@435 | 901 | __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); |
duke@435 | 902 | |
duke@435 | 903 | // move between xmm-registers |
duke@435 | 904 | } else if (dest->is_single_xmm()) { |
duke@435 | 905 | assert(src->is_single_xmm(), "must match"); |
duke@435 | 906 | __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); |
duke@435 | 907 | } else if (dest->is_double_xmm()) { |
duke@435 | 908 | assert(src->is_double_xmm(), "must match"); |
duke@435 | 909 | __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); |
duke@435 | 910 | |
duke@435 | 911 | // move between fpu-registers (no instruction necessary because of fpu-stack) |
duke@435 | 912 | } else if (dest->is_single_fpu() || dest->is_double_fpu()) { |
duke@435 | 913 | assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); |
duke@435 | 914 | assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); |
duke@435 | 915 | } else { |
duke@435 | 916 | ShouldNotReachHere(); |
duke@435 | 917 | } |
duke@435 | 918 | } |
duke@435 | 919 | |
duke@435 | 920 | void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { |
duke@435 | 921 | assert(src->is_register(), "should not call otherwise"); |
duke@435 | 922 | assert(dest->is_stack(), "should not call otherwise"); |
duke@435 | 923 | |
duke@435 | 924 | if (src->is_single_cpu()) { |
duke@435 | 925 | Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 926 | if (type == T_OBJECT || type == T_ARRAY) { |
duke@435 | 927 | __ verify_oop(src->as_register()); |
never@739 | 928 | __ movptr (dst, src->as_register()); |
never@739 | 929 | } else { |
never@739 | 930 | __ movl (dst, src->as_register()); |
duke@435 | 931 | } |
duke@435 | 932 | |
duke@435 | 933 | } else if (src->is_double_cpu()) { |
duke@435 | 934 | Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); |
duke@435 | 935 | Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); |
never@739 | 936 | __ movptr (dstLO, src->as_register_lo()); |
never@739 | 937 | NOT_LP64(__ movptr (dstHI, src->as_register_hi())); |
duke@435 | 938 | |
duke@435 | 939 | } else if (src->is_single_xmm()) { |
duke@435 | 940 | Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 941 | __ movflt(dst_addr, src->as_xmm_float_reg()); |
duke@435 | 942 | |
duke@435 | 943 | } else if (src->is_double_xmm()) { |
duke@435 | 944 | Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
duke@435 | 945 | __ movdbl(dst_addr, src->as_xmm_double_reg()); |
duke@435 | 946 | |
duke@435 | 947 | } else if (src->is_single_fpu()) { |
duke@435 | 948 | assert(src->fpu_regnr() == 0, "argument must be on TOS"); |
duke@435 | 949 | Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 950 | if (pop_fpu_stack) __ fstp_s (dst_addr); |
duke@435 | 951 | else __ fst_s (dst_addr); |
duke@435 | 952 | |
duke@435 | 953 | } else if (src->is_double_fpu()) { |
duke@435 | 954 | assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); |
duke@435 | 955 | Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
duke@435 | 956 | if (pop_fpu_stack) __ fstp_d (dst_addr); |
duke@435 | 957 | else __ fst_d (dst_addr); |
duke@435 | 958 | |
duke@435 | 959 | } else { |
duke@435 | 960 | ShouldNotReachHere(); |
duke@435 | 961 | } |
duke@435 | 962 | } |
duke@435 | 963 | |
duke@435 | 964 | |
iveresov@2344 | 965 | void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { |
duke@435 | 966 | LIR_Address* to_addr = dest->as_address_ptr(); |
duke@435 | 967 | PatchingStub* patch = NULL; |
iveresov@2344 | 968 | Register compressed_src = rscratch1; |
duke@435 | 969 | |
duke@435 | 970 | if (type == T_ARRAY || type == T_OBJECT) { |
duke@435 | 971 | __ verify_oop(src->as_register()); |
iveresov@2344 | 972 | #ifdef _LP64 |
iveresov@2344 | 973 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 974 | __ movptr(compressed_src, src->as_register()); |
iveresov@2344 | 975 | __ encode_heap_oop(compressed_src); |
iveresov@2344 | 976 | } |
iveresov@2344 | 977 | #endif |
duke@435 | 978 | } |
iveresov@2344 | 979 | |
duke@435 | 980 | if (patch_code != lir_patch_none) { |
duke@435 | 981 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
never@739 | 982 | Address toa = as_Address(to_addr); |
never@739 | 983 | assert(toa.disp() != 0, "must have"); |
duke@435 | 984 | } |
iveresov@2344 | 985 | |
iveresov@2344 | 986 | int null_check_here = code_offset(); |
duke@435 | 987 | switch (type) { |
duke@435 | 988 | case T_FLOAT: { |
duke@435 | 989 | if (src->is_single_xmm()) { |
duke@435 | 990 | __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); |
duke@435 | 991 | } else { |
duke@435 | 992 | assert(src->is_single_fpu(), "must be"); |
duke@435 | 993 | assert(src->fpu_regnr() == 0, "argument must be on TOS"); |
duke@435 | 994 | if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); |
duke@435 | 995 | else __ fst_s (as_Address(to_addr)); |
duke@435 | 996 | } |
duke@435 | 997 | break; |
duke@435 | 998 | } |
duke@435 | 999 | |
duke@435 | 1000 | case T_DOUBLE: { |
duke@435 | 1001 | if (src->is_double_xmm()) { |
duke@435 | 1002 | __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); |
duke@435 | 1003 | } else { |
duke@435 | 1004 | assert(src->is_double_fpu(), "must be"); |
duke@435 | 1005 | assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); |
duke@435 | 1006 | if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); |
duke@435 | 1007 | else __ fst_d (as_Address(to_addr)); |
duke@435 | 1008 | } |
duke@435 | 1009 | break; |
duke@435 | 1010 | } |
duke@435 | 1011 | |
duke@435 | 1012 | case T_ARRAY: // fall through |
duke@435 | 1013 | case T_OBJECT: // fall through |
iveresov@2344 | 1014 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 1015 | __ movl(as_Address(to_addr), compressed_src); |
iveresov@2344 | 1016 | } else { |
iveresov@2344 | 1017 | __ movptr(as_Address(to_addr), src->as_register()); |
iveresov@2344 | 1018 | } |
iveresov@2344 | 1019 | break; |
iveresov@2344 | 1020 | case T_ADDRESS: |
never@739 | 1021 | __ movptr(as_Address(to_addr), src->as_register()); |
never@739 | 1022 | break; |
duke@435 | 1023 | case T_INT: |
duke@435 | 1024 | __ movl(as_Address(to_addr), src->as_register()); |
duke@435 | 1025 | break; |
duke@435 | 1026 | |
duke@435 | 1027 | case T_LONG: { |
duke@435 | 1028 | Register from_lo = src->as_register_lo(); |
duke@435 | 1029 | Register from_hi = src->as_register_hi(); |
never@739 | 1030 | #ifdef _LP64 |
never@739 | 1031 | __ movptr(as_Address_lo(to_addr), from_lo); |
never@739 | 1032 | #else |
duke@435 | 1033 | Register base = to_addr->base()->as_register(); |
duke@435 | 1034 | Register index = noreg; |
duke@435 | 1035 | if (to_addr->index()->is_register()) { |
duke@435 | 1036 | index = to_addr->index()->as_register(); |
duke@435 | 1037 | } |
duke@435 | 1038 | if (base == from_lo || index == from_lo) { |
duke@435 | 1039 | assert(base != from_hi, "can't be"); |
duke@435 | 1040 | assert(index == noreg || (index != base && index != from_hi), "can't handle this"); |
duke@435 | 1041 | __ movl(as_Address_hi(to_addr), from_hi); |
duke@435 | 1042 | if (patch != NULL) { |
duke@435 | 1043 | patching_epilog(patch, lir_patch_high, base, info); |
duke@435 | 1044 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1045 | patch_code = lir_patch_low; |
duke@435 | 1046 | } |
duke@435 | 1047 | __ movl(as_Address_lo(to_addr), from_lo); |
duke@435 | 1048 | } else { |
duke@435 | 1049 | assert(index == noreg || (index != base && index != from_lo), "can't handle this"); |
duke@435 | 1050 | __ movl(as_Address_lo(to_addr), from_lo); |
duke@435 | 1051 | if (patch != NULL) { |
duke@435 | 1052 | patching_epilog(patch, lir_patch_low, base, info); |
duke@435 | 1053 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1054 | patch_code = lir_patch_high; |
duke@435 | 1055 | } |
duke@435 | 1056 | __ movl(as_Address_hi(to_addr), from_hi); |
duke@435 | 1057 | } |
never@739 | 1058 | #endif // _LP64 |
duke@435 | 1059 | break; |
duke@435 | 1060 | } |
duke@435 | 1061 | |
duke@435 | 1062 | case T_BYTE: // fall through |
duke@435 | 1063 | case T_BOOLEAN: { |
duke@435 | 1064 | Register src_reg = src->as_register(); |
duke@435 | 1065 | Address dst_addr = as_Address(to_addr); |
duke@435 | 1066 | assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1067 | __ movb(dst_addr, src_reg); |
duke@435 | 1068 | break; |
duke@435 | 1069 | } |
duke@435 | 1070 | |
duke@435 | 1071 | case T_CHAR: // fall through |
duke@435 | 1072 | case T_SHORT: |
duke@435 | 1073 | __ movw(as_Address(to_addr), src->as_register()); |
duke@435 | 1074 | break; |
duke@435 | 1075 | |
duke@435 | 1076 | default: |
duke@435 | 1077 | ShouldNotReachHere(); |
duke@435 | 1078 | } |
iveresov@2344 | 1079 | if (info != NULL) { |
iveresov@2344 | 1080 | add_debug_info_for_null_check(null_check_here, info); |
iveresov@2344 | 1081 | } |
duke@435 | 1082 | |
duke@435 | 1083 | if (patch_code != lir_patch_none) { |
duke@435 | 1084 | patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); |
duke@435 | 1085 | } |
duke@435 | 1086 | } |
duke@435 | 1087 | |
duke@435 | 1088 | |
duke@435 | 1089 | void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { |
duke@435 | 1090 | assert(src->is_stack(), "should not call otherwise"); |
duke@435 | 1091 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 1092 | |
duke@435 | 1093 | if (dest->is_single_cpu()) { |
duke@435 | 1094 | if (type == T_ARRAY || type == T_OBJECT) { |
never@739 | 1095 | __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
duke@435 | 1096 | __ verify_oop(dest->as_register()); |
never@739 | 1097 | } else { |
never@739 | 1098 | __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
duke@435 | 1099 | } |
duke@435 | 1100 | |
duke@435 | 1101 | } else if (dest->is_double_cpu()) { |
duke@435 | 1102 | Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); |
duke@435 | 1103 | Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); |
never@739 | 1104 | __ movptr(dest->as_register_lo(), src_addr_LO); |
never@739 | 1105 | NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); |
duke@435 | 1106 | |
duke@435 | 1107 | } else if (dest->is_single_xmm()) { |
duke@435 | 1108 | Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1109 | __ movflt(dest->as_xmm_float_reg(), src_addr); |
duke@435 | 1110 | |
duke@435 | 1111 | } else if (dest->is_double_xmm()) { |
duke@435 | 1112 | Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); |
duke@435 | 1113 | __ movdbl(dest->as_xmm_double_reg(), src_addr); |
duke@435 | 1114 | |
duke@435 | 1115 | } else if (dest->is_single_fpu()) { |
duke@435 | 1116 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 1117 | Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1118 | __ fld_s(src_addr); |
duke@435 | 1119 | |
duke@435 | 1120 | } else if (dest->is_double_fpu()) { |
duke@435 | 1121 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 1122 | Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); |
duke@435 | 1123 | __ fld_d(src_addr); |
duke@435 | 1124 | |
duke@435 | 1125 | } else { |
duke@435 | 1126 | ShouldNotReachHere(); |
duke@435 | 1127 | } |
duke@435 | 1128 | } |
duke@435 | 1129 | |
duke@435 | 1130 | |
duke@435 | 1131 | void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { |
duke@435 | 1132 | if (src->is_single_stack()) { |
never@739 | 1133 | if (type == T_OBJECT || type == T_ARRAY) { |
never@739 | 1134 | __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); |
never@739 | 1135 | __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); |
never@739 | 1136 | } else { |
roland@1495 | 1137 | #ifndef _LP64 |
never@739 | 1138 | __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
never@739 | 1139 | __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); |
roland@1495 | 1140 | #else |
roland@1495 | 1141 | //no pushl on 64bits |
roland@1495 | 1142 | __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); |
roland@1495 | 1143 | __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); |
roland@1495 | 1144 | #endif |
never@739 | 1145 | } |
duke@435 | 1146 | |
duke@435 | 1147 | } else if (src->is_double_stack()) { |
never@739 | 1148 | #ifdef _LP64 |
never@739 | 1149 | __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); |
never@739 | 1150 | __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); |
never@739 | 1151 | #else |
duke@435 | 1152 | __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
never@739 | 1153 | // push and pop the part at src + wordSize, adding wordSize for the previous push |
never@756 | 1154 | __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
never@756 | 1155 | __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
duke@435 | 1156 | __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
never@739 | 1157 | #endif // _LP64 |
duke@435 | 1158 | |
duke@435 | 1159 | } else { |
duke@435 | 1160 | ShouldNotReachHere(); |
duke@435 | 1161 | } |
duke@435 | 1162 | } |
duke@435 | 1163 | |
duke@435 | 1164 | |
iveresov@2344 | 1165 | void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { |
duke@435 | 1166 | assert(src->is_address(), "should not call otherwise"); |
duke@435 | 1167 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 1168 | |
duke@435 | 1169 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1170 | Address from_addr = as_Address(addr); |
duke@435 | 1171 | |
duke@435 | 1172 | switch (type) { |
duke@435 | 1173 | case T_BOOLEAN: // fall through |
duke@435 | 1174 | case T_BYTE: // fall through |
duke@435 | 1175 | case T_CHAR: // fall through |
duke@435 | 1176 | case T_SHORT: |
duke@435 | 1177 | if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { |
duke@435 | 1178 | // on pre P6 processors we may get partial register stalls |
duke@435 | 1179 | // so blow away the value of to_rinfo before loading a |
duke@435 | 1180 | // partial word into it. Do it here so that it precedes |
duke@435 | 1181 | // the potential patch point below. |
never@739 | 1182 | __ xorptr(dest->as_register(), dest->as_register()); |
duke@435 | 1183 | } |
duke@435 | 1184 | break; |
duke@435 | 1185 | } |
duke@435 | 1186 | |
duke@435 | 1187 | PatchingStub* patch = NULL; |
duke@435 | 1188 | if (patch_code != lir_patch_none) { |
duke@435 | 1189 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
never@739 | 1190 | assert(from_addr.disp() != 0, "must have"); |
duke@435 | 1191 | } |
duke@435 | 1192 | if (info != NULL) { |
duke@435 | 1193 | add_debug_info_for_null_check_here(info); |
duke@435 | 1194 | } |
duke@435 | 1195 | |
duke@435 | 1196 | switch (type) { |
duke@435 | 1197 | case T_FLOAT: { |
duke@435 | 1198 | if (dest->is_single_xmm()) { |
duke@435 | 1199 | __ movflt(dest->as_xmm_float_reg(), from_addr); |
duke@435 | 1200 | } else { |
duke@435 | 1201 | assert(dest->is_single_fpu(), "must be"); |
duke@435 | 1202 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 1203 | __ fld_s(from_addr); |
duke@435 | 1204 | } |
duke@435 | 1205 | break; |
duke@435 | 1206 | } |
duke@435 | 1207 | |
duke@435 | 1208 | case T_DOUBLE: { |
duke@435 | 1209 | if (dest->is_double_xmm()) { |
duke@435 | 1210 | __ movdbl(dest->as_xmm_double_reg(), from_addr); |
duke@435 | 1211 | } else { |
duke@435 | 1212 | assert(dest->is_double_fpu(), "must be"); |
duke@435 | 1213 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 1214 | __ fld_d(from_addr); |
duke@435 | 1215 | } |
duke@435 | 1216 | break; |
duke@435 | 1217 | } |
duke@435 | 1218 | |
duke@435 | 1219 | case T_OBJECT: // fall through |
duke@435 | 1220 | case T_ARRAY: // fall through |
iveresov@2344 | 1221 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 1222 | __ movl(dest->as_register(), from_addr); |
iveresov@2344 | 1223 | } else { |
iveresov@2344 | 1224 | __ movptr(dest->as_register(), from_addr); |
iveresov@2344 | 1225 | } |
iveresov@2344 | 1226 | break; |
iveresov@2344 | 1227 | |
iveresov@2344 | 1228 | case T_ADDRESS: |
never@739 | 1229 | __ movptr(dest->as_register(), from_addr); |
never@739 | 1230 | break; |
duke@435 | 1231 | case T_INT: |
iveresov@1833 | 1232 | __ movl(dest->as_register(), from_addr); |
duke@435 | 1233 | break; |
duke@435 | 1234 | |
duke@435 | 1235 | case T_LONG: { |
duke@435 | 1236 | Register to_lo = dest->as_register_lo(); |
duke@435 | 1237 | Register to_hi = dest->as_register_hi(); |
never@739 | 1238 | #ifdef _LP64 |
never@739 | 1239 | __ movptr(to_lo, as_Address_lo(addr)); |
never@739 | 1240 | #else |
duke@435 | 1241 | Register base = addr->base()->as_register(); |
duke@435 | 1242 | Register index = noreg; |
duke@435 | 1243 | if (addr->index()->is_register()) { |
duke@435 | 1244 | index = addr->index()->as_register(); |
duke@435 | 1245 | } |
duke@435 | 1246 | if ((base == to_lo && index == to_hi) || |
duke@435 | 1247 | (base == to_hi && index == to_lo)) { |
duke@435 | 1248 | // addresses with 2 registers are only formed as a result of |
duke@435 | 1249 | // array access so this code will never have to deal with |
duke@435 | 1250 | // patches or null checks. |
duke@435 | 1251 | assert(info == NULL && patch == NULL, "must be"); |
never@739 | 1252 | __ lea(to_hi, as_Address(addr)); |
duke@435 | 1253 | __ movl(to_lo, Address(to_hi, 0)); |
duke@435 | 1254 | __ movl(to_hi, Address(to_hi, BytesPerWord)); |
duke@435 | 1255 | } else if (base == to_lo || index == to_lo) { |
duke@435 | 1256 | assert(base != to_hi, "can't be"); |
duke@435 | 1257 | assert(index == noreg || (index != base && index != to_hi), "can't handle this"); |
duke@435 | 1258 | __ movl(to_hi, as_Address_hi(addr)); |
duke@435 | 1259 | if (patch != NULL) { |
duke@435 | 1260 | patching_epilog(patch, lir_patch_high, base, info); |
duke@435 | 1261 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1262 | patch_code = lir_patch_low; |
duke@435 | 1263 | } |
duke@435 | 1264 | __ movl(to_lo, as_Address_lo(addr)); |
duke@435 | 1265 | } else { |
duke@435 | 1266 | assert(index == noreg || (index != base && index != to_lo), "can't handle this"); |
duke@435 | 1267 | __ movl(to_lo, as_Address_lo(addr)); |
duke@435 | 1268 | if (patch != NULL) { |
duke@435 | 1269 | patching_epilog(patch, lir_patch_low, base, info); |
duke@435 | 1270 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1271 | patch_code = lir_patch_high; |
duke@435 | 1272 | } |
duke@435 | 1273 | __ movl(to_hi, as_Address_hi(addr)); |
duke@435 | 1274 | } |
never@739 | 1275 | #endif // _LP64 |
duke@435 | 1276 | break; |
duke@435 | 1277 | } |
duke@435 | 1278 | |
duke@435 | 1279 | case T_BOOLEAN: // fall through |
duke@435 | 1280 | case T_BYTE: { |
duke@435 | 1281 | Register dest_reg = dest->as_register(); |
duke@435 | 1282 | assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1283 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1284 | __ movsbl(dest_reg, from_addr); |
duke@435 | 1285 | } else { |
duke@435 | 1286 | __ movb(dest_reg, from_addr); |
duke@435 | 1287 | __ shll(dest_reg, 24); |
duke@435 | 1288 | __ sarl(dest_reg, 24); |
duke@435 | 1289 | } |
duke@435 | 1290 | break; |
duke@435 | 1291 | } |
duke@435 | 1292 | |
duke@435 | 1293 | case T_CHAR: { |
duke@435 | 1294 | Register dest_reg = dest->as_register(); |
duke@435 | 1295 | assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1296 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1297 | __ movzwl(dest_reg, from_addr); |
duke@435 | 1298 | } else { |
duke@435 | 1299 | __ movw(dest_reg, from_addr); |
duke@435 | 1300 | } |
duke@435 | 1301 | break; |
duke@435 | 1302 | } |
duke@435 | 1303 | |
duke@435 | 1304 | case T_SHORT: { |
duke@435 | 1305 | Register dest_reg = dest->as_register(); |
duke@435 | 1306 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1307 | __ movswl(dest_reg, from_addr); |
duke@435 | 1308 | } else { |
duke@435 | 1309 | __ movw(dest_reg, from_addr); |
duke@435 | 1310 | __ shll(dest_reg, 16); |
duke@435 | 1311 | __ sarl(dest_reg, 16); |
duke@435 | 1312 | } |
duke@435 | 1313 | break; |
duke@435 | 1314 | } |
duke@435 | 1315 | |
duke@435 | 1316 | default: |
duke@435 | 1317 | ShouldNotReachHere(); |
duke@435 | 1318 | } |
duke@435 | 1319 | |
duke@435 | 1320 | if (patch != NULL) { |
duke@435 | 1321 | patching_epilog(patch, patch_code, addr->base()->as_register(), info); |
duke@435 | 1322 | } |
duke@435 | 1323 | |
duke@435 | 1324 | if (type == T_ARRAY || type == T_OBJECT) { |
iveresov@2344 | 1325 | #ifdef _LP64 |
iveresov@2344 | 1326 | if (UseCompressedOops && !wide) { |
iveresov@2344 | 1327 | __ decode_heap_oop(dest->as_register()); |
iveresov@2344 | 1328 | } |
iveresov@2344 | 1329 | #endif |
duke@435 | 1330 | __ verify_oop(dest->as_register()); |
duke@435 | 1331 | } |
duke@435 | 1332 | } |
duke@435 | 1333 | |
duke@435 | 1334 | |
duke@435 | 1335 | void LIR_Assembler::prefetchr(LIR_Opr src) { |
duke@435 | 1336 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1337 | Address from_addr = as_Address(addr); |
duke@435 | 1338 | |
duke@435 | 1339 | if (VM_Version::supports_sse()) { |
duke@435 | 1340 | switch (ReadPrefetchInstr) { |
duke@435 | 1341 | case 0: |
duke@435 | 1342 | __ prefetchnta(from_addr); break; |
duke@435 | 1343 | case 1: |
duke@435 | 1344 | __ prefetcht0(from_addr); break; |
duke@435 | 1345 | case 2: |
duke@435 | 1346 | __ prefetcht2(from_addr); break; |
duke@435 | 1347 | default: |
duke@435 | 1348 | ShouldNotReachHere(); break; |
duke@435 | 1349 | } |
kvn@2761 | 1350 | } else if (VM_Version::supports_3dnow_prefetch()) { |
duke@435 | 1351 | __ prefetchr(from_addr); |
duke@435 | 1352 | } |
duke@435 | 1353 | } |
duke@435 | 1354 | |
duke@435 | 1355 | |
duke@435 | 1356 | void LIR_Assembler::prefetchw(LIR_Opr src) { |
duke@435 | 1357 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1358 | Address from_addr = as_Address(addr); |
duke@435 | 1359 | |
duke@435 | 1360 | if (VM_Version::supports_sse()) { |
duke@435 | 1361 | switch (AllocatePrefetchInstr) { |
duke@435 | 1362 | case 0: |
duke@435 | 1363 | __ prefetchnta(from_addr); break; |
duke@435 | 1364 | case 1: |
duke@435 | 1365 | __ prefetcht0(from_addr); break; |
duke@435 | 1366 | case 2: |
duke@435 | 1367 | __ prefetcht2(from_addr); break; |
duke@435 | 1368 | case 3: |
duke@435 | 1369 | __ prefetchw(from_addr); break; |
duke@435 | 1370 | default: |
duke@435 | 1371 | ShouldNotReachHere(); break; |
duke@435 | 1372 | } |
kvn@2761 | 1373 | } else if (VM_Version::supports_3dnow_prefetch()) { |
duke@435 | 1374 | __ prefetchw(from_addr); |
duke@435 | 1375 | } |
duke@435 | 1376 | } |
duke@435 | 1377 | |
duke@435 | 1378 | |
duke@435 | 1379 | NEEDS_CLEANUP; // This could be static? |
duke@435 | 1380 | Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { |
kvn@464 | 1381 | int elem_size = type2aelembytes(type); |
duke@435 | 1382 | switch (elem_size) { |
duke@435 | 1383 | case 1: return Address::times_1; |
duke@435 | 1384 | case 2: return Address::times_2; |
duke@435 | 1385 | case 4: return Address::times_4; |
duke@435 | 1386 | case 8: return Address::times_8; |
duke@435 | 1387 | } |
duke@435 | 1388 | ShouldNotReachHere(); |
duke@435 | 1389 | return Address::no_scale; |
duke@435 | 1390 | } |
duke@435 | 1391 | |
duke@435 | 1392 | |
duke@435 | 1393 | void LIR_Assembler::emit_op3(LIR_Op3* op) { |
duke@435 | 1394 | switch (op->code()) { |
duke@435 | 1395 | case lir_idiv: |
duke@435 | 1396 | case lir_irem: |
duke@435 | 1397 | arithmetic_idiv(op->code(), |
duke@435 | 1398 | op->in_opr1(), |
duke@435 | 1399 | op->in_opr2(), |
duke@435 | 1400 | op->in_opr3(), |
duke@435 | 1401 | op->result_opr(), |
duke@435 | 1402 | op->info()); |
duke@435 | 1403 | break; |
duke@435 | 1404 | default: ShouldNotReachHere(); break; |
duke@435 | 1405 | } |
duke@435 | 1406 | } |
duke@435 | 1407 | |
duke@435 | 1408 | void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { |
duke@435 | 1409 | #ifdef ASSERT |
duke@435 | 1410 | assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); |
duke@435 | 1411 | if (op->block() != NULL) _branch_target_blocks.append(op->block()); |
duke@435 | 1412 | if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); |
duke@435 | 1413 | #endif |
duke@435 | 1414 | |
duke@435 | 1415 | if (op->cond() == lir_cond_always) { |
duke@435 | 1416 | if (op->info() != NULL) add_debug_info_for_branch(op->info()); |
duke@435 | 1417 | __ jmp (*(op->label())); |
duke@435 | 1418 | } else { |
duke@435 | 1419 | Assembler::Condition acond = Assembler::zero; |
duke@435 | 1420 | if (op->code() == lir_cond_float_branch) { |
duke@435 | 1421 | assert(op->ublock() != NULL, "must have unordered successor"); |
duke@435 | 1422 | __ jcc(Assembler::parity, *(op->ublock()->label())); |
duke@435 | 1423 | switch(op->cond()) { |
duke@435 | 1424 | case lir_cond_equal: acond = Assembler::equal; break; |
duke@435 | 1425 | case lir_cond_notEqual: acond = Assembler::notEqual; break; |
duke@435 | 1426 | case lir_cond_less: acond = Assembler::below; break; |
duke@435 | 1427 | case lir_cond_lessEqual: acond = Assembler::belowEqual; break; |
duke@435 | 1428 | case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; |
duke@435 | 1429 | case lir_cond_greater: acond = Assembler::above; break; |
duke@435 | 1430 | default: ShouldNotReachHere(); |
duke@435 | 1431 | } |
duke@435 | 1432 | } else { |
duke@435 | 1433 | switch (op->cond()) { |
duke@435 | 1434 | case lir_cond_equal: acond = Assembler::equal; break; |
duke@435 | 1435 | case lir_cond_notEqual: acond = Assembler::notEqual; break; |
duke@435 | 1436 | case lir_cond_less: acond = Assembler::less; break; |
duke@435 | 1437 | case lir_cond_lessEqual: acond = Assembler::lessEqual; break; |
duke@435 | 1438 | case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; |
duke@435 | 1439 | case lir_cond_greater: acond = Assembler::greater; break; |
duke@435 | 1440 | case lir_cond_belowEqual: acond = Assembler::belowEqual; break; |
duke@435 | 1441 | case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; |
duke@435 | 1442 | default: ShouldNotReachHere(); |
duke@435 | 1443 | } |
duke@435 | 1444 | } |
duke@435 | 1445 | __ jcc(acond,*(op->label())); |
duke@435 | 1446 | } |
duke@435 | 1447 | } |
duke@435 | 1448 | |
duke@435 | 1449 | void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { |
duke@435 | 1450 | LIR_Opr src = op->in_opr(); |
duke@435 | 1451 | LIR_Opr dest = op->result_opr(); |
duke@435 | 1452 | |
duke@435 | 1453 | switch (op->bytecode()) { |
duke@435 | 1454 | case Bytecodes::_i2l: |
never@739 | 1455 | #ifdef _LP64 |
never@739 | 1456 | __ movl2ptr(dest->as_register_lo(), src->as_register()); |
never@739 | 1457 | #else |
duke@435 | 1458 | move_regs(src->as_register(), dest->as_register_lo()); |
duke@435 | 1459 | move_regs(src->as_register(), dest->as_register_hi()); |
duke@435 | 1460 | __ sarl(dest->as_register_hi(), 31); |
never@739 | 1461 | #endif // LP64 |
duke@435 | 1462 | break; |
duke@435 | 1463 | |
duke@435 | 1464 | case Bytecodes::_l2i: |
duke@435 | 1465 | move_regs(src->as_register_lo(), dest->as_register()); |
duke@435 | 1466 | break; |
duke@435 | 1467 | |
duke@435 | 1468 | case Bytecodes::_i2b: |
duke@435 | 1469 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1470 | __ sign_extend_byte(dest->as_register()); |
duke@435 | 1471 | break; |
duke@435 | 1472 | |
duke@435 | 1473 | case Bytecodes::_i2c: |
duke@435 | 1474 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1475 | __ andl(dest->as_register(), 0xFFFF); |
duke@435 | 1476 | break; |
duke@435 | 1477 | |
duke@435 | 1478 | case Bytecodes::_i2s: |
duke@435 | 1479 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1480 | __ sign_extend_short(dest->as_register()); |
duke@435 | 1481 | break; |
duke@435 | 1482 | |
duke@435 | 1483 | |
duke@435 | 1484 | case Bytecodes::_f2d: |
duke@435 | 1485 | case Bytecodes::_d2f: |
duke@435 | 1486 | if (dest->is_single_xmm()) { |
duke@435 | 1487 | __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); |
duke@435 | 1488 | } else if (dest->is_double_xmm()) { |
duke@435 | 1489 | __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); |
duke@435 | 1490 | } else { |
duke@435 | 1491 | assert(src->fpu() == dest->fpu(), "register must be equal"); |
duke@435 | 1492 | // do nothing (float result is rounded later through spilling) |
duke@435 | 1493 | } |
duke@435 | 1494 | break; |
duke@435 | 1495 | |
duke@435 | 1496 | case Bytecodes::_i2f: |
duke@435 | 1497 | case Bytecodes::_i2d: |
duke@435 | 1498 | if (dest->is_single_xmm()) { |
never@739 | 1499 | __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
duke@435 | 1500 | } else if (dest->is_double_xmm()) { |
never@739 | 1501 | __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
duke@435 | 1502 | } else { |
duke@435 | 1503 | assert(dest->fpu() == 0, "result must be on TOS"); |
duke@435 | 1504 | __ movl(Address(rsp, 0), src->as_register()); |
duke@435 | 1505 | __ fild_s(Address(rsp, 0)); |
duke@435 | 1506 | } |
duke@435 | 1507 | break; |
duke@435 | 1508 | |
duke@435 | 1509 | case Bytecodes::_f2i: |
duke@435 | 1510 | case Bytecodes::_d2i: |
duke@435 | 1511 | if (src->is_single_xmm()) { |
never@739 | 1512 | __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
duke@435 | 1513 | } else if (src->is_double_xmm()) { |
never@739 | 1514 | __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
duke@435 | 1515 | } else { |
duke@435 | 1516 | assert(src->fpu() == 0, "input must be on TOS"); |
duke@435 | 1517 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); |
duke@435 | 1518 | __ fist_s(Address(rsp, 0)); |
duke@435 | 1519 | __ movl(dest->as_register(), Address(rsp, 0)); |
duke@435 | 1520 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
duke@435 | 1521 | } |
duke@435 | 1522 | |
duke@435 | 1523 | // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub |
duke@435 | 1524 | assert(op->stub() != NULL, "stub required"); |
duke@435 | 1525 | __ cmpl(dest->as_register(), 0x80000000); |
duke@435 | 1526 | __ jcc(Assembler::equal, *op->stub()->entry()); |
duke@435 | 1527 | __ bind(*op->stub()->continuation()); |
duke@435 | 1528 | break; |
duke@435 | 1529 | |
duke@435 | 1530 | case Bytecodes::_l2f: |
duke@435 | 1531 | case Bytecodes::_l2d: |
duke@435 | 1532 | assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); |
duke@435 | 1533 | assert(dest->fpu() == 0, "result must be on TOS"); |
duke@435 | 1534 | |
never@739 | 1535 | __ movptr(Address(rsp, 0), src->as_register_lo()); |
never@739 | 1536 | NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); |
duke@435 | 1537 | __ fild_d(Address(rsp, 0)); |
duke@435 | 1538 | // float result is rounded later through spilling |
duke@435 | 1539 | break; |
duke@435 | 1540 | |
duke@435 | 1541 | case Bytecodes::_f2l: |
duke@435 | 1542 | case Bytecodes::_d2l: |
duke@435 | 1543 | assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); |
duke@435 | 1544 | assert(src->fpu() == 0, "input must be on TOS"); |
never@739 | 1545 | assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
duke@435 | 1546 | |
duke@435 | 1547 | // instruction sequence too long to inline it here |
duke@435 | 1548 | { |
duke@435 | 1549 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); |
duke@435 | 1550 | } |
duke@435 | 1551 | break; |
duke@435 | 1552 | |
duke@435 | 1553 | default: ShouldNotReachHere(); |
duke@435 | 1554 | } |
duke@435 | 1555 | } |
duke@435 | 1556 | |
duke@435 | 1557 | void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { |
duke@435 | 1558 | if (op->init_check()) { |
coleenp@3368 | 1559 | __ cmpb(Address(op->klass()->as_register(), |
stefank@3391 | 1560 | instanceKlass::init_state_offset()), |
duke@435 | 1561 | instanceKlass::fully_initialized); |
duke@435 | 1562 | add_debug_info_for_null_check_here(op->stub()->info()); |
duke@435 | 1563 | __ jcc(Assembler::notEqual, *op->stub()->entry()); |
duke@435 | 1564 | } |
duke@435 | 1565 | __ allocate_object(op->obj()->as_register(), |
duke@435 | 1566 | op->tmp1()->as_register(), |
duke@435 | 1567 | op->tmp2()->as_register(), |
duke@435 | 1568 | op->header_size(), |
duke@435 | 1569 | op->object_size(), |
duke@435 | 1570 | op->klass()->as_register(), |
duke@435 | 1571 | *op->stub()->entry()); |
duke@435 | 1572 | __ bind(*op->stub()->continuation()); |
duke@435 | 1573 | } |
duke@435 | 1574 | |
duke@435 | 1575 | void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { |
iveresov@2432 | 1576 | Register len = op->len()->as_register(); |
iveresov@2432 | 1577 | LP64_ONLY( __ movslq(len, len); ) |
iveresov@2432 | 1578 | |
duke@435 | 1579 | if (UseSlowPath || |
duke@435 | 1580 | (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || |
duke@435 | 1581 | (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { |
duke@435 | 1582 | __ jmp(*op->stub()->entry()); |
duke@435 | 1583 | } else { |
duke@435 | 1584 | Register tmp1 = op->tmp1()->as_register(); |
duke@435 | 1585 | Register tmp2 = op->tmp2()->as_register(); |
duke@435 | 1586 | Register tmp3 = op->tmp3()->as_register(); |
duke@435 | 1587 | if (len == tmp1) { |
duke@435 | 1588 | tmp1 = tmp3; |
duke@435 | 1589 | } else if (len == tmp2) { |
duke@435 | 1590 | tmp2 = tmp3; |
duke@435 | 1591 | } else if (len == tmp3) { |
duke@435 | 1592 | // everything is ok |
duke@435 | 1593 | } else { |
never@739 | 1594 | __ mov(tmp3, len); |
duke@435 | 1595 | } |
duke@435 | 1596 | __ allocate_array(op->obj()->as_register(), |
duke@435 | 1597 | len, |
duke@435 | 1598 | tmp1, |
duke@435 | 1599 | tmp2, |
duke@435 | 1600 | arrayOopDesc::header_size(op->type()), |
duke@435 | 1601 | array_element_size(op->type()), |
duke@435 | 1602 | op->klass()->as_register(), |
duke@435 | 1603 | *op->stub()->entry()); |
duke@435 | 1604 | } |
duke@435 | 1605 | __ bind(*op->stub()->continuation()); |
duke@435 | 1606 | } |
duke@435 | 1607 | |
iveresov@2138 | 1608 | void LIR_Assembler::type_profile_helper(Register mdo, |
iveresov@2138 | 1609 | ciMethodData *md, ciProfileData *data, |
iveresov@2138 | 1610 | Register recv, Label* update_done) { |
iveresov@2163 | 1611 | for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
iveresov@2138 | 1612 | Label next_test; |
iveresov@2138 | 1613 | // See if the receiver is receiver[n]. |
iveresov@2138 | 1614 | __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); |
iveresov@2138 | 1615 | __ jccb(Assembler::notEqual, next_test); |
iveresov@2138 | 1616 | Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); |
iveresov@2138 | 1617 | __ addptr(data_addr, DataLayout::counter_increment); |
iveresov@2146 | 1618 | __ jmp(*update_done); |
iveresov@2138 | 1619 | __ bind(next_test); |
iveresov@2138 | 1620 | } |
iveresov@2138 | 1621 | |
iveresov@2138 | 1622 | // Didn't find receiver; find next empty slot and fill it in |
iveresov@2163 | 1623 | for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
iveresov@2138 | 1624 | Label next_test; |
iveresov@2138 | 1625 | Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); |
iveresov@2138 | 1626 | __ cmpptr(recv_addr, (intptr_t)NULL_WORD); |
iveresov@2138 | 1627 | __ jccb(Assembler::notEqual, next_test); |
iveresov@2138 | 1628 | __ movptr(recv_addr, recv); |
iveresov@2138 | 1629 | __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); |
iveresov@2146 | 1630 | __ jmp(*update_done); |
iveresov@2138 | 1631 | __ bind(next_test); |
iveresov@2138 | 1632 | } |
iveresov@2138 | 1633 | } |
iveresov@2138 | 1634 | |
iveresov@2146 | 1635 | void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
iveresov@2138 | 1636 | // we always need a stub for the failure case. |
iveresov@2138 | 1637 | CodeStub* stub = op->stub(); |
iveresov@2138 | 1638 | Register obj = op->object()->as_register(); |
iveresov@2138 | 1639 | Register k_RInfo = op->tmp1()->as_register(); |
iveresov@2138 | 1640 | Register klass_RInfo = op->tmp2()->as_register(); |
iveresov@2138 | 1641 | Register dst = op->result_opr()->as_register(); |
iveresov@2138 | 1642 | ciKlass* k = op->klass(); |
iveresov@2138 | 1643 | Register Rtmp1 = noreg; |
iveresov@2138 | 1644 | |
iveresov@2138 | 1645 | // check if it needs to be profiled |
iveresov@2138 | 1646 | ciMethodData* md; |
iveresov@2138 | 1647 | ciProfileData* data; |
iveresov@2138 | 1648 | |
iveresov@2138 | 1649 | if (op->should_profile()) { |
iveresov@2138 | 1650 | ciMethod* method = op->profiled_method(); |
iveresov@2138 | 1651 | assert(method != NULL, "Should have method"); |
iveresov@2138 | 1652 | int bci = op->profiled_bci(); |
iveresov@2349 | 1653 | md = method->method_data_or_null(); |
iveresov@2349 | 1654 | assert(md != NULL, "Sanity"); |
iveresov@2138 | 1655 | data = md->bci_to_data(bci); |
iveresov@2146 | 1656 | assert(data != NULL, "need data for type check"); |
iveresov@2146 | 1657 | assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
iveresov@2138 | 1658 | } |
iveresov@2146 | 1659 | Label profile_cast_success, profile_cast_failure; |
iveresov@2146 | 1660 | Label *success_target = op->should_profile() ? &profile_cast_success : success; |
iveresov@2146 | 1661 | Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
iveresov@2138 | 1662 | |
iveresov@2138 | 1663 | if (obj == k_RInfo) { |
iveresov@2138 | 1664 | k_RInfo = dst; |
iveresov@2138 | 1665 | } else if (obj == klass_RInfo) { |
iveresov@2138 | 1666 | klass_RInfo = dst; |
iveresov@2138 | 1667 | } |
iveresov@2344 | 1668 | if (k->is_loaded() && !UseCompressedOops) { |
iveresov@2138 | 1669 | select_different_registers(obj, dst, k_RInfo, klass_RInfo); |
iveresov@2138 | 1670 | } else { |
iveresov@2138 | 1671 | Rtmp1 = op->tmp3()->as_register(); |
iveresov@2138 | 1672 | select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); |
iveresov@2138 | 1673 | } |
iveresov@2138 | 1674 | |
iveresov@2138 | 1675 | assert_different_registers(obj, k_RInfo, klass_RInfo); |
iveresov@2138 | 1676 | if (!k->is_loaded()) { |
iveresov@2138 | 1677 | jobject2reg_with_patching(k_RInfo, op->info_for_patch()); |
iveresov@2138 | 1678 | } else { |
iveresov@2138 | 1679 | #ifdef _LP64 |
iveresov@2138 | 1680 | __ movoop(k_RInfo, k->constant_encoding()); |
iveresov@2138 | 1681 | #endif // _LP64 |
iveresov@2138 | 1682 | } |
iveresov@2138 | 1683 | assert(obj != k_RInfo, "must be different"); |
iveresov@2138 | 1684 | |
iveresov@2138 | 1685 | __ cmpptr(obj, (int32_t)NULL_WORD); |
iveresov@2138 | 1686 | if (op->should_profile()) { |
iveresov@2146 | 1687 | Label not_null; |
iveresov@2146 | 1688 | __ jccb(Assembler::notEqual, not_null); |
iveresov@2146 | 1689 | // Object is null; update MDO and exit |
iveresov@2138 | 1690 | Register mdo = klass_RInfo; |
iveresov@2138 | 1691 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2138 | 1692 | Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
iveresov@2138 | 1693 | int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
iveresov@2138 | 1694 | __ orl(data_addr, header_bits); |
iveresov@2146 | 1695 | __ jmp(*obj_is_null); |
iveresov@2146 | 1696 | __ bind(not_null); |
iveresov@2138 | 1697 | } else { |
iveresov@2146 | 1698 | __ jcc(Assembler::equal, *obj_is_null); |
iveresov@2138 | 1699 | } |
iveresov@2138 | 1700 | __ verify_oop(obj); |
iveresov@2138 | 1701 | |
iveresov@2138 | 1702 | if (op->fast_check()) { |
iveresov@2146 | 1703 | // get object class |
iveresov@2138 | 1704 | // not a safepoint as obj null check happens earlier |
iveresov@2138 | 1705 | #ifdef _LP64 |
iveresov@2344 | 1706 | if (UseCompressedOops) { |
iveresov@2344 | 1707 | __ load_klass(Rtmp1, obj); |
iveresov@2344 | 1708 | __ cmpptr(k_RInfo, Rtmp1); |
iveresov@2138 | 1709 | } else { |
iveresov@2138 | 1710 | __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
iveresov@2138 | 1711 | } |
iveresov@2344 | 1712 | #else |
iveresov@2344 | 1713 | if (k->is_loaded()) { |
iveresov@2344 | 1714 | __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); |
iveresov@2344 | 1715 | } else { |
iveresov@2344 | 1716 | __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
iveresov@2344 | 1717 | } |
iveresov@2344 | 1718 | #endif |
iveresov@2138 | 1719 | __ jcc(Assembler::notEqual, *failure_target); |
iveresov@2146 | 1720 | // successful cast, fall through to profile or jump |
iveresov@2138 | 1721 | } else { |
iveresov@2138 | 1722 | // get object class |
iveresov@2138 | 1723 | // not a safepoint as obj null check happens earlier |
iveresov@2344 | 1724 | __ load_klass(klass_RInfo, obj); |
iveresov@2138 | 1725 | if (k->is_loaded()) { |
iveresov@2138 | 1726 | // See if we get an immediate positive hit |
iveresov@2138 | 1727 | #ifdef _LP64 |
iveresov@2138 | 1728 | __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); |
iveresov@2138 | 1729 | #else |
iveresov@2138 | 1730 | __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); |
iveresov@2138 | 1731 | #endif // _LP64 |
stefank@3391 | 1732 | if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { |
iveresov@2138 | 1733 | __ jcc(Assembler::notEqual, *failure_target); |
iveresov@2146 | 1734 | // successful cast, fall through to profile or jump |
iveresov@2138 | 1735 | } else { |
iveresov@2138 | 1736 | // See if we get an immediate positive hit |
iveresov@2146 | 1737 | __ jcc(Assembler::equal, *success_target); |
iveresov@2138 | 1738 | // check for self |
iveresov@2138 | 1739 | #ifdef _LP64 |
iveresov@2138 | 1740 | __ cmpptr(klass_RInfo, k_RInfo); |
iveresov@2138 | 1741 | #else |
iveresov@2138 | 1742 | __ cmpoop(klass_RInfo, k->constant_encoding()); |
iveresov@2138 | 1743 | #endif // _LP64 |
iveresov@2146 | 1744 | __ jcc(Assembler::equal, *success_target); |
iveresov@2138 | 1745 | |
iveresov@2138 | 1746 | __ push(klass_RInfo); |
iveresov@2138 | 1747 | #ifdef _LP64 |
iveresov@2138 | 1748 | __ push(k_RInfo); |
iveresov@2138 | 1749 | #else |
iveresov@2138 | 1750 | __ pushoop(k->constant_encoding()); |
iveresov@2138 | 1751 | #endif // _LP64 |
iveresov@2138 | 1752 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
iveresov@2138 | 1753 | __ pop(klass_RInfo); |
iveresov@2138 | 1754 | __ pop(klass_RInfo); |
iveresov@2138 | 1755 | // result is a boolean |
iveresov@2138 | 1756 | __ cmpl(klass_RInfo, 0); |
iveresov@2138 | 1757 | __ jcc(Assembler::equal, *failure_target); |
iveresov@2146 | 1758 | // successful cast, fall through to profile or jump |
iveresov@2138 | 1759 | } |
iveresov@2138 | 1760 | } else { |
iveresov@2138 | 1761 | // perform the fast part of the checking logic |
iveresov@2146 | 1762 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
iveresov@2138 | 1763 | // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
iveresov@2138 | 1764 | __ push(klass_RInfo); |
iveresov@2138 | 1765 | __ push(k_RInfo); |
iveresov@2138 | 1766 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
iveresov@2138 | 1767 | __ pop(klass_RInfo); |
iveresov@2138 | 1768 | __ pop(k_RInfo); |
iveresov@2138 | 1769 | // result is a boolean |
iveresov@2138 | 1770 | __ cmpl(k_RInfo, 0); |
iveresov@2138 | 1771 | __ jcc(Assembler::equal, *failure_target); |
iveresov@2146 | 1772 | // successful cast, fall through to profile or jump |
iveresov@2138 | 1773 | } |
iveresov@2138 | 1774 | } |
iveresov@2138 | 1775 | if (op->should_profile()) { |
iveresov@2138 | 1776 | Register mdo = klass_RInfo, recv = k_RInfo; |
iveresov@2146 | 1777 | __ bind(profile_cast_success); |
iveresov@2138 | 1778 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2344 | 1779 | __ load_klass(recv, obj); |
iveresov@2138 | 1780 | Label update_done; |
iveresov@2146 | 1781 | type_profile_helper(mdo, md, data, recv, success); |
iveresov@2146 | 1782 | __ jmp(*success); |
iveresov@2138 | 1783 | |
iveresov@2138 | 1784 | __ bind(profile_cast_failure); |
iveresov@2138 | 1785 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2138 | 1786 | Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
iveresov@2138 | 1787 | __ subptr(counter_addr, DataLayout::counter_increment); |
iveresov@2146 | 1788 | __ jmp(*failure); |
iveresov@2138 | 1789 | } |
iveresov@2146 | 1790 | __ jmp(*success); |
iveresov@2138 | 1791 | } |
duke@435 | 1792 | |
iveresov@2146 | 1793 | |
duke@435 | 1794 | void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
duke@435 | 1795 | LIR_Code code = op->code(); |
duke@435 | 1796 | if (code == lir_store_check) { |
duke@435 | 1797 | Register value = op->object()->as_register(); |
duke@435 | 1798 | Register array = op->array()->as_register(); |
duke@435 | 1799 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 1800 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 1801 | Register Rtmp1 = op->tmp3()->as_register(); |
duke@435 | 1802 | |
duke@435 | 1803 | CodeStub* stub = op->stub(); |
iveresov@2146 | 1804 | |
iveresov@2146 | 1805 | // check if it needs to be profiled |
iveresov@2146 | 1806 | ciMethodData* md; |
iveresov@2146 | 1807 | ciProfileData* data; |
iveresov@2146 | 1808 | |
iveresov@2146 | 1809 | if (op->should_profile()) { |
iveresov@2146 | 1810 | ciMethod* method = op->profiled_method(); |
iveresov@2146 | 1811 | assert(method != NULL, "Should have method"); |
iveresov@2146 | 1812 | int bci = op->profiled_bci(); |
iveresov@2349 | 1813 | md = method->method_data_or_null(); |
iveresov@2349 | 1814 | assert(md != NULL, "Sanity"); |
iveresov@2146 | 1815 | data = md->bci_to_data(bci); |
iveresov@2146 | 1816 | assert(data != NULL, "need data for type check"); |
iveresov@2146 | 1817 | assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
iveresov@2146 | 1818 | } |
iveresov@2146 | 1819 | Label profile_cast_success, profile_cast_failure, done; |
iveresov@2146 | 1820 | Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
iveresov@2146 | 1821 | Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
iveresov@2146 | 1822 | |
never@739 | 1823 | __ cmpptr(value, (int32_t)NULL_WORD); |
iveresov@2146 | 1824 | if (op->should_profile()) { |
iveresov@2146 | 1825 | Label not_null; |
iveresov@2146 | 1826 | __ jccb(Assembler::notEqual, not_null); |
iveresov@2146 | 1827 | // Object is null; update MDO and exit |
iveresov@2146 | 1828 | Register mdo = klass_RInfo; |
iveresov@2146 | 1829 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2146 | 1830 | Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
iveresov@2146 | 1831 | int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
iveresov@2146 | 1832 | __ orl(data_addr, header_bits); |
iveresov@2146 | 1833 | __ jmp(done); |
iveresov@2146 | 1834 | __ bind(not_null); |
iveresov@2146 | 1835 | } else { |
iveresov@2146 | 1836 | __ jcc(Assembler::equal, done); |
iveresov@2146 | 1837 | } |
iveresov@2146 | 1838 | |
duke@435 | 1839 | add_debug_info_for_null_check_here(op->info_for_exception()); |
iveresov@2344 | 1840 | __ load_klass(k_RInfo, array); |
iveresov@2344 | 1841 | __ load_klass(klass_RInfo, value); |
iveresov@2344 | 1842 | |
iveresov@2344 | 1843 | // get instance klass (it's already uncompressed) |
stefank@3391 | 1844 | __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset())); |
jrose@1079 | 1845 | // perform the fast part of the checking logic |
iveresov@2146 | 1846 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
jrose@1079 | 1847 | // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
never@739 | 1848 | __ push(klass_RInfo); |
never@739 | 1849 | __ push(k_RInfo); |
duke@435 | 1850 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1851 | __ pop(klass_RInfo); |
never@739 | 1852 | __ pop(k_RInfo); |
never@739 | 1853 | // result is a boolean |
duke@435 | 1854 | __ cmpl(k_RInfo, 0); |
iveresov@2146 | 1855 | __ jcc(Assembler::equal, *failure_target); |
iveresov@2146 | 1856 | // fall through to the success case |
iveresov@2146 | 1857 | |
iveresov@2146 | 1858 | if (op->should_profile()) { |
iveresov@2146 | 1859 | Register mdo = klass_RInfo, recv = k_RInfo; |
iveresov@2146 | 1860 | __ bind(profile_cast_success); |
iveresov@2146 | 1861 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2344 | 1862 | __ load_klass(recv, value); |
iveresov@2146 | 1863 | Label update_done; |
iveresov@2146 | 1864 | type_profile_helper(mdo, md, data, recv, &done); |
iveresov@2146 | 1865 | __ jmpb(done); |
iveresov@2146 | 1866 | |
iveresov@2146 | 1867 | __ bind(profile_cast_failure); |
iveresov@2146 | 1868 | __ movoop(mdo, md->constant_encoding()); |
iveresov@2146 | 1869 | Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
iveresov@2146 | 1870 | __ subptr(counter_addr, DataLayout::counter_increment); |
iveresov@2146 | 1871 | __ jmp(*stub->entry()); |
iveresov@2146 | 1872 | } |
iveresov@2146 | 1873 | |
duke@435 | 1874 | __ bind(done); |
iveresov@2146 | 1875 | } else |
iveresov@2146 | 1876 | if (code == lir_checkcast) { |
iveresov@2146 | 1877 | Register obj = op->object()->as_register(); |
iveresov@2146 | 1878 | Register dst = op->result_opr()->as_register(); |
iveresov@2146 | 1879 | Label success; |
iveresov@2146 | 1880 | emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
iveresov@2146 | 1881 | __ bind(success); |
iveresov@2146 | 1882 | if (dst != obj) { |
iveresov@2146 | 1883 | __ mov(dst, obj); |
iveresov@2146 | 1884 | } |
iveresov@2146 | 1885 | } else |
iveresov@2146 | 1886 | if (code == lir_instanceof) { |
iveresov@2146 | 1887 | Register obj = op->object()->as_register(); |
iveresov@2146 | 1888 | Register dst = op->result_opr()->as_register(); |
iveresov@2146 | 1889 | Label success, failure, done; |
iveresov@2146 | 1890 | emit_typecheck_helper(op, &success, &failure, &failure); |
iveresov@2146 | 1891 | __ bind(failure); |
iveresov@2146 | 1892 | __ xorptr(dst, dst); |
iveresov@2146 | 1893 | __ jmpb(done); |
iveresov@2146 | 1894 | __ bind(success); |
iveresov@2146 | 1895 | __ movptr(dst, 1); |
iveresov@2146 | 1896 | __ bind(done); |
duke@435 | 1897 | } else { |
iveresov@2146 | 1898 | ShouldNotReachHere(); |
duke@435 | 1899 | } |
duke@435 | 1900 | |
duke@435 | 1901 | } |
duke@435 | 1902 | |
duke@435 | 1903 | |
duke@435 | 1904 | void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { |
never@739 | 1905 | if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
duke@435 | 1906 | assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
duke@435 | 1907 | assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); |
duke@435 | 1908 | assert(op->new_value()->as_register_lo() == rbx, "wrong register"); |
duke@435 | 1909 | assert(op->new_value()->as_register_hi() == rcx, "wrong register"); |
duke@435 | 1910 | Register addr = op->addr()->as_register(); |
duke@435 | 1911 | if (os::is_MP()) { |
duke@435 | 1912 | __ lock(); |
duke@435 | 1913 | } |
never@739 | 1914 | NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
never@739 | 1915 | |
never@739 | 1916 | } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { |
never@739 | 1917 | NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) |
never@739 | 1918 | Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); |
duke@435 | 1919 | Register newval = op->new_value()->as_register(); |
duke@435 | 1920 | Register cmpval = op->cmp_value()->as_register(); |
duke@435 | 1921 | assert(cmpval == rax, "wrong register"); |
duke@435 | 1922 | assert(newval != NULL, "new val must be register"); |
duke@435 | 1923 | assert(cmpval != newval, "cmp and new values must be in different registers"); |
duke@435 | 1924 | assert(cmpval != addr, "cmp and addr must be in different registers"); |
duke@435 | 1925 | assert(newval != addr, "new value and addr must be in different registers"); |
iveresov@2344 | 1926 | |
never@739 | 1927 | if ( op->code() == lir_cas_obj) { |
iveresov@2344 | 1928 | #ifdef _LP64 |
iveresov@2344 | 1929 | if (UseCompressedOops) { |
iveresov@2344 | 1930 | __ encode_heap_oop(cmpval); |
iveresov@2355 | 1931 | __ mov(rscratch1, newval); |
iveresov@2355 | 1932 | __ encode_heap_oop(rscratch1); |
iveresov@2344 | 1933 | if (os::is_MP()) { |
iveresov@2344 | 1934 | __ lock(); |
iveresov@2344 | 1935 | } |
iveresov@2355 | 1936 | // cmpval (rax) is implicitly used by this instruction |
iveresov@2355 | 1937 | __ cmpxchgl(rscratch1, Address(addr, 0)); |
iveresov@2344 | 1938 | } else |
iveresov@2344 | 1939 | #endif |
iveresov@2344 | 1940 | { |
iveresov@2344 | 1941 | if (os::is_MP()) { |
iveresov@2344 | 1942 | __ lock(); |
iveresov@2344 | 1943 | } |
iveresov@2344 | 1944 | __ cmpxchgptr(newval, Address(addr, 0)); |
iveresov@2344 | 1945 | } |
iveresov@2344 | 1946 | } else { |
iveresov@2344 | 1947 | assert(op->code() == lir_cas_int, "lir_cas_int expected"); |
iveresov@2344 | 1948 | if (os::is_MP()) { |
iveresov@2344 | 1949 | __ lock(); |
iveresov@2344 | 1950 | } |
never@739 | 1951 | __ cmpxchgl(newval, Address(addr, 0)); |
never@739 | 1952 | } |
never@739 | 1953 | #ifdef _LP64 |
never@739 | 1954 | } else if (op->code() == lir_cas_long) { |
never@739 | 1955 | Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); |
never@739 | 1956 | Register newval = op->new_value()->as_register_lo(); |
never@739 | 1957 | Register cmpval = op->cmp_value()->as_register_lo(); |
never@739 | 1958 | assert(cmpval == rax, "wrong register"); |
never@739 | 1959 | assert(newval != NULL, "new val must be register"); |
never@739 | 1960 | assert(cmpval != newval, "cmp and new values must be in different registers"); |
never@739 | 1961 | assert(cmpval != addr, "cmp and addr must be in different registers"); |
never@739 | 1962 | assert(newval != addr, "new value and addr must be in different registers"); |
never@739 | 1963 | if (os::is_MP()) { |
never@739 | 1964 | __ lock(); |
never@739 | 1965 | } |
never@739 | 1966 | __ cmpxchgq(newval, Address(addr, 0)); |
never@739 | 1967 | #endif // _LP64 |
duke@435 | 1968 | } else { |
duke@435 | 1969 | Unimplemented(); |
duke@435 | 1970 | } |
duke@435 | 1971 | } |
duke@435 | 1972 | |
iveresov@2412 | 1973 | void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { |
duke@435 | 1974 | Assembler::Condition acond, ncond; |
duke@435 | 1975 | switch (condition) { |
duke@435 | 1976 | case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; |
duke@435 | 1977 | case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; |
duke@435 | 1978 | case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; |
duke@435 | 1979 | case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; |
duke@435 | 1980 | case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; |
duke@435 | 1981 | case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; |
duke@435 | 1982 | case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; |
duke@435 | 1983 | case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; |
duke@435 | 1984 | default: ShouldNotReachHere(); |
duke@435 | 1985 | } |
duke@435 | 1986 | |
duke@435 | 1987 | if (opr1->is_cpu_register()) { |
duke@435 | 1988 | reg2reg(opr1, result); |
duke@435 | 1989 | } else if (opr1->is_stack()) { |
duke@435 | 1990 | stack2reg(opr1, result, result->type()); |
duke@435 | 1991 | } else if (opr1->is_constant()) { |
duke@435 | 1992 | const2reg(opr1, result, lir_patch_none, NULL); |
duke@435 | 1993 | } else { |
duke@435 | 1994 | ShouldNotReachHere(); |
duke@435 | 1995 | } |
duke@435 | 1996 | |
duke@435 | 1997 | if (VM_Version::supports_cmov() && !opr2->is_constant()) { |
duke@435 | 1998 | // optimized version that does not require a branch |
duke@435 | 1999 | if (opr2->is_single_cpu()) { |
duke@435 | 2000 | assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); |
never@739 | 2001 | __ cmov(ncond, result->as_register(), opr2->as_register()); |
duke@435 | 2002 | } else if (opr2->is_double_cpu()) { |
duke@435 | 2003 | assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); |
duke@435 | 2004 | assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); |
never@739 | 2005 | __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
never@739 | 2006 | NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) |
duke@435 | 2007 | } else if (opr2->is_single_stack()) { |
duke@435 | 2008 | __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); |
duke@435 | 2009 | } else if (opr2->is_double_stack()) { |
never@739 | 2010 | __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
never@739 | 2011 | NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) |
duke@435 | 2012 | } else { |
duke@435 | 2013 | ShouldNotReachHere(); |
duke@435 | 2014 | } |
duke@435 | 2015 | |
duke@435 | 2016 | } else { |
duke@435 | 2017 | Label skip; |
duke@435 | 2018 | __ jcc (acond, skip); |
duke@435 | 2019 | if (opr2->is_cpu_register()) { |
duke@435 | 2020 | reg2reg(opr2, result); |
duke@435 | 2021 | } else if (opr2->is_stack()) { |
duke@435 | 2022 | stack2reg(opr2, result, result->type()); |
duke@435 | 2023 | } else if (opr2->is_constant()) { |
duke@435 | 2024 | const2reg(opr2, result, lir_patch_none, NULL); |
duke@435 | 2025 | } else { |
duke@435 | 2026 | ShouldNotReachHere(); |
duke@435 | 2027 | } |
duke@435 | 2028 | __ bind(skip); |
duke@435 | 2029 | } |
duke@435 | 2030 | } |
duke@435 | 2031 | |
duke@435 | 2032 | |
duke@435 | 2033 | void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { |
duke@435 | 2034 | assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); |
duke@435 | 2035 | |
duke@435 | 2036 | if (left->is_single_cpu()) { |
duke@435 | 2037 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2038 | Register lreg = left->as_register(); |
duke@435 | 2039 | |
duke@435 | 2040 | if (right->is_single_cpu()) { |
duke@435 | 2041 | // cpu register - cpu register |
duke@435 | 2042 | Register rreg = right->as_register(); |
duke@435 | 2043 | switch (code) { |
duke@435 | 2044 | case lir_add: __ addl (lreg, rreg); break; |
duke@435 | 2045 | case lir_sub: __ subl (lreg, rreg); break; |
duke@435 | 2046 | case lir_mul: __ imull(lreg, rreg); break; |
duke@435 | 2047 | default: ShouldNotReachHere(); |
duke@435 | 2048 | } |
duke@435 | 2049 | |
duke@435 | 2050 | } else if (right->is_stack()) { |
duke@435 | 2051 | // cpu register - stack |
duke@435 | 2052 | Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2053 | switch (code) { |
duke@435 | 2054 | case lir_add: __ addl(lreg, raddr); break; |
duke@435 | 2055 | case lir_sub: __ subl(lreg, raddr); break; |
duke@435 | 2056 | default: ShouldNotReachHere(); |
duke@435 | 2057 | } |
duke@435 | 2058 | |
duke@435 | 2059 | } else if (right->is_constant()) { |
duke@435 | 2060 | // cpu register - constant |
duke@435 | 2061 | jint c = right->as_constant_ptr()->as_jint(); |
duke@435 | 2062 | switch (code) { |
duke@435 | 2063 | case lir_add: { |
iveresov@2145 | 2064 | __ incrementl(lreg, c); |
duke@435 | 2065 | break; |
duke@435 | 2066 | } |
duke@435 | 2067 | case lir_sub: { |
iveresov@2145 | 2068 | __ decrementl(lreg, c); |
duke@435 | 2069 | break; |
duke@435 | 2070 | } |
duke@435 | 2071 | default: ShouldNotReachHere(); |
duke@435 | 2072 | } |
duke@435 | 2073 | |
duke@435 | 2074 | } else { |
duke@435 | 2075 | ShouldNotReachHere(); |
duke@435 | 2076 | } |
duke@435 | 2077 | |
duke@435 | 2078 | } else if (left->is_double_cpu()) { |
duke@435 | 2079 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2080 | Register lreg_lo = left->as_register_lo(); |
duke@435 | 2081 | Register lreg_hi = left->as_register_hi(); |
duke@435 | 2082 | |
duke@435 | 2083 | if (right->is_double_cpu()) { |
duke@435 | 2084 | // cpu register - cpu register |
duke@435 | 2085 | Register rreg_lo = right->as_register_lo(); |
duke@435 | 2086 | Register rreg_hi = right->as_register_hi(); |
never@739 | 2087 | NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
never@739 | 2088 | LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); |
duke@435 | 2089 | switch (code) { |
duke@435 | 2090 | case lir_add: |
never@739 | 2091 | __ addptr(lreg_lo, rreg_lo); |
never@739 | 2092 | NOT_LP64(__ adcl(lreg_hi, rreg_hi)); |
duke@435 | 2093 | break; |
duke@435 | 2094 | case lir_sub: |
never@739 | 2095 | __ subptr(lreg_lo, rreg_lo); |
never@739 | 2096 | NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); |
duke@435 | 2097 | break; |
duke@435 | 2098 | case lir_mul: |
never@739 | 2099 | #ifdef _LP64 |
never@739 | 2100 | __ imulq(lreg_lo, rreg_lo); |
never@739 | 2101 | #else |
duke@435 | 2102 | assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
duke@435 | 2103 | __ imull(lreg_hi, rreg_lo); |
duke@435 | 2104 | __ imull(rreg_hi, lreg_lo); |
duke@435 | 2105 | __ addl (rreg_hi, lreg_hi); |
duke@435 | 2106 | __ mull (rreg_lo); |
duke@435 | 2107 | __ addl (lreg_hi, rreg_hi); |
never@739 | 2108 | #endif // _LP64 |
duke@435 | 2109 | break; |
duke@435 | 2110 | default: |
duke@435 | 2111 | ShouldNotReachHere(); |
duke@435 | 2112 | } |
duke@435 | 2113 | |
duke@435 | 2114 | } else if (right->is_constant()) { |
duke@435 | 2115 | // cpu register - constant |
never@739 | 2116 | #ifdef _LP64 |
never@739 | 2117 | jlong c = right->as_constant_ptr()->as_jlong_bits(); |
never@739 | 2118 | __ movptr(r10, (intptr_t) c); |
never@739 | 2119 | switch (code) { |
never@739 | 2120 | case lir_add: |
never@739 | 2121 | __ addptr(lreg_lo, r10); |
never@739 | 2122 | break; |
never@739 | 2123 | case lir_sub: |
never@739 | 2124 | __ subptr(lreg_lo, r10); |
never@739 | 2125 | break; |
never@739 | 2126 | default: |
never@739 | 2127 | ShouldNotReachHere(); |
never@739 | 2128 | } |
never@739 | 2129 | #else |
duke@435 | 2130 | jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
duke@435 | 2131 | jint c_hi = right->as_constant_ptr()->as_jint_hi(); |
duke@435 | 2132 | switch (code) { |
duke@435 | 2133 | case lir_add: |
never@739 | 2134 | __ addptr(lreg_lo, c_lo); |
duke@435 | 2135 | __ adcl(lreg_hi, c_hi); |
duke@435 | 2136 | break; |
duke@435 | 2137 | case lir_sub: |
never@739 | 2138 | __ subptr(lreg_lo, c_lo); |
duke@435 | 2139 | __ sbbl(lreg_hi, c_hi); |
duke@435 | 2140 | break; |
duke@435 | 2141 | default: |
duke@435 | 2142 | ShouldNotReachHere(); |
duke@435 | 2143 | } |
never@739 | 2144 | #endif // _LP64 |
duke@435 | 2145 | |
duke@435 | 2146 | } else { |
duke@435 | 2147 | ShouldNotReachHere(); |
duke@435 | 2148 | } |
duke@435 | 2149 | |
duke@435 | 2150 | } else if (left->is_single_xmm()) { |
duke@435 | 2151 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2152 | XMMRegister lreg = left->as_xmm_float_reg(); |
duke@435 | 2153 | |
duke@435 | 2154 | if (right->is_single_xmm()) { |
duke@435 | 2155 | XMMRegister rreg = right->as_xmm_float_reg(); |
duke@435 | 2156 | switch (code) { |
duke@435 | 2157 | case lir_add: __ addss(lreg, rreg); break; |
duke@435 | 2158 | case lir_sub: __ subss(lreg, rreg); break; |
duke@435 | 2159 | case lir_mul_strictfp: // fall through |
duke@435 | 2160 | case lir_mul: __ mulss(lreg, rreg); break; |
duke@435 | 2161 | case lir_div_strictfp: // fall through |
duke@435 | 2162 | case lir_div: __ divss(lreg, rreg); break; |
duke@435 | 2163 | default: ShouldNotReachHere(); |
duke@435 | 2164 | } |
duke@435 | 2165 | } else { |
duke@435 | 2166 | Address raddr; |
duke@435 | 2167 | if (right->is_single_stack()) { |
duke@435 | 2168 | raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2169 | } else if (right->is_constant()) { |
duke@435 | 2170 | // hack for now |
duke@435 | 2171 | raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); |
duke@435 | 2172 | } else { |
duke@435 | 2173 | ShouldNotReachHere(); |
duke@435 | 2174 | } |
duke@435 | 2175 | switch (code) { |
duke@435 | 2176 | case lir_add: __ addss(lreg, raddr); break; |
duke@435 | 2177 | case lir_sub: __ subss(lreg, raddr); break; |
duke@435 | 2178 | case lir_mul_strictfp: // fall through |
duke@435 | 2179 | case lir_mul: __ mulss(lreg, raddr); break; |
duke@435 | 2180 | case lir_div_strictfp: // fall through |
duke@435 | 2181 | case lir_div: __ divss(lreg, raddr); break; |
duke@435 | 2182 | default: ShouldNotReachHere(); |
duke@435 | 2183 | } |
duke@435 | 2184 | } |
duke@435 | 2185 | |
duke@435 | 2186 | } else if (left->is_double_xmm()) { |
duke@435 | 2187 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2188 | |
duke@435 | 2189 | XMMRegister lreg = left->as_xmm_double_reg(); |
duke@435 | 2190 | if (right->is_double_xmm()) { |
duke@435 | 2191 | XMMRegister rreg = right->as_xmm_double_reg(); |
duke@435 | 2192 | switch (code) { |
duke@435 | 2193 | case lir_add: __ addsd(lreg, rreg); break; |
duke@435 | 2194 | case lir_sub: __ subsd(lreg, rreg); break; |
duke@435 | 2195 | case lir_mul_strictfp: // fall through |
duke@435 | 2196 | case lir_mul: __ mulsd(lreg, rreg); break; |
duke@435 | 2197 | case lir_div_strictfp: // fall through |
duke@435 | 2198 | case lir_div: __ divsd(lreg, rreg); break; |
duke@435 | 2199 | default: ShouldNotReachHere(); |
duke@435 | 2200 | } |
duke@435 | 2201 | } else { |
duke@435 | 2202 | Address raddr; |
duke@435 | 2203 | if (right->is_double_stack()) { |
duke@435 | 2204 | raddr = frame_map()->address_for_slot(right->double_stack_ix()); |
duke@435 | 2205 | } else if (right->is_constant()) { |
duke@435 | 2206 | // hack for now |
duke@435 | 2207 | raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); |
duke@435 | 2208 | } else { |
duke@435 | 2209 | ShouldNotReachHere(); |
duke@435 | 2210 | } |
duke@435 | 2211 | switch (code) { |
duke@435 | 2212 | case lir_add: __ addsd(lreg, raddr); break; |
duke@435 | 2213 | case lir_sub: __ subsd(lreg, raddr); break; |
duke@435 | 2214 | case lir_mul_strictfp: // fall through |
duke@435 | 2215 | case lir_mul: __ mulsd(lreg, raddr); break; |
duke@435 | 2216 | case lir_div_strictfp: // fall through |
duke@435 | 2217 | case lir_div: __ divsd(lreg, raddr); break; |
duke@435 | 2218 | default: ShouldNotReachHere(); |
duke@435 | 2219 | } |
duke@435 | 2220 | } |
duke@435 | 2221 | |
duke@435 | 2222 | } else if (left->is_single_fpu()) { |
duke@435 | 2223 | assert(dest->is_single_fpu(), "fpu stack allocation required"); |
duke@435 | 2224 | |
duke@435 | 2225 | if (right->is_single_fpu()) { |
duke@435 | 2226 | arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); |
duke@435 | 2227 | |
duke@435 | 2228 | } else { |
duke@435 | 2229 | assert(left->fpu_regnr() == 0, "left must be on TOS"); |
duke@435 | 2230 | assert(dest->fpu_regnr() == 0, "dest must be on TOS"); |
duke@435 | 2231 | |
duke@435 | 2232 | Address raddr; |
duke@435 | 2233 | if (right->is_single_stack()) { |
duke@435 | 2234 | raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2235 | } else if (right->is_constant()) { |
duke@435 | 2236 | address const_addr = float_constant(right->as_jfloat()); |
duke@435 | 2237 | assert(const_addr != NULL, "incorrect float/double constant maintainance"); |
duke@435 | 2238 | // hack for now |
duke@435 | 2239 | raddr = __ as_Address(InternalAddress(const_addr)); |
duke@435 | 2240 | } else { |
duke@435 | 2241 | ShouldNotReachHere(); |
duke@435 | 2242 | } |
duke@435 | 2243 | |
duke@435 | 2244 | switch (code) { |
duke@435 | 2245 | case lir_add: __ fadd_s(raddr); break; |
duke@435 | 2246 | case lir_sub: __ fsub_s(raddr); break; |
duke@435 | 2247 | case lir_mul_strictfp: // fall through |
duke@435 | 2248 | case lir_mul: __ fmul_s(raddr); break; |
duke@435 | 2249 | case lir_div_strictfp: // fall through |
duke@435 | 2250 | case lir_div: __ fdiv_s(raddr); break; |
duke@435 | 2251 | default: ShouldNotReachHere(); |
duke@435 | 2252 | } |
duke@435 | 2253 | } |
duke@435 | 2254 | |
duke@435 | 2255 | } else if (left->is_double_fpu()) { |
duke@435 | 2256 | assert(dest->is_double_fpu(), "fpu stack allocation required"); |
duke@435 | 2257 | |
duke@435 | 2258 | if (code == lir_mul_strictfp || code == lir_div_strictfp) { |
duke@435 | 2259 | // Double values require special handling for strictfp mul/div on x86 |
duke@435 | 2260 | __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); |
duke@435 | 2261 | __ fmulp(left->fpu_regnrLo() + 1); |
duke@435 | 2262 | } |
duke@435 | 2263 | |
duke@435 | 2264 | if (right->is_double_fpu()) { |
duke@435 | 2265 | arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); |
duke@435 | 2266 | |
duke@435 | 2267 | } else { |
duke@435 | 2268 | assert(left->fpu_regnrLo() == 0, "left must be on TOS"); |
duke@435 | 2269 | assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); |
duke@435 | 2270 | |
duke@435 | 2271 | Address raddr; |
duke@435 | 2272 | if (right->is_double_stack()) { |
duke@435 | 2273 | raddr = frame_map()->address_for_slot(right->double_stack_ix()); |
duke@435 | 2274 | } else if (right->is_constant()) { |
duke@435 | 2275 | // hack for now |
duke@435 | 2276 | raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); |
duke@435 | 2277 | } else { |
duke@435 | 2278 | ShouldNotReachHere(); |
duke@435 | 2279 | } |
duke@435 | 2280 | |
duke@435 | 2281 | switch (code) { |
duke@435 | 2282 | case lir_add: __ fadd_d(raddr); break; |
duke@435 | 2283 | case lir_sub: __ fsub_d(raddr); break; |
duke@435 | 2284 | case lir_mul_strictfp: // fall through |
duke@435 | 2285 | case lir_mul: __ fmul_d(raddr); break; |
duke@435 | 2286 | case lir_div_strictfp: // fall through |
duke@435 | 2287 | case lir_div: __ fdiv_d(raddr); break; |
duke@435 | 2288 | default: ShouldNotReachHere(); |
duke@435 | 2289 | } |
duke@435 | 2290 | } |
duke@435 | 2291 | |
duke@435 | 2292 | if (code == lir_mul_strictfp || code == lir_div_strictfp) { |
duke@435 | 2293 | // Double values require special handling for strictfp mul/div on x86 |
duke@435 | 2294 | __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); |
duke@435 | 2295 | __ fmulp(dest->fpu_regnrLo() + 1); |
duke@435 | 2296 | } |
duke@435 | 2297 | |
duke@435 | 2298 | } else if (left->is_single_stack() || left->is_address()) { |
duke@435 | 2299 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2300 | |
duke@435 | 2301 | Address laddr; |
duke@435 | 2302 | if (left->is_single_stack()) { |
duke@435 | 2303 | laddr = frame_map()->address_for_slot(left->single_stack_ix()); |
duke@435 | 2304 | } else if (left->is_address()) { |
duke@435 | 2305 | laddr = as_Address(left->as_address_ptr()); |
duke@435 | 2306 | } else { |
duke@435 | 2307 | ShouldNotReachHere(); |
duke@435 | 2308 | } |
duke@435 | 2309 | |
duke@435 | 2310 | if (right->is_single_cpu()) { |
duke@435 | 2311 | Register rreg = right->as_register(); |
duke@435 | 2312 | switch (code) { |
duke@435 | 2313 | case lir_add: __ addl(laddr, rreg); break; |
duke@435 | 2314 | case lir_sub: __ subl(laddr, rreg); break; |
duke@435 | 2315 | default: ShouldNotReachHere(); |
duke@435 | 2316 | } |
duke@435 | 2317 | } else if (right->is_constant()) { |
duke@435 | 2318 | jint c = right->as_constant_ptr()->as_jint(); |
duke@435 | 2319 | switch (code) { |
duke@435 | 2320 | case lir_add: { |
never@739 | 2321 | __ incrementl(laddr, c); |
duke@435 | 2322 | break; |
duke@435 | 2323 | } |
duke@435 | 2324 | case lir_sub: { |
never@739 | 2325 | __ decrementl(laddr, c); |
duke@435 | 2326 | break; |
duke@435 | 2327 | } |
duke@435 | 2328 | default: ShouldNotReachHere(); |
duke@435 | 2329 | } |
duke@435 | 2330 | } else { |
duke@435 | 2331 | ShouldNotReachHere(); |
duke@435 | 2332 | } |
duke@435 | 2333 | |
duke@435 | 2334 | } else { |
duke@435 | 2335 | ShouldNotReachHere(); |
duke@435 | 2336 | } |
duke@435 | 2337 | } |
duke@435 | 2338 | |
duke@435 | 2339 | void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { |
duke@435 | 2340 | assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); |
duke@435 | 2341 | assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); |
duke@435 | 2342 | assert(left_index == 0 || right_index == 0, "either must be on top of stack"); |
duke@435 | 2343 | |
duke@435 | 2344 | bool left_is_tos = (left_index == 0); |
duke@435 | 2345 | bool dest_is_tos = (dest_index == 0); |
duke@435 | 2346 | int non_tos_index = (left_is_tos ? right_index : left_index); |
duke@435 | 2347 | |
duke@435 | 2348 | switch (code) { |
duke@435 | 2349 | case lir_add: |
duke@435 | 2350 | if (pop_fpu_stack) __ faddp(non_tos_index); |
duke@435 | 2351 | else if (dest_is_tos) __ fadd (non_tos_index); |
duke@435 | 2352 | else __ fadda(non_tos_index); |
duke@435 | 2353 | break; |
duke@435 | 2354 | |
duke@435 | 2355 | case lir_sub: |
duke@435 | 2356 | if (left_is_tos) { |
duke@435 | 2357 | if (pop_fpu_stack) __ fsubrp(non_tos_index); |
duke@435 | 2358 | else if (dest_is_tos) __ fsub (non_tos_index); |
duke@435 | 2359 | else __ fsubra(non_tos_index); |
duke@435 | 2360 | } else { |
duke@435 | 2361 | if (pop_fpu_stack) __ fsubp (non_tos_index); |
duke@435 | 2362 | else if (dest_is_tos) __ fsubr (non_tos_index); |
duke@435 | 2363 | else __ fsuba (non_tos_index); |
duke@435 | 2364 | } |
duke@435 | 2365 | break; |
duke@435 | 2366 | |
duke@435 | 2367 | case lir_mul_strictfp: // fall through |
duke@435 | 2368 | case lir_mul: |
duke@435 | 2369 | if (pop_fpu_stack) __ fmulp(non_tos_index); |
duke@435 | 2370 | else if (dest_is_tos) __ fmul (non_tos_index); |
duke@435 | 2371 | else __ fmula(non_tos_index); |
duke@435 | 2372 | break; |
duke@435 | 2373 | |
duke@435 | 2374 | case lir_div_strictfp: // fall through |
duke@435 | 2375 | case lir_div: |
duke@435 | 2376 | if (left_is_tos) { |
duke@435 | 2377 | if (pop_fpu_stack) __ fdivrp(non_tos_index); |
duke@435 | 2378 | else if (dest_is_tos) __ fdiv (non_tos_index); |
duke@435 | 2379 | else __ fdivra(non_tos_index); |
duke@435 | 2380 | } else { |
duke@435 | 2381 | if (pop_fpu_stack) __ fdivp (non_tos_index); |
duke@435 | 2382 | else if (dest_is_tos) __ fdivr (non_tos_index); |
duke@435 | 2383 | else __ fdiva (non_tos_index); |
duke@435 | 2384 | } |
duke@435 | 2385 | break; |
duke@435 | 2386 | |
duke@435 | 2387 | case lir_rem: |
duke@435 | 2388 | assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); |
duke@435 | 2389 | __ fremr(noreg); |
duke@435 | 2390 | break; |
duke@435 | 2391 | |
duke@435 | 2392 | default: |
duke@435 | 2393 | ShouldNotReachHere(); |
duke@435 | 2394 | } |
duke@435 | 2395 | } |
duke@435 | 2396 | |
duke@435 | 2397 | |
duke@435 | 2398 | void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { |
duke@435 | 2399 | if (value->is_double_xmm()) { |
duke@435 | 2400 | switch(code) { |
duke@435 | 2401 | case lir_abs : |
duke@435 | 2402 | { |
duke@435 | 2403 | if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { |
duke@435 | 2404 | __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); |
duke@435 | 2405 | } |
duke@435 | 2406 | __ andpd(dest->as_xmm_double_reg(), |
duke@435 | 2407 | ExternalAddress((address)double_signmask_pool)); |
duke@435 | 2408 | } |
duke@435 | 2409 | break; |
duke@435 | 2410 | |
duke@435 | 2411 | case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; |
duke@435 | 2412 | // all other intrinsics are not available in the SSE instruction set, so FPU is used |
duke@435 | 2413 | default : ShouldNotReachHere(); |
duke@435 | 2414 | } |
duke@435 | 2415 | |
duke@435 | 2416 | } else if (value->is_double_fpu()) { |
duke@435 | 2417 | assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); |
duke@435 | 2418 | switch(code) { |
duke@435 | 2419 | case lir_log : __ flog() ; break; |
duke@435 | 2420 | case lir_log10 : __ flog10() ; break; |
duke@435 | 2421 | case lir_abs : __ fabs() ; break; |
duke@435 | 2422 | case lir_sqrt : __ fsqrt(); break; |
duke@435 | 2423 | case lir_sin : |
duke@435 | 2424 | // Should consider not saving rbx, if not necessary |
duke@435 | 2425 | __ trigfunc('s', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2426 | break; |
duke@435 | 2427 | case lir_cos : |
duke@435 | 2428 | // Should consider not saving rbx, if not necessary |
duke@435 | 2429 | assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); |
duke@435 | 2430 | __ trigfunc('c', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2431 | break; |
duke@435 | 2432 | case lir_tan : |
duke@435 | 2433 | // Should consider not saving rbx, if not necessary |
duke@435 | 2434 | __ trigfunc('t', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2435 | break; |
duke@435 | 2436 | default : ShouldNotReachHere(); |
duke@435 | 2437 | } |
duke@435 | 2438 | } else { |
duke@435 | 2439 | Unimplemented(); |
duke@435 | 2440 | } |
duke@435 | 2441 | } |
duke@435 | 2442 | |
duke@435 | 2443 | void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { |
duke@435 | 2444 | // assert(left->destroys_register(), "check"); |
duke@435 | 2445 | if (left->is_single_cpu()) { |
duke@435 | 2446 | Register reg = left->as_register(); |
duke@435 | 2447 | if (right->is_constant()) { |
duke@435 | 2448 | int val = right->as_constant_ptr()->as_jint(); |
duke@435 | 2449 | switch (code) { |
duke@435 | 2450 | case lir_logic_and: __ andl (reg, val); break; |
duke@435 | 2451 | case lir_logic_or: __ orl (reg, val); break; |
duke@435 | 2452 | case lir_logic_xor: __ xorl (reg, val); break; |
duke@435 | 2453 | default: ShouldNotReachHere(); |
duke@435 | 2454 | } |
duke@435 | 2455 | } else if (right->is_stack()) { |
duke@435 | 2456 | // added support for stack operands |
duke@435 | 2457 | Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2458 | switch (code) { |
duke@435 | 2459 | case lir_logic_and: __ andl (reg, raddr); break; |
duke@435 | 2460 | case lir_logic_or: __ orl (reg, raddr); break; |
duke@435 | 2461 | case lir_logic_xor: __ xorl (reg, raddr); break; |
duke@435 | 2462 | default: ShouldNotReachHere(); |
duke@435 | 2463 | } |
duke@435 | 2464 | } else { |
duke@435 | 2465 | Register rright = right->as_register(); |
duke@435 | 2466 | switch (code) { |
never@739 | 2467 | case lir_logic_and: __ andptr (reg, rright); break; |
never@739 | 2468 | case lir_logic_or : __ orptr (reg, rright); break; |
never@739 | 2469 | case lir_logic_xor: __ xorptr (reg, rright); break; |
duke@435 | 2470 | default: ShouldNotReachHere(); |
duke@435 | 2471 | } |
duke@435 | 2472 | } |
duke@435 | 2473 | move_regs(reg, dst->as_register()); |
duke@435 | 2474 | } else { |
duke@435 | 2475 | Register l_lo = left->as_register_lo(); |
duke@435 | 2476 | Register l_hi = left->as_register_hi(); |
duke@435 | 2477 | if (right->is_constant()) { |
never@739 | 2478 | #ifdef _LP64 |
never@739 | 2479 | __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); |
never@739 | 2480 | switch (code) { |
never@739 | 2481 | case lir_logic_and: |
never@739 | 2482 | __ andq(l_lo, rscratch1); |
never@739 | 2483 | break; |
never@739 | 2484 | case lir_logic_or: |
never@739 | 2485 | __ orq(l_lo, rscratch1); |
never@739 | 2486 | break; |
never@739 | 2487 | case lir_logic_xor: |
never@739 | 2488 | __ xorq(l_lo, rscratch1); |
never@739 | 2489 | break; |
never@739 | 2490 | default: ShouldNotReachHere(); |
never@739 | 2491 | } |
never@739 | 2492 | #else |
duke@435 | 2493 | int r_lo = right->as_constant_ptr()->as_jint_lo(); |
duke@435 | 2494 | int r_hi = right->as_constant_ptr()->as_jint_hi(); |
duke@435 | 2495 | switch (code) { |
duke@435 | 2496 | case lir_logic_and: |
duke@435 | 2497 | __ andl(l_lo, r_lo); |
duke@435 | 2498 | __ andl(l_hi, r_hi); |
duke@435 | 2499 | break; |
duke@435 | 2500 | case lir_logic_or: |
duke@435 | 2501 | __ orl(l_lo, r_lo); |
duke@435 | 2502 | __ orl(l_hi, r_hi); |
duke@435 | 2503 | break; |
duke@435 | 2504 | case lir_logic_xor: |
duke@435 | 2505 | __ xorl(l_lo, r_lo); |
duke@435 | 2506 | __ xorl(l_hi, r_hi); |
duke@435 | 2507 | break; |
duke@435 | 2508 | default: ShouldNotReachHere(); |
duke@435 | 2509 | } |
never@739 | 2510 | #endif // _LP64 |
duke@435 | 2511 | } else { |
iveresov@1927 | 2512 | #ifdef _LP64 |
iveresov@1927 | 2513 | Register r_lo; |
iveresov@1927 | 2514 | if (right->type() == T_OBJECT || right->type() == T_ARRAY) { |
iveresov@1927 | 2515 | r_lo = right->as_register(); |
iveresov@1927 | 2516 | } else { |
iveresov@1927 | 2517 | r_lo = right->as_register_lo(); |
iveresov@1927 | 2518 | } |
iveresov@1927 | 2519 | #else |
duke@435 | 2520 | Register r_lo = right->as_register_lo(); |
duke@435 | 2521 | Register r_hi = right->as_register_hi(); |
duke@435 | 2522 | assert(l_lo != r_hi, "overwriting registers"); |
iveresov@1927 | 2523 | #endif |
duke@435 | 2524 | switch (code) { |
duke@435 | 2525 | case lir_logic_and: |
never@739 | 2526 | __ andptr(l_lo, r_lo); |
never@739 | 2527 | NOT_LP64(__ andptr(l_hi, r_hi);) |
duke@435 | 2528 | break; |
duke@435 | 2529 | case lir_logic_or: |
never@739 | 2530 | __ orptr(l_lo, r_lo); |
never@739 | 2531 | NOT_LP64(__ orptr(l_hi, r_hi);) |
duke@435 | 2532 | break; |
duke@435 | 2533 | case lir_logic_xor: |
never@739 | 2534 | __ xorptr(l_lo, r_lo); |
never@739 | 2535 | NOT_LP64(__ xorptr(l_hi, r_hi);) |
duke@435 | 2536 | break; |
duke@435 | 2537 | default: ShouldNotReachHere(); |
duke@435 | 2538 | } |
duke@435 | 2539 | } |
duke@435 | 2540 | |
duke@435 | 2541 | Register dst_lo = dst->as_register_lo(); |
duke@435 | 2542 | Register dst_hi = dst->as_register_hi(); |
duke@435 | 2543 | |
never@739 | 2544 | #ifdef _LP64 |
never@739 | 2545 | move_regs(l_lo, dst_lo); |
never@739 | 2546 | #else |
duke@435 | 2547 | if (dst_lo == l_hi) { |
duke@435 | 2548 | assert(dst_hi != l_lo, "overwriting registers"); |
duke@435 | 2549 | move_regs(l_hi, dst_hi); |
duke@435 | 2550 | move_regs(l_lo, dst_lo); |
duke@435 | 2551 | } else { |
duke@435 | 2552 | assert(dst_lo != l_hi, "overwriting registers"); |
duke@435 | 2553 | move_regs(l_lo, dst_lo); |
duke@435 | 2554 | move_regs(l_hi, dst_hi); |
duke@435 | 2555 | } |
never@739 | 2556 | #endif // _LP64 |
duke@435 | 2557 | } |
duke@435 | 2558 | } |
duke@435 | 2559 | |
duke@435 | 2560 | |
duke@435 | 2561 | // we assume that rax, and rdx can be overwritten |
duke@435 | 2562 | void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { |
duke@435 | 2563 | |
duke@435 | 2564 | assert(left->is_single_cpu(), "left must be register"); |
duke@435 | 2565 | assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); |
duke@435 | 2566 | assert(result->is_single_cpu(), "result must be register"); |
duke@435 | 2567 | |
duke@435 | 2568 | // assert(left->destroys_register(), "check"); |
duke@435 | 2569 | // assert(right->destroys_register(), "check"); |
duke@435 | 2570 | |
duke@435 | 2571 | Register lreg = left->as_register(); |
duke@435 | 2572 | Register dreg = result->as_register(); |
duke@435 | 2573 | |
duke@435 | 2574 | if (right->is_constant()) { |
duke@435 | 2575 | int divisor = right->as_constant_ptr()->as_jint(); |
duke@435 | 2576 | assert(divisor > 0 && is_power_of_2(divisor), "must be"); |
duke@435 | 2577 | if (code == lir_idiv) { |
duke@435 | 2578 | assert(lreg == rax, "must be rax,"); |
duke@435 | 2579 | assert(temp->as_register() == rdx, "tmp register must be rdx"); |
duke@435 | 2580 | __ cdql(); // sign extend into rdx:rax |
duke@435 | 2581 | if (divisor == 2) { |
duke@435 | 2582 | __ subl(lreg, rdx); |
duke@435 | 2583 | } else { |
duke@435 | 2584 | __ andl(rdx, divisor - 1); |
duke@435 | 2585 | __ addl(lreg, rdx); |
duke@435 | 2586 | } |
duke@435 | 2587 | __ sarl(lreg, log2_intptr(divisor)); |
duke@435 | 2588 | move_regs(lreg, dreg); |
duke@435 | 2589 | } else if (code == lir_irem) { |
duke@435 | 2590 | Label done; |
never@739 | 2591 | __ mov(dreg, lreg); |
duke@435 | 2592 | __ andl(dreg, 0x80000000 | (divisor - 1)); |
duke@435 | 2593 | __ jcc(Assembler::positive, done); |
duke@435 | 2594 | __ decrement(dreg); |
duke@435 | 2595 | __ orl(dreg, ~(divisor - 1)); |
duke@435 | 2596 | __ increment(dreg); |
duke@435 | 2597 | __ bind(done); |
duke@435 | 2598 | } else { |
duke@435 | 2599 | ShouldNotReachHere(); |
duke@435 | 2600 | } |
duke@435 | 2601 | } else { |
duke@435 | 2602 | Register rreg = right->as_register(); |
duke@435 | 2603 | assert(lreg == rax, "left register must be rax,"); |
duke@435 | 2604 | assert(rreg != rdx, "right register must not be rdx"); |
duke@435 | 2605 | assert(temp->as_register() == rdx, "tmp register must be rdx"); |
duke@435 | 2606 | |
duke@435 | 2607 | move_regs(lreg, rax); |
duke@435 | 2608 | |
duke@435 | 2609 | int idivl_offset = __ corrected_idivl(rreg); |
duke@435 | 2610 | add_debug_info_for_div0(idivl_offset, info); |
duke@435 | 2611 | if (code == lir_irem) { |
duke@435 | 2612 | move_regs(rdx, dreg); // result is in rdx |
duke@435 | 2613 | } else { |
duke@435 | 2614 | move_regs(rax, dreg); |
duke@435 | 2615 | } |
duke@435 | 2616 | } |
duke@435 | 2617 | } |
duke@435 | 2618 | |
duke@435 | 2619 | |
duke@435 | 2620 | void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { |
duke@435 | 2621 | if (opr1->is_single_cpu()) { |
duke@435 | 2622 | Register reg1 = opr1->as_register(); |
duke@435 | 2623 | if (opr2->is_single_cpu()) { |
duke@435 | 2624 | // cpu register - cpu register |
never@739 | 2625 | if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
never@739 | 2626 | __ cmpptr(reg1, opr2->as_register()); |
never@739 | 2627 | } else { |
never@739 | 2628 | assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); |
never@739 | 2629 | __ cmpl(reg1, opr2->as_register()); |
never@739 | 2630 | } |
duke@435 | 2631 | } else if (opr2->is_stack()) { |
duke@435 | 2632 | // cpu register - stack |
never@739 | 2633 | if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
never@739 | 2634 | __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
never@739 | 2635 | } else { |
never@739 | 2636 | __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
never@739 | 2637 | } |
duke@435 | 2638 | } else if (opr2->is_constant()) { |
duke@435 | 2639 | // cpu register - constant |
duke@435 | 2640 | LIR_Const* c = opr2->as_constant_ptr(); |
duke@435 | 2641 | if (c->type() == T_INT) { |
duke@435 | 2642 | __ cmpl(reg1, c->as_jint()); |
never@739 | 2643 | } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2644 | // In 64bit oops are single register |
duke@435 | 2645 | jobject o = c->as_jobject(); |
duke@435 | 2646 | if (o == NULL) { |
never@739 | 2647 | __ cmpptr(reg1, (int32_t)NULL_WORD); |
duke@435 | 2648 | } else { |
never@739 | 2649 | #ifdef _LP64 |
never@739 | 2650 | __ movoop(rscratch1, o); |
never@739 | 2651 | __ cmpptr(reg1, rscratch1); |
never@739 | 2652 | #else |
duke@435 | 2653 | __ cmpoop(reg1, c->as_jobject()); |
never@739 | 2654 | #endif // _LP64 |
duke@435 | 2655 | } |
duke@435 | 2656 | } else { |
duke@435 | 2657 | ShouldNotReachHere(); |
duke@435 | 2658 | } |
duke@435 | 2659 | // cpu register - address |
duke@435 | 2660 | } else if (opr2->is_address()) { |
duke@435 | 2661 | if (op->info() != NULL) { |
duke@435 | 2662 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2663 | } |
duke@435 | 2664 | __ cmpl(reg1, as_Address(opr2->as_address_ptr())); |
duke@435 | 2665 | } else { |
duke@435 | 2666 | ShouldNotReachHere(); |
duke@435 | 2667 | } |
duke@435 | 2668 | |
duke@435 | 2669 | } else if(opr1->is_double_cpu()) { |
duke@435 | 2670 | Register xlo = opr1->as_register_lo(); |
duke@435 | 2671 | Register xhi = opr1->as_register_hi(); |
duke@435 | 2672 | if (opr2->is_double_cpu()) { |
never@739 | 2673 | #ifdef _LP64 |
never@739 | 2674 | __ cmpptr(xlo, opr2->as_register_lo()); |
never@739 | 2675 | #else |
duke@435 | 2676 | // cpu register - cpu register |
duke@435 | 2677 | Register ylo = opr2->as_register_lo(); |
duke@435 | 2678 | Register yhi = opr2->as_register_hi(); |
duke@435 | 2679 | __ subl(xlo, ylo); |
duke@435 | 2680 | __ sbbl(xhi, yhi); |
duke@435 | 2681 | if (condition == lir_cond_equal || condition == lir_cond_notEqual) { |
duke@435 | 2682 | __ orl(xhi, xlo); |
duke@435 | 2683 | } |
never@739 | 2684 | #endif // _LP64 |
duke@435 | 2685 | } else if (opr2->is_constant()) { |
duke@435 | 2686 | // cpu register - constant 0 |
duke@435 | 2687 | assert(opr2->as_jlong() == (jlong)0, "only handles zero"); |
never@739 | 2688 | #ifdef _LP64 |
never@739 | 2689 | __ cmpptr(xlo, (int32_t)opr2->as_jlong()); |
never@739 | 2690 | #else |
duke@435 | 2691 | assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
duke@435 | 2692 | __ orl(xhi, xlo); |
never@739 | 2693 | #endif // _LP64 |
duke@435 | 2694 | } else { |
duke@435 | 2695 | ShouldNotReachHere(); |
duke@435 | 2696 | } |
duke@435 | 2697 | |
duke@435 | 2698 | } else if (opr1->is_single_xmm()) { |
duke@435 | 2699 | XMMRegister reg1 = opr1->as_xmm_float_reg(); |
duke@435 | 2700 | if (opr2->is_single_xmm()) { |
duke@435 | 2701 | // xmm register - xmm register |
duke@435 | 2702 | __ ucomiss(reg1, opr2->as_xmm_float_reg()); |
duke@435 | 2703 | } else if (opr2->is_stack()) { |
duke@435 | 2704 | // xmm register - stack |
duke@435 | 2705 | __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
duke@435 | 2706 | } else if (opr2->is_constant()) { |
duke@435 | 2707 | // xmm register - constant |
duke@435 | 2708 | __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); |
duke@435 | 2709 | } else if (opr2->is_address()) { |
duke@435 | 2710 | // xmm register - address |
duke@435 | 2711 | if (op->info() != NULL) { |
duke@435 | 2712 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2713 | } |
duke@435 | 2714 | __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); |
duke@435 | 2715 | } else { |
duke@435 | 2716 | ShouldNotReachHere(); |
duke@435 | 2717 | } |
duke@435 | 2718 | |
duke@435 | 2719 | } else if (opr1->is_double_xmm()) { |
duke@435 | 2720 | XMMRegister reg1 = opr1->as_xmm_double_reg(); |
duke@435 | 2721 | if (opr2->is_double_xmm()) { |
duke@435 | 2722 | // xmm register - xmm register |
duke@435 | 2723 | __ ucomisd(reg1, opr2->as_xmm_double_reg()); |
duke@435 | 2724 | } else if (opr2->is_stack()) { |
duke@435 | 2725 | // xmm register - stack |
duke@435 | 2726 | __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); |
duke@435 | 2727 | } else if (opr2->is_constant()) { |
duke@435 | 2728 | // xmm register - constant |
duke@435 | 2729 | __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); |
duke@435 | 2730 | } else if (opr2->is_address()) { |
duke@435 | 2731 | // xmm register - address |
duke@435 | 2732 | if (op->info() != NULL) { |
duke@435 | 2733 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2734 | } |
duke@435 | 2735 | __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); |
duke@435 | 2736 | } else { |
duke@435 | 2737 | ShouldNotReachHere(); |
duke@435 | 2738 | } |
duke@435 | 2739 | |
duke@435 | 2740 | } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { |
duke@435 | 2741 | assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); |
duke@435 | 2742 | assert(opr2->is_fpu_register(), "both must be registers"); |
duke@435 | 2743 | __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); |
duke@435 | 2744 | |
duke@435 | 2745 | } else if (opr1->is_address() && opr2->is_constant()) { |
never@739 | 2746 | LIR_Const* c = opr2->as_constant_ptr(); |
never@739 | 2747 | #ifdef _LP64 |
never@739 | 2748 | if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2749 | assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); |
never@739 | 2750 | __ movoop(rscratch1, c->as_jobject()); |
never@739 | 2751 | } |
never@739 | 2752 | #endif // LP64 |
duke@435 | 2753 | if (op->info() != NULL) { |
duke@435 | 2754 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2755 | } |
duke@435 | 2756 | // special case: address - constant |
duke@435 | 2757 | LIR_Address* addr = opr1->as_address_ptr(); |
duke@435 | 2758 | if (c->type() == T_INT) { |
duke@435 | 2759 | __ cmpl(as_Address(addr), c->as_jint()); |
never@739 | 2760 | } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2761 | #ifdef _LP64 |
never@739 | 2762 | // %%% Make this explode if addr isn't reachable until we figure out a |
never@739 | 2763 | // better strategy by giving noreg as the temp for as_Address |
never@739 | 2764 | __ cmpptr(rscratch1, as_Address(addr, noreg)); |
never@739 | 2765 | #else |
duke@435 | 2766 | __ cmpoop(as_Address(addr), c->as_jobject()); |
never@739 | 2767 | #endif // _LP64 |
duke@435 | 2768 | } else { |
duke@435 | 2769 | ShouldNotReachHere(); |
duke@435 | 2770 | } |
duke@435 | 2771 | |
duke@435 | 2772 | } else { |
duke@435 | 2773 | ShouldNotReachHere(); |
duke@435 | 2774 | } |
duke@435 | 2775 | } |
duke@435 | 2776 | |
duke@435 | 2777 | void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { |
duke@435 | 2778 | if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { |
duke@435 | 2779 | if (left->is_single_xmm()) { |
duke@435 | 2780 | assert(right->is_single_xmm(), "must match"); |
duke@435 | 2781 | __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); |
duke@435 | 2782 | } else if (left->is_double_xmm()) { |
duke@435 | 2783 | assert(right->is_double_xmm(), "must match"); |
duke@435 | 2784 | __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); |
duke@435 | 2785 | |
duke@435 | 2786 | } else { |
duke@435 | 2787 | assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); |
duke@435 | 2788 | assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); |
duke@435 | 2789 | |
duke@435 | 2790 | assert(left->fpu() == 0, "left must be on TOS"); |
duke@435 | 2791 | __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), |
duke@435 | 2792 | op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); |
duke@435 | 2793 | } |
duke@435 | 2794 | } else { |
duke@435 | 2795 | assert(code == lir_cmp_l2i, "check"); |
never@739 | 2796 | #ifdef _LP64 |
iveresov@1804 | 2797 | Label done; |
iveresov@1804 | 2798 | Register dest = dst->as_register(); |
iveresov@1804 | 2799 | __ cmpptr(left->as_register_lo(), right->as_register_lo()); |
iveresov@1804 | 2800 | __ movl(dest, -1); |
iveresov@1804 | 2801 | __ jccb(Assembler::less, done); |
iveresov@1804 | 2802 | __ set_byte_if_not_zero(dest); |
iveresov@1804 | 2803 | __ movzbl(dest, dest); |
iveresov@1804 | 2804 | __ bind(done); |
never@739 | 2805 | #else |
duke@435 | 2806 | __ lcmp2int(left->as_register_hi(), |
duke@435 | 2807 | left->as_register_lo(), |
duke@435 | 2808 | right->as_register_hi(), |
duke@435 | 2809 | right->as_register_lo()); |
duke@435 | 2810 | move_regs(left->as_register_hi(), dst->as_register()); |
never@739 | 2811 | #endif // _LP64 |
duke@435 | 2812 | } |
duke@435 | 2813 | } |
duke@435 | 2814 | |
duke@435 | 2815 | |
duke@435 | 2816 | void LIR_Assembler::align_call(LIR_Code code) { |
duke@435 | 2817 | if (os::is_MP()) { |
duke@435 | 2818 | // make sure that the displacement word of the call ends up word aligned |
duke@435 | 2819 | int offset = __ offset(); |
duke@435 | 2820 | switch (code) { |
duke@435 | 2821 | case lir_static_call: |
duke@435 | 2822 | case lir_optvirtual_call: |
twisti@1730 | 2823 | case lir_dynamic_call: |
duke@435 | 2824 | offset += NativeCall::displacement_offset; |
duke@435 | 2825 | break; |
duke@435 | 2826 | case lir_icvirtual_call: |
duke@435 | 2827 | offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; |
duke@435 | 2828 | break; |
duke@435 | 2829 | case lir_virtual_call: // currently, sparc-specific for niagara |
duke@435 | 2830 | default: ShouldNotReachHere(); |
duke@435 | 2831 | } |
duke@435 | 2832 | while (offset++ % BytesPerWord != 0) { |
duke@435 | 2833 | __ nop(); |
duke@435 | 2834 | } |
duke@435 | 2835 | } |
duke@435 | 2836 | } |
duke@435 | 2837 | |
duke@435 | 2838 | |
twisti@1730 | 2839 | void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
duke@435 | 2840 | assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
duke@435 | 2841 | "must be aligned"); |
twisti@1730 | 2842 | __ call(AddressLiteral(op->addr(), rtype)); |
twisti@1919 | 2843 | add_call_info(code_offset(), op->info()); |
duke@435 | 2844 | } |
duke@435 | 2845 | |
duke@435 | 2846 | |
twisti@1730 | 2847 | void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
duke@435 | 2848 | RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
duke@435 | 2849 | __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); |
duke@435 | 2850 | assert(!os::is_MP() || |
duke@435 | 2851 | (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
duke@435 | 2852 | "must be aligned"); |
twisti@1730 | 2853 | __ call(AddressLiteral(op->addr(), rh)); |
twisti@1919 | 2854 | add_call_info(code_offset(), op->info()); |
duke@435 | 2855 | } |
duke@435 | 2856 | |
duke@435 | 2857 | |
duke@435 | 2858 | /* Currently, vtable-dispatch is only enabled for sparc platforms */ |
twisti@1730 | 2859 | void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
duke@435 | 2860 | ShouldNotReachHere(); |
duke@435 | 2861 | } |
duke@435 | 2862 | |
twisti@1730 | 2863 | |
duke@435 | 2864 | void LIR_Assembler::emit_static_call_stub() { |
duke@435 | 2865 | address call_pc = __ pc(); |
duke@435 | 2866 | address stub = __ start_a_stub(call_stub_size); |
duke@435 | 2867 | if (stub == NULL) { |
duke@435 | 2868 | bailout("static call stub overflow"); |
duke@435 | 2869 | return; |
duke@435 | 2870 | } |
duke@435 | 2871 | |
duke@435 | 2872 | int start = __ offset(); |
duke@435 | 2873 | if (os::is_MP()) { |
duke@435 | 2874 | // make sure that the displacement word of the call ends up word aligned |
duke@435 | 2875 | int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; |
duke@435 | 2876 | while (offset++ % BytesPerWord != 0) { |
duke@435 | 2877 | __ nop(); |
duke@435 | 2878 | } |
duke@435 | 2879 | } |
duke@435 | 2880 | __ relocate(static_stub_Relocation::spec(call_pc)); |
duke@435 | 2881 | __ movoop(rbx, (jobject)NULL); |
duke@435 | 2882 | // must be set to -1 at code generation time |
duke@435 | 2883 | assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); |
never@739 | 2884 | // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
never@739 | 2885 | __ jump(RuntimeAddress(__ pc())); |
duke@435 | 2886 | |
jcoomes@1844 | 2887 | assert(__ offset() - start <= call_stub_size, "stub too big"); |
duke@435 | 2888 | __ end_a_stub(); |
duke@435 | 2889 | } |
duke@435 | 2890 | |
duke@435 | 2891 | |
never@1813 | 2892 | void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
duke@435 | 2893 | assert(exceptionOop->as_register() == rax, "must match"); |
never@1813 | 2894 | assert(exceptionPC->as_register() == rdx, "must match"); |
duke@435 | 2895 | |
duke@435 | 2896 | // exception object is not added to oop map by LinearScan |
duke@435 | 2897 | // (LinearScan assumes that no oops are in fixed registers) |
duke@435 | 2898 | info->add_register_oop(exceptionOop); |
duke@435 | 2899 | Runtime1::StubID unwind_id; |
duke@435 | 2900 | |
never@1813 | 2901 | // get current pc information |
never@1813 | 2902 | // pc is only needed if the method has an exception handler, the unwind code does not need it. |
never@1813 | 2903 | int pc_for_athrow_offset = __ offset(); |
never@1813 | 2904 | InternalAddress pc_for_athrow(__ pc()); |
never@1813 | 2905 | __ lea(exceptionPC->as_register(), pc_for_athrow); |
never@1813 | 2906 | add_call_info(pc_for_athrow_offset, info); // for exception handler |
never@1813 | 2907 | |
never@1813 | 2908 | __ verify_not_null_oop(rax); |
never@1813 | 2909 | // search an exception handler (rax: exception oop, rdx: throwing pc) |
never@1813 | 2910 | if (compilation()->has_fpu_code()) { |
never@1813 | 2911 | unwind_id = Runtime1::handle_exception_id; |
duke@435 | 2912 | } else { |
never@1813 | 2913 | unwind_id = Runtime1::handle_exception_nofpu_id; |
duke@435 | 2914 | } |
never@1813 | 2915 | __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
duke@435 | 2916 | |
duke@435 | 2917 | // enough room for two byte trap |
duke@435 | 2918 | __ nop(); |
duke@435 | 2919 | } |
duke@435 | 2920 | |
duke@435 | 2921 | |
never@1813 | 2922 | void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
never@1813 | 2923 | assert(exceptionOop->as_register() == rax, "must match"); |
never@1813 | 2924 | |
never@1813 | 2925 | __ jmp(_unwind_handler_entry); |
never@1813 | 2926 | } |
never@1813 | 2927 | |
never@1813 | 2928 | |
duke@435 | 2929 | void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
duke@435 | 2930 | |
duke@435 | 2931 | // optimized version for linear scan: |
duke@435 | 2932 | // * count must be already in ECX (guaranteed by LinearScan) |
duke@435 | 2933 | // * left and dest must be equal |
duke@435 | 2934 | // * tmp must be unused |
duke@435 | 2935 | assert(count->as_register() == SHIFT_count, "count must be in ECX"); |
duke@435 | 2936 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2937 | assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); |
duke@435 | 2938 | |
duke@435 | 2939 | if (left->is_single_cpu()) { |
duke@435 | 2940 | Register value = left->as_register(); |
duke@435 | 2941 | assert(value != SHIFT_count, "left cannot be ECX"); |
duke@435 | 2942 | |
duke@435 | 2943 | switch (code) { |
duke@435 | 2944 | case lir_shl: __ shll(value); break; |
duke@435 | 2945 | case lir_shr: __ sarl(value); break; |
duke@435 | 2946 | case lir_ushr: __ shrl(value); break; |
duke@435 | 2947 | default: ShouldNotReachHere(); |
duke@435 | 2948 | } |
duke@435 | 2949 | } else if (left->is_double_cpu()) { |
duke@435 | 2950 | Register lo = left->as_register_lo(); |
duke@435 | 2951 | Register hi = left->as_register_hi(); |
duke@435 | 2952 | assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); |
never@739 | 2953 | #ifdef _LP64 |
never@739 | 2954 | switch (code) { |
never@739 | 2955 | case lir_shl: __ shlptr(lo); break; |
never@739 | 2956 | case lir_shr: __ sarptr(lo); break; |
never@739 | 2957 | case lir_ushr: __ shrptr(lo); break; |
never@739 | 2958 | default: ShouldNotReachHere(); |
never@739 | 2959 | } |
never@739 | 2960 | #else |
duke@435 | 2961 | |
duke@435 | 2962 | switch (code) { |
duke@435 | 2963 | case lir_shl: __ lshl(hi, lo); break; |
duke@435 | 2964 | case lir_shr: __ lshr(hi, lo, true); break; |
duke@435 | 2965 | case lir_ushr: __ lshr(hi, lo, false); break; |
duke@435 | 2966 | default: ShouldNotReachHere(); |
duke@435 | 2967 | } |
never@739 | 2968 | #endif // LP64 |
duke@435 | 2969 | } else { |
duke@435 | 2970 | ShouldNotReachHere(); |
duke@435 | 2971 | } |
duke@435 | 2972 | } |
duke@435 | 2973 | |
duke@435 | 2974 | |
duke@435 | 2975 | void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { |
duke@435 | 2976 | if (dest->is_single_cpu()) { |
duke@435 | 2977 | // first move left into dest so that left is not destroyed by the shift |
duke@435 | 2978 | Register value = dest->as_register(); |
duke@435 | 2979 | count = count & 0x1F; // Java spec |
duke@435 | 2980 | |
duke@435 | 2981 | move_regs(left->as_register(), value); |
duke@435 | 2982 | switch (code) { |
duke@435 | 2983 | case lir_shl: __ shll(value, count); break; |
duke@435 | 2984 | case lir_shr: __ sarl(value, count); break; |
duke@435 | 2985 | case lir_ushr: __ shrl(value, count); break; |
duke@435 | 2986 | default: ShouldNotReachHere(); |
duke@435 | 2987 | } |
duke@435 | 2988 | } else if (dest->is_double_cpu()) { |
never@739 | 2989 | #ifndef _LP64 |
duke@435 | 2990 | Unimplemented(); |
never@739 | 2991 | #else |
never@739 | 2992 | // first move left into dest so that left is not destroyed by the shift |
never@739 | 2993 | Register value = dest->as_register_lo(); |
never@739 | 2994 | count = count & 0x1F; // Java spec |
never@739 | 2995 | |
never@739 | 2996 | move_regs(left->as_register_lo(), value); |
never@739 | 2997 | switch (code) { |
never@739 | 2998 | case lir_shl: __ shlptr(value, count); break; |
never@739 | 2999 | case lir_shr: __ sarptr(value, count); break; |
never@739 | 3000 | case lir_ushr: __ shrptr(value, count); break; |
never@739 | 3001 | default: ShouldNotReachHere(); |
never@739 | 3002 | } |
never@739 | 3003 | #endif // _LP64 |
duke@435 | 3004 | } else { |
duke@435 | 3005 | ShouldNotReachHere(); |
duke@435 | 3006 | } |
duke@435 | 3007 | } |
duke@435 | 3008 | |
duke@435 | 3009 | |
duke@435 | 3010 | void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { |
duke@435 | 3011 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 3012 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 3013 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
never@739 | 3014 | __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
duke@435 | 3015 | } |
duke@435 | 3016 | |
duke@435 | 3017 | |
duke@435 | 3018 | void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { |
duke@435 | 3019 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 3020 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 3021 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
never@739 | 3022 | __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
duke@435 | 3023 | } |
duke@435 | 3024 | |
duke@435 | 3025 | |
duke@435 | 3026 | void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { |
duke@435 | 3027 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 3028 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 3029 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
duke@435 | 3030 | __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); |
duke@435 | 3031 | } |
duke@435 | 3032 | |
duke@435 | 3033 | |
duke@435 | 3034 | // This code replaces a call to arraycopy; no exception may |
duke@435 | 3035 | // be thrown in this code, they must be thrown in the System.arraycopy |
duke@435 | 3036 | // activation frame; we could save some checks if this would not be the case |
duke@435 | 3037 | void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { |
duke@435 | 3038 | ciArrayKlass* default_type = op->expected_type(); |
duke@435 | 3039 | Register src = op->src()->as_register(); |
duke@435 | 3040 | Register dst = op->dst()->as_register(); |
duke@435 | 3041 | Register src_pos = op->src_pos()->as_register(); |
duke@435 | 3042 | Register dst_pos = op->dst_pos()->as_register(); |
duke@435 | 3043 | Register length = op->length()->as_register(); |
duke@435 | 3044 | Register tmp = op->tmp()->as_register(); |
duke@435 | 3045 | |
duke@435 | 3046 | CodeStub* stub = op->stub(); |
duke@435 | 3047 | int flags = op->flags(); |
duke@435 | 3048 | BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; |
duke@435 | 3049 | if (basic_type == T_ARRAY) basic_type = T_OBJECT; |
duke@435 | 3050 | |
roland@2728 | 3051 | // if we don't know anything, just go through the generic arraycopy |
duke@435 | 3052 | if (default_type == NULL) { |
duke@435 | 3053 | Label done; |
duke@435 | 3054 | // save outgoing arguments on stack in case call to System.arraycopy is needed |
duke@435 | 3055 | // HACK ALERT. This code used to push the parameters in a hardwired fashion |
duke@435 | 3056 | // for interpreter calling conventions. Now we have to do it in new style conventions. |
duke@435 | 3057 | // For the moment until C1 gets the new register allocator I just force all the |
duke@435 | 3058 | // args to the right place (except the register args) and then on the back side |
duke@435 | 3059 | // reload the register args properly if we go slow path. Yuck |
duke@435 | 3060 | |
duke@435 | 3061 | // These are proper for the calling convention |
duke@435 | 3062 | store_parameter(length, 2); |
duke@435 | 3063 | store_parameter(dst_pos, 1); |
duke@435 | 3064 | store_parameter(dst, 0); |
duke@435 | 3065 | |
duke@435 | 3066 | // these are just temporary placements until we need to reload |
duke@435 | 3067 | store_parameter(src_pos, 3); |
duke@435 | 3068 | store_parameter(src, 4); |
never@739 | 3069 | NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
never@739 | 3070 | |
roland@2728 | 3071 | address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); |
roland@2728 | 3072 | |
roland@2728 | 3073 | address copyfunc_addr = StubRoutines::generic_arraycopy(); |
duke@435 | 3074 | |
duke@435 | 3075 | // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint |
never@739 | 3076 | #ifdef _LP64 |
never@739 | 3077 | // The arguments are in java calling convention so we can trivially shift them to C |
never@739 | 3078 | // convention |
never@739 | 3079 | assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); |
never@739 | 3080 | __ mov(c_rarg0, j_rarg0); |
never@739 | 3081 | assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); |
never@739 | 3082 | __ mov(c_rarg1, j_rarg1); |
never@739 | 3083 | assert_different_registers(c_rarg2, j_rarg3, j_rarg4); |
never@739 | 3084 | __ mov(c_rarg2, j_rarg2); |
never@739 | 3085 | assert_different_registers(c_rarg3, j_rarg4); |
never@739 | 3086 | __ mov(c_rarg3, j_rarg3); |
never@739 | 3087 | #ifdef _WIN64 |
never@739 | 3088 | // Allocate abi space for args but be sure to keep stack aligned |
never@739 | 3089 | __ subptr(rsp, 6*wordSize); |
never@739 | 3090 | store_parameter(j_rarg4, 4); |
roland@2728 | 3091 | if (copyfunc_addr == NULL) { // Use C version if stub was not generated |
roland@2728 | 3092 | __ call(RuntimeAddress(C_entry)); |
roland@2728 | 3093 | } else { |
roland@2728 | 3094 | #ifndef PRODUCT |
roland@2728 | 3095 | if (PrintC1Statistics) { |
roland@2728 | 3096 | __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); |
roland@2728 | 3097 | } |
roland@2728 | 3098 | #endif |
roland@2728 | 3099 | __ call(RuntimeAddress(copyfunc_addr)); |
roland@2728 | 3100 | } |
never@739 | 3101 | __ addptr(rsp, 6*wordSize); |
never@739 | 3102 | #else |
never@739 | 3103 | __ mov(c_rarg4, j_rarg4); |
roland@2728 | 3104 | if (copyfunc_addr == NULL) { // Use C version if stub was not generated |
roland@2728 | 3105 | __ call(RuntimeAddress(C_entry)); |
roland@2728 | 3106 | } else { |
roland@2728 | 3107 | #ifndef PRODUCT |
roland@2728 | 3108 | if (PrintC1Statistics) { |
roland@2728 | 3109 | __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); |
roland@2728 | 3110 | } |
roland@2728 | 3111 | #endif |
roland@2728 | 3112 | __ call(RuntimeAddress(copyfunc_addr)); |
roland@2728 | 3113 | } |
never@739 | 3114 | #endif // _WIN64 |
never@739 | 3115 | #else |
never@739 | 3116 | __ push(length); |
never@739 | 3117 | __ push(dst_pos); |
never@739 | 3118 | __ push(dst); |
never@739 | 3119 | __ push(src_pos); |
never@739 | 3120 | __ push(src); |
roland@2728 | 3121 | |
roland@2728 | 3122 | if (copyfunc_addr == NULL) { // Use C version if stub was not generated |
roland@2728 | 3123 | __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack |
roland@2728 | 3124 | } else { |
roland@2728 | 3125 | #ifndef PRODUCT |
roland@2728 | 3126 | if (PrintC1Statistics) { |
roland@2728 | 3127 | __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); |
roland@2728 | 3128 | } |
roland@2728 | 3129 | #endif |
roland@2728 | 3130 | __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack |
roland@2728 | 3131 | } |
duke@435 | 3132 | |
never@739 | 3133 | #endif // _LP64 |
never@739 | 3134 | |
duke@435 | 3135 | __ cmpl(rax, 0); |
duke@435 | 3136 | __ jcc(Assembler::equal, *stub->continuation()); |
duke@435 | 3137 | |
roland@2728 | 3138 | if (copyfunc_addr != NULL) { |
roland@2728 | 3139 | __ mov(tmp, rax); |
roland@2728 | 3140 | __ xorl(tmp, -1); |
roland@2728 | 3141 | } |
roland@2728 | 3142 | |
duke@435 | 3143 | // Reload values from the stack so they are where the stub |
duke@435 | 3144 | // expects them. |
never@739 | 3145 | __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
never@739 | 3146 | __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); |
never@739 | 3147 | __ movptr (length, Address(rsp, 2*BytesPerWord)); |
never@739 | 3148 | __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); |
never@739 | 3149 | __ movptr (src, Address(rsp, 4*BytesPerWord)); |
roland@2728 | 3150 | |
roland@2728 | 3151 | if (copyfunc_addr != NULL) { |
roland@2728 | 3152 | __ subl(length, tmp); |
roland@2728 | 3153 | __ addl(src_pos, tmp); |
roland@2728 | 3154 | __ addl(dst_pos, tmp); |
roland@2728 | 3155 | } |
duke@435 | 3156 | __ jmp(*stub->entry()); |
duke@435 | 3157 | |
duke@435 | 3158 | __ bind(*stub->continuation()); |
duke@435 | 3159 | return; |
duke@435 | 3160 | } |
duke@435 | 3161 | |
duke@435 | 3162 | assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); |
duke@435 | 3163 | |
kvn@464 | 3164 | int elem_size = type2aelembytes(basic_type); |
duke@435 | 3165 | int shift_amount; |
duke@435 | 3166 | Address::ScaleFactor scale; |
duke@435 | 3167 | |
duke@435 | 3168 | switch (elem_size) { |
duke@435 | 3169 | case 1 : |
duke@435 | 3170 | shift_amount = 0; |
duke@435 | 3171 | scale = Address::times_1; |
duke@435 | 3172 | break; |
duke@435 | 3173 | case 2 : |
duke@435 | 3174 | shift_amount = 1; |
duke@435 | 3175 | scale = Address::times_2; |
duke@435 | 3176 | break; |
duke@435 | 3177 | case 4 : |
duke@435 | 3178 | shift_amount = 2; |
duke@435 | 3179 | scale = Address::times_4; |
duke@435 | 3180 | break; |
duke@435 | 3181 | case 8 : |
duke@435 | 3182 | shift_amount = 3; |
duke@435 | 3183 | scale = Address::times_8; |
duke@435 | 3184 | break; |
duke@435 | 3185 | default: |
duke@435 | 3186 | ShouldNotReachHere(); |
duke@435 | 3187 | } |
duke@435 | 3188 | |
duke@435 | 3189 | Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); |
duke@435 | 3190 | Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); |
duke@435 | 3191 | Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); |
duke@435 | 3192 | Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); |
duke@435 | 3193 | |
never@739 | 3194 | // length and pos's are all sign extended at this point on 64bit |
never@739 | 3195 | |
duke@435 | 3196 | // test for NULL |
duke@435 | 3197 | if (flags & LIR_OpArrayCopy::src_null_check) { |
never@739 | 3198 | __ testptr(src, src); |
duke@435 | 3199 | __ jcc(Assembler::zero, *stub->entry()); |
duke@435 | 3200 | } |
duke@435 | 3201 | if (flags & LIR_OpArrayCopy::dst_null_check) { |
never@739 | 3202 | __ testptr(dst, dst); |
duke@435 | 3203 | __ jcc(Assembler::zero, *stub->entry()); |
duke@435 | 3204 | } |
duke@435 | 3205 | |
duke@435 | 3206 | // check if negative |
duke@435 | 3207 | if (flags & LIR_OpArrayCopy::src_pos_positive_check) { |
duke@435 | 3208 | __ testl(src_pos, src_pos); |
duke@435 | 3209 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3210 | } |
duke@435 | 3211 | if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { |
duke@435 | 3212 | __ testl(dst_pos, dst_pos); |
duke@435 | 3213 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3214 | } |
duke@435 | 3215 | |
duke@435 | 3216 | if (flags & LIR_OpArrayCopy::src_range_check) { |
never@739 | 3217 | __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
duke@435 | 3218 | __ cmpl(tmp, src_length_addr); |
duke@435 | 3219 | __ jcc(Assembler::above, *stub->entry()); |
duke@435 | 3220 | } |
duke@435 | 3221 | if (flags & LIR_OpArrayCopy::dst_range_check) { |
never@739 | 3222 | __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
duke@435 | 3223 | __ cmpl(tmp, dst_length_addr); |
duke@435 | 3224 | __ jcc(Assembler::above, *stub->entry()); |
duke@435 | 3225 | } |
duke@435 | 3226 | |
roland@2728 | 3227 | if (flags & LIR_OpArrayCopy::length_positive_check) { |
roland@2728 | 3228 | __ testl(length, length); |
roland@2728 | 3229 | __ jcc(Assembler::less, *stub->entry()); |
roland@2728 | 3230 | __ jcc(Assembler::zero, *stub->continuation()); |
roland@2728 | 3231 | } |
roland@2728 | 3232 | |
roland@2728 | 3233 | #ifdef _LP64 |
roland@2728 | 3234 | __ movl2ptr(src_pos, src_pos); //higher 32bits must be null |
roland@2728 | 3235 | __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null |
roland@2728 | 3236 | #endif |
roland@2728 | 3237 | |
duke@435 | 3238 | if (flags & LIR_OpArrayCopy::type_check) { |
roland@2728 | 3239 | // We don't know the array types are compatible |
roland@2728 | 3240 | if (basic_type != T_OBJECT) { |
roland@2728 | 3241 | // Simple test for basic type arrays |
roland@2728 | 3242 | if (UseCompressedOops) { |
roland@2728 | 3243 | __ movl(tmp, src_klass_addr); |
roland@2728 | 3244 | __ cmpl(tmp, dst_klass_addr); |
roland@2728 | 3245 | } else { |
roland@2728 | 3246 | __ movptr(tmp, src_klass_addr); |
roland@2728 | 3247 | __ cmpptr(tmp, dst_klass_addr); |
roland@2728 | 3248 | } |
roland@2728 | 3249 | __ jcc(Assembler::notEqual, *stub->entry()); |
iveresov@2344 | 3250 | } else { |
roland@2728 | 3251 | // For object arrays, if src is a sub class of dst then we can |
roland@2728 | 3252 | // safely do the copy. |
roland@2728 | 3253 | Label cont, slow; |
roland@2728 | 3254 | |
roland@2728 | 3255 | __ push(src); |
roland@2728 | 3256 | __ push(dst); |
roland@2728 | 3257 | |
roland@2728 | 3258 | __ load_klass(src, src); |
roland@2728 | 3259 | __ load_klass(dst, dst); |
roland@2728 | 3260 | |
roland@2728 | 3261 | __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); |
roland@2728 | 3262 | |
roland@2728 | 3263 | __ push(src); |
roland@2728 | 3264 | __ push(dst); |
roland@2728 | 3265 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
roland@2728 | 3266 | __ pop(dst); |
roland@2728 | 3267 | __ pop(src); |
roland@2728 | 3268 | |
roland@2728 | 3269 | __ cmpl(src, 0); |
roland@2728 | 3270 | __ jcc(Assembler::notEqual, cont); |
roland@2728 | 3271 | |
roland@2728 | 3272 | __ bind(slow); |
roland@2728 | 3273 | __ pop(dst); |
roland@2728 | 3274 | __ pop(src); |
roland@2728 | 3275 | |
roland@2728 | 3276 | address copyfunc_addr = StubRoutines::checkcast_arraycopy(); |
roland@2728 | 3277 | if (copyfunc_addr != NULL) { // use stub if available |
roland@2728 | 3278 | // src is not a sub class of dst so we have to do a |
roland@2728 | 3279 | // per-element check. |
roland@2728 | 3280 | |
roland@2728 | 3281 | int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; |
roland@2728 | 3282 | if ((flags & mask) != mask) { |
roland@2728 | 3283 | // Check that at least both of them object arrays. |
roland@2728 | 3284 | assert(flags & mask, "one of the two should be known to be an object array"); |
roland@2728 | 3285 | |
roland@2728 | 3286 | if (!(flags & LIR_OpArrayCopy::src_objarray)) { |
roland@2728 | 3287 | __ load_klass(tmp, src); |
roland@2728 | 3288 | } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { |
roland@2728 | 3289 | __ load_klass(tmp, dst); |
roland@2728 | 3290 | } |
stefank@3391 | 3291 | int lh_offset = in_bytes(Klass::layout_helper_offset()); |
roland@2728 | 3292 | Address klass_lh_addr(tmp, lh_offset); |
roland@2728 | 3293 | jint objArray_lh = Klass::array_layout_helper(T_OBJECT); |
roland@2728 | 3294 | __ cmpl(klass_lh_addr, objArray_lh); |
roland@2728 | 3295 | __ jcc(Assembler::notEqual, *stub->entry()); |
roland@2728 | 3296 | } |
roland@2728 | 3297 | |
iveresov@2936 | 3298 | // Spill because stubs can use any register they like and it's |
iveresov@2936 | 3299 | // easier to restore just those that we care about. |
iveresov@2936 | 3300 | store_parameter(dst, 0); |
iveresov@2936 | 3301 | store_parameter(dst_pos, 1); |
iveresov@2936 | 3302 | store_parameter(length, 2); |
iveresov@2936 | 3303 | store_parameter(src_pos, 3); |
iveresov@2936 | 3304 | store_parameter(src, 4); |
iveresov@2936 | 3305 | |
roland@2728 | 3306 | #ifndef _LP64 |
roland@2728 | 3307 | __ movptr(tmp, dst_klass_addr); |
stefank@3391 | 3308 | __ movptr(tmp, Address(tmp, objArrayKlass::element_klass_offset())); |
roland@2728 | 3309 | __ push(tmp); |
stefank@3391 | 3310 | __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); |
roland@2728 | 3311 | __ push(tmp); |
roland@2728 | 3312 | __ push(length); |
roland@2728 | 3313 | __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
roland@2728 | 3314 | __ push(tmp); |
roland@2728 | 3315 | __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
roland@2728 | 3316 | __ push(tmp); |
roland@2728 | 3317 | |
roland@2728 | 3318 | __ call_VM_leaf(copyfunc_addr, 5); |
roland@2728 | 3319 | #else |
roland@2728 | 3320 | __ movl2ptr(length, length); //higher 32bits must be null |
roland@2728 | 3321 | |
roland@2728 | 3322 | __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
roland@2728 | 3323 | assert_different_registers(c_rarg0, dst, dst_pos, length); |
roland@2728 | 3324 | __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
roland@2728 | 3325 | assert_different_registers(c_rarg1, dst, length); |
roland@2728 | 3326 | |
roland@2728 | 3327 | __ mov(c_rarg2, length); |
roland@2728 | 3328 | assert_different_registers(c_rarg2, dst); |
roland@2728 | 3329 | |
roland@2728 | 3330 | #ifdef _WIN64 |
roland@2728 | 3331 | // Allocate abi space for args but be sure to keep stack aligned |
roland@2728 | 3332 | __ subptr(rsp, 6*wordSize); |
roland@2728 | 3333 | __ load_klass(c_rarg3, dst); |
stefank@3391 | 3334 | __ movptr(c_rarg3, Address(c_rarg3, objArrayKlass::element_klass_offset())); |
roland@2728 | 3335 | store_parameter(c_rarg3, 4); |
stefank@3391 | 3336 | __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); |
roland@2728 | 3337 | __ call(RuntimeAddress(copyfunc_addr)); |
roland@2728 | 3338 | __ addptr(rsp, 6*wordSize); |
roland@2728 | 3339 | #else |
roland@2728 | 3340 | __ load_klass(c_rarg4, dst); |
stefank@3391 | 3341 | __ movptr(c_rarg4, Address(c_rarg4, objArrayKlass::element_klass_offset())); |
stefank@3391 | 3342 | __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); |
roland@2728 | 3343 | __ call(RuntimeAddress(copyfunc_addr)); |
roland@2728 | 3344 | #endif |
roland@2728 | 3345 | |
roland@2728 | 3346 | #endif |
roland@2728 | 3347 | |
roland@2728 | 3348 | #ifndef PRODUCT |
roland@2728 | 3349 | if (PrintC1Statistics) { |
roland@2728 | 3350 | Label failed; |
roland@2728 | 3351 | __ testl(rax, rax); |
roland@2728 | 3352 | __ jcc(Assembler::notZero, failed); |
roland@2728 | 3353 | __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); |
roland@2728 | 3354 | __ bind(failed); |
roland@2728 | 3355 | } |
roland@2728 | 3356 | #endif |
roland@2728 | 3357 | |
roland@2728 | 3358 | __ testl(rax, rax); |
roland@2728 | 3359 | __ jcc(Assembler::zero, *stub->continuation()); |
roland@2728 | 3360 | |
roland@2728 | 3361 | #ifndef PRODUCT |
roland@2728 | 3362 | if (PrintC1Statistics) { |
roland@2728 | 3363 | __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); |
roland@2728 | 3364 | } |
roland@2728 | 3365 | #endif |
roland@2728 | 3366 | |
roland@2728 | 3367 | __ mov(tmp, rax); |
roland@2728 | 3368 | |
roland@2728 | 3369 | __ xorl(tmp, -1); |
roland@2728 | 3370 | |
iveresov@2936 | 3371 | // Restore previously spilled arguments |
iveresov@2936 | 3372 | __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
iveresov@2936 | 3373 | __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); |
iveresov@2936 | 3374 | __ movptr (length, Address(rsp, 2*BytesPerWord)); |
iveresov@2936 | 3375 | __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); |
iveresov@2936 | 3376 | __ movptr (src, Address(rsp, 4*BytesPerWord)); |
iveresov@2936 | 3377 | |
roland@2728 | 3378 | |
roland@2728 | 3379 | __ subl(length, tmp); |
roland@2728 | 3380 | __ addl(src_pos, tmp); |
roland@2728 | 3381 | __ addl(dst_pos, tmp); |
roland@2728 | 3382 | } |
roland@2728 | 3383 | |
roland@2728 | 3384 | __ jmp(*stub->entry()); |
roland@2728 | 3385 | |
roland@2728 | 3386 | __ bind(cont); |
roland@2728 | 3387 | __ pop(dst); |
roland@2728 | 3388 | __ pop(src); |
iveresov@2344 | 3389 | } |
duke@435 | 3390 | } |
duke@435 | 3391 | |
duke@435 | 3392 | #ifdef ASSERT |
duke@435 | 3393 | if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { |
duke@435 | 3394 | // Sanity check the known type with the incoming class. For the |
duke@435 | 3395 | // primitive case the types must match exactly with src.klass and |
duke@435 | 3396 | // dst.klass each exactly matching the default type. For the |
duke@435 | 3397 | // object array case, if no type check is needed then either the |
duke@435 | 3398 | // dst type is exactly the expected type and the src type is a |
duke@435 | 3399 | // subtype which we can't check or src is the same array as dst |
duke@435 | 3400 | // but not necessarily exactly of type default_type. |
duke@435 | 3401 | Label known_ok, halt; |
jrose@1424 | 3402 | __ movoop(tmp, default_type->constant_encoding()); |
iveresov@2344 | 3403 | #ifdef _LP64 |
iveresov@2344 | 3404 | if (UseCompressedOops) { |
iveresov@2344 | 3405 | __ encode_heap_oop(tmp); |
iveresov@2344 | 3406 | } |
iveresov@2344 | 3407 | #endif |
iveresov@2344 | 3408 | |
duke@435 | 3409 | if (basic_type != T_OBJECT) { |
iveresov@2344 | 3410 | |
iveresov@2344 | 3411 | if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); |
iveresov@2344 | 3412 | else __ cmpptr(tmp, dst_klass_addr); |
duke@435 | 3413 | __ jcc(Assembler::notEqual, halt); |
iveresov@2344 | 3414 | if (UseCompressedOops) __ cmpl(tmp, src_klass_addr); |
iveresov@2344 | 3415 | else __ cmpptr(tmp, src_klass_addr); |
duke@435 | 3416 | __ jcc(Assembler::equal, known_ok); |
duke@435 | 3417 | } else { |
iveresov@2344 | 3418 | if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); |
iveresov@2344 | 3419 | else __ cmpptr(tmp, dst_klass_addr); |
duke@435 | 3420 | __ jcc(Assembler::equal, known_ok); |
never@739 | 3421 | __ cmpptr(src, dst); |
duke@435 | 3422 | __ jcc(Assembler::equal, known_ok); |
duke@435 | 3423 | } |
duke@435 | 3424 | __ bind(halt); |
duke@435 | 3425 | __ stop("incorrect type information in arraycopy"); |
duke@435 | 3426 | __ bind(known_ok); |
duke@435 | 3427 | } |
duke@435 | 3428 | #endif |
duke@435 | 3429 | |
roland@2728 | 3430 | #ifndef PRODUCT |
roland@2728 | 3431 | if (PrintC1Statistics) { |
roland@2728 | 3432 | __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); |
never@739 | 3433 | } |
roland@2728 | 3434 | #endif |
never@739 | 3435 | |
never@739 | 3436 | #ifdef _LP64 |
never@739 | 3437 | assert_different_registers(c_rarg0, dst, dst_pos, length); |
never@739 | 3438 | __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
never@739 | 3439 | assert_different_registers(c_rarg1, length); |
never@739 | 3440 | __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
never@739 | 3441 | __ mov(c_rarg2, length); |
never@739 | 3442 | |
never@739 | 3443 | #else |
never@739 | 3444 | __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
duke@435 | 3445 | store_parameter(tmp, 0); |
never@739 | 3446 | __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
duke@435 | 3447 | store_parameter(tmp, 1); |
duke@435 | 3448 | store_parameter(length, 2); |
never@739 | 3449 | #endif // _LP64 |
roland@2728 | 3450 | |
roland@2728 | 3451 | bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; |
roland@2728 | 3452 | bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; |
roland@2728 | 3453 | const char *name; |
roland@2728 | 3454 | address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); |
roland@2728 | 3455 | __ call_VM_leaf(entry, 0); |
duke@435 | 3456 | |
duke@435 | 3457 | __ bind(*stub->continuation()); |
duke@435 | 3458 | } |
duke@435 | 3459 | |
duke@435 | 3460 | |
duke@435 | 3461 | void LIR_Assembler::emit_lock(LIR_OpLock* op) { |
duke@435 | 3462 | Register obj = op->obj_opr()->as_register(); // may not be an oop |
duke@435 | 3463 | Register hdr = op->hdr_opr()->as_register(); |
duke@435 | 3464 | Register lock = op->lock_opr()->as_register(); |
duke@435 | 3465 | if (!UseFastLocking) { |
duke@435 | 3466 | __ jmp(*op->stub()->entry()); |
duke@435 | 3467 | } else if (op->code() == lir_lock) { |
duke@435 | 3468 | Register scratch = noreg; |
duke@435 | 3469 | if (UseBiasedLocking) { |
duke@435 | 3470 | scratch = op->scratch_opr()->as_register(); |
duke@435 | 3471 | } |
duke@435 | 3472 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 3473 | // add debug info for NullPointerException only if one is possible |
duke@435 | 3474 | int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); |
duke@435 | 3475 | if (op->info() != NULL) { |
duke@435 | 3476 | add_debug_info_for_null_check(null_check_offset, op->info()); |
duke@435 | 3477 | } |
duke@435 | 3478 | // done |
duke@435 | 3479 | } else if (op->code() == lir_unlock) { |
duke@435 | 3480 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 3481 | __ unlock_object(hdr, obj, lock, *op->stub()->entry()); |
duke@435 | 3482 | } else { |
duke@435 | 3483 | Unimplemented(); |
duke@435 | 3484 | } |
duke@435 | 3485 | __ bind(*op->stub()->continuation()); |
duke@435 | 3486 | } |
duke@435 | 3487 | |
duke@435 | 3488 | |
duke@435 | 3489 | void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { |
duke@435 | 3490 | ciMethod* method = op->profiled_method(); |
duke@435 | 3491 | int bci = op->profiled_bci(); |
duke@435 | 3492 | |
duke@435 | 3493 | // Update counter for all call types |
iveresov@2349 | 3494 | ciMethodData* md = method->method_data_or_null(); |
iveresov@2349 | 3495 | assert(md != NULL, "Sanity"); |
duke@435 | 3496 | ciProfileData* data = md->bci_to_data(bci); |
duke@435 | 3497 | assert(data->is_CounterData(), "need CounterData for calls"); |
duke@435 | 3498 | assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); |
duke@435 | 3499 | Register mdo = op->mdo()->as_register(); |
jrose@1424 | 3500 | __ movoop(mdo, md->constant_encoding()); |
duke@435 | 3501 | Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
duke@435 | 3502 | Bytecodes::Code bc = method->java_code_at_bci(bci); |
duke@435 | 3503 | // Perform additional virtual call profiling for invokevirtual and |
duke@435 | 3504 | // invokeinterface bytecodes |
duke@435 | 3505 | if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && |
iveresov@2138 | 3506 | C1ProfileVirtualCalls) { |
duke@435 | 3507 | assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
duke@435 | 3508 | Register recv = op->recv()->as_register(); |
duke@435 | 3509 | assert_different_registers(mdo, recv); |
duke@435 | 3510 | assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); |
duke@435 | 3511 | ciKlass* known_klass = op->known_holder(); |
iveresov@2138 | 3512 | if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
duke@435 | 3513 | // We know the type that will be seen at this call site; we can |
duke@435 | 3514 | // statically update the methodDataOop rather than needing to do |
duke@435 | 3515 | // dynamic tests on the receiver type |
duke@435 | 3516 | |
duke@435 | 3517 | // NOTE: we should probably put a lock around this search to |
duke@435 | 3518 | // avoid collisions by concurrent compilations |
duke@435 | 3519 | ciVirtualCallData* vc_data = (ciVirtualCallData*) data; |
duke@435 | 3520 | uint i; |
duke@435 | 3521 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3522 | ciKlass* receiver = vc_data->receiver(i); |
duke@435 | 3523 | if (known_klass->equals(receiver)) { |
duke@435 | 3524 | Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
iveresov@2138 | 3525 | __ addptr(data_addr, DataLayout::counter_increment); |
duke@435 | 3526 | return; |
duke@435 | 3527 | } |
duke@435 | 3528 | } |
duke@435 | 3529 | |
duke@435 | 3530 | // Receiver type not found in profile data; select an empty slot |
duke@435 | 3531 | |
duke@435 | 3532 | // Note that this is less efficient than it should be because it |
duke@435 | 3533 | // always does a write to the receiver part of the |
duke@435 | 3534 | // VirtualCallData rather than just the first time |
duke@435 | 3535 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3536 | ciKlass* receiver = vc_data->receiver(i); |
duke@435 | 3537 | if (receiver == NULL) { |
duke@435 | 3538 | Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); |
jrose@1424 | 3539 | __ movoop(recv_addr, known_klass->constant_encoding()); |
duke@435 | 3540 | Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
iveresov@2138 | 3541 | __ addptr(data_addr, DataLayout::counter_increment); |
duke@435 | 3542 | return; |
duke@435 | 3543 | } |
duke@435 | 3544 | } |
duke@435 | 3545 | } else { |
iveresov@2344 | 3546 | __ load_klass(recv, recv); |
duke@435 | 3547 | Label update_done; |
iveresov@2138 | 3548 | type_profile_helper(mdo, md, data, recv, &update_done); |
kvn@1641 | 3549 | // Receiver did not match any saved receiver and there is no empty row for it. |
kvn@1686 | 3550 | // Increment total counter to indicate polymorphic case. |
iveresov@2138 | 3551 | __ addptr(counter_addr, DataLayout::counter_increment); |
duke@435 | 3552 | |
duke@435 | 3553 | __ bind(update_done); |
duke@435 | 3554 | } |
kvn@1641 | 3555 | } else { |
kvn@1641 | 3556 | // Static call |
iveresov@2138 | 3557 | __ addptr(counter_addr, DataLayout::counter_increment); |
duke@435 | 3558 | } |
duke@435 | 3559 | } |
duke@435 | 3560 | |
duke@435 | 3561 | void LIR_Assembler::emit_delay(LIR_OpDelay*) { |
duke@435 | 3562 | Unimplemented(); |
duke@435 | 3563 | } |
duke@435 | 3564 | |
duke@435 | 3565 | |
duke@435 | 3566 | void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { |
never@739 | 3567 | __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
duke@435 | 3568 | } |
duke@435 | 3569 | |
duke@435 | 3570 | |
duke@435 | 3571 | void LIR_Assembler::align_backward_branch_target() { |
duke@435 | 3572 | __ align(BytesPerWord); |
duke@435 | 3573 | } |
duke@435 | 3574 | |
duke@435 | 3575 | |
duke@435 | 3576 | void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { |
duke@435 | 3577 | if (left->is_single_cpu()) { |
duke@435 | 3578 | __ negl(left->as_register()); |
duke@435 | 3579 | move_regs(left->as_register(), dest->as_register()); |
duke@435 | 3580 | |
duke@435 | 3581 | } else if (left->is_double_cpu()) { |
duke@435 | 3582 | Register lo = left->as_register_lo(); |
never@739 | 3583 | #ifdef _LP64 |
never@739 | 3584 | Register dst = dest->as_register_lo(); |
never@739 | 3585 | __ movptr(dst, lo); |
never@739 | 3586 | __ negptr(dst); |
never@739 | 3587 | #else |
duke@435 | 3588 | Register hi = left->as_register_hi(); |
duke@435 | 3589 | __ lneg(hi, lo); |
duke@435 | 3590 | if (dest->as_register_lo() == hi) { |
duke@435 | 3591 | assert(dest->as_register_hi() != lo, "destroying register"); |
duke@435 | 3592 | move_regs(hi, dest->as_register_hi()); |
duke@435 | 3593 | move_regs(lo, dest->as_register_lo()); |
duke@435 | 3594 | } else { |
duke@435 | 3595 | move_regs(lo, dest->as_register_lo()); |
duke@435 | 3596 | move_regs(hi, dest->as_register_hi()); |
duke@435 | 3597 | } |
never@739 | 3598 | #endif // _LP64 |
duke@435 | 3599 | |
duke@435 | 3600 | } else if (dest->is_single_xmm()) { |
duke@435 | 3601 | if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { |
duke@435 | 3602 | __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); |
duke@435 | 3603 | } |
duke@435 | 3604 | __ xorps(dest->as_xmm_float_reg(), |
duke@435 | 3605 | ExternalAddress((address)float_signflip_pool)); |
duke@435 | 3606 | |
duke@435 | 3607 | } else if (dest->is_double_xmm()) { |
duke@435 | 3608 | if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { |
duke@435 | 3609 | __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); |
duke@435 | 3610 | } |
duke@435 | 3611 | __ xorpd(dest->as_xmm_double_reg(), |
duke@435 | 3612 | ExternalAddress((address)double_signflip_pool)); |
duke@435 | 3613 | |
duke@435 | 3614 | } else if (left->is_single_fpu() || left->is_double_fpu()) { |
duke@435 | 3615 | assert(left->fpu() == 0, "arg must be on TOS"); |
duke@435 | 3616 | assert(dest->fpu() == 0, "dest must be TOS"); |
duke@435 | 3617 | __ fchs(); |
duke@435 | 3618 | |
duke@435 | 3619 | } else { |
duke@435 | 3620 | ShouldNotReachHere(); |
duke@435 | 3621 | } |
duke@435 | 3622 | } |
duke@435 | 3623 | |
duke@435 | 3624 | |
duke@435 | 3625 | void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { |
duke@435 | 3626 | assert(addr->is_address() && dest->is_register(), "check"); |
never@739 | 3627 | Register reg; |
never@739 | 3628 | reg = dest->as_pointer_register(); |
never@739 | 3629 | __ lea(reg, as_Address(addr->as_address_ptr())); |
duke@435 | 3630 | } |
duke@435 | 3631 | |
duke@435 | 3632 | |
duke@435 | 3633 | |
duke@435 | 3634 | void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { |
duke@435 | 3635 | assert(!tmp->is_valid(), "don't need temporary"); |
duke@435 | 3636 | __ call(RuntimeAddress(dest)); |
duke@435 | 3637 | if (info != NULL) { |
duke@435 | 3638 | add_call_info_here(info); |
duke@435 | 3639 | } |
duke@435 | 3640 | } |
duke@435 | 3641 | |
duke@435 | 3642 | |
duke@435 | 3643 | void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { |
duke@435 | 3644 | assert(type == T_LONG, "only for volatile long fields"); |
duke@435 | 3645 | |
duke@435 | 3646 | if (info != NULL) { |
duke@435 | 3647 | add_debug_info_for_null_check_here(info); |
duke@435 | 3648 | } |
duke@435 | 3649 | |
duke@435 | 3650 | if (src->is_double_xmm()) { |
duke@435 | 3651 | if (dest->is_double_cpu()) { |
never@739 | 3652 | #ifdef _LP64 |
never@739 | 3653 | __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); |
never@739 | 3654 | #else |
never@739 | 3655 | __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); |
duke@435 | 3656 | __ psrlq(src->as_xmm_double_reg(), 32); |
never@739 | 3657 | __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
never@739 | 3658 | #endif // _LP64 |
duke@435 | 3659 | } else if (dest->is_double_stack()) { |
duke@435 | 3660 | __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); |
duke@435 | 3661 | } else if (dest->is_address()) { |
duke@435 | 3662 | __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); |
duke@435 | 3663 | } else { |
duke@435 | 3664 | ShouldNotReachHere(); |
duke@435 | 3665 | } |
duke@435 | 3666 | |
duke@435 | 3667 | } else if (dest->is_double_xmm()) { |
duke@435 | 3668 | if (src->is_double_stack()) { |
duke@435 | 3669 | __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); |
duke@435 | 3670 | } else if (src->is_address()) { |
duke@435 | 3671 | __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); |
duke@435 | 3672 | } else { |
duke@435 | 3673 | ShouldNotReachHere(); |
duke@435 | 3674 | } |
duke@435 | 3675 | |
duke@435 | 3676 | } else if (src->is_double_fpu()) { |
duke@435 | 3677 | assert(src->fpu_regnrLo() == 0, "must be TOS"); |
duke@435 | 3678 | if (dest->is_double_stack()) { |
duke@435 | 3679 | __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); |
duke@435 | 3680 | } else if (dest->is_address()) { |
duke@435 | 3681 | __ fistp_d(as_Address(dest->as_address_ptr())); |
duke@435 | 3682 | } else { |
duke@435 | 3683 | ShouldNotReachHere(); |
duke@435 | 3684 | } |
duke@435 | 3685 | |
duke@435 | 3686 | } else if (dest->is_double_fpu()) { |
duke@435 | 3687 | assert(dest->fpu_regnrLo() == 0, "must be TOS"); |
duke@435 | 3688 | if (src->is_double_stack()) { |
duke@435 | 3689 | __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); |
duke@435 | 3690 | } else if (src->is_address()) { |
duke@435 | 3691 | __ fild_d(as_Address(src->as_address_ptr())); |
duke@435 | 3692 | } else { |
duke@435 | 3693 | ShouldNotReachHere(); |
duke@435 | 3694 | } |
duke@435 | 3695 | } else { |
duke@435 | 3696 | ShouldNotReachHere(); |
duke@435 | 3697 | } |
duke@435 | 3698 | } |
duke@435 | 3699 | |
duke@435 | 3700 | |
duke@435 | 3701 | void LIR_Assembler::membar() { |
never@739 | 3702 | // QQQ sparc TSO uses this, |
never@739 | 3703 | __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); |
duke@435 | 3704 | } |
duke@435 | 3705 | |
duke@435 | 3706 | void LIR_Assembler::membar_acquire() { |
duke@435 | 3707 | // No x86 machines currently require load fences |
duke@435 | 3708 | // __ load_fence(); |
duke@435 | 3709 | } |
duke@435 | 3710 | |
duke@435 | 3711 | void LIR_Assembler::membar_release() { |
duke@435 | 3712 | // No x86 machines currently require store fences |
duke@435 | 3713 | // __ store_fence(); |
duke@435 | 3714 | } |
duke@435 | 3715 | |
duke@435 | 3716 | void LIR_Assembler::get_thread(LIR_Opr result_reg) { |
duke@435 | 3717 | assert(result_reg->is_register(), "check"); |
never@739 | 3718 | #ifdef _LP64 |
never@739 | 3719 | // __ get_thread(result_reg->as_register_lo()); |
never@739 | 3720 | __ mov(result_reg->as_register(), r15_thread); |
never@739 | 3721 | #else |
duke@435 | 3722 | __ get_thread(result_reg->as_register()); |
never@739 | 3723 | #endif // _LP64 |
duke@435 | 3724 | } |
duke@435 | 3725 | |
duke@435 | 3726 | |
duke@435 | 3727 | void LIR_Assembler::peephole(LIR_List*) { |
duke@435 | 3728 | // do nothing for now |
duke@435 | 3729 | } |
duke@435 | 3730 | |
duke@435 | 3731 | |
duke@435 | 3732 | #undef __ |