Thu, 08 Apr 2010 12:13:07 -0700
6942223: c1 64 bit fixes
Summary: This fixes lir_cmp_l2i on x64 and sparc 64bit, and the debug info generation.
Reviewed-by: never
duke@435 | 1 | /* |
twisti@1639 | 2 | * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | # include "incls/_precompiled.incl" |
duke@435 | 26 | # include "incls/_c1_LIRAssembler_x86.cpp.incl" |
duke@435 | 27 | |
duke@435 | 28 | |
duke@435 | 29 | // These masks are used to provide 128-bit aligned bitmasks to the XMM |
duke@435 | 30 | // instructions, to allow sign-masking or sign-bit flipping. They allow |
duke@435 | 31 | // fast versions of NegF/NegD and AbsF/AbsD. |
duke@435 | 32 | |
duke@435 | 33 | // Note: 'double' and 'long long' have 32-bits alignment on x86. |
duke@435 | 34 | static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { |
duke@435 | 35 | // Use the expression (adr)&(~0xF) to provide 128-bits aligned address |
duke@435 | 36 | // of 128-bits operands for SSE instructions. |
duke@435 | 37 | jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); |
duke@435 | 38 | // Store the value to a 128-bits operand. |
duke@435 | 39 | operand[0] = lo; |
duke@435 | 40 | operand[1] = hi; |
duke@435 | 41 | return operand; |
duke@435 | 42 | } |
duke@435 | 43 | |
duke@435 | 44 | // Buffer for 128-bits masks used by SSE instructions. |
duke@435 | 45 | static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) |
duke@435 | 46 | |
duke@435 | 47 | // Static initialization during VM startup. |
duke@435 | 48 | static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); |
duke@435 | 49 | static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); |
duke@435 | 50 | static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); |
duke@435 | 51 | static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); |
duke@435 | 52 | |
duke@435 | 53 | |
duke@435 | 54 | |
duke@435 | 55 | NEEDS_CLEANUP // remove this definitions ? |
duke@435 | 56 | const Register IC_Klass = rax; // where the IC klass is cached |
duke@435 | 57 | const Register SYNC_header = rax; // synchronization header |
duke@435 | 58 | const Register SHIFT_count = rcx; // where count for shift operations must be |
duke@435 | 59 | |
duke@435 | 60 | #define __ _masm-> |
duke@435 | 61 | |
duke@435 | 62 | |
duke@435 | 63 | static void select_different_registers(Register preserve, |
duke@435 | 64 | Register extra, |
duke@435 | 65 | Register &tmp1, |
duke@435 | 66 | Register &tmp2) { |
duke@435 | 67 | if (tmp1 == preserve) { |
duke@435 | 68 | assert_different_registers(tmp1, tmp2, extra); |
duke@435 | 69 | tmp1 = extra; |
duke@435 | 70 | } else if (tmp2 == preserve) { |
duke@435 | 71 | assert_different_registers(tmp1, tmp2, extra); |
duke@435 | 72 | tmp2 = extra; |
duke@435 | 73 | } |
duke@435 | 74 | assert_different_registers(preserve, tmp1, tmp2); |
duke@435 | 75 | } |
duke@435 | 76 | |
duke@435 | 77 | |
duke@435 | 78 | |
duke@435 | 79 | static void select_different_registers(Register preserve, |
duke@435 | 80 | Register extra, |
duke@435 | 81 | Register &tmp1, |
duke@435 | 82 | Register &tmp2, |
duke@435 | 83 | Register &tmp3) { |
duke@435 | 84 | if (tmp1 == preserve) { |
duke@435 | 85 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 86 | tmp1 = extra; |
duke@435 | 87 | } else if (tmp2 == preserve) { |
duke@435 | 88 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 89 | tmp2 = extra; |
duke@435 | 90 | } else if (tmp3 == preserve) { |
duke@435 | 91 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 92 | tmp3 = extra; |
duke@435 | 93 | } |
duke@435 | 94 | assert_different_registers(preserve, tmp1, tmp2, tmp3); |
duke@435 | 95 | } |
duke@435 | 96 | |
duke@435 | 97 | |
duke@435 | 98 | |
duke@435 | 99 | bool LIR_Assembler::is_small_constant(LIR_Opr opr) { |
duke@435 | 100 | if (opr->is_constant()) { |
duke@435 | 101 | LIR_Const* constant = opr->as_constant_ptr(); |
duke@435 | 102 | switch (constant->type()) { |
duke@435 | 103 | case T_INT: { |
duke@435 | 104 | return true; |
duke@435 | 105 | } |
duke@435 | 106 | |
duke@435 | 107 | default: |
duke@435 | 108 | return false; |
duke@435 | 109 | } |
duke@435 | 110 | } |
duke@435 | 111 | return false; |
duke@435 | 112 | } |
duke@435 | 113 | |
duke@435 | 114 | |
duke@435 | 115 | LIR_Opr LIR_Assembler::receiverOpr() { |
never@739 | 116 | return FrameMap::receiver_opr; |
duke@435 | 117 | } |
duke@435 | 118 | |
duke@435 | 119 | LIR_Opr LIR_Assembler::incomingReceiverOpr() { |
duke@435 | 120 | return receiverOpr(); |
duke@435 | 121 | } |
duke@435 | 122 | |
duke@435 | 123 | LIR_Opr LIR_Assembler::osrBufferPointer() { |
never@739 | 124 | return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
duke@435 | 125 | } |
duke@435 | 126 | |
duke@435 | 127 | //--------------fpu register translations----------------------- |
duke@435 | 128 | |
duke@435 | 129 | |
duke@435 | 130 | address LIR_Assembler::float_constant(float f) { |
duke@435 | 131 | address const_addr = __ float_constant(f); |
duke@435 | 132 | if (const_addr == NULL) { |
duke@435 | 133 | bailout("const section overflow"); |
duke@435 | 134 | return __ code()->consts()->start(); |
duke@435 | 135 | } else { |
duke@435 | 136 | return const_addr; |
duke@435 | 137 | } |
duke@435 | 138 | } |
duke@435 | 139 | |
duke@435 | 140 | |
duke@435 | 141 | address LIR_Assembler::double_constant(double d) { |
duke@435 | 142 | address const_addr = __ double_constant(d); |
duke@435 | 143 | if (const_addr == NULL) { |
duke@435 | 144 | bailout("const section overflow"); |
duke@435 | 145 | return __ code()->consts()->start(); |
duke@435 | 146 | } else { |
duke@435 | 147 | return const_addr; |
duke@435 | 148 | } |
duke@435 | 149 | } |
duke@435 | 150 | |
duke@435 | 151 | |
duke@435 | 152 | void LIR_Assembler::set_24bit_FPU() { |
duke@435 | 153 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); |
duke@435 | 154 | } |
duke@435 | 155 | |
duke@435 | 156 | void LIR_Assembler::reset_FPU() { |
duke@435 | 157 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
duke@435 | 158 | } |
duke@435 | 159 | |
duke@435 | 160 | void LIR_Assembler::fpop() { |
duke@435 | 161 | __ fpop(); |
duke@435 | 162 | } |
duke@435 | 163 | |
duke@435 | 164 | void LIR_Assembler::fxch(int i) { |
duke@435 | 165 | __ fxch(i); |
duke@435 | 166 | } |
duke@435 | 167 | |
duke@435 | 168 | void LIR_Assembler::fld(int i) { |
duke@435 | 169 | __ fld_s(i); |
duke@435 | 170 | } |
duke@435 | 171 | |
duke@435 | 172 | void LIR_Assembler::ffree(int i) { |
duke@435 | 173 | __ ffree(i); |
duke@435 | 174 | } |
duke@435 | 175 | |
duke@435 | 176 | void LIR_Assembler::breakpoint() { |
duke@435 | 177 | __ int3(); |
duke@435 | 178 | } |
duke@435 | 179 | |
duke@435 | 180 | void LIR_Assembler::push(LIR_Opr opr) { |
duke@435 | 181 | if (opr->is_single_cpu()) { |
duke@435 | 182 | __ push_reg(opr->as_register()); |
duke@435 | 183 | } else if (opr->is_double_cpu()) { |
never@739 | 184 | NOT_LP64(__ push_reg(opr->as_register_hi())); |
duke@435 | 185 | __ push_reg(opr->as_register_lo()); |
duke@435 | 186 | } else if (opr->is_stack()) { |
duke@435 | 187 | __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); |
duke@435 | 188 | } else if (opr->is_constant()) { |
duke@435 | 189 | LIR_Const* const_opr = opr->as_constant_ptr(); |
duke@435 | 190 | if (const_opr->type() == T_OBJECT) { |
duke@435 | 191 | __ push_oop(const_opr->as_jobject()); |
duke@435 | 192 | } else if (const_opr->type() == T_INT) { |
duke@435 | 193 | __ push_jint(const_opr->as_jint()); |
duke@435 | 194 | } else { |
duke@435 | 195 | ShouldNotReachHere(); |
duke@435 | 196 | } |
duke@435 | 197 | |
duke@435 | 198 | } else { |
duke@435 | 199 | ShouldNotReachHere(); |
duke@435 | 200 | } |
duke@435 | 201 | } |
duke@435 | 202 | |
duke@435 | 203 | void LIR_Assembler::pop(LIR_Opr opr) { |
duke@435 | 204 | if (opr->is_single_cpu()) { |
never@739 | 205 | __ pop_reg(opr->as_register()); |
duke@435 | 206 | } else { |
duke@435 | 207 | ShouldNotReachHere(); |
duke@435 | 208 | } |
duke@435 | 209 | } |
duke@435 | 210 | |
never@739 | 211 | bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
never@739 | 212 | return addr->base()->is_illegal() && addr->index()->is_illegal(); |
never@739 | 213 | } |
never@739 | 214 | |
duke@435 | 215 | //------------------------------------------- |
never@739 | 216 | |
duke@435 | 217 | Address LIR_Assembler::as_Address(LIR_Address* addr) { |
never@739 | 218 | return as_Address(addr, rscratch1); |
never@739 | 219 | } |
never@739 | 220 | |
never@739 | 221 | Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { |
duke@435 | 222 | if (addr->base()->is_illegal()) { |
duke@435 | 223 | assert(addr->index()->is_illegal(), "must be illegal too"); |
never@739 | 224 | AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
never@739 | 225 | if (! __ reachable(laddr)) { |
never@739 | 226 | __ movptr(tmp, laddr.addr()); |
never@739 | 227 | Address res(tmp, 0); |
never@739 | 228 | return res; |
never@739 | 229 | } else { |
never@739 | 230 | return __ as_Address(laddr); |
never@739 | 231 | } |
duke@435 | 232 | } |
duke@435 | 233 | |
never@739 | 234 | Register base = addr->base()->as_pointer_register(); |
duke@435 | 235 | |
duke@435 | 236 | if (addr->index()->is_illegal()) { |
duke@435 | 237 | return Address( base, addr->disp()); |
never@739 | 238 | } else if (addr->index()->is_cpu_register()) { |
never@739 | 239 | Register index = addr->index()->as_pointer_register(); |
duke@435 | 240 | return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
duke@435 | 241 | } else if (addr->index()->is_constant()) { |
never@739 | 242 | intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
never@739 | 243 | assert(Assembler::is_simm32(addr_offset), "must be"); |
duke@435 | 244 | |
duke@435 | 245 | return Address(base, addr_offset); |
duke@435 | 246 | } else { |
duke@435 | 247 | Unimplemented(); |
duke@435 | 248 | return Address(); |
duke@435 | 249 | } |
duke@435 | 250 | } |
duke@435 | 251 | |
duke@435 | 252 | |
duke@435 | 253 | Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { |
duke@435 | 254 | Address base = as_Address(addr); |
duke@435 | 255 | return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); |
duke@435 | 256 | } |
duke@435 | 257 | |
duke@435 | 258 | |
duke@435 | 259 | Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { |
duke@435 | 260 | return as_Address(addr); |
duke@435 | 261 | } |
duke@435 | 262 | |
duke@435 | 263 | |
duke@435 | 264 | void LIR_Assembler::osr_entry() { |
duke@435 | 265 | offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); |
duke@435 | 266 | BlockBegin* osr_entry = compilation()->hir()->osr_entry(); |
duke@435 | 267 | ValueStack* entry_state = osr_entry->state(); |
duke@435 | 268 | int number_of_locks = entry_state->locks_size(); |
duke@435 | 269 | |
duke@435 | 270 | // we jump here if osr happens with the interpreter |
duke@435 | 271 | // state set up to continue at the beginning of the |
duke@435 | 272 | // loop that triggered osr - in particular, we have |
duke@435 | 273 | // the following registers setup: |
duke@435 | 274 | // |
duke@435 | 275 | // rcx: osr buffer |
duke@435 | 276 | // |
duke@435 | 277 | |
duke@435 | 278 | // build frame |
duke@435 | 279 | ciMethod* m = compilation()->method(); |
duke@435 | 280 | __ build_frame(initial_frame_size_in_bytes()); |
duke@435 | 281 | |
duke@435 | 282 | // OSR buffer is |
duke@435 | 283 | // |
duke@435 | 284 | // locals[nlocals-1..0] |
duke@435 | 285 | // monitors[0..number_of_locks] |
duke@435 | 286 | // |
duke@435 | 287 | // locals is a direct copy of the interpreter frame so in the osr buffer |
duke@435 | 288 | // so first slot in the local array is the last local from the interpreter |
duke@435 | 289 | // and last slot is local[0] (receiver) from the interpreter |
duke@435 | 290 | // |
duke@435 | 291 | // Similarly with locks. The first lock slot in the osr buffer is the nth lock |
duke@435 | 292 | // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock |
duke@435 | 293 | // in the interpreter frame (the method lock if a sync method) |
duke@435 | 294 | |
duke@435 | 295 | // Initialize monitors in the compiled activation. |
duke@435 | 296 | // rcx: pointer to osr buffer |
duke@435 | 297 | // |
duke@435 | 298 | // All other registers are dead at this point and the locals will be |
duke@435 | 299 | // copied into place by code emitted in the IR. |
duke@435 | 300 | |
never@739 | 301 | Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
duke@435 | 302 | { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
duke@435 | 303 | int monitor_offset = BytesPerWord * method()->max_locals() + |
roland@1495 | 304 | (2 * BytesPerWord) * (number_of_locks - 1); |
roland@1495 | 305 | // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in |
roland@1495 | 306 | // the OSR buffer using 2 word entries: first the lock and then |
roland@1495 | 307 | // the oop. |
duke@435 | 308 | for (int i = 0; i < number_of_locks; i++) { |
roland@1495 | 309 | int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
duke@435 | 310 | #ifdef ASSERT |
duke@435 | 311 | // verify the interpreter's monitor has a non-null object |
duke@435 | 312 | { |
duke@435 | 313 | Label L; |
roland@1495 | 314 | __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); |
duke@435 | 315 | __ jcc(Assembler::notZero, L); |
duke@435 | 316 | __ stop("locked object is NULL"); |
duke@435 | 317 | __ bind(L); |
duke@435 | 318 | } |
duke@435 | 319 | #endif |
roland@1495 | 320 | __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); |
never@739 | 321 | __ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
roland@1495 | 322 | __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); |
never@739 | 323 | __ movptr(frame_map()->address_for_monitor_object(i), rbx); |
duke@435 | 324 | } |
duke@435 | 325 | } |
duke@435 | 326 | } |
duke@435 | 327 | |
duke@435 | 328 | |
duke@435 | 329 | // inline cache check; done before the frame is built. |
duke@435 | 330 | int LIR_Assembler::check_icache() { |
duke@435 | 331 | Register receiver = FrameMap::receiver_opr->as_register(); |
duke@435 | 332 | Register ic_klass = IC_Klass; |
never@739 | 333 | const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
duke@435 | 334 | |
duke@435 | 335 | if (!VerifyOops) { |
duke@435 | 336 | // insert some nops so that the verified entry point is aligned on CodeEntryAlignment |
never@739 | 337 | while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
duke@435 | 338 | __ nop(); |
duke@435 | 339 | } |
duke@435 | 340 | } |
duke@435 | 341 | int offset = __ offset(); |
duke@435 | 342 | __ inline_cache_check(receiver, IC_Klass); |
duke@435 | 343 | assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); |
duke@435 | 344 | if (VerifyOops) { |
duke@435 | 345 | // force alignment after the cache check. |
duke@435 | 346 | // It's been verified to be aligned if !VerifyOops |
duke@435 | 347 | __ align(CodeEntryAlignment); |
duke@435 | 348 | } |
duke@435 | 349 | return offset; |
duke@435 | 350 | } |
duke@435 | 351 | |
duke@435 | 352 | |
duke@435 | 353 | void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { |
duke@435 | 354 | jobject o = NULL; |
duke@435 | 355 | PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); |
duke@435 | 356 | __ movoop(reg, o); |
duke@435 | 357 | patching_epilog(patch, lir_patch_normal, reg, info); |
duke@435 | 358 | } |
duke@435 | 359 | |
duke@435 | 360 | |
duke@435 | 361 | void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { |
duke@435 | 362 | if (exception->is_valid()) { |
duke@435 | 363 | // preserve exception |
duke@435 | 364 | // note: the monitor_exit runtime call is a leaf routine |
duke@435 | 365 | // and cannot block => no GC can happen |
duke@435 | 366 | // The slow case (MonitorAccessStub) uses the first two stack slots |
duke@435 | 367 | // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] |
never@739 | 368 | __ movptr (Address(rsp, 2*wordSize), exception); |
duke@435 | 369 | } |
duke@435 | 370 | |
duke@435 | 371 | Register obj_reg = obj_opr->as_register(); |
duke@435 | 372 | Register lock_reg = lock_opr->as_register(); |
duke@435 | 373 | |
duke@435 | 374 | // setup registers (lock_reg must be rax, for lock_object) |
duke@435 | 375 | assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); |
duke@435 | 376 | Register hdr = lock_reg; |
duke@435 | 377 | assert(new_hdr == SYNC_header, "wrong register"); |
duke@435 | 378 | lock_reg = new_hdr; |
duke@435 | 379 | // compute pointer to BasicLock |
duke@435 | 380 | Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); |
never@739 | 381 | __ lea(lock_reg, lock_addr); |
duke@435 | 382 | // unlock object |
duke@435 | 383 | MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); |
duke@435 | 384 | // _slow_case_stubs->append(slow_case); |
duke@435 | 385 | // temporary fix: must be created after exceptionhandler, therefore as call stub |
duke@435 | 386 | _slow_case_stubs->append(slow_case); |
duke@435 | 387 | if (UseFastLocking) { |
duke@435 | 388 | // try inlined fast unlocking first, revert to slow locking if it fails |
duke@435 | 389 | // note: lock_reg points to the displaced header since the displaced header offset is 0! |
duke@435 | 390 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 391 | __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); |
duke@435 | 392 | } else { |
duke@435 | 393 | // always do slow unlocking |
duke@435 | 394 | // note: the slow unlocking code could be inlined here, however if we use |
duke@435 | 395 | // slow unlocking, speed doesn't matter anyway and this solution is |
duke@435 | 396 | // simpler and requires less duplicated code - additionally, the |
duke@435 | 397 | // slow unlocking code is the same in either case which simplifies |
duke@435 | 398 | // debugging |
duke@435 | 399 | __ jmp(*slow_case->entry()); |
duke@435 | 400 | } |
duke@435 | 401 | // done |
duke@435 | 402 | __ bind(*slow_case->continuation()); |
duke@435 | 403 | |
duke@435 | 404 | if (exception->is_valid()) { |
duke@435 | 405 | // restore exception |
never@739 | 406 | __ movptr (exception, Address(rsp, 2 * wordSize)); |
duke@435 | 407 | } |
duke@435 | 408 | } |
duke@435 | 409 | |
duke@435 | 410 | // This specifies the rsp decrement needed to build the frame |
duke@435 | 411 | int LIR_Assembler::initial_frame_size_in_bytes() { |
duke@435 | 412 | // if rounding, must let FrameMap know! |
never@739 | 413 | |
never@739 | 414 | // The frame_map records size in slots (32bit word) |
never@739 | 415 | |
never@739 | 416 | // subtract two words to account for return address and link |
never@739 | 417 | return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; |
duke@435 | 418 | } |
duke@435 | 419 | |
duke@435 | 420 | |
twisti@1639 | 421 | int LIR_Assembler::emit_exception_handler() { |
duke@435 | 422 | // if the last instruction is a call (typically to do a throw which |
duke@435 | 423 | // is coming at the end after block reordering) the return address |
duke@435 | 424 | // must still point into the code area in order to avoid assertion |
duke@435 | 425 | // failures when searching for the corresponding bci => add a nop |
duke@435 | 426 | // (was bug 5/14/1999 - gri) |
duke@435 | 427 | __ nop(); |
duke@435 | 428 | |
duke@435 | 429 | // generate code for exception handler |
duke@435 | 430 | address handler_base = __ start_a_stub(exception_handler_size); |
duke@435 | 431 | if (handler_base == NULL) { |
duke@435 | 432 | // not enough space left for the handler |
duke@435 | 433 | bailout("exception handler overflow"); |
twisti@1639 | 434 | return -1; |
duke@435 | 435 | } |
twisti@1639 | 436 | |
duke@435 | 437 | int offset = code_offset(); |
duke@435 | 438 | |
twisti@1730 | 439 | // the exception oop and pc are in rax, and rdx |
duke@435 | 440 | // no other registers need to be preserved, so invalidate them |
twisti@1730 | 441 | __ invalidate_registers(false, true, true, false, true, true); |
duke@435 | 442 | |
duke@435 | 443 | // check that there is really an exception |
duke@435 | 444 | __ verify_not_null_oop(rax); |
duke@435 | 445 | |
twisti@1730 | 446 | // search an exception handler (rax: exception oop, rdx: throwing pc) |
twisti@1730 | 447 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); |
twisti@1730 | 448 | |
twisti@1730 | 449 | __ stop("should not reach here"); |
twisti@1730 | 450 | |
duke@435 | 451 | assert(code_offset() - offset <= exception_handler_size, "overflow"); |
duke@435 | 452 | __ end_a_stub(); |
twisti@1639 | 453 | |
twisti@1639 | 454 | return offset; |
duke@435 | 455 | } |
duke@435 | 456 | |
twisti@1639 | 457 | |
twisti@1639 | 458 | int LIR_Assembler::emit_deopt_handler() { |
duke@435 | 459 | // if the last instruction is a call (typically to do a throw which |
duke@435 | 460 | // is coming at the end after block reordering) the return address |
duke@435 | 461 | // must still point into the code area in order to avoid assertion |
duke@435 | 462 | // failures when searching for the corresponding bci => add a nop |
duke@435 | 463 | // (was bug 5/14/1999 - gri) |
duke@435 | 464 | __ nop(); |
duke@435 | 465 | |
duke@435 | 466 | // generate code for exception handler |
duke@435 | 467 | address handler_base = __ start_a_stub(deopt_handler_size); |
duke@435 | 468 | if (handler_base == NULL) { |
duke@435 | 469 | // not enough space left for the handler |
duke@435 | 470 | bailout("deopt handler overflow"); |
twisti@1639 | 471 | return -1; |
duke@435 | 472 | } |
twisti@1639 | 473 | |
duke@435 | 474 | int offset = code_offset(); |
duke@435 | 475 | InternalAddress here(__ pc()); |
twisti@1730 | 476 | |
duke@435 | 477 | __ pushptr(here.addr()); |
duke@435 | 478 | __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
twisti@1730 | 479 | |
duke@435 | 480 | assert(code_offset() - offset <= deopt_handler_size, "overflow"); |
duke@435 | 481 | __ end_a_stub(); |
duke@435 | 482 | |
twisti@1639 | 483 | return offset; |
duke@435 | 484 | } |
duke@435 | 485 | |
duke@435 | 486 | |
duke@435 | 487 | // This is the fast version of java.lang.String.compare; it has not |
duke@435 | 488 | // OSR-entry and therefore, we generate a slow version for OSR's |
duke@435 | 489 | void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { |
never@739 | 490 | __ movptr (rbx, rcx); // receiver is in rcx |
never@739 | 491 | __ movptr (rax, arg1->as_register()); |
duke@435 | 492 | |
duke@435 | 493 | // Get addresses of first characters from both Strings |
never@739 | 494 | __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
never@739 | 495 | __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); |
never@739 | 496 | __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); |
duke@435 | 497 | |
duke@435 | 498 | |
duke@435 | 499 | // rbx, may be NULL |
duke@435 | 500 | add_debug_info_for_null_check_here(info); |
never@739 | 501 | __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
never@739 | 502 | __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); |
never@739 | 503 | __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); |
duke@435 | 504 | |
duke@435 | 505 | // compute minimum length (in rax) and difference of lengths (on top of stack) |
duke@435 | 506 | if (VM_Version::supports_cmov()) { |
never@739 | 507 | __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
never@739 | 508 | __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); |
never@739 | 509 | __ mov (rcx, rbx); |
never@739 | 510 | __ subptr (rbx, rax); // subtract lengths |
never@739 | 511 | __ push (rbx); // result |
never@739 | 512 | __ cmov (Assembler::lessEqual, rax, rcx); |
duke@435 | 513 | } else { |
duke@435 | 514 | Label L; |
never@739 | 515 | __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
never@739 | 516 | __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); |
never@739 | 517 | __ mov (rax, rbx); |
never@739 | 518 | __ subptr (rbx, rcx); |
never@739 | 519 | __ push (rbx); |
never@739 | 520 | __ jcc (Assembler::lessEqual, L); |
never@739 | 521 | __ mov (rax, rcx); |
duke@435 | 522 | __ bind (L); |
duke@435 | 523 | } |
duke@435 | 524 | // is minimum length 0? |
duke@435 | 525 | Label noLoop, haveResult; |
never@739 | 526 | __ testptr (rax, rax); |
duke@435 | 527 | __ jcc (Assembler::zero, noLoop); |
duke@435 | 528 | |
duke@435 | 529 | // compare first characters |
jrose@1057 | 530 | __ load_unsigned_short(rcx, Address(rdi, 0)); |
jrose@1057 | 531 | __ load_unsigned_short(rbx, Address(rsi, 0)); |
duke@435 | 532 | __ subl(rcx, rbx); |
duke@435 | 533 | __ jcc(Assembler::notZero, haveResult); |
duke@435 | 534 | // starting loop |
duke@435 | 535 | __ decrement(rax); // we already tested index: skip one |
duke@435 | 536 | __ jcc(Assembler::zero, noLoop); |
duke@435 | 537 | |
duke@435 | 538 | // set rsi.edi to the end of the arrays (arrays have same length) |
duke@435 | 539 | // negate the index |
duke@435 | 540 | |
never@739 | 541 | __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
never@739 | 542 | __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
never@739 | 543 | __ negptr(rax); |
duke@435 | 544 | |
duke@435 | 545 | // compare the strings in a loop |
duke@435 | 546 | |
duke@435 | 547 | Label loop; |
duke@435 | 548 | __ align(wordSize); |
duke@435 | 549 | __ bind(loop); |
jrose@1057 | 550 | __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
jrose@1057 | 551 | __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
duke@435 | 552 | __ subl(rcx, rbx); |
duke@435 | 553 | __ jcc(Assembler::notZero, haveResult); |
duke@435 | 554 | __ increment(rax); |
duke@435 | 555 | __ jcc(Assembler::notZero, loop); |
duke@435 | 556 | |
duke@435 | 557 | // strings are equal up to min length |
duke@435 | 558 | |
duke@435 | 559 | __ bind(noLoop); |
never@739 | 560 | __ pop(rax); |
duke@435 | 561 | return_op(LIR_OprFact::illegalOpr); |
duke@435 | 562 | |
duke@435 | 563 | __ bind(haveResult); |
duke@435 | 564 | // leave instruction is going to discard the TOS value |
never@739 | 565 | __ mov (rax, rcx); // result of call is in rax, |
duke@435 | 566 | } |
duke@435 | 567 | |
duke@435 | 568 | |
duke@435 | 569 | void LIR_Assembler::return_op(LIR_Opr result) { |
duke@435 | 570 | assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); |
duke@435 | 571 | if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { |
duke@435 | 572 | assert(result->fpu() == 0, "result must already be on TOS"); |
duke@435 | 573 | } |
duke@435 | 574 | |
duke@435 | 575 | // Pop the stack before the safepoint code |
twisti@1730 | 576 | __ remove_frame(initial_frame_size_in_bytes()); |
duke@435 | 577 | |
duke@435 | 578 | bool result_is_oop = result->is_valid() ? result->is_oop() : false; |
duke@435 | 579 | |
duke@435 | 580 | // Note: we do not need to round double result; float result has the right precision |
duke@435 | 581 | // the poll sets the condition code, but no data registers |
duke@435 | 582 | AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), |
duke@435 | 583 | relocInfo::poll_return_type); |
never@739 | 584 | |
never@739 | 585 | // NOTE: the requires that the polling page be reachable else the reloc |
never@739 | 586 | // goes to the movq that loads the address and not the faulting instruction |
never@739 | 587 | // which breaks the signal handler code |
never@739 | 588 | |
duke@435 | 589 | __ test32(rax, polling_page); |
duke@435 | 590 | |
duke@435 | 591 | __ ret(0); |
duke@435 | 592 | } |
duke@435 | 593 | |
duke@435 | 594 | |
duke@435 | 595 | int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { |
duke@435 | 596 | AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), |
duke@435 | 597 | relocInfo::poll_type); |
duke@435 | 598 | |
duke@435 | 599 | if (info != NULL) { |
duke@435 | 600 | add_debug_info_for_branch(info); |
duke@435 | 601 | } else { |
duke@435 | 602 | ShouldNotReachHere(); |
duke@435 | 603 | } |
duke@435 | 604 | |
duke@435 | 605 | int offset = __ offset(); |
never@739 | 606 | |
never@739 | 607 | // NOTE: the requires that the polling page be reachable else the reloc |
never@739 | 608 | // goes to the movq that loads the address and not the faulting instruction |
never@739 | 609 | // which breaks the signal handler code |
never@739 | 610 | |
duke@435 | 611 | __ test32(rax, polling_page); |
duke@435 | 612 | return offset; |
duke@435 | 613 | } |
duke@435 | 614 | |
duke@435 | 615 | |
duke@435 | 616 | void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { |
never@739 | 617 | if (from_reg != to_reg) __ mov(to_reg, from_reg); |
duke@435 | 618 | } |
duke@435 | 619 | |
duke@435 | 620 | void LIR_Assembler::swap_reg(Register a, Register b) { |
never@739 | 621 | __ xchgptr(a, b); |
duke@435 | 622 | } |
duke@435 | 623 | |
duke@435 | 624 | |
duke@435 | 625 | void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { |
duke@435 | 626 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 627 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 628 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 629 | |
duke@435 | 630 | switch (c->type()) { |
roland@1732 | 631 | case T_INT: |
roland@1732 | 632 | case T_ADDRESS: { |
duke@435 | 633 | assert(patch_code == lir_patch_none, "no patching handled here"); |
duke@435 | 634 | __ movl(dest->as_register(), c->as_jint()); |
duke@435 | 635 | break; |
duke@435 | 636 | } |
duke@435 | 637 | |
duke@435 | 638 | case T_LONG: { |
duke@435 | 639 | assert(patch_code == lir_patch_none, "no patching handled here"); |
never@739 | 640 | #ifdef _LP64 |
never@739 | 641 | __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); |
never@739 | 642 | #else |
never@739 | 643 | __ movptr(dest->as_register_lo(), c->as_jint_lo()); |
never@739 | 644 | __ movptr(dest->as_register_hi(), c->as_jint_hi()); |
never@739 | 645 | #endif // _LP64 |
duke@435 | 646 | break; |
duke@435 | 647 | } |
duke@435 | 648 | |
duke@435 | 649 | case T_OBJECT: { |
duke@435 | 650 | if (patch_code != lir_patch_none) { |
duke@435 | 651 | jobject2reg_with_patching(dest->as_register(), info); |
duke@435 | 652 | } else { |
duke@435 | 653 | __ movoop(dest->as_register(), c->as_jobject()); |
duke@435 | 654 | } |
duke@435 | 655 | break; |
duke@435 | 656 | } |
duke@435 | 657 | |
duke@435 | 658 | case T_FLOAT: { |
duke@435 | 659 | if (dest->is_single_xmm()) { |
duke@435 | 660 | if (c->is_zero_float()) { |
duke@435 | 661 | __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); |
duke@435 | 662 | } else { |
duke@435 | 663 | __ movflt(dest->as_xmm_float_reg(), |
duke@435 | 664 | InternalAddress(float_constant(c->as_jfloat()))); |
duke@435 | 665 | } |
duke@435 | 666 | } else { |
duke@435 | 667 | assert(dest->is_single_fpu(), "must be"); |
duke@435 | 668 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 669 | if (c->is_zero_float()) { |
duke@435 | 670 | __ fldz(); |
duke@435 | 671 | } else if (c->is_one_float()) { |
duke@435 | 672 | __ fld1(); |
duke@435 | 673 | } else { |
duke@435 | 674 | __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); |
duke@435 | 675 | } |
duke@435 | 676 | } |
duke@435 | 677 | break; |
duke@435 | 678 | } |
duke@435 | 679 | |
duke@435 | 680 | case T_DOUBLE: { |
duke@435 | 681 | if (dest->is_double_xmm()) { |
duke@435 | 682 | if (c->is_zero_double()) { |
duke@435 | 683 | __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); |
duke@435 | 684 | } else { |
duke@435 | 685 | __ movdbl(dest->as_xmm_double_reg(), |
duke@435 | 686 | InternalAddress(double_constant(c->as_jdouble()))); |
duke@435 | 687 | } |
duke@435 | 688 | } else { |
duke@435 | 689 | assert(dest->is_double_fpu(), "must be"); |
duke@435 | 690 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 691 | if (c->is_zero_double()) { |
duke@435 | 692 | __ fldz(); |
duke@435 | 693 | } else if (c->is_one_double()) { |
duke@435 | 694 | __ fld1(); |
duke@435 | 695 | } else { |
duke@435 | 696 | __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); |
duke@435 | 697 | } |
duke@435 | 698 | } |
duke@435 | 699 | break; |
duke@435 | 700 | } |
duke@435 | 701 | |
duke@435 | 702 | default: |
duke@435 | 703 | ShouldNotReachHere(); |
duke@435 | 704 | } |
duke@435 | 705 | } |
duke@435 | 706 | |
duke@435 | 707 | void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { |
duke@435 | 708 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 709 | assert(dest->is_stack(), "should not call otherwise"); |
duke@435 | 710 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 711 | |
duke@435 | 712 | switch (c->type()) { |
duke@435 | 713 | case T_INT: // fall through |
duke@435 | 714 | case T_FLOAT: |
roland@1732 | 715 | case T_ADDRESS: |
duke@435 | 716 | __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
duke@435 | 717 | break; |
duke@435 | 718 | |
duke@435 | 719 | case T_OBJECT: |
duke@435 | 720 | __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); |
duke@435 | 721 | break; |
duke@435 | 722 | |
duke@435 | 723 | case T_LONG: // fall through |
duke@435 | 724 | case T_DOUBLE: |
never@739 | 725 | #ifdef _LP64 |
never@739 | 726 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 727 | lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); |
never@739 | 728 | #else |
never@739 | 729 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 730 | lo_word_offset_in_bytes), c->as_jint_lo_bits()); |
never@739 | 731 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 732 | hi_word_offset_in_bytes), c->as_jint_hi_bits()); |
never@739 | 733 | #endif // _LP64 |
duke@435 | 734 | break; |
duke@435 | 735 | |
duke@435 | 736 | default: |
duke@435 | 737 | ShouldNotReachHere(); |
duke@435 | 738 | } |
duke@435 | 739 | } |
duke@435 | 740 | |
duke@435 | 741 | void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { |
duke@435 | 742 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 743 | assert(dest->is_address(), "should not call otherwise"); |
duke@435 | 744 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 745 | LIR_Address* addr = dest->as_address_ptr(); |
duke@435 | 746 | |
never@739 | 747 | int null_check_here = code_offset(); |
duke@435 | 748 | switch (type) { |
duke@435 | 749 | case T_INT: // fall through |
duke@435 | 750 | case T_FLOAT: |
roland@1732 | 751 | case T_ADDRESS: |
duke@435 | 752 | __ movl(as_Address(addr), c->as_jint_bits()); |
duke@435 | 753 | break; |
duke@435 | 754 | |
duke@435 | 755 | case T_OBJECT: // fall through |
duke@435 | 756 | case T_ARRAY: |
duke@435 | 757 | if (c->as_jobject() == NULL) { |
xlu@947 | 758 | __ movptr(as_Address(addr), NULL_WORD); |
duke@435 | 759 | } else { |
never@739 | 760 | if (is_literal_address(addr)) { |
never@739 | 761 | ShouldNotReachHere(); |
never@739 | 762 | __ movoop(as_Address(addr, noreg), c->as_jobject()); |
never@739 | 763 | } else { |
roland@1495 | 764 | #ifdef _LP64 |
roland@1495 | 765 | __ movoop(rscratch1, c->as_jobject()); |
roland@1495 | 766 | null_check_here = code_offset(); |
roland@1495 | 767 | __ movptr(as_Address_lo(addr), rscratch1); |
roland@1495 | 768 | #else |
never@739 | 769 | __ movoop(as_Address(addr), c->as_jobject()); |
roland@1495 | 770 | #endif |
never@739 | 771 | } |
duke@435 | 772 | } |
duke@435 | 773 | break; |
duke@435 | 774 | |
duke@435 | 775 | case T_LONG: // fall through |
duke@435 | 776 | case T_DOUBLE: |
never@739 | 777 | #ifdef _LP64 |
never@739 | 778 | if (is_literal_address(addr)) { |
never@739 | 779 | ShouldNotReachHere(); |
never@739 | 780 | __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); |
never@739 | 781 | } else { |
never@739 | 782 | __ movptr(r10, (intptr_t)c->as_jlong_bits()); |
never@739 | 783 | null_check_here = code_offset(); |
never@739 | 784 | __ movptr(as_Address_lo(addr), r10); |
never@739 | 785 | } |
never@739 | 786 | #else |
never@739 | 787 | // Always reachable in 32bit so this doesn't produce useless move literal |
never@739 | 788 | __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); |
never@739 | 789 | __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); |
never@739 | 790 | #endif // _LP64 |
duke@435 | 791 | break; |
duke@435 | 792 | |
duke@435 | 793 | case T_BOOLEAN: // fall through |
duke@435 | 794 | case T_BYTE: |
duke@435 | 795 | __ movb(as_Address(addr), c->as_jint() & 0xFF); |
duke@435 | 796 | break; |
duke@435 | 797 | |
duke@435 | 798 | case T_CHAR: // fall through |
duke@435 | 799 | case T_SHORT: |
duke@435 | 800 | __ movw(as_Address(addr), c->as_jint() & 0xFFFF); |
duke@435 | 801 | break; |
duke@435 | 802 | |
duke@435 | 803 | default: |
duke@435 | 804 | ShouldNotReachHere(); |
duke@435 | 805 | }; |
never@739 | 806 | |
never@739 | 807 | if (info != NULL) { |
never@739 | 808 | add_debug_info_for_null_check(null_check_here, info); |
never@739 | 809 | } |
duke@435 | 810 | } |
duke@435 | 811 | |
duke@435 | 812 | |
duke@435 | 813 | void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { |
duke@435 | 814 | assert(src->is_register(), "should not call otherwise"); |
duke@435 | 815 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 816 | |
duke@435 | 817 | // move between cpu-registers |
duke@435 | 818 | if (dest->is_single_cpu()) { |
never@739 | 819 | #ifdef _LP64 |
never@739 | 820 | if (src->type() == T_LONG) { |
never@739 | 821 | // Can do LONG -> OBJECT |
never@739 | 822 | move_regs(src->as_register_lo(), dest->as_register()); |
never@739 | 823 | return; |
never@739 | 824 | } |
never@739 | 825 | #endif |
duke@435 | 826 | assert(src->is_single_cpu(), "must match"); |
duke@435 | 827 | if (src->type() == T_OBJECT) { |
duke@435 | 828 | __ verify_oop(src->as_register()); |
duke@435 | 829 | } |
duke@435 | 830 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 831 | |
duke@435 | 832 | } else if (dest->is_double_cpu()) { |
never@739 | 833 | #ifdef _LP64 |
never@739 | 834 | if (src->type() == T_OBJECT || src->type() == T_ARRAY) { |
never@739 | 835 | // Surprising to me but we can see move of a long to t_object |
never@739 | 836 | __ verify_oop(src->as_register()); |
never@739 | 837 | move_regs(src->as_register(), dest->as_register_lo()); |
never@739 | 838 | return; |
never@739 | 839 | } |
never@739 | 840 | #endif |
duke@435 | 841 | assert(src->is_double_cpu(), "must match"); |
duke@435 | 842 | Register f_lo = src->as_register_lo(); |
duke@435 | 843 | Register f_hi = src->as_register_hi(); |
duke@435 | 844 | Register t_lo = dest->as_register_lo(); |
duke@435 | 845 | Register t_hi = dest->as_register_hi(); |
never@739 | 846 | #ifdef _LP64 |
never@739 | 847 | assert(f_hi == f_lo, "must be same"); |
never@739 | 848 | assert(t_hi == t_lo, "must be same"); |
never@739 | 849 | move_regs(f_lo, t_lo); |
never@739 | 850 | #else |
duke@435 | 851 | assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
duke@435 | 852 | |
never@739 | 853 | |
duke@435 | 854 | if (f_lo == t_hi && f_hi == t_lo) { |
duke@435 | 855 | swap_reg(f_lo, f_hi); |
duke@435 | 856 | } else if (f_hi == t_lo) { |
duke@435 | 857 | assert(f_lo != t_hi, "overwriting register"); |
duke@435 | 858 | move_regs(f_hi, t_hi); |
duke@435 | 859 | move_regs(f_lo, t_lo); |
duke@435 | 860 | } else { |
duke@435 | 861 | assert(f_hi != t_lo, "overwriting register"); |
duke@435 | 862 | move_regs(f_lo, t_lo); |
duke@435 | 863 | move_regs(f_hi, t_hi); |
duke@435 | 864 | } |
never@739 | 865 | #endif // LP64 |
duke@435 | 866 | |
duke@435 | 867 | // special moves from fpu-register to xmm-register |
duke@435 | 868 | // necessary for method results |
duke@435 | 869 | } else if (src->is_single_xmm() && !dest->is_single_xmm()) { |
duke@435 | 870 | __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); |
duke@435 | 871 | __ fld_s(Address(rsp, 0)); |
duke@435 | 872 | } else if (src->is_double_xmm() && !dest->is_double_xmm()) { |
duke@435 | 873 | __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); |
duke@435 | 874 | __ fld_d(Address(rsp, 0)); |
duke@435 | 875 | } else if (dest->is_single_xmm() && !src->is_single_xmm()) { |
duke@435 | 876 | __ fstp_s(Address(rsp, 0)); |
duke@435 | 877 | __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); |
duke@435 | 878 | } else if (dest->is_double_xmm() && !src->is_double_xmm()) { |
duke@435 | 879 | __ fstp_d(Address(rsp, 0)); |
duke@435 | 880 | __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); |
duke@435 | 881 | |
duke@435 | 882 | // move between xmm-registers |
duke@435 | 883 | } else if (dest->is_single_xmm()) { |
duke@435 | 884 | assert(src->is_single_xmm(), "must match"); |
duke@435 | 885 | __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); |
duke@435 | 886 | } else if (dest->is_double_xmm()) { |
duke@435 | 887 | assert(src->is_double_xmm(), "must match"); |
duke@435 | 888 | __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); |
duke@435 | 889 | |
duke@435 | 890 | // move between fpu-registers (no instruction necessary because of fpu-stack) |
duke@435 | 891 | } else if (dest->is_single_fpu() || dest->is_double_fpu()) { |
duke@435 | 892 | assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); |
duke@435 | 893 | assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); |
duke@435 | 894 | } else { |
duke@435 | 895 | ShouldNotReachHere(); |
duke@435 | 896 | } |
duke@435 | 897 | } |
duke@435 | 898 | |
duke@435 | 899 | void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { |
duke@435 | 900 | assert(src->is_register(), "should not call otherwise"); |
duke@435 | 901 | assert(dest->is_stack(), "should not call otherwise"); |
duke@435 | 902 | |
duke@435 | 903 | if (src->is_single_cpu()) { |
duke@435 | 904 | Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 905 | if (type == T_OBJECT || type == T_ARRAY) { |
duke@435 | 906 | __ verify_oop(src->as_register()); |
never@739 | 907 | __ movptr (dst, src->as_register()); |
never@739 | 908 | } else { |
never@739 | 909 | __ movl (dst, src->as_register()); |
duke@435 | 910 | } |
duke@435 | 911 | |
duke@435 | 912 | } else if (src->is_double_cpu()) { |
duke@435 | 913 | Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); |
duke@435 | 914 | Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); |
never@739 | 915 | __ movptr (dstLO, src->as_register_lo()); |
never@739 | 916 | NOT_LP64(__ movptr (dstHI, src->as_register_hi())); |
duke@435 | 917 | |
duke@435 | 918 | } else if (src->is_single_xmm()) { |
duke@435 | 919 | Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 920 | __ movflt(dst_addr, src->as_xmm_float_reg()); |
duke@435 | 921 | |
duke@435 | 922 | } else if (src->is_double_xmm()) { |
duke@435 | 923 | Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
duke@435 | 924 | __ movdbl(dst_addr, src->as_xmm_double_reg()); |
duke@435 | 925 | |
duke@435 | 926 | } else if (src->is_single_fpu()) { |
duke@435 | 927 | assert(src->fpu_regnr() == 0, "argument must be on TOS"); |
duke@435 | 928 | Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 929 | if (pop_fpu_stack) __ fstp_s (dst_addr); |
duke@435 | 930 | else __ fst_s (dst_addr); |
duke@435 | 931 | |
duke@435 | 932 | } else if (src->is_double_fpu()) { |
duke@435 | 933 | assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); |
duke@435 | 934 | Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
duke@435 | 935 | if (pop_fpu_stack) __ fstp_d (dst_addr); |
duke@435 | 936 | else __ fst_d (dst_addr); |
duke@435 | 937 | |
duke@435 | 938 | } else { |
duke@435 | 939 | ShouldNotReachHere(); |
duke@435 | 940 | } |
duke@435 | 941 | } |
duke@435 | 942 | |
duke@435 | 943 | |
duke@435 | 944 | void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { |
duke@435 | 945 | LIR_Address* to_addr = dest->as_address_ptr(); |
duke@435 | 946 | PatchingStub* patch = NULL; |
duke@435 | 947 | |
duke@435 | 948 | if (type == T_ARRAY || type == T_OBJECT) { |
duke@435 | 949 | __ verify_oop(src->as_register()); |
duke@435 | 950 | } |
duke@435 | 951 | if (patch_code != lir_patch_none) { |
duke@435 | 952 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
never@739 | 953 | Address toa = as_Address(to_addr); |
never@739 | 954 | assert(toa.disp() != 0, "must have"); |
duke@435 | 955 | } |
duke@435 | 956 | if (info != NULL) { |
duke@435 | 957 | add_debug_info_for_null_check_here(info); |
duke@435 | 958 | } |
duke@435 | 959 | |
duke@435 | 960 | switch (type) { |
duke@435 | 961 | case T_FLOAT: { |
duke@435 | 962 | if (src->is_single_xmm()) { |
duke@435 | 963 | __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); |
duke@435 | 964 | } else { |
duke@435 | 965 | assert(src->is_single_fpu(), "must be"); |
duke@435 | 966 | assert(src->fpu_regnr() == 0, "argument must be on TOS"); |
duke@435 | 967 | if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); |
duke@435 | 968 | else __ fst_s (as_Address(to_addr)); |
duke@435 | 969 | } |
duke@435 | 970 | break; |
duke@435 | 971 | } |
duke@435 | 972 | |
duke@435 | 973 | case T_DOUBLE: { |
duke@435 | 974 | if (src->is_double_xmm()) { |
duke@435 | 975 | __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); |
duke@435 | 976 | } else { |
duke@435 | 977 | assert(src->is_double_fpu(), "must be"); |
duke@435 | 978 | assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); |
duke@435 | 979 | if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); |
duke@435 | 980 | else __ fst_d (as_Address(to_addr)); |
duke@435 | 981 | } |
duke@435 | 982 | break; |
duke@435 | 983 | } |
duke@435 | 984 | |
duke@435 | 985 | case T_ADDRESS: // fall through |
duke@435 | 986 | case T_ARRAY: // fall through |
duke@435 | 987 | case T_OBJECT: // fall through |
never@739 | 988 | #ifdef _LP64 |
never@739 | 989 | __ movptr(as_Address(to_addr), src->as_register()); |
never@739 | 990 | break; |
never@739 | 991 | #endif // _LP64 |
duke@435 | 992 | case T_INT: |
duke@435 | 993 | __ movl(as_Address(to_addr), src->as_register()); |
duke@435 | 994 | break; |
duke@435 | 995 | |
duke@435 | 996 | case T_LONG: { |
duke@435 | 997 | Register from_lo = src->as_register_lo(); |
duke@435 | 998 | Register from_hi = src->as_register_hi(); |
never@739 | 999 | #ifdef _LP64 |
never@739 | 1000 | __ movptr(as_Address_lo(to_addr), from_lo); |
never@739 | 1001 | #else |
duke@435 | 1002 | Register base = to_addr->base()->as_register(); |
duke@435 | 1003 | Register index = noreg; |
duke@435 | 1004 | if (to_addr->index()->is_register()) { |
duke@435 | 1005 | index = to_addr->index()->as_register(); |
duke@435 | 1006 | } |
duke@435 | 1007 | if (base == from_lo || index == from_lo) { |
duke@435 | 1008 | assert(base != from_hi, "can't be"); |
duke@435 | 1009 | assert(index == noreg || (index != base && index != from_hi), "can't handle this"); |
duke@435 | 1010 | __ movl(as_Address_hi(to_addr), from_hi); |
duke@435 | 1011 | if (patch != NULL) { |
duke@435 | 1012 | patching_epilog(patch, lir_patch_high, base, info); |
duke@435 | 1013 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1014 | patch_code = lir_patch_low; |
duke@435 | 1015 | } |
duke@435 | 1016 | __ movl(as_Address_lo(to_addr), from_lo); |
duke@435 | 1017 | } else { |
duke@435 | 1018 | assert(index == noreg || (index != base && index != from_lo), "can't handle this"); |
duke@435 | 1019 | __ movl(as_Address_lo(to_addr), from_lo); |
duke@435 | 1020 | if (patch != NULL) { |
duke@435 | 1021 | patching_epilog(patch, lir_patch_low, base, info); |
duke@435 | 1022 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1023 | patch_code = lir_patch_high; |
duke@435 | 1024 | } |
duke@435 | 1025 | __ movl(as_Address_hi(to_addr), from_hi); |
duke@435 | 1026 | } |
never@739 | 1027 | #endif // _LP64 |
duke@435 | 1028 | break; |
duke@435 | 1029 | } |
duke@435 | 1030 | |
duke@435 | 1031 | case T_BYTE: // fall through |
duke@435 | 1032 | case T_BOOLEAN: { |
duke@435 | 1033 | Register src_reg = src->as_register(); |
duke@435 | 1034 | Address dst_addr = as_Address(to_addr); |
duke@435 | 1035 | assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1036 | __ movb(dst_addr, src_reg); |
duke@435 | 1037 | break; |
duke@435 | 1038 | } |
duke@435 | 1039 | |
duke@435 | 1040 | case T_CHAR: // fall through |
duke@435 | 1041 | case T_SHORT: |
duke@435 | 1042 | __ movw(as_Address(to_addr), src->as_register()); |
duke@435 | 1043 | break; |
duke@435 | 1044 | |
duke@435 | 1045 | default: |
duke@435 | 1046 | ShouldNotReachHere(); |
duke@435 | 1047 | } |
duke@435 | 1048 | |
duke@435 | 1049 | if (patch_code != lir_patch_none) { |
duke@435 | 1050 | patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); |
duke@435 | 1051 | } |
duke@435 | 1052 | } |
duke@435 | 1053 | |
duke@435 | 1054 | |
duke@435 | 1055 | void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { |
duke@435 | 1056 | assert(src->is_stack(), "should not call otherwise"); |
duke@435 | 1057 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 1058 | |
duke@435 | 1059 | if (dest->is_single_cpu()) { |
duke@435 | 1060 | if (type == T_ARRAY || type == T_OBJECT) { |
never@739 | 1061 | __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
duke@435 | 1062 | __ verify_oop(dest->as_register()); |
never@739 | 1063 | } else { |
never@739 | 1064 | __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
duke@435 | 1065 | } |
duke@435 | 1066 | |
duke@435 | 1067 | } else if (dest->is_double_cpu()) { |
duke@435 | 1068 | Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); |
duke@435 | 1069 | Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); |
never@739 | 1070 | __ movptr(dest->as_register_lo(), src_addr_LO); |
never@739 | 1071 | NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); |
duke@435 | 1072 | |
duke@435 | 1073 | } else if (dest->is_single_xmm()) { |
duke@435 | 1074 | Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1075 | __ movflt(dest->as_xmm_float_reg(), src_addr); |
duke@435 | 1076 | |
duke@435 | 1077 | } else if (dest->is_double_xmm()) { |
duke@435 | 1078 | Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); |
duke@435 | 1079 | __ movdbl(dest->as_xmm_double_reg(), src_addr); |
duke@435 | 1080 | |
duke@435 | 1081 | } else if (dest->is_single_fpu()) { |
duke@435 | 1082 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 1083 | Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1084 | __ fld_s(src_addr); |
duke@435 | 1085 | |
duke@435 | 1086 | } else if (dest->is_double_fpu()) { |
duke@435 | 1087 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 1088 | Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); |
duke@435 | 1089 | __ fld_d(src_addr); |
duke@435 | 1090 | |
duke@435 | 1091 | } else { |
duke@435 | 1092 | ShouldNotReachHere(); |
duke@435 | 1093 | } |
duke@435 | 1094 | } |
duke@435 | 1095 | |
duke@435 | 1096 | |
duke@435 | 1097 | void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { |
duke@435 | 1098 | if (src->is_single_stack()) { |
never@739 | 1099 | if (type == T_OBJECT || type == T_ARRAY) { |
never@739 | 1100 | __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); |
never@739 | 1101 | __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); |
never@739 | 1102 | } else { |
roland@1495 | 1103 | #ifndef _LP64 |
never@739 | 1104 | __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
never@739 | 1105 | __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); |
roland@1495 | 1106 | #else |
roland@1495 | 1107 | //no pushl on 64bits |
roland@1495 | 1108 | __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); |
roland@1495 | 1109 | __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); |
roland@1495 | 1110 | #endif |
never@739 | 1111 | } |
duke@435 | 1112 | |
duke@435 | 1113 | } else if (src->is_double_stack()) { |
never@739 | 1114 | #ifdef _LP64 |
never@739 | 1115 | __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); |
never@739 | 1116 | __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); |
never@739 | 1117 | #else |
duke@435 | 1118 | __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
never@739 | 1119 | // push and pop the part at src + wordSize, adding wordSize for the previous push |
never@756 | 1120 | __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
never@756 | 1121 | __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
duke@435 | 1122 | __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
never@739 | 1123 | #endif // _LP64 |
duke@435 | 1124 | |
duke@435 | 1125 | } else { |
duke@435 | 1126 | ShouldNotReachHere(); |
duke@435 | 1127 | } |
duke@435 | 1128 | } |
duke@435 | 1129 | |
duke@435 | 1130 | |
duke@435 | 1131 | void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { |
duke@435 | 1132 | assert(src->is_address(), "should not call otherwise"); |
duke@435 | 1133 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 1134 | |
duke@435 | 1135 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1136 | Address from_addr = as_Address(addr); |
duke@435 | 1137 | |
duke@435 | 1138 | switch (type) { |
duke@435 | 1139 | case T_BOOLEAN: // fall through |
duke@435 | 1140 | case T_BYTE: // fall through |
duke@435 | 1141 | case T_CHAR: // fall through |
duke@435 | 1142 | case T_SHORT: |
duke@435 | 1143 | if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { |
duke@435 | 1144 | // on pre P6 processors we may get partial register stalls |
duke@435 | 1145 | // so blow away the value of to_rinfo before loading a |
duke@435 | 1146 | // partial word into it. Do it here so that it precedes |
duke@435 | 1147 | // the potential patch point below. |
never@739 | 1148 | __ xorptr(dest->as_register(), dest->as_register()); |
duke@435 | 1149 | } |
duke@435 | 1150 | break; |
duke@435 | 1151 | } |
duke@435 | 1152 | |
duke@435 | 1153 | PatchingStub* patch = NULL; |
duke@435 | 1154 | if (patch_code != lir_patch_none) { |
duke@435 | 1155 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
never@739 | 1156 | assert(from_addr.disp() != 0, "must have"); |
duke@435 | 1157 | } |
duke@435 | 1158 | if (info != NULL) { |
duke@435 | 1159 | add_debug_info_for_null_check_here(info); |
duke@435 | 1160 | } |
duke@435 | 1161 | |
duke@435 | 1162 | switch (type) { |
duke@435 | 1163 | case T_FLOAT: { |
duke@435 | 1164 | if (dest->is_single_xmm()) { |
duke@435 | 1165 | __ movflt(dest->as_xmm_float_reg(), from_addr); |
duke@435 | 1166 | } else { |
duke@435 | 1167 | assert(dest->is_single_fpu(), "must be"); |
duke@435 | 1168 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 1169 | __ fld_s(from_addr); |
duke@435 | 1170 | } |
duke@435 | 1171 | break; |
duke@435 | 1172 | } |
duke@435 | 1173 | |
duke@435 | 1174 | case T_DOUBLE: { |
duke@435 | 1175 | if (dest->is_double_xmm()) { |
duke@435 | 1176 | __ movdbl(dest->as_xmm_double_reg(), from_addr); |
duke@435 | 1177 | } else { |
duke@435 | 1178 | assert(dest->is_double_fpu(), "must be"); |
duke@435 | 1179 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 1180 | __ fld_d(from_addr); |
duke@435 | 1181 | } |
duke@435 | 1182 | break; |
duke@435 | 1183 | } |
duke@435 | 1184 | |
duke@435 | 1185 | case T_ADDRESS: // fall through |
duke@435 | 1186 | case T_OBJECT: // fall through |
duke@435 | 1187 | case T_ARRAY: // fall through |
never@739 | 1188 | #ifdef _LP64 |
never@739 | 1189 | __ movptr(dest->as_register(), from_addr); |
never@739 | 1190 | break; |
never@739 | 1191 | #endif // _L64 |
duke@435 | 1192 | case T_INT: |
never@739 | 1193 | // %%% could this be a movl? this is safer but longer instruction |
never@739 | 1194 | __ movl2ptr(dest->as_register(), from_addr); |
duke@435 | 1195 | break; |
duke@435 | 1196 | |
duke@435 | 1197 | case T_LONG: { |
duke@435 | 1198 | Register to_lo = dest->as_register_lo(); |
duke@435 | 1199 | Register to_hi = dest->as_register_hi(); |
never@739 | 1200 | #ifdef _LP64 |
never@739 | 1201 | __ movptr(to_lo, as_Address_lo(addr)); |
never@739 | 1202 | #else |
duke@435 | 1203 | Register base = addr->base()->as_register(); |
duke@435 | 1204 | Register index = noreg; |
duke@435 | 1205 | if (addr->index()->is_register()) { |
duke@435 | 1206 | index = addr->index()->as_register(); |
duke@435 | 1207 | } |
duke@435 | 1208 | if ((base == to_lo && index == to_hi) || |
duke@435 | 1209 | (base == to_hi && index == to_lo)) { |
duke@435 | 1210 | // addresses with 2 registers are only formed as a result of |
duke@435 | 1211 | // array access so this code will never have to deal with |
duke@435 | 1212 | // patches or null checks. |
duke@435 | 1213 | assert(info == NULL && patch == NULL, "must be"); |
never@739 | 1214 | __ lea(to_hi, as_Address(addr)); |
duke@435 | 1215 | __ movl(to_lo, Address(to_hi, 0)); |
duke@435 | 1216 | __ movl(to_hi, Address(to_hi, BytesPerWord)); |
duke@435 | 1217 | } else if (base == to_lo || index == to_lo) { |
duke@435 | 1218 | assert(base != to_hi, "can't be"); |
duke@435 | 1219 | assert(index == noreg || (index != base && index != to_hi), "can't handle this"); |
duke@435 | 1220 | __ movl(to_hi, as_Address_hi(addr)); |
duke@435 | 1221 | if (patch != NULL) { |
duke@435 | 1222 | patching_epilog(patch, lir_patch_high, base, info); |
duke@435 | 1223 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1224 | patch_code = lir_patch_low; |
duke@435 | 1225 | } |
duke@435 | 1226 | __ movl(to_lo, as_Address_lo(addr)); |
duke@435 | 1227 | } else { |
duke@435 | 1228 | assert(index == noreg || (index != base && index != to_lo), "can't handle this"); |
duke@435 | 1229 | __ movl(to_lo, as_Address_lo(addr)); |
duke@435 | 1230 | if (patch != NULL) { |
duke@435 | 1231 | patching_epilog(patch, lir_patch_low, base, info); |
duke@435 | 1232 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1233 | patch_code = lir_patch_high; |
duke@435 | 1234 | } |
duke@435 | 1235 | __ movl(to_hi, as_Address_hi(addr)); |
duke@435 | 1236 | } |
never@739 | 1237 | #endif // _LP64 |
duke@435 | 1238 | break; |
duke@435 | 1239 | } |
duke@435 | 1240 | |
duke@435 | 1241 | case T_BOOLEAN: // fall through |
duke@435 | 1242 | case T_BYTE: { |
duke@435 | 1243 | Register dest_reg = dest->as_register(); |
duke@435 | 1244 | assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1245 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1246 | __ movsbl(dest_reg, from_addr); |
duke@435 | 1247 | } else { |
duke@435 | 1248 | __ movb(dest_reg, from_addr); |
duke@435 | 1249 | __ shll(dest_reg, 24); |
duke@435 | 1250 | __ sarl(dest_reg, 24); |
duke@435 | 1251 | } |
never@739 | 1252 | // These are unsigned so the zero extension on 64bit is just what we need |
duke@435 | 1253 | break; |
duke@435 | 1254 | } |
duke@435 | 1255 | |
duke@435 | 1256 | case T_CHAR: { |
duke@435 | 1257 | Register dest_reg = dest->as_register(); |
duke@435 | 1258 | assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1259 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1260 | __ movzwl(dest_reg, from_addr); |
duke@435 | 1261 | } else { |
duke@435 | 1262 | __ movw(dest_reg, from_addr); |
duke@435 | 1263 | } |
never@739 | 1264 | // This is unsigned so the zero extension on 64bit is just what we need |
never@739 | 1265 | // __ movl2ptr(dest_reg, dest_reg); |
duke@435 | 1266 | break; |
duke@435 | 1267 | } |
duke@435 | 1268 | |
duke@435 | 1269 | case T_SHORT: { |
duke@435 | 1270 | Register dest_reg = dest->as_register(); |
duke@435 | 1271 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1272 | __ movswl(dest_reg, from_addr); |
duke@435 | 1273 | } else { |
duke@435 | 1274 | __ movw(dest_reg, from_addr); |
duke@435 | 1275 | __ shll(dest_reg, 16); |
duke@435 | 1276 | __ sarl(dest_reg, 16); |
duke@435 | 1277 | } |
never@739 | 1278 | // Might not be needed in 64bit but certainly doesn't hurt (except for code size) |
never@739 | 1279 | __ movl2ptr(dest_reg, dest_reg); |
duke@435 | 1280 | break; |
duke@435 | 1281 | } |
duke@435 | 1282 | |
duke@435 | 1283 | default: |
duke@435 | 1284 | ShouldNotReachHere(); |
duke@435 | 1285 | } |
duke@435 | 1286 | |
duke@435 | 1287 | if (patch != NULL) { |
duke@435 | 1288 | patching_epilog(patch, patch_code, addr->base()->as_register(), info); |
duke@435 | 1289 | } |
duke@435 | 1290 | |
duke@435 | 1291 | if (type == T_ARRAY || type == T_OBJECT) { |
duke@435 | 1292 | __ verify_oop(dest->as_register()); |
duke@435 | 1293 | } |
duke@435 | 1294 | } |
duke@435 | 1295 | |
duke@435 | 1296 | |
duke@435 | 1297 | void LIR_Assembler::prefetchr(LIR_Opr src) { |
duke@435 | 1298 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1299 | Address from_addr = as_Address(addr); |
duke@435 | 1300 | |
duke@435 | 1301 | if (VM_Version::supports_sse()) { |
duke@435 | 1302 | switch (ReadPrefetchInstr) { |
duke@435 | 1303 | case 0: |
duke@435 | 1304 | __ prefetchnta(from_addr); break; |
duke@435 | 1305 | case 1: |
duke@435 | 1306 | __ prefetcht0(from_addr); break; |
duke@435 | 1307 | case 2: |
duke@435 | 1308 | __ prefetcht2(from_addr); break; |
duke@435 | 1309 | default: |
duke@435 | 1310 | ShouldNotReachHere(); break; |
duke@435 | 1311 | } |
duke@435 | 1312 | } else if (VM_Version::supports_3dnow()) { |
duke@435 | 1313 | __ prefetchr(from_addr); |
duke@435 | 1314 | } |
duke@435 | 1315 | } |
duke@435 | 1316 | |
duke@435 | 1317 | |
duke@435 | 1318 | void LIR_Assembler::prefetchw(LIR_Opr src) { |
duke@435 | 1319 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1320 | Address from_addr = as_Address(addr); |
duke@435 | 1321 | |
duke@435 | 1322 | if (VM_Version::supports_sse()) { |
duke@435 | 1323 | switch (AllocatePrefetchInstr) { |
duke@435 | 1324 | case 0: |
duke@435 | 1325 | __ prefetchnta(from_addr); break; |
duke@435 | 1326 | case 1: |
duke@435 | 1327 | __ prefetcht0(from_addr); break; |
duke@435 | 1328 | case 2: |
duke@435 | 1329 | __ prefetcht2(from_addr); break; |
duke@435 | 1330 | case 3: |
duke@435 | 1331 | __ prefetchw(from_addr); break; |
duke@435 | 1332 | default: |
duke@435 | 1333 | ShouldNotReachHere(); break; |
duke@435 | 1334 | } |
duke@435 | 1335 | } else if (VM_Version::supports_3dnow()) { |
duke@435 | 1336 | __ prefetchw(from_addr); |
duke@435 | 1337 | } |
duke@435 | 1338 | } |
duke@435 | 1339 | |
duke@435 | 1340 | |
duke@435 | 1341 | NEEDS_CLEANUP; // This could be static? |
duke@435 | 1342 | Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { |
kvn@464 | 1343 | int elem_size = type2aelembytes(type); |
duke@435 | 1344 | switch (elem_size) { |
duke@435 | 1345 | case 1: return Address::times_1; |
duke@435 | 1346 | case 2: return Address::times_2; |
duke@435 | 1347 | case 4: return Address::times_4; |
duke@435 | 1348 | case 8: return Address::times_8; |
duke@435 | 1349 | } |
duke@435 | 1350 | ShouldNotReachHere(); |
duke@435 | 1351 | return Address::no_scale; |
duke@435 | 1352 | } |
duke@435 | 1353 | |
duke@435 | 1354 | |
duke@435 | 1355 | void LIR_Assembler::emit_op3(LIR_Op3* op) { |
duke@435 | 1356 | switch (op->code()) { |
duke@435 | 1357 | case lir_idiv: |
duke@435 | 1358 | case lir_irem: |
duke@435 | 1359 | arithmetic_idiv(op->code(), |
duke@435 | 1360 | op->in_opr1(), |
duke@435 | 1361 | op->in_opr2(), |
duke@435 | 1362 | op->in_opr3(), |
duke@435 | 1363 | op->result_opr(), |
duke@435 | 1364 | op->info()); |
duke@435 | 1365 | break; |
duke@435 | 1366 | default: ShouldNotReachHere(); break; |
duke@435 | 1367 | } |
duke@435 | 1368 | } |
duke@435 | 1369 | |
duke@435 | 1370 | void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { |
duke@435 | 1371 | #ifdef ASSERT |
duke@435 | 1372 | assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); |
duke@435 | 1373 | if (op->block() != NULL) _branch_target_blocks.append(op->block()); |
duke@435 | 1374 | if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); |
duke@435 | 1375 | #endif |
duke@435 | 1376 | |
duke@435 | 1377 | if (op->cond() == lir_cond_always) { |
duke@435 | 1378 | if (op->info() != NULL) add_debug_info_for_branch(op->info()); |
duke@435 | 1379 | __ jmp (*(op->label())); |
duke@435 | 1380 | } else { |
duke@435 | 1381 | Assembler::Condition acond = Assembler::zero; |
duke@435 | 1382 | if (op->code() == lir_cond_float_branch) { |
duke@435 | 1383 | assert(op->ublock() != NULL, "must have unordered successor"); |
duke@435 | 1384 | __ jcc(Assembler::parity, *(op->ublock()->label())); |
duke@435 | 1385 | switch(op->cond()) { |
duke@435 | 1386 | case lir_cond_equal: acond = Assembler::equal; break; |
duke@435 | 1387 | case lir_cond_notEqual: acond = Assembler::notEqual; break; |
duke@435 | 1388 | case lir_cond_less: acond = Assembler::below; break; |
duke@435 | 1389 | case lir_cond_lessEqual: acond = Assembler::belowEqual; break; |
duke@435 | 1390 | case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; |
duke@435 | 1391 | case lir_cond_greater: acond = Assembler::above; break; |
duke@435 | 1392 | default: ShouldNotReachHere(); |
duke@435 | 1393 | } |
duke@435 | 1394 | } else { |
duke@435 | 1395 | switch (op->cond()) { |
duke@435 | 1396 | case lir_cond_equal: acond = Assembler::equal; break; |
duke@435 | 1397 | case lir_cond_notEqual: acond = Assembler::notEqual; break; |
duke@435 | 1398 | case lir_cond_less: acond = Assembler::less; break; |
duke@435 | 1399 | case lir_cond_lessEqual: acond = Assembler::lessEqual; break; |
duke@435 | 1400 | case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; |
duke@435 | 1401 | case lir_cond_greater: acond = Assembler::greater; break; |
duke@435 | 1402 | case lir_cond_belowEqual: acond = Assembler::belowEqual; break; |
duke@435 | 1403 | case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; |
duke@435 | 1404 | default: ShouldNotReachHere(); |
duke@435 | 1405 | } |
duke@435 | 1406 | } |
duke@435 | 1407 | __ jcc(acond,*(op->label())); |
duke@435 | 1408 | } |
duke@435 | 1409 | } |
duke@435 | 1410 | |
duke@435 | 1411 | void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { |
duke@435 | 1412 | LIR_Opr src = op->in_opr(); |
duke@435 | 1413 | LIR_Opr dest = op->result_opr(); |
duke@435 | 1414 | |
duke@435 | 1415 | switch (op->bytecode()) { |
duke@435 | 1416 | case Bytecodes::_i2l: |
never@739 | 1417 | #ifdef _LP64 |
never@739 | 1418 | __ movl2ptr(dest->as_register_lo(), src->as_register()); |
never@739 | 1419 | #else |
duke@435 | 1420 | move_regs(src->as_register(), dest->as_register_lo()); |
duke@435 | 1421 | move_regs(src->as_register(), dest->as_register_hi()); |
duke@435 | 1422 | __ sarl(dest->as_register_hi(), 31); |
never@739 | 1423 | #endif // LP64 |
duke@435 | 1424 | break; |
duke@435 | 1425 | |
duke@435 | 1426 | case Bytecodes::_l2i: |
duke@435 | 1427 | move_regs(src->as_register_lo(), dest->as_register()); |
duke@435 | 1428 | break; |
duke@435 | 1429 | |
duke@435 | 1430 | case Bytecodes::_i2b: |
duke@435 | 1431 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1432 | __ sign_extend_byte(dest->as_register()); |
duke@435 | 1433 | break; |
duke@435 | 1434 | |
duke@435 | 1435 | case Bytecodes::_i2c: |
duke@435 | 1436 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1437 | __ andl(dest->as_register(), 0xFFFF); |
duke@435 | 1438 | break; |
duke@435 | 1439 | |
duke@435 | 1440 | case Bytecodes::_i2s: |
duke@435 | 1441 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1442 | __ sign_extend_short(dest->as_register()); |
duke@435 | 1443 | break; |
duke@435 | 1444 | |
duke@435 | 1445 | |
duke@435 | 1446 | case Bytecodes::_f2d: |
duke@435 | 1447 | case Bytecodes::_d2f: |
duke@435 | 1448 | if (dest->is_single_xmm()) { |
duke@435 | 1449 | __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); |
duke@435 | 1450 | } else if (dest->is_double_xmm()) { |
duke@435 | 1451 | __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); |
duke@435 | 1452 | } else { |
duke@435 | 1453 | assert(src->fpu() == dest->fpu(), "register must be equal"); |
duke@435 | 1454 | // do nothing (float result is rounded later through spilling) |
duke@435 | 1455 | } |
duke@435 | 1456 | break; |
duke@435 | 1457 | |
duke@435 | 1458 | case Bytecodes::_i2f: |
duke@435 | 1459 | case Bytecodes::_i2d: |
duke@435 | 1460 | if (dest->is_single_xmm()) { |
never@739 | 1461 | __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
duke@435 | 1462 | } else if (dest->is_double_xmm()) { |
never@739 | 1463 | __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
duke@435 | 1464 | } else { |
duke@435 | 1465 | assert(dest->fpu() == 0, "result must be on TOS"); |
duke@435 | 1466 | __ movl(Address(rsp, 0), src->as_register()); |
duke@435 | 1467 | __ fild_s(Address(rsp, 0)); |
duke@435 | 1468 | } |
duke@435 | 1469 | break; |
duke@435 | 1470 | |
duke@435 | 1471 | case Bytecodes::_f2i: |
duke@435 | 1472 | case Bytecodes::_d2i: |
duke@435 | 1473 | if (src->is_single_xmm()) { |
never@739 | 1474 | __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
duke@435 | 1475 | } else if (src->is_double_xmm()) { |
never@739 | 1476 | __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
duke@435 | 1477 | } else { |
duke@435 | 1478 | assert(src->fpu() == 0, "input must be on TOS"); |
duke@435 | 1479 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); |
duke@435 | 1480 | __ fist_s(Address(rsp, 0)); |
duke@435 | 1481 | __ movl(dest->as_register(), Address(rsp, 0)); |
duke@435 | 1482 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
duke@435 | 1483 | } |
duke@435 | 1484 | |
duke@435 | 1485 | // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub |
duke@435 | 1486 | assert(op->stub() != NULL, "stub required"); |
duke@435 | 1487 | __ cmpl(dest->as_register(), 0x80000000); |
duke@435 | 1488 | __ jcc(Assembler::equal, *op->stub()->entry()); |
duke@435 | 1489 | __ bind(*op->stub()->continuation()); |
duke@435 | 1490 | break; |
duke@435 | 1491 | |
duke@435 | 1492 | case Bytecodes::_l2f: |
duke@435 | 1493 | case Bytecodes::_l2d: |
duke@435 | 1494 | assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); |
duke@435 | 1495 | assert(dest->fpu() == 0, "result must be on TOS"); |
duke@435 | 1496 | |
never@739 | 1497 | __ movptr(Address(rsp, 0), src->as_register_lo()); |
never@739 | 1498 | NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); |
duke@435 | 1499 | __ fild_d(Address(rsp, 0)); |
duke@435 | 1500 | // float result is rounded later through spilling |
duke@435 | 1501 | break; |
duke@435 | 1502 | |
duke@435 | 1503 | case Bytecodes::_f2l: |
duke@435 | 1504 | case Bytecodes::_d2l: |
duke@435 | 1505 | assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); |
duke@435 | 1506 | assert(src->fpu() == 0, "input must be on TOS"); |
never@739 | 1507 | assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
duke@435 | 1508 | |
duke@435 | 1509 | // instruction sequence too long to inline it here |
duke@435 | 1510 | { |
duke@435 | 1511 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); |
duke@435 | 1512 | } |
duke@435 | 1513 | break; |
duke@435 | 1514 | |
duke@435 | 1515 | default: ShouldNotReachHere(); |
duke@435 | 1516 | } |
duke@435 | 1517 | } |
duke@435 | 1518 | |
duke@435 | 1519 | void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { |
duke@435 | 1520 | if (op->init_check()) { |
duke@435 | 1521 | __ cmpl(Address(op->klass()->as_register(), |
duke@435 | 1522 | instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), |
duke@435 | 1523 | instanceKlass::fully_initialized); |
duke@435 | 1524 | add_debug_info_for_null_check_here(op->stub()->info()); |
duke@435 | 1525 | __ jcc(Assembler::notEqual, *op->stub()->entry()); |
duke@435 | 1526 | } |
duke@435 | 1527 | __ allocate_object(op->obj()->as_register(), |
duke@435 | 1528 | op->tmp1()->as_register(), |
duke@435 | 1529 | op->tmp2()->as_register(), |
duke@435 | 1530 | op->header_size(), |
duke@435 | 1531 | op->object_size(), |
duke@435 | 1532 | op->klass()->as_register(), |
duke@435 | 1533 | *op->stub()->entry()); |
duke@435 | 1534 | __ bind(*op->stub()->continuation()); |
duke@435 | 1535 | } |
duke@435 | 1536 | |
duke@435 | 1537 | void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { |
duke@435 | 1538 | if (UseSlowPath || |
duke@435 | 1539 | (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || |
duke@435 | 1540 | (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { |
duke@435 | 1541 | __ jmp(*op->stub()->entry()); |
duke@435 | 1542 | } else { |
duke@435 | 1543 | Register len = op->len()->as_register(); |
duke@435 | 1544 | Register tmp1 = op->tmp1()->as_register(); |
duke@435 | 1545 | Register tmp2 = op->tmp2()->as_register(); |
duke@435 | 1546 | Register tmp3 = op->tmp3()->as_register(); |
duke@435 | 1547 | if (len == tmp1) { |
duke@435 | 1548 | tmp1 = tmp3; |
duke@435 | 1549 | } else if (len == tmp2) { |
duke@435 | 1550 | tmp2 = tmp3; |
duke@435 | 1551 | } else if (len == tmp3) { |
duke@435 | 1552 | // everything is ok |
duke@435 | 1553 | } else { |
never@739 | 1554 | __ mov(tmp3, len); |
duke@435 | 1555 | } |
duke@435 | 1556 | __ allocate_array(op->obj()->as_register(), |
duke@435 | 1557 | len, |
duke@435 | 1558 | tmp1, |
duke@435 | 1559 | tmp2, |
duke@435 | 1560 | arrayOopDesc::header_size(op->type()), |
duke@435 | 1561 | array_element_size(op->type()), |
duke@435 | 1562 | op->klass()->as_register(), |
duke@435 | 1563 | *op->stub()->entry()); |
duke@435 | 1564 | } |
duke@435 | 1565 | __ bind(*op->stub()->continuation()); |
duke@435 | 1566 | } |
duke@435 | 1567 | |
duke@435 | 1568 | |
duke@435 | 1569 | |
duke@435 | 1570 | void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
duke@435 | 1571 | LIR_Code code = op->code(); |
duke@435 | 1572 | if (code == lir_store_check) { |
duke@435 | 1573 | Register value = op->object()->as_register(); |
duke@435 | 1574 | Register array = op->array()->as_register(); |
duke@435 | 1575 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 1576 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 1577 | Register Rtmp1 = op->tmp3()->as_register(); |
duke@435 | 1578 | |
duke@435 | 1579 | CodeStub* stub = op->stub(); |
duke@435 | 1580 | Label done; |
never@739 | 1581 | __ cmpptr(value, (int32_t)NULL_WORD); |
duke@435 | 1582 | __ jcc(Assembler::equal, done); |
duke@435 | 1583 | add_debug_info_for_null_check_here(op->info_for_exception()); |
never@739 | 1584 | __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); |
never@739 | 1585 | __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); |
duke@435 | 1586 | |
duke@435 | 1587 | // get instance klass |
never@739 | 1588 | __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); |
jrose@1079 | 1589 | // perform the fast part of the checking logic |
jrose@1079 | 1590 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); |
jrose@1079 | 1591 | // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
never@739 | 1592 | __ push(klass_RInfo); |
never@739 | 1593 | __ push(k_RInfo); |
duke@435 | 1594 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1595 | __ pop(klass_RInfo); |
never@739 | 1596 | __ pop(k_RInfo); |
never@739 | 1597 | // result is a boolean |
duke@435 | 1598 | __ cmpl(k_RInfo, 0); |
duke@435 | 1599 | __ jcc(Assembler::equal, *stub->entry()); |
duke@435 | 1600 | __ bind(done); |
duke@435 | 1601 | } else if (op->code() == lir_checkcast) { |
duke@435 | 1602 | // we always need a stub for the failure case. |
duke@435 | 1603 | CodeStub* stub = op->stub(); |
duke@435 | 1604 | Register obj = op->object()->as_register(); |
duke@435 | 1605 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 1606 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 1607 | Register dst = op->result_opr()->as_register(); |
duke@435 | 1608 | ciKlass* k = op->klass(); |
duke@435 | 1609 | Register Rtmp1 = noreg; |
duke@435 | 1610 | |
duke@435 | 1611 | Label done; |
duke@435 | 1612 | if (obj == k_RInfo) { |
duke@435 | 1613 | k_RInfo = dst; |
duke@435 | 1614 | } else if (obj == klass_RInfo) { |
duke@435 | 1615 | klass_RInfo = dst; |
duke@435 | 1616 | } |
duke@435 | 1617 | if (k->is_loaded()) { |
duke@435 | 1618 | select_different_registers(obj, dst, k_RInfo, klass_RInfo); |
duke@435 | 1619 | } else { |
duke@435 | 1620 | Rtmp1 = op->tmp3()->as_register(); |
duke@435 | 1621 | select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); |
duke@435 | 1622 | } |
duke@435 | 1623 | |
duke@435 | 1624 | assert_different_registers(obj, k_RInfo, klass_RInfo); |
duke@435 | 1625 | if (!k->is_loaded()) { |
duke@435 | 1626 | jobject2reg_with_patching(k_RInfo, op->info_for_patch()); |
duke@435 | 1627 | } else { |
never@739 | 1628 | #ifdef _LP64 |
jrose@1424 | 1629 | __ movoop(k_RInfo, k->constant_encoding()); |
never@739 | 1630 | #else |
duke@435 | 1631 | k_RInfo = noreg; |
never@739 | 1632 | #endif // _LP64 |
duke@435 | 1633 | } |
duke@435 | 1634 | assert(obj != k_RInfo, "must be different"); |
never@739 | 1635 | __ cmpptr(obj, (int32_t)NULL_WORD); |
duke@435 | 1636 | if (op->profiled_method() != NULL) { |
duke@435 | 1637 | ciMethod* method = op->profiled_method(); |
duke@435 | 1638 | int bci = op->profiled_bci(); |
duke@435 | 1639 | |
duke@435 | 1640 | Label profile_done; |
duke@435 | 1641 | __ jcc(Assembler::notEqual, profile_done); |
duke@435 | 1642 | // Object is null; update methodDataOop |
duke@435 | 1643 | ciMethodData* md = method->method_data(); |
duke@435 | 1644 | if (md == NULL) { |
duke@435 | 1645 | bailout("out of memory building methodDataOop"); |
duke@435 | 1646 | return; |
duke@435 | 1647 | } |
duke@435 | 1648 | ciProfileData* data = md->bci_to_data(bci); |
duke@435 | 1649 | assert(data != NULL, "need data for checkcast"); |
duke@435 | 1650 | assert(data->is_BitData(), "need BitData for checkcast"); |
duke@435 | 1651 | Register mdo = klass_RInfo; |
jrose@1424 | 1652 | __ movoop(mdo, md->constant_encoding()); |
duke@435 | 1653 | Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
duke@435 | 1654 | int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
duke@435 | 1655 | __ orl(data_addr, header_bits); |
duke@435 | 1656 | __ jmp(done); |
duke@435 | 1657 | __ bind(profile_done); |
duke@435 | 1658 | } else { |
duke@435 | 1659 | __ jcc(Assembler::equal, done); |
duke@435 | 1660 | } |
duke@435 | 1661 | __ verify_oop(obj); |
duke@435 | 1662 | |
duke@435 | 1663 | if (op->fast_check()) { |
duke@435 | 1664 | // get object classo |
duke@435 | 1665 | // not a safepoint as obj null check happens earlier |
duke@435 | 1666 | if (k->is_loaded()) { |
never@739 | 1667 | #ifdef _LP64 |
never@739 | 1668 | __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
never@739 | 1669 | #else |
jrose@1424 | 1670 | __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); |
never@739 | 1671 | #endif // _LP64 |
duke@435 | 1672 | } else { |
never@739 | 1673 | __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
duke@435 | 1674 | |
duke@435 | 1675 | } |
duke@435 | 1676 | __ jcc(Assembler::notEqual, *stub->entry()); |
duke@435 | 1677 | __ bind(done); |
duke@435 | 1678 | } else { |
duke@435 | 1679 | // get object class |
duke@435 | 1680 | // not a safepoint as obj null check happens earlier |
never@739 | 1681 | __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
duke@435 | 1682 | if (k->is_loaded()) { |
duke@435 | 1683 | // See if we get an immediate positive hit |
never@739 | 1684 | #ifdef _LP64 |
never@739 | 1685 | __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); |
never@739 | 1686 | #else |
jrose@1424 | 1687 | __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); |
never@739 | 1688 | #endif // _LP64 |
duke@435 | 1689 | if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { |
duke@435 | 1690 | __ jcc(Assembler::notEqual, *stub->entry()); |
duke@435 | 1691 | } else { |
duke@435 | 1692 | // See if we get an immediate positive hit |
duke@435 | 1693 | __ jcc(Assembler::equal, done); |
duke@435 | 1694 | // check for self |
never@739 | 1695 | #ifdef _LP64 |
never@739 | 1696 | __ cmpptr(klass_RInfo, k_RInfo); |
never@739 | 1697 | #else |
jrose@1424 | 1698 | __ cmpoop(klass_RInfo, k->constant_encoding()); |
never@739 | 1699 | #endif // _LP64 |
duke@435 | 1700 | __ jcc(Assembler::equal, done); |
duke@435 | 1701 | |
never@739 | 1702 | __ push(klass_RInfo); |
never@739 | 1703 | #ifdef _LP64 |
never@739 | 1704 | __ push(k_RInfo); |
never@739 | 1705 | #else |
jrose@1424 | 1706 | __ pushoop(k->constant_encoding()); |
never@739 | 1707 | #endif // _LP64 |
duke@435 | 1708 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1709 | __ pop(klass_RInfo); |
never@739 | 1710 | __ pop(klass_RInfo); |
never@739 | 1711 | // result is a boolean |
duke@435 | 1712 | __ cmpl(klass_RInfo, 0); |
duke@435 | 1713 | __ jcc(Assembler::equal, *stub->entry()); |
duke@435 | 1714 | } |
duke@435 | 1715 | __ bind(done); |
duke@435 | 1716 | } else { |
jrose@1079 | 1717 | // perform the fast part of the checking logic |
jrose@1079 | 1718 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); |
jrose@1079 | 1719 | // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
never@739 | 1720 | __ push(klass_RInfo); |
never@739 | 1721 | __ push(k_RInfo); |
duke@435 | 1722 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1723 | __ pop(klass_RInfo); |
never@739 | 1724 | __ pop(k_RInfo); |
never@739 | 1725 | // result is a boolean |
duke@435 | 1726 | __ cmpl(k_RInfo, 0); |
duke@435 | 1727 | __ jcc(Assembler::equal, *stub->entry()); |
duke@435 | 1728 | __ bind(done); |
duke@435 | 1729 | } |
duke@435 | 1730 | |
duke@435 | 1731 | } |
duke@435 | 1732 | if (dst != obj) { |
never@739 | 1733 | __ mov(dst, obj); |
duke@435 | 1734 | } |
duke@435 | 1735 | } else if (code == lir_instanceof) { |
duke@435 | 1736 | Register obj = op->object()->as_register(); |
duke@435 | 1737 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 1738 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 1739 | Register dst = op->result_opr()->as_register(); |
duke@435 | 1740 | ciKlass* k = op->klass(); |
duke@435 | 1741 | |
duke@435 | 1742 | Label done; |
duke@435 | 1743 | Label zero; |
duke@435 | 1744 | Label one; |
duke@435 | 1745 | if (obj == k_RInfo) { |
duke@435 | 1746 | k_RInfo = klass_RInfo; |
duke@435 | 1747 | klass_RInfo = obj; |
duke@435 | 1748 | } |
duke@435 | 1749 | // patching may screw with our temporaries on sparc, |
duke@435 | 1750 | // so let's do it before loading the class |
duke@435 | 1751 | if (!k->is_loaded()) { |
duke@435 | 1752 | jobject2reg_with_patching(k_RInfo, op->info_for_patch()); |
never@739 | 1753 | } else { |
jrose@1424 | 1754 | LP64_ONLY(__ movoop(k_RInfo, k->constant_encoding())); |
duke@435 | 1755 | } |
duke@435 | 1756 | assert(obj != k_RInfo, "must be different"); |
duke@435 | 1757 | |
duke@435 | 1758 | __ verify_oop(obj); |
duke@435 | 1759 | if (op->fast_check()) { |
never@739 | 1760 | __ cmpptr(obj, (int32_t)NULL_WORD); |
duke@435 | 1761 | __ jcc(Assembler::equal, zero); |
duke@435 | 1762 | // get object class |
duke@435 | 1763 | // not a safepoint as obj null check happens earlier |
never@739 | 1764 | if (LP64_ONLY(false &&) k->is_loaded()) { |
jrose@1424 | 1765 | NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding())); |
duke@435 | 1766 | k_RInfo = noreg; |
duke@435 | 1767 | } else { |
never@739 | 1768 | __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
duke@435 | 1769 | |
duke@435 | 1770 | } |
duke@435 | 1771 | __ jcc(Assembler::equal, one); |
duke@435 | 1772 | } else { |
duke@435 | 1773 | // get object class |
duke@435 | 1774 | // not a safepoint as obj null check happens earlier |
never@739 | 1775 | __ cmpptr(obj, (int32_t)NULL_WORD); |
duke@435 | 1776 | __ jcc(Assembler::equal, zero); |
never@739 | 1777 | __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
never@739 | 1778 | |
never@739 | 1779 | #ifndef _LP64 |
duke@435 | 1780 | if (k->is_loaded()) { |
duke@435 | 1781 | // See if we get an immediate positive hit |
jrose@1424 | 1782 | __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); |
duke@435 | 1783 | __ jcc(Assembler::equal, one); |
duke@435 | 1784 | if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) { |
duke@435 | 1785 | // check for self |
jrose@1424 | 1786 | __ cmpoop(klass_RInfo, k->constant_encoding()); |
duke@435 | 1787 | __ jcc(Assembler::equal, one); |
never@739 | 1788 | __ push(klass_RInfo); |
jrose@1424 | 1789 | __ pushoop(k->constant_encoding()); |
duke@435 | 1790 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1791 | __ pop(klass_RInfo); |
never@739 | 1792 | __ pop(dst); |
duke@435 | 1793 | __ jmp(done); |
duke@435 | 1794 | } |
jrose@1079 | 1795 | } |
jrose@1079 | 1796 | else // next block is unconditional if LP64: |
never@739 | 1797 | #endif // LP64 |
jrose@1079 | 1798 | { |
duke@435 | 1799 | assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); |
duke@435 | 1800 | |
jrose@1079 | 1801 | // perform the fast part of the checking logic |
jrose@1079 | 1802 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, dst, &one, &zero, NULL); |
jrose@1079 | 1803 | // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
never@739 | 1804 | __ push(klass_RInfo); |
never@739 | 1805 | __ push(k_RInfo); |
duke@435 | 1806 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1807 | __ pop(klass_RInfo); |
never@739 | 1808 | __ pop(dst); |
duke@435 | 1809 | __ jmp(done); |
duke@435 | 1810 | } |
duke@435 | 1811 | } |
duke@435 | 1812 | __ bind(zero); |
never@739 | 1813 | __ xorptr(dst, dst); |
duke@435 | 1814 | __ jmp(done); |
duke@435 | 1815 | __ bind(one); |
never@739 | 1816 | __ movptr(dst, 1); |
duke@435 | 1817 | __ bind(done); |
duke@435 | 1818 | } else { |
duke@435 | 1819 | ShouldNotReachHere(); |
duke@435 | 1820 | } |
duke@435 | 1821 | |
duke@435 | 1822 | } |
duke@435 | 1823 | |
duke@435 | 1824 | |
duke@435 | 1825 | void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { |
never@739 | 1826 | if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
duke@435 | 1827 | assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
duke@435 | 1828 | assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); |
duke@435 | 1829 | assert(op->new_value()->as_register_lo() == rbx, "wrong register"); |
duke@435 | 1830 | assert(op->new_value()->as_register_hi() == rcx, "wrong register"); |
duke@435 | 1831 | Register addr = op->addr()->as_register(); |
duke@435 | 1832 | if (os::is_MP()) { |
duke@435 | 1833 | __ lock(); |
duke@435 | 1834 | } |
never@739 | 1835 | NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
never@739 | 1836 | |
never@739 | 1837 | } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { |
never@739 | 1838 | NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) |
never@739 | 1839 | Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); |
duke@435 | 1840 | Register newval = op->new_value()->as_register(); |
duke@435 | 1841 | Register cmpval = op->cmp_value()->as_register(); |
duke@435 | 1842 | assert(cmpval == rax, "wrong register"); |
duke@435 | 1843 | assert(newval != NULL, "new val must be register"); |
duke@435 | 1844 | assert(cmpval != newval, "cmp and new values must be in different registers"); |
duke@435 | 1845 | assert(cmpval != addr, "cmp and addr must be in different registers"); |
duke@435 | 1846 | assert(newval != addr, "new value and addr must be in different registers"); |
duke@435 | 1847 | if (os::is_MP()) { |
duke@435 | 1848 | __ lock(); |
duke@435 | 1849 | } |
never@739 | 1850 | if ( op->code() == lir_cas_obj) { |
never@739 | 1851 | __ cmpxchgptr(newval, Address(addr, 0)); |
never@739 | 1852 | } else if (op->code() == lir_cas_int) { |
never@739 | 1853 | __ cmpxchgl(newval, Address(addr, 0)); |
never@739 | 1854 | } else { |
never@739 | 1855 | LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0))); |
never@739 | 1856 | } |
never@739 | 1857 | #ifdef _LP64 |
never@739 | 1858 | } else if (op->code() == lir_cas_long) { |
never@739 | 1859 | Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); |
never@739 | 1860 | Register newval = op->new_value()->as_register_lo(); |
never@739 | 1861 | Register cmpval = op->cmp_value()->as_register_lo(); |
never@739 | 1862 | assert(cmpval == rax, "wrong register"); |
never@739 | 1863 | assert(newval != NULL, "new val must be register"); |
never@739 | 1864 | assert(cmpval != newval, "cmp and new values must be in different registers"); |
never@739 | 1865 | assert(cmpval != addr, "cmp and addr must be in different registers"); |
never@739 | 1866 | assert(newval != addr, "new value and addr must be in different registers"); |
never@739 | 1867 | if (os::is_MP()) { |
never@739 | 1868 | __ lock(); |
never@739 | 1869 | } |
never@739 | 1870 | __ cmpxchgq(newval, Address(addr, 0)); |
never@739 | 1871 | #endif // _LP64 |
duke@435 | 1872 | } else { |
duke@435 | 1873 | Unimplemented(); |
duke@435 | 1874 | } |
duke@435 | 1875 | } |
duke@435 | 1876 | |
duke@435 | 1877 | |
duke@435 | 1878 | void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { |
duke@435 | 1879 | Assembler::Condition acond, ncond; |
duke@435 | 1880 | switch (condition) { |
duke@435 | 1881 | case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; |
duke@435 | 1882 | case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; |
duke@435 | 1883 | case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; |
duke@435 | 1884 | case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; |
duke@435 | 1885 | case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; |
duke@435 | 1886 | case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; |
duke@435 | 1887 | case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; |
duke@435 | 1888 | case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; |
duke@435 | 1889 | default: ShouldNotReachHere(); |
duke@435 | 1890 | } |
duke@435 | 1891 | |
duke@435 | 1892 | if (opr1->is_cpu_register()) { |
duke@435 | 1893 | reg2reg(opr1, result); |
duke@435 | 1894 | } else if (opr1->is_stack()) { |
duke@435 | 1895 | stack2reg(opr1, result, result->type()); |
duke@435 | 1896 | } else if (opr1->is_constant()) { |
duke@435 | 1897 | const2reg(opr1, result, lir_patch_none, NULL); |
duke@435 | 1898 | } else { |
duke@435 | 1899 | ShouldNotReachHere(); |
duke@435 | 1900 | } |
duke@435 | 1901 | |
duke@435 | 1902 | if (VM_Version::supports_cmov() && !opr2->is_constant()) { |
duke@435 | 1903 | // optimized version that does not require a branch |
duke@435 | 1904 | if (opr2->is_single_cpu()) { |
duke@435 | 1905 | assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); |
never@739 | 1906 | __ cmov(ncond, result->as_register(), opr2->as_register()); |
duke@435 | 1907 | } else if (opr2->is_double_cpu()) { |
duke@435 | 1908 | assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); |
duke@435 | 1909 | assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); |
never@739 | 1910 | __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
never@739 | 1911 | NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) |
duke@435 | 1912 | } else if (opr2->is_single_stack()) { |
duke@435 | 1913 | __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); |
duke@435 | 1914 | } else if (opr2->is_double_stack()) { |
never@739 | 1915 | __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
never@739 | 1916 | NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) |
duke@435 | 1917 | } else { |
duke@435 | 1918 | ShouldNotReachHere(); |
duke@435 | 1919 | } |
duke@435 | 1920 | |
duke@435 | 1921 | } else { |
duke@435 | 1922 | Label skip; |
duke@435 | 1923 | __ jcc (acond, skip); |
duke@435 | 1924 | if (opr2->is_cpu_register()) { |
duke@435 | 1925 | reg2reg(opr2, result); |
duke@435 | 1926 | } else if (opr2->is_stack()) { |
duke@435 | 1927 | stack2reg(opr2, result, result->type()); |
duke@435 | 1928 | } else if (opr2->is_constant()) { |
duke@435 | 1929 | const2reg(opr2, result, lir_patch_none, NULL); |
duke@435 | 1930 | } else { |
duke@435 | 1931 | ShouldNotReachHere(); |
duke@435 | 1932 | } |
duke@435 | 1933 | __ bind(skip); |
duke@435 | 1934 | } |
duke@435 | 1935 | } |
duke@435 | 1936 | |
duke@435 | 1937 | |
duke@435 | 1938 | void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { |
duke@435 | 1939 | assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); |
duke@435 | 1940 | |
duke@435 | 1941 | if (left->is_single_cpu()) { |
duke@435 | 1942 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 1943 | Register lreg = left->as_register(); |
duke@435 | 1944 | |
duke@435 | 1945 | if (right->is_single_cpu()) { |
duke@435 | 1946 | // cpu register - cpu register |
duke@435 | 1947 | Register rreg = right->as_register(); |
duke@435 | 1948 | switch (code) { |
duke@435 | 1949 | case lir_add: __ addl (lreg, rreg); break; |
duke@435 | 1950 | case lir_sub: __ subl (lreg, rreg); break; |
duke@435 | 1951 | case lir_mul: __ imull(lreg, rreg); break; |
duke@435 | 1952 | default: ShouldNotReachHere(); |
duke@435 | 1953 | } |
duke@435 | 1954 | |
duke@435 | 1955 | } else if (right->is_stack()) { |
duke@435 | 1956 | // cpu register - stack |
duke@435 | 1957 | Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 1958 | switch (code) { |
duke@435 | 1959 | case lir_add: __ addl(lreg, raddr); break; |
duke@435 | 1960 | case lir_sub: __ subl(lreg, raddr); break; |
duke@435 | 1961 | default: ShouldNotReachHere(); |
duke@435 | 1962 | } |
duke@435 | 1963 | |
duke@435 | 1964 | } else if (right->is_constant()) { |
duke@435 | 1965 | // cpu register - constant |
duke@435 | 1966 | jint c = right->as_constant_ptr()->as_jint(); |
duke@435 | 1967 | switch (code) { |
duke@435 | 1968 | case lir_add: { |
duke@435 | 1969 | __ increment(lreg, c); |
duke@435 | 1970 | break; |
duke@435 | 1971 | } |
duke@435 | 1972 | case lir_sub: { |
duke@435 | 1973 | __ decrement(lreg, c); |
duke@435 | 1974 | break; |
duke@435 | 1975 | } |
duke@435 | 1976 | default: ShouldNotReachHere(); |
duke@435 | 1977 | } |
duke@435 | 1978 | |
duke@435 | 1979 | } else { |
duke@435 | 1980 | ShouldNotReachHere(); |
duke@435 | 1981 | } |
duke@435 | 1982 | |
duke@435 | 1983 | } else if (left->is_double_cpu()) { |
duke@435 | 1984 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 1985 | Register lreg_lo = left->as_register_lo(); |
duke@435 | 1986 | Register lreg_hi = left->as_register_hi(); |
duke@435 | 1987 | |
duke@435 | 1988 | if (right->is_double_cpu()) { |
duke@435 | 1989 | // cpu register - cpu register |
duke@435 | 1990 | Register rreg_lo = right->as_register_lo(); |
duke@435 | 1991 | Register rreg_hi = right->as_register_hi(); |
never@739 | 1992 | NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
never@739 | 1993 | LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); |
duke@435 | 1994 | switch (code) { |
duke@435 | 1995 | case lir_add: |
never@739 | 1996 | __ addptr(lreg_lo, rreg_lo); |
never@739 | 1997 | NOT_LP64(__ adcl(lreg_hi, rreg_hi)); |
duke@435 | 1998 | break; |
duke@435 | 1999 | case lir_sub: |
never@739 | 2000 | __ subptr(lreg_lo, rreg_lo); |
never@739 | 2001 | NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); |
duke@435 | 2002 | break; |
duke@435 | 2003 | case lir_mul: |
never@739 | 2004 | #ifdef _LP64 |
never@739 | 2005 | __ imulq(lreg_lo, rreg_lo); |
never@739 | 2006 | #else |
duke@435 | 2007 | assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
duke@435 | 2008 | __ imull(lreg_hi, rreg_lo); |
duke@435 | 2009 | __ imull(rreg_hi, lreg_lo); |
duke@435 | 2010 | __ addl (rreg_hi, lreg_hi); |
duke@435 | 2011 | __ mull (rreg_lo); |
duke@435 | 2012 | __ addl (lreg_hi, rreg_hi); |
never@739 | 2013 | #endif // _LP64 |
duke@435 | 2014 | break; |
duke@435 | 2015 | default: |
duke@435 | 2016 | ShouldNotReachHere(); |
duke@435 | 2017 | } |
duke@435 | 2018 | |
duke@435 | 2019 | } else if (right->is_constant()) { |
duke@435 | 2020 | // cpu register - constant |
never@739 | 2021 | #ifdef _LP64 |
never@739 | 2022 | jlong c = right->as_constant_ptr()->as_jlong_bits(); |
never@739 | 2023 | __ movptr(r10, (intptr_t) c); |
never@739 | 2024 | switch (code) { |
never@739 | 2025 | case lir_add: |
never@739 | 2026 | __ addptr(lreg_lo, r10); |
never@739 | 2027 | break; |
never@739 | 2028 | case lir_sub: |
never@739 | 2029 | __ subptr(lreg_lo, r10); |
never@739 | 2030 | break; |
never@739 | 2031 | default: |
never@739 | 2032 | ShouldNotReachHere(); |
never@739 | 2033 | } |
never@739 | 2034 | #else |
duke@435 | 2035 | jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
duke@435 | 2036 | jint c_hi = right->as_constant_ptr()->as_jint_hi(); |
duke@435 | 2037 | switch (code) { |
duke@435 | 2038 | case lir_add: |
never@739 | 2039 | __ addptr(lreg_lo, c_lo); |
duke@435 | 2040 | __ adcl(lreg_hi, c_hi); |
duke@435 | 2041 | break; |
duke@435 | 2042 | case lir_sub: |
never@739 | 2043 | __ subptr(lreg_lo, c_lo); |
duke@435 | 2044 | __ sbbl(lreg_hi, c_hi); |
duke@435 | 2045 | break; |
duke@435 | 2046 | default: |
duke@435 | 2047 | ShouldNotReachHere(); |
duke@435 | 2048 | } |
never@739 | 2049 | #endif // _LP64 |
duke@435 | 2050 | |
duke@435 | 2051 | } else { |
duke@435 | 2052 | ShouldNotReachHere(); |
duke@435 | 2053 | } |
duke@435 | 2054 | |
duke@435 | 2055 | } else if (left->is_single_xmm()) { |
duke@435 | 2056 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2057 | XMMRegister lreg = left->as_xmm_float_reg(); |
duke@435 | 2058 | |
duke@435 | 2059 | if (right->is_single_xmm()) { |
duke@435 | 2060 | XMMRegister rreg = right->as_xmm_float_reg(); |
duke@435 | 2061 | switch (code) { |
duke@435 | 2062 | case lir_add: __ addss(lreg, rreg); break; |
duke@435 | 2063 | case lir_sub: __ subss(lreg, rreg); break; |
duke@435 | 2064 | case lir_mul_strictfp: // fall through |
duke@435 | 2065 | case lir_mul: __ mulss(lreg, rreg); break; |
duke@435 | 2066 | case lir_div_strictfp: // fall through |
duke@435 | 2067 | case lir_div: __ divss(lreg, rreg); break; |
duke@435 | 2068 | default: ShouldNotReachHere(); |
duke@435 | 2069 | } |
duke@435 | 2070 | } else { |
duke@435 | 2071 | Address raddr; |
duke@435 | 2072 | if (right->is_single_stack()) { |
duke@435 | 2073 | raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2074 | } else if (right->is_constant()) { |
duke@435 | 2075 | // hack for now |
duke@435 | 2076 | raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); |
duke@435 | 2077 | } else { |
duke@435 | 2078 | ShouldNotReachHere(); |
duke@435 | 2079 | } |
duke@435 | 2080 | switch (code) { |
duke@435 | 2081 | case lir_add: __ addss(lreg, raddr); break; |
duke@435 | 2082 | case lir_sub: __ subss(lreg, raddr); break; |
duke@435 | 2083 | case lir_mul_strictfp: // fall through |
duke@435 | 2084 | case lir_mul: __ mulss(lreg, raddr); break; |
duke@435 | 2085 | case lir_div_strictfp: // fall through |
duke@435 | 2086 | case lir_div: __ divss(lreg, raddr); break; |
duke@435 | 2087 | default: ShouldNotReachHere(); |
duke@435 | 2088 | } |
duke@435 | 2089 | } |
duke@435 | 2090 | |
duke@435 | 2091 | } else if (left->is_double_xmm()) { |
duke@435 | 2092 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2093 | |
duke@435 | 2094 | XMMRegister lreg = left->as_xmm_double_reg(); |
duke@435 | 2095 | if (right->is_double_xmm()) { |
duke@435 | 2096 | XMMRegister rreg = right->as_xmm_double_reg(); |
duke@435 | 2097 | switch (code) { |
duke@435 | 2098 | case lir_add: __ addsd(lreg, rreg); break; |
duke@435 | 2099 | case lir_sub: __ subsd(lreg, rreg); break; |
duke@435 | 2100 | case lir_mul_strictfp: // fall through |
duke@435 | 2101 | case lir_mul: __ mulsd(lreg, rreg); break; |
duke@435 | 2102 | case lir_div_strictfp: // fall through |
duke@435 | 2103 | case lir_div: __ divsd(lreg, rreg); break; |
duke@435 | 2104 | default: ShouldNotReachHere(); |
duke@435 | 2105 | } |
duke@435 | 2106 | } else { |
duke@435 | 2107 | Address raddr; |
duke@435 | 2108 | if (right->is_double_stack()) { |
duke@435 | 2109 | raddr = frame_map()->address_for_slot(right->double_stack_ix()); |
duke@435 | 2110 | } else if (right->is_constant()) { |
duke@435 | 2111 | // hack for now |
duke@435 | 2112 | raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); |
duke@435 | 2113 | } else { |
duke@435 | 2114 | ShouldNotReachHere(); |
duke@435 | 2115 | } |
duke@435 | 2116 | switch (code) { |
duke@435 | 2117 | case lir_add: __ addsd(lreg, raddr); break; |
duke@435 | 2118 | case lir_sub: __ subsd(lreg, raddr); break; |
duke@435 | 2119 | case lir_mul_strictfp: // fall through |
duke@435 | 2120 | case lir_mul: __ mulsd(lreg, raddr); break; |
duke@435 | 2121 | case lir_div_strictfp: // fall through |
duke@435 | 2122 | case lir_div: __ divsd(lreg, raddr); break; |
duke@435 | 2123 | default: ShouldNotReachHere(); |
duke@435 | 2124 | } |
duke@435 | 2125 | } |
duke@435 | 2126 | |
duke@435 | 2127 | } else if (left->is_single_fpu()) { |
duke@435 | 2128 | assert(dest->is_single_fpu(), "fpu stack allocation required"); |
duke@435 | 2129 | |
duke@435 | 2130 | if (right->is_single_fpu()) { |
duke@435 | 2131 | arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); |
duke@435 | 2132 | |
duke@435 | 2133 | } else { |
duke@435 | 2134 | assert(left->fpu_regnr() == 0, "left must be on TOS"); |
duke@435 | 2135 | assert(dest->fpu_regnr() == 0, "dest must be on TOS"); |
duke@435 | 2136 | |
duke@435 | 2137 | Address raddr; |
duke@435 | 2138 | if (right->is_single_stack()) { |
duke@435 | 2139 | raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2140 | } else if (right->is_constant()) { |
duke@435 | 2141 | address const_addr = float_constant(right->as_jfloat()); |
duke@435 | 2142 | assert(const_addr != NULL, "incorrect float/double constant maintainance"); |
duke@435 | 2143 | // hack for now |
duke@435 | 2144 | raddr = __ as_Address(InternalAddress(const_addr)); |
duke@435 | 2145 | } else { |
duke@435 | 2146 | ShouldNotReachHere(); |
duke@435 | 2147 | } |
duke@435 | 2148 | |
duke@435 | 2149 | switch (code) { |
duke@435 | 2150 | case lir_add: __ fadd_s(raddr); break; |
duke@435 | 2151 | case lir_sub: __ fsub_s(raddr); break; |
duke@435 | 2152 | case lir_mul_strictfp: // fall through |
duke@435 | 2153 | case lir_mul: __ fmul_s(raddr); break; |
duke@435 | 2154 | case lir_div_strictfp: // fall through |
duke@435 | 2155 | case lir_div: __ fdiv_s(raddr); break; |
duke@435 | 2156 | default: ShouldNotReachHere(); |
duke@435 | 2157 | } |
duke@435 | 2158 | } |
duke@435 | 2159 | |
duke@435 | 2160 | } else if (left->is_double_fpu()) { |
duke@435 | 2161 | assert(dest->is_double_fpu(), "fpu stack allocation required"); |
duke@435 | 2162 | |
duke@435 | 2163 | if (code == lir_mul_strictfp || code == lir_div_strictfp) { |
duke@435 | 2164 | // Double values require special handling for strictfp mul/div on x86 |
duke@435 | 2165 | __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); |
duke@435 | 2166 | __ fmulp(left->fpu_regnrLo() + 1); |
duke@435 | 2167 | } |
duke@435 | 2168 | |
duke@435 | 2169 | if (right->is_double_fpu()) { |
duke@435 | 2170 | arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); |
duke@435 | 2171 | |
duke@435 | 2172 | } else { |
duke@435 | 2173 | assert(left->fpu_regnrLo() == 0, "left must be on TOS"); |
duke@435 | 2174 | assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); |
duke@435 | 2175 | |
duke@435 | 2176 | Address raddr; |
duke@435 | 2177 | if (right->is_double_stack()) { |
duke@435 | 2178 | raddr = frame_map()->address_for_slot(right->double_stack_ix()); |
duke@435 | 2179 | } else if (right->is_constant()) { |
duke@435 | 2180 | // hack for now |
duke@435 | 2181 | raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); |
duke@435 | 2182 | } else { |
duke@435 | 2183 | ShouldNotReachHere(); |
duke@435 | 2184 | } |
duke@435 | 2185 | |
duke@435 | 2186 | switch (code) { |
duke@435 | 2187 | case lir_add: __ fadd_d(raddr); break; |
duke@435 | 2188 | case lir_sub: __ fsub_d(raddr); break; |
duke@435 | 2189 | case lir_mul_strictfp: // fall through |
duke@435 | 2190 | case lir_mul: __ fmul_d(raddr); break; |
duke@435 | 2191 | case lir_div_strictfp: // fall through |
duke@435 | 2192 | case lir_div: __ fdiv_d(raddr); break; |
duke@435 | 2193 | default: ShouldNotReachHere(); |
duke@435 | 2194 | } |
duke@435 | 2195 | } |
duke@435 | 2196 | |
duke@435 | 2197 | if (code == lir_mul_strictfp || code == lir_div_strictfp) { |
duke@435 | 2198 | // Double values require special handling for strictfp mul/div on x86 |
duke@435 | 2199 | __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); |
duke@435 | 2200 | __ fmulp(dest->fpu_regnrLo() + 1); |
duke@435 | 2201 | } |
duke@435 | 2202 | |
duke@435 | 2203 | } else if (left->is_single_stack() || left->is_address()) { |
duke@435 | 2204 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2205 | |
duke@435 | 2206 | Address laddr; |
duke@435 | 2207 | if (left->is_single_stack()) { |
duke@435 | 2208 | laddr = frame_map()->address_for_slot(left->single_stack_ix()); |
duke@435 | 2209 | } else if (left->is_address()) { |
duke@435 | 2210 | laddr = as_Address(left->as_address_ptr()); |
duke@435 | 2211 | } else { |
duke@435 | 2212 | ShouldNotReachHere(); |
duke@435 | 2213 | } |
duke@435 | 2214 | |
duke@435 | 2215 | if (right->is_single_cpu()) { |
duke@435 | 2216 | Register rreg = right->as_register(); |
duke@435 | 2217 | switch (code) { |
duke@435 | 2218 | case lir_add: __ addl(laddr, rreg); break; |
duke@435 | 2219 | case lir_sub: __ subl(laddr, rreg); break; |
duke@435 | 2220 | default: ShouldNotReachHere(); |
duke@435 | 2221 | } |
duke@435 | 2222 | } else if (right->is_constant()) { |
duke@435 | 2223 | jint c = right->as_constant_ptr()->as_jint(); |
duke@435 | 2224 | switch (code) { |
duke@435 | 2225 | case lir_add: { |
never@739 | 2226 | __ incrementl(laddr, c); |
duke@435 | 2227 | break; |
duke@435 | 2228 | } |
duke@435 | 2229 | case lir_sub: { |
never@739 | 2230 | __ decrementl(laddr, c); |
duke@435 | 2231 | break; |
duke@435 | 2232 | } |
duke@435 | 2233 | default: ShouldNotReachHere(); |
duke@435 | 2234 | } |
duke@435 | 2235 | } else { |
duke@435 | 2236 | ShouldNotReachHere(); |
duke@435 | 2237 | } |
duke@435 | 2238 | |
duke@435 | 2239 | } else { |
duke@435 | 2240 | ShouldNotReachHere(); |
duke@435 | 2241 | } |
duke@435 | 2242 | } |
duke@435 | 2243 | |
duke@435 | 2244 | void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { |
duke@435 | 2245 | assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); |
duke@435 | 2246 | assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); |
duke@435 | 2247 | assert(left_index == 0 || right_index == 0, "either must be on top of stack"); |
duke@435 | 2248 | |
duke@435 | 2249 | bool left_is_tos = (left_index == 0); |
duke@435 | 2250 | bool dest_is_tos = (dest_index == 0); |
duke@435 | 2251 | int non_tos_index = (left_is_tos ? right_index : left_index); |
duke@435 | 2252 | |
duke@435 | 2253 | switch (code) { |
duke@435 | 2254 | case lir_add: |
duke@435 | 2255 | if (pop_fpu_stack) __ faddp(non_tos_index); |
duke@435 | 2256 | else if (dest_is_tos) __ fadd (non_tos_index); |
duke@435 | 2257 | else __ fadda(non_tos_index); |
duke@435 | 2258 | break; |
duke@435 | 2259 | |
duke@435 | 2260 | case lir_sub: |
duke@435 | 2261 | if (left_is_tos) { |
duke@435 | 2262 | if (pop_fpu_stack) __ fsubrp(non_tos_index); |
duke@435 | 2263 | else if (dest_is_tos) __ fsub (non_tos_index); |
duke@435 | 2264 | else __ fsubra(non_tos_index); |
duke@435 | 2265 | } else { |
duke@435 | 2266 | if (pop_fpu_stack) __ fsubp (non_tos_index); |
duke@435 | 2267 | else if (dest_is_tos) __ fsubr (non_tos_index); |
duke@435 | 2268 | else __ fsuba (non_tos_index); |
duke@435 | 2269 | } |
duke@435 | 2270 | break; |
duke@435 | 2271 | |
duke@435 | 2272 | case lir_mul_strictfp: // fall through |
duke@435 | 2273 | case lir_mul: |
duke@435 | 2274 | if (pop_fpu_stack) __ fmulp(non_tos_index); |
duke@435 | 2275 | else if (dest_is_tos) __ fmul (non_tos_index); |
duke@435 | 2276 | else __ fmula(non_tos_index); |
duke@435 | 2277 | break; |
duke@435 | 2278 | |
duke@435 | 2279 | case lir_div_strictfp: // fall through |
duke@435 | 2280 | case lir_div: |
duke@435 | 2281 | if (left_is_tos) { |
duke@435 | 2282 | if (pop_fpu_stack) __ fdivrp(non_tos_index); |
duke@435 | 2283 | else if (dest_is_tos) __ fdiv (non_tos_index); |
duke@435 | 2284 | else __ fdivra(non_tos_index); |
duke@435 | 2285 | } else { |
duke@435 | 2286 | if (pop_fpu_stack) __ fdivp (non_tos_index); |
duke@435 | 2287 | else if (dest_is_tos) __ fdivr (non_tos_index); |
duke@435 | 2288 | else __ fdiva (non_tos_index); |
duke@435 | 2289 | } |
duke@435 | 2290 | break; |
duke@435 | 2291 | |
duke@435 | 2292 | case lir_rem: |
duke@435 | 2293 | assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); |
duke@435 | 2294 | __ fremr(noreg); |
duke@435 | 2295 | break; |
duke@435 | 2296 | |
duke@435 | 2297 | default: |
duke@435 | 2298 | ShouldNotReachHere(); |
duke@435 | 2299 | } |
duke@435 | 2300 | } |
duke@435 | 2301 | |
duke@435 | 2302 | |
duke@435 | 2303 | void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { |
duke@435 | 2304 | if (value->is_double_xmm()) { |
duke@435 | 2305 | switch(code) { |
duke@435 | 2306 | case lir_abs : |
duke@435 | 2307 | { |
duke@435 | 2308 | if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { |
duke@435 | 2309 | __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); |
duke@435 | 2310 | } |
duke@435 | 2311 | __ andpd(dest->as_xmm_double_reg(), |
duke@435 | 2312 | ExternalAddress((address)double_signmask_pool)); |
duke@435 | 2313 | } |
duke@435 | 2314 | break; |
duke@435 | 2315 | |
duke@435 | 2316 | case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; |
duke@435 | 2317 | // all other intrinsics are not available in the SSE instruction set, so FPU is used |
duke@435 | 2318 | default : ShouldNotReachHere(); |
duke@435 | 2319 | } |
duke@435 | 2320 | |
duke@435 | 2321 | } else if (value->is_double_fpu()) { |
duke@435 | 2322 | assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); |
duke@435 | 2323 | switch(code) { |
duke@435 | 2324 | case lir_log : __ flog() ; break; |
duke@435 | 2325 | case lir_log10 : __ flog10() ; break; |
duke@435 | 2326 | case lir_abs : __ fabs() ; break; |
duke@435 | 2327 | case lir_sqrt : __ fsqrt(); break; |
duke@435 | 2328 | case lir_sin : |
duke@435 | 2329 | // Should consider not saving rbx, if not necessary |
duke@435 | 2330 | __ trigfunc('s', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2331 | break; |
duke@435 | 2332 | case lir_cos : |
duke@435 | 2333 | // Should consider not saving rbx, if not necessary |
duke@435 | 2334 | assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); |
duke@435 | 2335 | __ trigfunc('c', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2336 | break; |
duke@435 | 2337 | case lir_tan : |
duke@435 | 2338 | // Should consider not saving rbx, if not necessary |
duke@435 | 2339 | __ trigfunc('t', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2340 | break; |
duke@435 | 2341 | default : ShouldNotReachHere(); |
duke@435 | 2342 | } |
duke@435 | 2343 | } else { |
duke@435 | 2344 | Unimplemented(); |
duke@435 | 2345 | } |
duke@435 | 2346 | } |
duke@435 | 2347 | |
duke@435 | 2348 | void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { |
duke@435 | 2349 | // assert(left->destroys_register(), "check"); |
duke@435 | 2350 | if (left->is_single_cpu()) { |
duke@435 | 2351 | Register reg = left->as_register(); |
duke@435 | 2352 | if (right->is_constant()) { |
duke@435 | 2353 | int val = right->as_constant_ptr()->as_jint(); |
duke@435 | 2354 | switch (code) { |
duke@435 | 2355 | case lir_logic_and: __ andl (reg, val); break; |
duke@435 | 2356 | case lir_logic_or: __ orl (reg, val); break; |
duke@435 | 2357 | case lir_logic_xor: __ xorl (reg, val); break; |
duke@435 | 2358 | default: ShouldNotReachHere(); |
duke@435 | 2359 | } |
duke@435 | 2360 | } else if (right->is_stack()) { |
duke@435 | 2361 | // added support for stack operands |
duke@435 | 2362 | Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2363 | switch (code) { |
duke@435 | 2364 | case lir_logic_and: __ andl (reg, raddr); break; |
duke@435 | 2365 | case lir_logic_or: __ orl (reg, raddr); break; |
duke@435 | 2366 | case lir_logic_xor: __ xorl (reg, raddr); break; |
duke@435 | 2367 | default: ShouldNotReachHere(); |
duke@435 | 2368 | } |
duke@435 | 2369 | } else { |
duke@435 | 2370 | Register rright = right->as_register(); |
duke@435 | 2371 | switch (code) { |
never@739 | 2372 | case lir_logic_and: __ andptr (reg, rright); break; |
never@739 | 2373 | case lir_logic_or : __ orptr (reg, rright); break; |
never@739 | 2374 | case lir_logic_xor: __ xorptr (reg, rright); break; |
duke@435 | 2375 | default: ShouldNotReachHere(); |
duke@435 | 2376 | } |
duke@435 | 2377 | } |
duke@435 | 2378 | move_regs(reg, dst->as_register()); |
duke@435 | 2379 | } else { |
duke@435 | 2380 | Register l_lo = left->as_register_lo(); |
duke@435 | 2381 | Register l_hi = left->as_register_hi(); |
duke@435 | 2382 | if (right->is_constant()) { |
never@739 | 2383 | #ifdef _LP64 |
never@739 | 2384 | __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); |
never@739 | 2385 | switch (code) { |
never@739 | 2386 | case lir_logic_and: |
never@739 | 2387 | __ andq(l_lo, rscratch1); |
never@739 | 2388 | break; |
never@739 | 2389 | case lir_logic_or: |
never@739 | 2390 | __ orq(l_lo, rscratch1); |
never@739 | 2391 | break; |
never@739 | 2392 | case lir_logic_xor: |
never@739 | 2393 | __ xorq(l_lo, rscratch1); |
never@739 | 2394 | break; |
never@739 | 2395 | default: ShouldNotReachHere(); |
never@739 | 2396 | } |
never@739 | 2397 | #else |
duke@435 | 2398 | int r_lo = right->as_constant_ptr()->as_jint_lo(); |
duke@435 | 2399 | int r_hi = right->as_constant_ptr()->as_jint_hi(); |
duke@435 | 2400 | switch (code) { |
duke@435 | 2401 | case lir_logic_and: |
duke@435 | 2402 | __ andl(l_lo, r_lo); |
duke@435 | 2403 | __ andl(l_hi, r_hi); |
duke@435 | 2404 | break; |
duke@435 | 2405 | case lir_logic_or: |
duke@435 | 2406 | __ orl(l_lo, r_lo); |
duke@435 | 2407 | __ orl(l_hi, r_hi); |
duke@435 | 2408 | break; |
duke@435 | 2409 | case lir_logic_xor: |
duke@435 | 2410 | __ xorl(l_lo, r_lo); |
duke@435 | 2411 | __ xorl(l_hi, r_hi); |
duke@435 | 2412 | break; |
duke@435 | 2413 | default: ShouldNotReachHere(); |
duke@435 | 2414 | } |
never@739 | 2415 | #endif // _LP64 |
duke@435 | 2416 | } else { |
duke@435 | 2417 | Register r_lo = right->as_register_lo(); |
duke@435 | 2418 | Register r_hi = right->as_register_hi(); |
duke@435 | 2419 | assert(l_lo != r_hi, "overwriting registers"); |
duke@435 | 2420 | switch (code) { |
duke@435 | 2421 | case lir_logic_and: |
never@739 | 2422 | __ andptr(l_lo, r_lo); |
never@739 | 2423 | NOT_LP64(__ andptr(l_hi, r_hi);) |
duke@435 | 2424 | break; |
duke@435 | 2425 | case lir_logic_or: |
never@739 | 2426 | __ orptr(l_lo, r_lo); |
never@739 | 2427 | NOT_LP64(__ orptr(l_hi, r_hi);) |
duke@435 | 2428 | break; |
duke@435 | 2429 | case lir_logic_xor: |
never@739 | 2430 | __ xorptr(l_lo, r_lo); |
never@739 | 2431 | NOT_LP64(__ xorptr(l_hi, r_hi);) |
duke@435 | 2432 | break; |
duke@435 | 2433 | default: ShouldNotReachHere(); |
duke@435 | 2434 | } |
duke@435 | 2435 | } |
duke@435 | 2436 | |
duke@435 | 2437 | Register dst_lo = dst->as_register_lo(); |
duke@435 | 2438 | Register dst_hi = dst->as_register_hi(); |
duke@435 | 2439 | |
never@739 | 2440 | #ifdef _LP64 |
never@739 | 2441 | move_regs(l_lo, dst_lo); |
never@739 | 2442 | #else |
duke@435 | 2443 | if (dst_lo == l_hi) { |
duke@435 | 2444 | assert(dst_hi != l_lo, "overwriting registers"); |
duke@435 | 2445 | move_regs(l_hi, dst_hi); |
duke@435 | 2446 | move_regs(l_lo, dst_lo); |
duke@435 | 2447 | } else { |
duke@435 | 2448 | assert(dst_lo != l_hi, "overwriting registers"); |
duke@435 | 2449 | move_regs(l_lo, dst_lo); |
duke@435 | 2450 | move_regs(l_hi, dst_hi); |
duke@435 | 2451 | } |
never@739 | 2452 | #endif // _LP64 |
duke@435 | 2453 | } |
duke@435 | 2454 | } |
duke@435 | 2455 | |
duke@435 | 2456 | |
duke@435 | 2457 | // we assume that rax, and rdx can be overwritten |
duke@435 | 2458 | void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { |
duke@435 | 2459 | |
duke@435 | 2460 | assert(left->is_single_cpu(), "left must be register"); |
duke@435 | 2461 | assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); |
duke@435 | 2462 | assert(result->is_single_cpu(), "result must be register"); |
duke@435 | 2463 | |
duke@435 | 2464 | // assert(left->destroys_register(), "check"); |
duke@435 | 2465 | // assert(right->destroys_register(), "check"); |
duke@435 | 2466 | |
duke@435 | 2467 | Register lreg = left->as_register(); |
duke@435 | 2468 | Register dreg = result->as_register(); |
duke@435 | 2469 | |
duke@435 | 2470 | if (right->is_constant()) { |
duke@435 | 2471 | int divisor = right->as_constant_ptr()->as_jint(); |
duke@435 | 2472 | assert(divisor > 0 && is_power_of_2(divisor), "must be"); |
duke@435 | 2473 | if (code == lir_idiv) { |
duke@435 | 2474 | assert(lreg == rax, "must be rax,"); |
duke@435 | 2475 | assert(temp->as_register() == rdx, "tmp register must be rdx"); |
duke@435 | 2476 | __ cdql(); // sign extend into rdx:rax |
duke@435 | 2477 | if (divisor == 2) { |
duke@435 | 2478 | __ subl(lreg, rdx); |
duke@435 | 2479 | } else { |
duke@435 | 2480 | __ andl(rdx, divisor - 1); |
duke@435 | 2481 | __ addl(lreg, rdx); |
duke@435 | 2482 | } |
duke@435 | 2483 | __ sarl(lreg, log2_intptr(divisor)); |
duke@435 | 2484 | move_regs(lreg, dreg); |
duke@435 | 2485 | } else if (code == lir_irem) { |
duke@435 | 2486 | Label done; |
never@739 | 2487 | __ mov(dreg, lreg); |
duke@435 | 2488 | __ andl(dreg, 0x80000000 | (divisor - 1)); |
duke@435 | 2489 | __ jcc(Assembler::positive, done); |
duke@435 | 2490 | __ decrement(dreg); |
duke@435 | 2491 | __ orl(dreg, ~(divisor - 1)); |
duke@435 | 2492 | __ increment(dreg); |
duke@435 | 2493 | __ bind(done); |
duke@435 | 2494 | } else { |
duke@435 | 2495 | ShouldNotReachHere(); |
duke@435 | 2496 | } |
duke@435 | 2497 | } else { |
duke@435 | 2498 | Register rreg = right->as_register(); |
duke@435 | 2499 | assert(lreg == rax, "left register must be rax,"); |
duke@435 | 2500 | assert(rreg != rdx, "right register must not be rdx"); |
duke@435 | 2501 | assert(temp->as_register() == rdx, "tmp register must be rdx"); |
duke@435 | 2502 | |
duke@435 | 2503 | move_regs(lreg, rax); |
duke@435 | 2504 | |
duke@435 | 2505 | int idivl_offset = __ corrected_idivl(rreg); |
duke@435 | 2506 | add_debug_info_for_div0(idivl_offset, info); |
duke@435 | 2507 | if (code == lir_irem) { |
duke@435 | 2508 | move_regs(rdx, dreg); // result is in rdx |
duke@435 | 2509 | } else { |
duke@435 | 2510 | move_regs(rax, dreg); |
duke@435 | 2511 | } |
duke@435 | 2512 | } |
duke@435 | 2513 | } |
duke@435 | 2514 | |
duke@435 | 2515 | |
duke@435 | 2516 | void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { |
duke@435 | 2517 | if (opr1->is_single_cpu()) { |
duke@435 | 2518 | Register reg1 = opr1->as_register(); |
duke@435 | 2519 | if (opr2->is_single_cpu()) { |
duke@435 | 2520 | // cpu register - cpu register |
never@739 | 2521 | if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
never@739 | 2522 | __ cmpptr(reg1, opr2->as_register()); |
never@739 | 2523 | } else { |
never@739 | 2524 | assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); |
never@739 | 2525 | __ cmpl(reg1, opr2->as_register()); |
never@739 | 2526 | } |
duke@435 | 2527 | } else if (opr2->is_stack()) { |
duke@435 | 2528 | // cpu register - stack |
never@739 | 2529 | if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
never@739 | 2530 | __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
never@739 | 2531 | } else { |
never@739 | 2532 | __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
never@739 | 2533 | } |
duke@435 | 2534 | } else if (opr2->is_constant()) { |
duke@435 | 2535 | // cpu register - constant |
duke@435 | 2536 | LIR_Const* c = opr2->as_constant_ptr(); |
duke@435 | 2537 | if (c->type() == T_INT) { |
duke@435 | 2538 | __ cmpl(reg1, c->as_jint()); |
never@739 | 2539 | } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2540 | // In 64bit oops are single register |
duke@435 | 2541 | jobject o = c->as_jobject(); |
duke@435 | 2542 | if (o == NULL) { |
never@739 | 2543 | __ cmpptr(reg1, (int32_t)NULL_WORD); |
duke@435 | 2544 | } else { |
never@739 | 2545 | #ifdef _LP64 |
never@739 | 2546 | __ movoop(rscratch1, o); |
never@739 | 2547 | __ cmpptr(reg1, rscratch1); |
never@739 | 2548 | #else |
duke@435 | 2549 | __ cmpoop(reg1, c->as_jobject()); |
never@739 | 2550 | #endif // _LP64 |
duke@435 | 2551 | } |
duke@435 | 2552 | } else { |
duke@435 | 2553 | ShouldNotReachHere(); |
duke@435 | 2554 | } |
duke@435 | 2555 | // cpu register - address |
duke@435 | 2556 | } else if (opr2->is_address()) { |
duke@435 | 2557 | if (op->info() != NULL) { |
duke@435 | 2558 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2559 | } |
duke@435 | 2560 | __ cmpl(reg1, as_Address(opr2->as_address_ptr())); |
duke@435 | 2561 | } else { |
duke@435 | 2562 | ShouldNotReachHere(); |
duke@435 | 2563 | } |
duke@435 | 2564 | |
duke@435 | 2565 | } else if(opr1->is_double_cpu()) { |
duke@435 | 2566 | Register xlo = opr1->as_register_lo(); |
duke@435 | 2567 | Register xhi = opr1->as_register_hi(); |
duke@435 | 2568 | if (opr2->is_double_cpu()) { |
never@739 | 2569 | #ifdef _LP64 |
never@739 | 2570 | __ cmpptr(xlo, opr2->as_register_lo()); |
never@739 | 2571 | #else |
duke@435 | 2572 | // cpu register - cpu register |
duke@435 | 2573 | Register ylo = opr2->as_register_lo(); |
duke@435 | 2574 | Register yhi = opr2->as_register_hi(); |
duke@435 | 2575 | __ subl(xlo, ylo); |
duke@435 | 2576 | __ sbbl(xhi, yhi); |
duke@435 | 2577 | if (condition == lir_cond_equal || condition == lir_cond_notEqual) { |
duke@435 | 2578 | __ orl(xhi, xlo); |
duke@435 | 2579 | } |
never@739 | 2580 | #endif // _LP64 |
duke@435 | 2581 | } else if (opr2->is_constant()) { |
duke@435 | 2582 | // cpu register - constant 0 |
duke@435 | 2583 | assert(opr2->as_jlong() == (jlong)0, "only handles zero"); |
never@739 | 2584 | #ifdef _LP64 |
never@739 | 2585 | __ cmpptr(xlo, (int32_t)opr2->as_jlong()); |
never@739 | 2586 | #else |
duke@435 | 2587 | assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
duke@435 | 2588 | __ orl(xhi, xlo); |
never@739 | 2589 | #endif // _LP64 |
duke@435 | 2590 | } else { |
duke@435 | 2591 | ShouldNotReachHere(); |
duke@435 | 2592 | } |
duke@435 | 2593 | |
duke@435 | 2594 | } else if (opr1->is_single_xmm()) { |
duke@435 | 2595 | XMMRegister reg1 = opr1->as_xmm_float_reg(); |
duke@435 | 2596 | if (opr2->is_single_xmm()) { |
duke@435 | 2597 | // xmm register - xmm register |
duke@435 | 2598 | __ ucomiss(reg1, opr2->as_xmm_float_reg()); |
duke@435 | 2599 | } else if (opr2->is_stack()) { |
duke@435 | 2600 | // xmm register - stack |
duke@435 | 2601 | __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
duke@435 | 2602 | } else if (opr2->is_constant()) { |
duke@435 | 2603 | // xmm register - constant |
duke@435 | 2604 | __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); |
duke@435 | 2605 | } else if (opr2->is_address()) { |
duke@435 | 2606 | // xmm register - address |
duke@435 | 2607 | if (op->info() != NULL) { |
duke@435 | 2608 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2609 | } |
duke@435 | 2610 | __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); |
duke@435 | 2611 | } else { |
duke@435 | 2612 | ShouldNotReachHere(); |
duke@435 | 2613 | } |
duke@435 | 2614 | |
duke@435 | 2615 | } else if (opr1->is_double_xmm()) { |
duke@435 | 2616 | XMMRegister reg1 = opr1->as_xmm_double_reg(); |
duke@435 | 2617 | if (opr2->is_double_xmm()) { |
duke@435 | 2618 | // xmm register - xmm register |
duke@435 | 2619 | __ ucomisd(reg1, opr2->as_xmm_double_reg()); |
duke@435 | 2620 | } else if (opr2->is_stack()) { |
duke@435 | 2621 | // xmm register - stack |
duke@435 | 2622 | __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); |
duke@435 | 2623 | } else if (opr2->is_constant()) { |
duke@435 | 2624 | // xmm register - constant |
duke@435 | 2625 | __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); |
duke@435 | 2626 | } else if (opr2->is_address()) { |
duke@435 | 2627 | // xmm register - address |
duke@435 | 2628 | if (op->info() != NULL) { |
duke@435 | 2629 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2630 | } |
duke@435 | 2631 | __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); |
duke@435 | 2632 | } else { |
duke@435 | 2633 | ShouldNotReachHere(); |
duke@435 | 2634 | } |
duke@435 | 2635 | |
duke@435 | 2636 | } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { |
duke@435 | 2637 | assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); |
duke@435 | 2638 | assert(opr2->is_fpu_register(), "both must be registers"); |
duke@435 | 2639 | __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); |
duke@435 | 2640 | |
duke@435 | 2641 | } else if (opr1->is_address() && opr2->is_constant()) { |
never@739 | 2642 | LIR_Const* c = opr2->as_constant_ptr(); |
never@739 | 2643 | #ifdef _LP64 |
never@739 | 2644 | if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2645 | assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); |
never@739 | 2646 | __ movoop(rscratch1, c->as_jobject()); |
never@739 | 2647 | } |
never@739 | 2648 | #endif // LP64 |
duke@435 | 2649 | if (op->info() != NULL) { |
duke@435 | 2650 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2651 | } |
duke@435 | 2652 | // special case: address - constant |
duke@435 | 2653 | LIR_Address* addr = opr1->as_address_ptr(); |
duke@435 | 2654 | if (c->type() == T_INT) { |
duke@435 | 2655 | __ cmpl(as_Address(addr), c->as_jint()); |
never@739 | 2656 | } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2657 | #ifdef _LP64 |
never@739 | 2658 | // %%% Make this explode if addr isn't reachable until we figure out a |
never@739 | 2659 | // better strategy by giving noreg as the temp for as_Address |
never@739 | 2660 | __ cmpptr(rscratch1, as_Address(addr, noreg)); |
never@739 | 2661 | #else |
duke@435 | 2662 | __ cmpoop(as_Address(addr), c->as_jobject()); |
never@739 | 2663 | #endif // _LP64 |
duke@435 | 2664 | } else { |
duke@435 | 2665 | ShouldNotReachHere(); |
duke@435 | 2666 | } |
duke@435 | 2667 | |
duke@435 | 2668 | } else { |
duke@435 | 2669 | ShouldNotReachHere(); |
duke@435 | 2670 | } |
duke@435 | 2671 | } |
duke@435 | 2672 | |
duke@435 | 2673 | void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { |
duke@435 | 2674 | if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { |
duke@435 | 2675 | if (left->is_single_xmm()) { |
duke@435 | 2676 | assert(right->is_single_xmm(), "must match"); |
duke@435 | 2677 | __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); |
duke@435 | 2678 | } else if (left->is_double_xmm()) { |
duke@435 | 2679 | assert(right->is_double_xmm(), "must match"); |
duke@435 | 2680 | __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); |
duke@435 | 2681 | |
duke@435 | 2682 | } else { |
duke@435 | 2683 | assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); |
duke@435 | 2684 | assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); |
duke@435 | 2685 | |
duke@435 | 2686 | assert(left->fpu() == 0, "left must be on TOS"); |
duke@435 | 2687 | __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), |
duke@435 | 2688 | op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); |
duke@435 | 2689 | } |
duke@435 | 2690 | } else { |
duke@435 | 2691 | assert(code == lir_cmp_l2i, "check"); |
never@739 | 2692 | #ifdef _LP64 |
iveresov@1804 | 2693 | Label done; |
iveresov@1804 | 2694 | Register dest = dst->as_register(); |
iveresov@1804 | 2695 | __ cmpptr(left->as_register_lo(), right->as_register_lo()); |
iveresov@1804 | 2696 | __ movl(dest, -1); |
iveresov@1804 | 2697 | __ jccb(Assembler::less, done); |
iveresov@1804 | 2698 | __ set_byte_if_not_zero(dest); |
iveresov@1804 | 2699 | __ movzbl(dest, dest); |
iveresov@1804 | 2700 | __ bind(done); |
never@739 | 2701 | #else |
duke@435 | 2702 | __ lcmp2int(left->as_register_hi(), |
duke@435 | 2703 | left->as_register_lo(), |
duke@435 | 2704 | right->as_register_hi(), |
duke@435 | 2705 | right->as_register_lo()); |
duke@435 | 2706 | move_regs(left->as_register_hi(), dst->as_register()); |
never@739 | 2707 | #endif // _LP64 |
duke@435 | 2708 | } |
duke@435 | 2709 | } |
duke@435 | 2710 | |
duke@435 | 2711 | |
duke@435 | 2712 | void LIR_Assembler::align_call(LIR_Code code) { |
duke@435 | 2713 | if (os::is_MP()) { |
duke@435 | 2714 | // make sure that the displacement word of the call ends up word aligned |
duke@435 | 2715 | int offset = __ offset(); |
duke@435 | 2716 | switch (code) { |
duke@435 | 2717 | case lir_static_call: |
duke@435 | 2718 | case lir_optvirtual_call: |
twisti@1730 | 2719 | case lir_dynamic_call: |
duke@435 | 2720 | offset += NativeCall::displacement_offset; |
duke@435 | 2721 | break; |
duke@435 | 2722 | case lir_icvirtual_call: |
duke@435 | 2723 | offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; |
duke@435 | 2724 | break; |
duke@435 | 2725 | case lir_virtual_call: // currently, sparc-specific for niagara |
duke@435 | 2726 | default: ShouldNotReachHere(); |
duke@435 | 2727 | } |
duke@435 | 2728 | while (offset++ % BytesPerWord != 0) { |
duke@435 | 2729 | __ nop(); |
duke@435 | 2730 | } |
duke@435 | 2731 | } |
duke@435 | 2732 | } |
duke@435 | 2733 | |
duke@435 | 2734 | |
twisti@1730 | 2735 | void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
duke@435 | 2736 | assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
duke@435 | 2737 | "must be aligned"); |
twisti@1730 | 2738 | __ call(AddressLiteral(op->addr(), rtype)); |
twisti@1730 | 2739 | add_call_info(code_offset(), op->info(), op->is_method_handle_invoke()); |
duke@435 | 2740 | } |
duke@435 | 2741 | |
duke@435 | 2742 | |
twisti@1730 | 2743 | void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
duke@435 | 2744 | RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
duke@435 | 2745 | __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); |
duke@435 | 2746 | assert(!os::is_MP() || |
duke@435 | 2747 | (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
duke@435 | 2748 | "must be aligned"); |
twisti@1730 | 2749 | __ call(AddressLiteral(op->addr(), rh)); |
twisti@1730 | 2750 | add_call_info(code_offset(), op->info(), op->is_method_handle_invoke()); |
duke@435 | 2751 | } |
duke@435 | 2752 | |
duke@435 | 2753 | |
duke@435 | 2754 | /* Currently, vtable-dispatch is only enabled for sparc platforms */ |
twisti@1730 | 2755 | void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
duke@435 | 2756 | ShouldNotReachHere(); |
duke@435 | 2757 | } |
duke@435 | 2758 | |
twisti@1730 | 2759 | |
twisti@1736 | 2760 | void LIR_Assembler::preserve_SP(LIR_OpJavaCall* op) { |
twisti@1736 | 2761 | __ movptr(FrameMap::method_handle_invoke_SP_save_opr()->as_register(), rsp); |
twisti@1730 | 2762 | } |
twisti@1730 | 2763 | |
twisti@1730 | 2764 | |
twisti@1736 | 2765 | void LIR_Assembler::restore_SP(LIR_OpJavaCall* op) { |
twisti@1736 | 2766 | __ movptr(rsp, FrameMap::method_handle_invoke_SP_save_opr()->as_register()); |
twisti@1730 | 2767 | } |
twisti@1730 | 2768 | |
twisti@1730 | 2769 | |
duke@435 | 2770 | void LIR_Assembler::emit_static_call_stub() { |
duke@435 | 2771 | address call_pc = __ pc(); |
duke@435 | 2772 | address stub = __ start_a_stub(call_stub_size); |
duke@435 | 2773 | if (stub == NULL) { |
duke@435 | 2774 | bailout("static call stub overflow"); |
duke@435 | 2775 | return; |
duke@435 | 2776 | } |
duke@435 | 2777 | |
duke@435 | 2778 | int start = __ offset(); |
duke@435 | 2779 | if (os::is_MP()) { |
duke@435 | 2780 | // make sure that the displacement word of the call ends up word aligned |
duke@435 | 2781 | int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; |
duke@435 | 2782 | while (offset++ % BytesPerWord != 0) { |
duke@435 | 2783 | __ nop(); |
duke@435 | 2784 | } |
duke@435 | 2785 | } |
duke@435 | 2786 | __ relocate(static_stub_Relocation::spec(call_pc)); |
duke@435 | 2787 | __ movoop(rbx, (jobject)NULL); |
duke@435 | 2788 | // must be set to -1 at code generation time |
duke@435 | 2789 | assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); |
never@739 | 2790 | // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
never@739 | 2791 | __ jump(RuntimeAddress(__ pc())); |
duke@435 | 2792 | |
duke@435 | 2793 | assert(__ offset() - start <= call_stub_size, "stub too big") |
duke@435 | 2794 | __ end_a_stub(); |
duke@435 | 2795 | } |
duke@435 | 2796 | |
duke@435 | 2797 | |
duke@435 | 2798 | void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) { |
duke@435 | 2799 | assert(exceptionOop->as_register() == rax, "must match"); |
duke@435 | 2800 | assert(unwind || exceptionPC->as_register() == rdx, "must match"); |
duke@435 | 2801 | |
duke@435 | 2802 | // exception object is not added to oop map by LinearScan |
duke@435 | 2803 | // (LinearScan assumes that no oops are in fixed registers) |
duke@435 | 2804 | info->add_register_oop(exceptionOop); |
duke@435 | 2805 | Runtime1::StubID unwind_id; |
duke@435 | 2806 | |
duke@435 | 2807 | if (!unwind) { |
duke@435 | 2808 | // get current pc information |
duke@435 | 2809 | // pc is only needed if the method has an exception handler, the unwind code does not need it. |
duke@435 | 2810 | int pc_for_athrow_offset = __ offset(); |
duke@435 | 2811 | InternalAddress pc_for_athrow(__ pc()); |
duke@435 | 2812 | __ lea(exceptionPC->as_register(), pc_for_athrow); |
duke@435 | 2813 | add_call_info(pc_for_athrow_offset, info); // for exception handler |
duke@435 | 2814 | |
duke@435 | 2815 | __ verify_not_null_oop(rax); |
duke@435 | 2816 | // search an exception handler (rax: exception oop, rdx: throwing pc) |
duke@435 | 2817 | if (compilation()->has_fpu_code()) { |
duke@435 | 2818 | unwind_id = Runtime1::handle_exception_id; |
duke@435 | 2819 | } else { |
duke@435 | 2820 | unwind_id = Runtime1::handle_exception_nofpu_id; |
duke@435 | 2821 | } |
twisti@1730 | 2822 | __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
duke@435 | 2823 | } else { |
twisti@1730 | 2824 | // remove the activation |
twisti@1730 | 2825 | __ remove_frame(initial_frame_size_in_bytes()); |
twisti@1730 | 2826 | __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
duke@435 | 2827 | } |
duke@435 | 2828 | |
duke@435 | 2829 | // enough room for two byte trap |
duke@435 | 2830 | __ nop(); |
duke@435 | 2831 | } |
duke@435 | 2832 | |
duke@435 | 2833 | |
duke@435 | 2834 | void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
duke@435 | 2835 | |
duke@435 | 2836 | // optimized version for linear scan: |
duke@435 | 2837 | // * count must be already in ECX (guaranteed by LinearScan) |
duke@435 | 2838 | // * left and dest must be equal |
duke@435 | 2839 | // * tmp must be unused |
duke@435 | 2840 | assert(count->as_register() == SHIFT_count, "count must be in ECX"); |
duke@435 | 2841 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2842 | assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); |
duke@435 | 2843 | |
duke@435 | 2844 | if (left->is_single_cpu()) { |
duke@435 | 2845 | Register value = left->as_register(); |
duke@435 | 2846 | assert(value != SHIFT_count, "left cannot be ECX"); |
duke@435 | 2847 | |
duke@435 | 2848 | switch (code) { |
duke@435 | 2849 | case lir_shl: __ shll(value); break; |
duke@435 | 2850 | case lir_shr: __ sarl(value); break; |
duke@435 | 2851 | case lir_ushr: __ shrl(value); break; |
duke@435 | 2852 | default: ShouldNotReachHere(); |
duke@435 | 2853 | } |
duke@435 | 2854 | } else if (left->is_double_cpu()) { |
duke@435 | 2855 | Register lo = left->as_register_lo(); |
duke@435 | 2856 | Register hi = left->as_register_hi(); |
duke@435 | 2857 | assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); |
never@739 | 2858 | #ifdef _LP64 |
never@739 | 2859 | switch (code) { |
never@739 | 2860 | case lir_shl: __ shlptr(lo); break; |
never@739 | 2861 | case lir_shr: __ sarptr(lo); break; |
never@739 | 2862 | case lir_ushr: __ shrptr(lo); break; |
never@739 | 2863 | default: ShouldNotReachHere(); |
never@739 | 2864 | } |
never@739 | 2865 | #else |
duke@435 | 2866 | |
duke@435 | 2867 | switch (code) { |
duke@435 | 2868 | case lir_shl: __ lshl(hi, lo); break; |
duke@435 | 2869 | case lir_shr: __ lshr(hi, lo, true); break; |
duke@435 | 2870 | case lir_ushr: __ lshr(hi, lo, false); break; |
duke@435 | 2871 | default: ShouldNotReachHere(); |
duke@435 | 2872 | } |
never@739 | 2873 | #endif // LP64 |
duke@435 | 2874 | } else { |
duke@435 | 2875 | ShouldNotReachHere(); |
duke@435 | 2876 | } |
duke@435 | 2877 | } |
duke@435 | 2878 | |
duke@435 | 2879 | |
duke@435 | 2880 | void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { |
duke@435 | 2881 | if (dest->is_single_cpu()) { |
duke@435 | 2882 | // first move left into dest so that left is not destroyed by the shift |
duke@435 | 2883 | Register value = dest->as_register(); |
duke@435 | 2884 | count = count & 0x1F; // Java spec |
duke@435 | 2885 | |
duke@435 | 2886 | move_regs(left->as_register(), value); |
duke@435 | 2887 | switch (code) { |
duke@435 | 2888 | case lir_shl: __ shll(value, count); break; |
duke@435 | 2889 | case lir_shr: __ sarl(value, count); break; |
duke@435 | 2890 | case lir_ushr: __ shrl(value, count); break; |
duke@435 | 2891 | default: ShouldNotReachHere(); |
duke@435 | 2892 | } |
duke@435 | 2893 | } else if (dest->is_double_cpu()) { |
never@739 | 2894 | #ifndef _LP64 |
duke@435 | 2895 | Unimplemented(); |
never@739 | 2896 | #else |
never@739 | 2897 | // first move left into dest so that left is not destroyed by the shift |
never@739 | 2898 | Register value = dest->as_register_lo(); |
never@739 | 2899 | count = count & 0x1F; // Java spec |
never@739 | 2900 | |
never@739 | 2901 | move_regs(left->as_register_lo(), value); |
never@739 | 2902 | switch (code) { |
never@739 | 2903 | case lir_shl: __ shlptr(value, count); break; |
never@739 | 2904 | case lir_shr: __ sarptr(value, count); break; |
never@739 | 2905 | case lir_ushr: __ shrptr(value, count); break; |
never@739 | 2906 | default: ShouldNotReachHere(); |
never@739 | 2907 | } |
never@739 | 2908 | #endif // _LP64 |
duke@435 | 2909 | } else { |
duke@435 | 2910 | ShouldNotReachHere(); |
duke@435 | 2911 | } |
duke@435 | 2912 | } |
duke@435 | 2913 | |
duke@435 | 2914 | |
duke@435 | 2915 | void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { |
duke@435 | 2916 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 2917 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 2918 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
never@739 | 2919 | __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
duke@435 | 2920 | } |
duke@435 | 2921 | |
duke@435 | 2922 | |
duke@435 | 2923 | void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { |
duke@435 | 2924 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 2925 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 2926 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
never@739 | 2927 | __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
duke@435 | 2928 | } |
duke@435 | 2929 | |
duke@435 | 2930 | |
duke@435 | 2931 | void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { |
duke@435 | 2932 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 2933 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 2934 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
duke@435 | 2935 | __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); |
duke@435 | 2936 | } |
duke@435 | 2937 | |
duke@435 | 2938 | |
duke@435 | 2939 | // This code replaces a call to arraycopy; no exception may |
duke@435 | 2940 | // be thrown in this code, they must be thrown in the System.arraycopy |
duke@435 | 2941 | // activation frame; we could save some checks if this would not be the case |
duke@435 | 2942 | void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { |
duke@435 | 2943 | ciArrayKlass* default_type = op->expected_type(); |
duke@435 | 2944 | Register src = op->src()->as_register(); |
duke@435 | 2945 | Register dst = op->dst()->as_register(); |
duke@435 | 2946 | Register src_pos = op->src_pos()->as_register(); |
duke@435 | 2947 | Register dst_pos = op->dst_pos()->as_register(); |
duke@435 | 2948 | Register length = op->length()->as_register(); |
duke@435 | 2949 | Register tmp = op->tmp()->as_register(); |
duke@435 | 2950 | |
duke@435 | 2951 | CodeStub* stub = op->stub(); |
duke@435 | 2952 | int flags = op->flags(); |
duke@435 | 2953 | BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; |
duke@435 | 2954 | if (basic_type == T_ARRAY) basic_type = T_OBJECT; |
duke@435 | 2955 | |
duke@435 | 2956 | // if we don't know anything or it's an object array, just go through the generic arraycopy |
duke@435 | 2957 | if (default_type == NULL) { |
duke@435 | 2958 | Label done; |
duke@435 | 2959 | // save outgoing arguments on stack in case call to System.arraycopy is needed |
duke@435 | 2960 | // HACK ALERT. This code used to push the parameters in a hardwired fashion |
duke@435 | 2961 | // for interpreter calling conventions. Now we have to do it in new style conventions. |
duke@435 | 2962 | // For the moment until C1 gets the new register allocator I just force all the |
duke@435 | 2963 | // args to the right place (except the register args) and then on the back side |
duke@435 | 2964 | // reload the register args properly if we go slow path. Yuck |
duke@435 | 2965 | |
duke@435 | 2966 | // These are proper for the calling convention |
duke@435 | 2967 | |
duke@435 | 2968 | store_parameter(length, 2); |
duke@435 | 2969 | store_parameter(dst_pos, 1); |
duke@435 | 2970 | store_parameter(dst, 0); |
duke@435 | 2971 | |
duke@435 | 2972 | // these are just temporary placements until we need to reload |
duke@435 | 2973 | store_parameter(src_pos, 3); |
duke@435 | 2974 | store_parameter(src, 4); |
never@739 | 2975 | NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
never@739 | 2976 | |
never@739 | 2977 | address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); |
duke@435 | 2978 | |
duke@435 | 2979 | // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint |
never@739 | 2980 | #ifdef _LP64 |
never@739 | 2981 | // The arguments are in java calling convention so we can trivially shift them to C |
never@739 | 2982 | // convention |
never@739 | 2983 | assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); |
never@739 | 2984 | __ mov(c_rarg0, j_rarg0); |
never@739 | 2985 | assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); |
never@739 | 2986 | __ mov(c_rarg1, j_rarg1); |
never@739 | 2987 | assert_different_registers(c_rarg2, j_rarg3, j_rarg4); |
never@739 | 2988 | __ mov(c_rarg2, j_rarg2); |
never@739 | 2989 | assert_different_registers(c_rarg3, j_rarg4); |
never@739 | 2990 | __ mov(c_rarg3, j_rarg3); |
never@739 | 2991 | #ifdef _WIN64 |
never@739 | 2992 | // Allocate abi space for args but be sure to keep stack aligned |
never@739 | 2993 | __ subptr(rsp, 6*wordSize); |
never@739 | 2994 | store_parameter(j_rarg4, 4); |
never@739 | 2995 | __ call(RuntimeAddress(entry)); |
never@739 | 2996 | __ addptr(rsp, 6*wordSize); |
never@739 | 2997 | #else |
never@739 | 2998 | __ mov(c_rarg4, j_rarg4); |
never@739 | 2999 | __ call(RuntimeAddress(entry)); |
never@739 | 3000 | #endif // _WIN64 |
never@739 | 3001 | #else |
never@739 | 3002 | __ push(length); |
never@739 | 3003 | __ push(dst_pos); |
never@739 | 3004 | __ push(dst); |
never@739 | 3005 | __ push(src_pos); |
never@739 | 3006 | __ push(src); |
duke@435 | 3007 | __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack |
duke@435 | 3008 | |
never@739 | 3009 | #endif // _LP64 |
never@739 | 3010 | |
duke@435 | 3011 | __ cmpl(rax, 0); |
duke@435 | 3012 | __ jcc(Assembler::equal, *stub->continuation()); |
duke@435 | 3013 | |
duke@435 | 3014 | // Reload values from the stack so they are where the stub |
duke@435 | 3015 | // expects them. |
never@739 | 3016 | __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
never@739 | 3017 | __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); |
never@739 | 3018 | __ movptr (length, Address(rsp, 2*BytesPerWord)); |
never@739 | 3019 | __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); |
never@739 | 3020 | __ movptr (src, Address(rsp, 4*BytesPerWord)); |
duke@435 | 3021 | __ jmp(*stub->entry()); |
duke@435 | 3022 | |
duke@435 | 3023 | __ bind(*stub->continuation()); |
duke@435 | 3024 | return; |
duke@435 | 3025 | } |
duke@435 | 3026 | |
duke@435 | 3027 | assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); |
duke@435 | 3028 | |
kvn@464 | 3029 | int elem_size = type2aelembytes(basic_type); |
duke@435 | 3030 | int shift_amount; |
duke@435 | 3031 | Address::ScaleFactor scale; |
duke@435 | 3032 | |
duke@435 | 3033 | switch (elem_size) { |
duke@435 | 3034 | case 1 : |
duke@435 | 3035 | shift_amount = 0; |
duke@435 | 3036 | scale = Address::times_1; |
duke@435 | 3037 | break; |
duke@435 | 3038 | case 2 : |
duke@435 | 3039 | shift_amount = 1; |
duke@435 | 3040 | scale = Address::times_2; |
duke@435 | 3041 | break; |
duke@435 | 3042 | case 4 : |
duke@435 | 3043 | shift_amount = 2; |
duke@435 | 3044 | scale = Address::times_4; |
duke@435 | 3045 | break; |
duke@435 | 3046 | case 8 : |
duke@435 | 3047 | shift_amount = 3; |
duke@435 | 3048 | scale = Address::times_8; |
duke@435 | 3049 | break; |
duke@435 | 3050 | default: |
duke@435 | 3051 | ShouldNotReachHere(); |
duke@435 | 3052 | } |
duke@435 | 3053 | |
duke@435 | 3054 | Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); |
duke@435 | 3055 | Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); |
duke@435 | 3056 | Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); |
duke@435 | 3057 | Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); |
duke@435 | 3058 | |
never@739 | 3059 | // length and pos's are all sign extended at this point on 64bit |
never@739 | 3060 | |
duke@435 | 3061 | // test for NULL |
duke@435 | 3062 | if (flags & LIR_OpArrayCopy::src_null_check) { |
never@739 | 3063 | __ testptr(src, src); |
duke@435 | 3064 | __ jcc(Assembler::zero, *stub->entry()); |
duke@435 | 3065 | } |
duke@435 | 3066 | if (flags & LIR_OpArrayCopy::dst_null_check) { |
never@739 | 3067 | __ testptr(dst, dst); |
duke@435 | 3068 | __ jcc(Assembler::zero, *stub->entry()); |
duke@435 | 3069 | } |
duke@435 | 3070 | |
duke@435 | 3071 | // check if negative |
duke@435 | 3072 | if (flags & LIR_OpArrayCopy::src_pos_positive_check) { |
duke@435 | 3073 | __ testl(src_pos, src_pos); |
duke@435 | 3074 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3075 | } |
duke@435 | 3076 | if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { |
duke@435 | 3077 | __ testl(dst_pos, dst_pos); |
duke@435 | 3078 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3079 | } |
duke@435 | 3080 | if (flags & LIR_OpArrayCopy::length_positive_check) { |
duke@435 | 3081 | __ testl(length, length); |
duke@435 | 3082 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3083 | } |
duke@435 | 3084 | |
duke@435 | 3085 | if (flags & LIR_OpArrayCopy::src_range_check) { |
never@739 | 3086 | __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
duke@435 | 3087 | __ cmpl(tmp, src_length_addr); |
duke@435 | 3088 | __ jcc(Assembler::above, *stub->entry()); |
duke@435 | 3089 | } |
duke@435 | 3090 | if (flags & LIR_OpArrayCopy::dst_range_check) { |
never@739 | 3091 | __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
duke@435 | 3092 | __ cmpl(tmp, dst_length_addr); |
duke@435 | 3093 | __ jcc(Assembler::above, *stub->entry()); |
duke@435 | 3094 | } |
duke@435 | 3095 | |
duke@435 | 3096 | if (flags & LIR_OpArrayCopy::type_check) { |
never@739 | 3097 | __ movptr(tmp, src_klass_addr); |
never@739 | 3098 | __ cmpptr(tmp, dst_klass_addr); |
duke@435 | 3099 | __ jcc(Assembler::notEqual, *stub->entry()); |
duke@435 | 3100 | } |
duke@435 | 3101 | |
duke@435 | 3102 | #ifdef ASSERT |
duke@435 | 3103 | if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { |
duke@435 | 3104 | // Sanity check the known type with the incoming class. For the |
duke@435 | 3105 | // primitive case the types must match exactly with src.klass and |
duke@435 | 3106 | // dst.klass each exactly matching the default type. For the |
duke@435 | 3107 | // object array case, if no type check is needed then either the |
duke@435 | 3108 | // dst type is exactly the expected type and the src type is a |
duke@435 | 3109 | // subtype which we can't check or src is the same array as dst |
duke@435 | 3110 | // but not necessarily exactly of type default_type. |
duke@435 | 3111 | Label known_ok, halt; |
jrose@1424 | 3112 | __ movoop(tmp, default_type->constant_encoding()); |
duke@435 | 3113 | if (basic_type != T_OBJECT) { |
never@739 | 3114 | __ cmpptr(tmp, dst_klass_addr); |
duke@435 | 3115 | __ jcc(Assembler::notEqual, halt); |
never@739 | 3116 | __ cmpptr(tmp, src_klass_addr); |
duke@435 | 3117 | __ jcc(Assembler::equal, known_ok); |
duke@435 | 3118 | } else { |
never@739 | 3119 | __ cmpptr(tmp, dst_klass_addr); |
duke@435 | 3120 | __ jcc(Assembler::equal, known_ok); |
never@739 | 3121 | __ cmpptr(src, dst); |
duke@435 | 3122 | __ jcc(Assembler::equal, known_ok); |
duke@435 | 3123 | } |
duke@435 | 3124 | __ bind(halt); |
duke@435 | 3125 | __ stop("incorrect type information in arraycopy"); |
duke@435 | 3126 | __ bind(known_ok); |
duke@435 | 3127 | } |
duke@435 | 3128 | #endif |
duke@435 | 3129 | |
never@739 | 3130 | if (shift_amount > 0 && basic_type != T_OBJECT) { |
never@739 | 3131 | __ shlptr(length, shift_amount); |
never@739 | 3132 | } |
never@739 | 3133 | |
never@739 | 3134 | #ifdef _LP64 |
never@739 | 3135 | assert_different_registers(c_rarg0, dst, dst_pos, length); |
roland@1495 | 3136 | __ movl2ptr(src_pos, src_pos); //higher 32bits must be null |
never@739 | 3137 | __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
never@739 | 3138 | assert_different_registers(c_rarg1, length); |
roland@1495 | 3139 | __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null |
never@739 | 3140 | __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
never@739 | 3141 | __ mov(c_rarg2, length); |
never@739 | 3142 | |
never@739 | 3143 | #else |
never@739 | 3144 | __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
duke@435 | 3145 | store_parameter(tmp, 0); |
never@739 | 3146 | __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
duke@435 | 3147 | store_parameter(tmp, 1); |
duke@435 | 3148 | store_parameter(length, 2); |
never@739 | 3149 | #endif // _LP64 |
duke@435 | 3150 | if (basic_type == T_OBJECT) { |
duke@435 | 3151 | __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); |
duke@435 | 3152 | } else { |
duke@435 | 3153 | __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); |
duke@435 | 3154 | } |
duke@435 | 3155 | |
duke@435 | 3156 | __ bind(*stub->continuation()); |
duke@435 | 3157 | } |
duke@435 | 3158 | |
duke@435 | 3159 | |
duke@435 | 3160 | void LIR_Assembler::emit_lock(LIR_OpLock* op) { |
duke@435 | 3161 | Register obj = op->obj_opr()->as_register(); // may not be an oop |
duke@435 | 3162 | Register hdr = op->hdr_opr()->as_register(); |
duke@435 | 3163 | Register lock = op->lock_opr()->as_register(); |
duke@435 | 3164 | if (!UseFastLocking) { |
duke@435 | 3165 | __ jmp(*op->stub()->entry()); |
duke@435 | 3166 | } else if (op->code() == lir_lock) { |
duke@435 | 3167 | Register scratch = noreg; |
duke@435 | 3168 | if (UseBiasedLocking) { |
duke@435 | 3169 | scratch = op->scratch_opr()->as_register(); |
duke@435 | 3170 | } |
duke@435 | 3171 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 3172 | // add debug info for NullPointerException only if one is possible |
duke@435 | 3173 | int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); |
duke@435 | 3174 | if (op->info() != NULL) { |
duke@435 | 3175 | add_debug_info_for_null_check(null_check_offset, op->info()); |
duke@435 | 3176 | } |
duke@435 | 3177 | // done |
duke@435 | 3178 | } else if (op->code() == lir_unlock) { |
duke@435 | 3179 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 3180 | __ unlock_object(hdr, obj, lock, *op->stub()->entry()); |
duke@435 | 3181 | } else { |
duke@435 | 3182 | Unimplemented(); |
duke@435 | 3183 | } |
duke@435 | 3184 | __ bind(*op->stub()->continuation()); |
duke@435 | 3185 | } |
duke@435 | 3186 | |
duke@435 | 3187 | |
duke@435 | 3188 | void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { |
duke@435 | 3189 | ciMethod* method = op->profiled_method(); |
duke@435 | 3190 | int bci = op->profiled_bci(); |
duke@435 | 3191 | |
duke@435 | 3192 | // Update counter for all call types |
duke@435 | 3193 | ciMethodData* md = method->method_data(); |
duke@435 | 3194 | if (md == NULL) { |
duke@435 | 3195 | bailout("out of memory building methodDataOop"); |
duke@435 | 3196 | return; |
duke@435 | 3197 | } |
duke@435 | 3198 | ciProfileData* data = md->bci_to_data(bci); |
duke@435 | 3199 | assert(data->is_CounterData(), "need CounterData for calls"); |
duke@435 | 3200 | assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); |
duke@435 | 3201 | Register mdo = op->mdo()->as_register(); |
jrose@1424 | 3202 | __ movoop(mdo, md->constant_encoding()); |
duke@435 | 3203 | Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
duke@435 | 3204 | Bytecodes::Code bc = method->java_code_at_bci(bci); |
duke@435 | 3205 | // Perform additional virtual call profiling for invokevirtual and |
duke@435 | 3206 | // invokeinterface bytecodes |
duke@435 | 3207 | if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && |
duke@435 | 3208 | Tier1ProfileVirtualCalls) { |
duke@435 | 3209 | assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
duke@435 | 3210 | Register recv = op->recv()->as_register(); |
duke@435 | 3211 | assert_different_registers(mdo, recv); |
duke@435 | 3212 | assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); |
duke@435 | 3213 | ciKlass* known_klass = op->known_holder(); |
duke@435 | 3214 | if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { |
duke@435 | 3215 | // We know the type that will be seen at this call site; we can |
duke@435 | 3216 | // statically update the methodDataOop rather than needing to do |
duke@435 | 3217 | // dynamic tests on the receiver type |
duke@435 | 3218 | |
duke@435 | 3219 | // NOTE: we should probably put a lock around this search to |
duke@435 | 3220 | // avoid collisions by concurrent compilations |
duke@435 | 3221 | ciVirtualCallData* vc_data = (ciVirtualCallData*) data; |
duke@435 | 3222 | uint i; |
duke@435 | 3223 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3224 | ciKlass* receiver = vc_data->receiver(i); |
duke@435 | 3225 | if (known_klass->equals(receiver)) { |
duke@435 | 3226 | Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
duke@435 | 3227 | __ addl(data_addr, DataLayout::counter_increment); |
duke@435 | 3228 | return; |
duke@435 | 3229 | } |
duke@435 | 3230 | } |
duke@435 | 3231 | |
duke@435 | 3232 | // Receiver type not found in profile data; select an empty slot |
duke@435 | 3233 | |
duke@435 | 3234 | // Note that this is less efficient than it should be because it |
duke@435 | 3235 | // always does a write to the receiver part of the |
duke@435 | 3236 | // VirtualCallData rather than just the first time |
duke@435 | 3237 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3238 | ciKlass* receiver = vc_data->receiver(i); |
duke@435 | 3239 | if (receiver == NULL) { |
duke@435 | 3240 | Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); |
jrose@1424 | 3241 | __ movoop(recv_addr, known_klass->constant_encoding()); |
duke@435 | 3242 | Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
duke@435 | 3243 | __ addl(data_addr, DataLayout::counter_increment); |
duke@435 | 3244 | return; |
duke@435 | 3245 | } |
duke@435 | 3246 | } |
duke@435 | 3247 | } else { |
never@739 | 3248 | __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); |
duke@435 | 3249 | Label update_done; |
duke@435 | 3250 | uint i; |
duke@435 | 3251 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3252 | Label next_test; |
duke@435 | 3253 | // See if the receiver is receiver[n]. |
never@739 | 3254 | __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)))); |
duke@435 | 3255 | __ jcc(Assembler::notEqual, next_test); |
duke@435 | 3256 | Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
duke@435 | 3257 | __ addl(data_addr, DataLayout::counter_increment); |
duke@435 | 3258 | __ jmp(update_done); |
duke@435 | 3259 | __ bind(next_test); |
duke@435 | 3260 | } |
duke@435 | 3261 | |
duke@435 | 3262 | // Didn't find receiver; find next empty slot and fill it in |
duke@435 | 3263 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3264 | Label next_test; |
duke@435 | 3265 | Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); |
never@739 | 3266 | __ cmpptr(recv_addr, (int32_t)NULL_WORD); |
duke@435 | 3267 | __ jcc(Assembler::notEqual, next_test); |
never@739 | 3268 | __ movptr(recv_addr, recv); |
duke@435 | 3269 | __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment); |
kvn@1641 | 3270 | __ jmp(update_done); |
duke@435 | 3271 | __ bind(next_test); |
duke@435 | 3272 | } |
kvn@1641 | 3273 | // Receiver did not match any saved receiver and there is no empty row for it. |
kvn@1686 | 3274 | // Increment total counter to indicate polymorphic case. |
kvn@1641 | 3275 | __ addl(counter_addr, DataLayout::counter_increment); |
duke@435 | 3276 | |
duke@435 | 3277 | __ bind(update_done); |
duke@435 | 3278 | } |
kvn@1641 | 3279 | } else { |
kvn@1641 | 3280 | // Static call |
kvn@1641 | 3281 | __ addl(counter_addr, DataLayout::counter_increment); |
duke@435 | 3282 | } |
duke@435 | 3283 | } |
duke@435 | 3284 | |
duke@435 | 3285 | |
duke@435 | 3286 | void LIR_Assembler::emit_delay(LIR_OpDelay*) { |
duke@435 | 3287 | Unimplemented(); |
duke@435 | 3288 | } |
duke@435 | 3289 | |
duke@435 | 3290 | |
duke@435 | 3291 | void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { |
never@739 | 3292 | __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
duke@435 | 3293 | } |
duke@435 | 3294 | |
duke@435 | 3295 | |
duke@435 | 3296 | void LIR_Assembler::align_backward_branch_target() { |
duke@435 | 3297 | __ align(BytesPerWord); |
duke@435 | 3298 | } |
duke@435 | 3299 | |
duke@435 | 3300 | |
duke@435 | 3301 | void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { |
duke@435 | 3302 | if (left->is_single_cpu()) { |
duke@435 | 3303 | __ negl(left->as_register()); |
duke@435 | 3304 | move_regs(left->as_register(), dest->as_register()); |
duke@435 | 3305 | |
duke@435 | 3306 | } else if (left->is_double_cpu()) { |
duke@435 | 3307 | Register lo = left->as_register_lo(); |
never@739 | 3308 | #ifdef _LP64 |
never@739 | 3309 | Register dst = dest->as_register_lo(); |
never@739 | 3310 | __ movptr(dst, lo); |
never@739 | 3311 | __ negptr(dst); |
never@739 | 3312 | #else |
duke@435 | 3313 | Register hi = left->as_register_hi(); |
duke@435 | 3314 | __ lneg(hi, lo); |
duke@435 | 3315 | if (dest->as_register_lo() == hi) { |
duke@435 | 3316 | assert(dest->as_register_hi() != lo, "destroying register"); |
duke@435 | 3317 | move_regs(hi, dest->as_register_hi()); |
duke@435 | 3318 | move_regs(lo, dest->as_register_lo()); |
duke@435 | 3319 | } else { |
duke@435 | 3320 | move_regs(lo, dest->as_register_lo()); |
duke@435 | 3321 | move_regs(hi, dest->as_register_hi()); |
duke@435 | 3322 | } |
never@739 | 3323 | #endif // _LP64 |
duke@435 | 3324 | |
duke@435 | 3325 | } else if (dest->is_single_xmm()) { |
duke@435 | 3326 | if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { |
duke@435 | 3327 | __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); |
duke@435 | 3328 | } |
duke@435 | 3329 | __ xorps(dest->as_xmm_float_reg(), |
duke@435 | 3330 | ExternalAddress((address)float_signflip_pool)); |
duke@435 | 3331 | |
duke@435 | 3332 | } else if (dest->is_double_xmm()) { |
duke@435 | 3333 | if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { |
duke@435 | 3334 | __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); |
duke@435 | 3335 | } |
duke@435 | 3336 | __ xorpd(dest->as_xmm_double_reg(), |
duke@435 | 3337 | ExternalAddress((address)double_signflip_pool)); |
duke@435 | 3338 | |
duke@435 | 3339 | } else if (left->is_single_fpu() || left->is_double_fpu()) { |
duke@435 | 3340 | assert(left->fpu() == 0, "arg must be on TOS"); |
duke@435 | 3341 | assert(dest->fpu() == 0, "dest must be TOS"); |
duke@435 | 3342 | __ fchs(); |
duke@435 | 3343 | |
duke@435 | 3344 | } else { |
duke@435 | 3345 | ShouldNotReachHere(); |
duke@435 | 3346 | } |
duke@435 | 3347 | } |
duke@435 | 3348 | |
duke@435 | 3349 | |
duke@435 | 3350 | void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { |
duke@435 | 3351 | assert(addr->is_address() && dest->is_register(), "check"); |
never@739 | 3352 | Register reg; |
never@739 | 3353 | reg = dest->as_pointer_register(); |
never@739 | 3354 | __ lea(reg, as_Address(addr->as_address_ptr())); |
duke@435 | 3355 | } |
duke@435 | 3356 | |
duke@435 | 3357 | |
duke@435 | 3358 | |
duke@435 | 3359 | void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { |
duke@435 | 3360 | assert(!tmp->is_valid(), "don't need temporary"); |
duke@435 | 3361 | __ call(RuntimeAddress(dest)); |
duke@435 | 3362 | if (info != NULL) { |
duke@435 | 3363 | add_call_info_here(info); |
duke@435 | 3364 | } |
duke@435 | 3365 | } |
duke@435 | 3366 | |
duke@435 | 3367 | |
duke@435 | 3368 | void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { |
duke@435 | 3369 | assert(type == T_LONG, "only for volatile long fields"); |
duke@435 | 3370 | |
duke@435 | 3371 | if (info != NULL) { |
duke@435 | 3372 | add_debug_info_for_null_check_here(info); |
duke@435 | 3373 | } |
duke@435 | 3374 | |
duke@435 | 3375 | if (src->is_double_xmm()) { |
duke@435 | 3376 | if (dest->is_double_cpu()) { |
never@739 | 3377 | #ifdef _LP64 |
never@739 | 3378 | __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); |
never@739 | 3379 | #else |
never@739 | 3380 | __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); |
duke@435 | 3381 | __ psrlq(src->as_xmm_double_reg(), 32); |
never@739 | 3382 | __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
never@739 | 3383 | #endif // _LP64 |
duke@435 | 3384 | } else if (dest->is_double_stack()) { |
duke@435 | 3385 | __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); |
duke@435 | 3386 | } else if (dest->is_address()) { |
duke@435 | 3387 | __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); |
duke@435 | 3388 | } else { |
duke@435 | 3389 | ShouldNotReachHere(); |
duke@435 | 3390 | } |
duke@435 | 3391 | |
duke@435 | 3392 | } else if (dest->is_double_xmm()) { |
duke@435 | 3393 | if (src->is_double_stack()) { |
duke@435 | 3394 | __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); |
duke@435 | 3395 | } else if (src->is_address()) { |
duke@435 | 3396 | __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); |
duke@435 | 3397 | } else { |
duke@435 | 3398 | ShouldNotReachHere(); |
duke@435 | 3399 | } |
duke@435 | 3400 | |
duke@435 | 3401 | } else if (src->is_double_fpu()) { |
duke@435 | 3402 | assert(src->fpu_regnrLo() == 0, "must be TOS"); |
duke@435 | 3403 | if (dest->is_double_stack()) { |
duke@435 | 3404 | __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); |
duke@435 | 3405 | } else if (dest->is_address()) { |
duke@435 | 3406 | __ fistp_d(as_Address(dest->as_address_ptr())); |
duke@435 | 3407 | } else { |
duke@435 | 3408 | ShouldNotReachHere(); |
duke@435 | 3409 | } |
duke@435 | 3410 | |
duke@435 | 3411 | } else if (dest->is_double_fpu()) { |
duke@435 | 3412 | assert(dest->fpu_regnrLo() == 0, "must be TOS"); |
duke@435 | 3413 | if (src->is_double_stack()) { |
duke@435 | 3414 | __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); |
duke@435 | 3415 | } else if (src->is_address()) { |
duke@435 | 3416 | __ fild_d(as_Address(src->as_address_ptr())); |
duke@435 | 3417 | } else { |
duke@435 | 3418 | ShouldNotReachHere(); |
duke@435 | 3419 | } |
duke@435 | 3420 | } else { |
duke@435 | 3421 | ShouldNotReachHere(); |
duke@435 | 3422 | } |
duke@435 | 3423 | } |
duke@435 | 3424 | |
duke@435 | 3425 | |
duke@435 | 3426 | void LIR_Assembler::membar() { |
never@739 | 3427 | // QQQ sparc TSO uses this, |
never@739 | 3428 | __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); |
duke@435 | 3429 | } |
duke@435 | 3430 | |
duke@435 | 3431 | void LIR_Assembler::membar_acquire() { |
duke@435 | 3432 | // No x86 machines currently require load fences |
duke@435 | 3433 | // __ load_fence(); |
duke@435 | 3434 | } |
duke@435 | 3435 | |
duke@435 | 3436 | void LIR_Assembler::membar_release() { |
duke@435 | 3437 | // No x86 machines currently require store fences |
duke@435 | 3438 | // __ store_fence(); |
duke@435 | 3439 | } |
duke@435 | 3440 | |
duke@435 | 3441 | void LIR_Assembler::get_thread(LIR_Opr result_reg) { |
duke@435 | 3442 | assert(result_reg->is_register(), "check"); |
never@739 | 3443 | #ifdef _LP64 |
never@739 | 3444 | // __ get_thread(result_reg->as_register_lo()); |
never@739 | 3445 | __ mov(result_reg->as_register(), r15_thread); |
never@739 | 3446 | #else |
duke@435 | 3447 | __ get_thread(result_reg->as_register()); |
never@739 | 3448 | #endif // _LP64 |
duke@435 | 3449 | } |
duke@435 | 3450 | |
duke@435 | 3451 | |
duke@435 | 3452 | void LIR_Assembler::peephole(LIR_List*) { |
duke@435 | 3453 | // do nothing for now |
duke@435 | 3454 | } |
duke@435 | 3455 | |
duke@435 | 3456 | |
duke@435 | 3457 | #undef __ |