Wed, 15 Feb 2012 21:37:49 -0800
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
Summary: For C2 moved saving EBP after ESP adjustment. For C1 generated 5 byte nop instruction first if needed.
Reviewed-by: never, twisti, azeemj
duke@435 | 1 | /* |
phh@2423 | 2 | * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP |
stefank@2314 | 26 | #define CPU_X86_VM_ASSEMBLER_X86_HPP |
stefank@2314 | 27 | |
duke@435 | 28 | class BiasedLockingCounters; |
duke@435 | 29 | |
duke@435 | 30 | // Contains all the definitions needed for x86 assembly code generation. |
duke@435 | 31 | |
duke@435 | 32 | // Calling convention |
duke@435 | 33 | class Argument VALUE_OBJ_CLASS_SPEC { |
duke@435 | 34 | public: |
duke@435 | 35 | enum { |
duke@435 | 36 | #ifdef _LP64 |
duke@435 | 37 | #ifdef _WIN64 |
duke@435 | 38 | n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
duke@435 | 39 | n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) |
duke@435 | 40 | #else |
duke@435 | 41 | n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
duke@435 | 42 | n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) |
duke@435 | 43 | #endif // _WIN64 |
duke@435 | 44 | n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... |
duke@435 | 45 | n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... |
duke@435 | 46 | #else |
duke@435 | 47 | n_register_parameters = 0 // 0 registers used to pass arguments |
duke@435 | 48 | #endif // _LP64 |
duke@435 | 49 | }; |
duke@435 | 50 | }; |
duke@435 | 51 | |
duke@435 | 52 | |
duke@435 | 53 | #ifdef _LP64 |
duke@435 | 54 | // Symbolically name the register arguments used by the c calling convention. |
duke@435 | 55 | // Windows is different from linux/solaris. So much for standards... |
duke@435 | 56 | |
duke@435 | 57 | #ifdef _WIN64 |
duke@435 | 58 | |
duke@435 | 59 | REGISTER_DECLARATION(Register, c_rarg0, rcx); |
duke@435 | 60 | REGISTER_DECLARATION(Register, c_rarg1, rdx); |
duke@435 | 61 | REGISTER_DECLARATION(Register, c_rarg2, r8); |
duke@435 | 62 | REGISTER_DECLARATION(Register, c_rarg3, r9); |
duke@435 | 63 | |
never@739 | 64 | REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
never@739 | 65 | REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
never@739 | 66 | REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
never@739 | 67 | REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
duke@435 | 68 | |
duke@435 | 69 | #else |
duke@435 | 70 | |
duke@435 | 71 | REGISTER_DECLARATION(Register, c_rarg0, rdi); |
duke@435 | 72 | REGISTER_DECLARATION(Register, c_rarg1, rsi); |
duke@435 | 73 | REGISTER_DECLARATION(Register, c_rarg2, rdx); |
duke@435 | 74 | REGISTER_DECLARATION(Register, c_rarg3, rcx); |
duke@435 | 75 | REGISTER_DECLARATION(Register, c_rarg4, r8); |
duke@435 | 76 | REGISTER_DECLARATION(Register, c_rarg5, r9); |
duke@435 | 77 | |
never@739 | 78 | REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
never@739 | 79 | REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
never@739 | 80 | REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
never@739 | 81 | REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
never@739 | 82 | REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); |
never@739 | 83 | REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); |
never@739 | 84 | REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); |
never@739 | 85 | REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); |
duke@435 | 86 | |
duke@435 | 87 | #endif // _WIN64 |
duke@435 | 88 | |
duke@435 | 89 | // Symbolically name the register arguments used by the Java calling convention. |
duke@435 | 90 | // We have control over the convention for java so we can do what we please. |
duke@435 | 91 | // What pleases us is to offset the java calling convention so that when |
duke@435 | 92 | // we call a suitable jni method the arguments are lined up and we don't |
duke@435 | 93 | // have to do little shuffling. A suitable jni method is non-static and a |
duke@435 | 94 | // small number of arguments (two fewer args on windows) |
duke@435 | 95 | // |
duke@435 | 96 | // |-------------------------------------------------------| |
duke@435 | 97 | // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | |
duke@435 | 98 | // |-------------------------------------------------------| |
duke@435 | 99 | // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) |
duke@435 | 100 | // | rdi rsi rdx rcx r8 r9 | solaris/linux |
duke@435 | 101 | // |-------------------------------------------------------| |
duke@435 | 102 | // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | |
duke@435 | 103 | // |-------------------------------------------------------| |
duke@435 | 104 | |
duke@435 | 105 | REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); |
duke@435 | 106 | REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); |
duke@435 | 107 | REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); |
duke@435 | 108 | // Windows runs out of register args here |
duke@435 | 109 | #ifdef _WIN64 |
duke@435 | 110 | REGISTER_DECLARATION(Register, j_rarg3, rdi); |
duke@435 | 111 | REGISTER_DECLARATION(Register, j_rarg4, rsi); |
duke@435 | 112 | #else |
duke@435 | 113 | REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); |
duke@435 | 114 | REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); |
duke@435 | 115 | #endif /* _WIN64 */ |
duke@435 | 116 | REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); |
duke@435 | 117 | |
never@739 | 118 | REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
never@739 | 119 | REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); |
never@739 | 120 | REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); |
never@739 | 121 | REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); |
never@739 | 122 | REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); |
never@739 | 123 | REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); |
never@739 | 124 | REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); |
never@739 | 125 | REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); |
duke@435 | 126 | |
duke@435 | 127 | REGISTER_DECLARATION(Register, rscratch1, r10); // volatile |
duke@435 | 128 | REGISTER_DECLARATION(Register, rscratch2, r11); // volatile |
duke@435 | 129 | |
never@739 | 130 | REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
duke@435 | 131 | REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
duke@435 | 132 | |
never@739 | 133 | #else |
never@739 | 134 | // rscratch1 will apear in 32bit code that is dead but of course must compile |
never@739 | 135 | // Using noreg ensures if the dead code is incorrectly live and executed it |
never@739 | 136 | // will cause an assertion failure |
never@739 | 137 | #define rscratch1 noreg |
iveresov@2344 | 138 | #define rscratch2 noreg |
never@739 | 139 | |
duke@435 | 140 | #endif // _LP64 |
duke@435 | 141 | |
twisti@1919 | 142 | // JSR 292 fixed register usages: |
twisti@1919 | 143 | REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); |
twisti@1919 | 144 | |
duke@435 | 145 | // Address is an abstraction used to represent a memory location |
duke@435 | 146 | // using any of the amd64 addressing modes with one object. |
duke@435 | 147 | // |
duke@435 | 148 | // Note: A register location is represented via a Register, not |
duke@435 | 149 | // via an address for efficiency & simplicity reasons. |
duke@435 | 150 | |
duke@435 | 151 | class ArrayAddress; |
duke@435 | 152 | |
duke@435 | 153 | class Address VALUE_OBJ_CLASS_SPEC { |
duke@435 | 154 | public: |
duke@435 | 155 | enum ScaleFactor { |
duke@435 | 156 | no_scale = -1, |
duke@435 | 157 | times_1 = 0, |
duke@435 | 158 | times_2 = 1, |
duke@435 | 159 | times_4 = 2, |
never@739 | 160 | times_8 = 3, |
never@739 | 161 | times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) |
duke@435 | 162 | }; |
jrose@1057 | 163 | static ScaleFactor times(int size) { |
jrose@1057 | 164 | assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
jrose@1057 | 165 | if (size == 8) return times_8; |
jrose@1057 | 166 | if (size == 4) return times_4; |
jrose@1057 | 167 | if (size == 2) return times_2; |
jrose@1057 | 168 | return times_1; |
jrose@1057 | 169 | } |
jrose@1057 | 170 | static int scale_size(ScaleFactor scale) { |
jrose@1057 | 171 | assert(scale != no_scale, ""); |
jrose@1057 | 172 | assert(((1 << (int)times_1) == 1 && |
jrose@1057 | 173 | (1 << (int)times_2) == 2 && |
jrose@1057 | 174 | (1 << (int)times_4) == 4 && |
jrose@1057 | 175 | (1 << (int)times_8) == 8), ""); |
jrose@1057 | 176 | return (1 << (int)scale); |
jrose@1057 | 177 | } |
duke@435 | 178 | |
duke@435 | 179 | private: |
duke@435 | 180 | Register _base; |
duke@435 | 181 | Register _index; |
duke@435 | 182 | ScaleFactor _scale; |
duke@435 | 183 | int _disp; |
duke@435 | 184 | RelocationHolder _rspec; |
duke@435 | 185 | |
never@739 | 186 | // Easily misused constructors make them private |
never@739 | 187 | // %%% can we make these go away? |
never@739 | 188 | NOT_LP64(Address(address loc, RelocationHolder spec);) |
never@739 | 189 | Address(int disp, address loc, relocInfo::relocType rtype); |
never@739 | 190 | Address(int disp, address loc, RelocationHolder spec); |
duke@435 | 191 | |
duke@435 | 192 | public: |
never@739 | 193 | |
never@739 | 194 | int disp() { return _disp; } |
duke@435 | 195 | // creation |
duke@435 | 196 | Address() |
duke@435 | 197 | : _base(noreg), |
duke@435 | 198 | _index(noreg), |
duke@435 | 199 | _scale(no_scale), |
duke@435 | 200 | _disp(0) { |
duke@435 | 201 | } |
duke@435 | 202 | |
duke@435 | 203 | // No default displacement otherwise Register can be implicitly |
duke@435 | 204 | // converted to 0(Register) which is quite a different animal. |
duke@435 | 205 | |
duke@435 | 206 | Address(Register base, int disp) |
duke@435 | 207 | : _base(base), |
duke@435 | 208 | _index(noreg), |
duke@435 | 209 | _scale(no_scale), |
duke@435 | 210 | _disp(disp) { |
duke@435 | 211 | } |
duke@435 | 212 | |
duke@435 | 213 | Address(Register base, Register index, ScaleFactor scale, int disp = 0) |
duke@435 | 214 | : _base (base), |
duke@435 | 215 | _index(index), |
duke@435 | 216 | _scale(scale), |
duke@435 | 217 | _disp (disp) { |
duke@435 | 218 | assert(!index->is_valid() == (scale == Address::no_scale), |
duke@435 | 219 | "inconsistent address"); |
duke@435 | 220 | } |
duke@435 | 221 | |
jrose@1100 | 222 | Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
jrose@1057 | 223 | : _base (base), |
jrose@1057 | 224 | _index(index.register_or_noreg()), |
jrose@1057 | 225 | _scale(scale), |
jrose@1057 | 226 | _disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
jrose@1057 | 227 | if (!index.is_register()) scale = Address::no_scale; |
jrose@1057 | 228 | assert(!_index->is_valid() == (scale == Address::no_scale), |
jrose@1057 | 229 | "inconsistent address"); |
jrose@1057 | 230 | } |
jrose@1057 | 231 | |
jrose@1057 | 232 | Address plus_disp(int disp) const { |
jrose@1057 | 233 | Address a = (*this); |
jrose@1057 | 234 | a._disp += disp; |
jrose@1057 | 235 | return a; |
jrose@1057 | 236 | } |
never@2895 | 237 | Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { |
never@2895 | 238 | Address a = (*this); |
never@2895 | 239 | a._disp += disp.constant_or_zero() * scale_size(scale); |
never@2895 | 240 | if (disp.is_register()) { |
never@2895 | 241 | assert(!a.index()->is_valid(), "competing indexes"); |
never@2895 | 242 | a._index = disp.as_register(); |
never@2895 | 243 | a._scale = scale; |
never@2895 | 244 | } |
never@2895 | 245 | return a; |
never@2895 | 246 | } |
never@2895 | 247 | bool is_same_address(Address a) const { |
never@2895 | 248 | // disregard _rspec |
never@2895 | 249 | return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; |
never@2895 | 250 | } |
jrose@1057 | 251 | |
duke@435 | 252 | // The following two overloads are used in connection with the |
duke@435 | 253 | // ByteSize type (see sizes.hpp). They simplify the use of |
duke@435 | 254 | // ByteSize'd arguments in assembly code. Note that their equivalent |
duke@435 | 255 | // for the optimized build are the member functions with int disp |
duke@435 | 256 | // argument since ByteSize is mapped to an int type in that case. |
duke@435 | 257 | // |
duke@435 | 258 | // Note: DO NOT introduce similar overloaded functions for WordSize |
duke@435 | 259 | // arguments as in the optimized mode, both ByteSize and WordSize |
duke@435 | 260 | // are mapped to the same type and thus the compiler cannot make a |
duke@435 | 261 | // distinction anymore (=> compiler errors). |
duke@435 | 262 | |
duke@435 | 263 | #ifdef ASSERT |
duke@435 | 264 | Address(Register base, ByteSize disp) |
duke@435 | 265 | : _base(base), |
duke@435 | 266 | _index(noreg), |
duke@435 | 267 | _scale(no_scale), |
duke@435 | 268 | _disp(in_bytes(disp)) { |
duke@435 | 269 | } |
duke@435 | 270 | |
duke@435 | 271 | Address(Register base, Register index, ScaleFactor scale, ByteSize disp) |
duke@435 | 272 | : _base(base), |
duke@435 | 273 | _index(index), |
duke@435 | 274 | _scale(scale), |
duke@435 | 275 | _disp(in_bytes(disp)) { |
duke@435 | 276 | assert(!index->is_valid() == (scale == Address::no_scale), |
duke@435 | 277 | "inconsistent address"); |
duke@435 | 278 | } |
jrose@1057 | 279 | |
jrose@1100 | 280 | Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
jrose@1057 | 281 | : _base (base), |
jrose@1057 | 282 | _index(index.register_or_noreg()), |
jrose@1057 | 283 | _scale(scale), |
jrose@1057 | 284 | _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
jrose@1057 | 285 | if (!index.is_register()) scale = Address::no_scale; |
jrose@1057 | 286 | assert(!_index->is_valid() == (scale == Address::no_scale), |
jrose@1057 | 287 | "inconsistent address"); |
jrose@1057 | 288 | } |
jrose@1057 | 289 | |
duke@435 | 290 | #endif // ASSERT |
duke@435 | 291 | |
duke@435 | 292 | // accessors |
ysr@777 | 293 | bool uses(Register reg) const { return _base == reg || _index == reg; } |
ysr@777 | 294 | Register base() const { return _base; } |
ysr@777 | 295 | Register index() const { return _index; } |
ysr@777 | 296 | ScaleFactor scale() const { return _scale; } |
ysr@777 | 297 | int disp() const { return _disp; } |
duke@435 | 298 | |
duke@435 | 299 | // Convert the raw encoding form into the form expected by the constructor for |
duke@435 | 300 | // Address. An index of 4 (rsp) corresponds to having no index, so convert |
duke@435 | 301 | // that to noreg for the Address constructor. |
twisti@1059 | 302 | static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); |
duke@435 | 303 | |
duke@435 | 304 | static Address make_array(ArrayAddress); |
duke@435 | 305 | |
duke@435 | 306 | private: |
duke@435 | 307 | bool base_needs_rex() const { |
duke@435 | 308 | return _base != noreg && _base->encoding() >= 8; |
duke@435 | 309 | } |
duke@435 | 310 | |
duke@435 | 311 | bool index_needs_rex() const { |
duke@435 | 312 | return _index != noreg &&_index->encoding() >= 8; |
duke@435 | 313 | } |
duke@435 | 314 | |
duke@435 | 315 | relocInfo::relocType reloc() const { return _rspec.type(); } |
duke@435 | 316 | |
duke@435 | 317 | friend class Assembler; |
duke@435 | 318 | friend class MacroAssembler; |
duke@435 | 319 | friend class LIR_Assembler; // base/index/scale/disp |
duke@435 | 320 | }; |
duke@435 | 321 | |
duke@435 | 322 | // |
duke@435 | 323 | // AddressLiteral has been split out from Address because operands of this type |
duke@435 | 324 | // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out |
duke@435 | 325 | // the few instructions that need to deal with address literals are unique and the |
duke@435 | 326 | // MacroAssembler does not have to implement every instruction in the Assembler |
duke@435 | 327 | // in order to search for address literals that may need special handling depending |
duke@435 | 328 | // on the instruction and the platform. As small step on the way to merging i486/amd64 |
duke@435 | 329 | // directories. |
duke@435 | 330 | // |
duke@435 | 331 | class AddressLiteral VALUE_OBJ_CLASS_SPEC { |
duke@435 | 332 | friend class ArrayAddress; |
duke@435 | 333 | RelocationHolder _rspec; |
duke@435 | 334 | // Typically we use AddressLiterals we want to use their rval |
duke@435 | 335 | // However in some situations we want the lval (effect address) of the item. |
duke@435 | 336 | // We provide a special factory for making those lvals. |
duke@435 | 337 | bool _is_lval; |
duke@435 | 338 | |
duke@435 | 339 | // If the target is far we'll need to load the ea of this to |
duke@435 | 340 | // a register to reach it. Otherwise if near we can do rip |
duke@435 | 341 | // relative addressing. |
duke@435 | 342 | |
duke@435 | 343 | address _target; |
duke@435 | 344 | |
duke@435 | 345 | protected: |
duke@435 | 346 | // creation |
duke@435 | 347 | AddressLiteral() |
duke@435 | 348 | : _is_lval(false), |
duke@435 | 349 | _target(NULL) |
duke@435 | 350 | {} |
duke@435 | 351 | |
duke@435 | 352 | public: |
duke@435 | 353 | |
duke@435 | 354 | |
duke@435 | 355 | AddressLiteral(address target, relocInfo::relocType rtype); |
duke@435 | 356 | |
duke@435 | 357 | AddressLiteral(address target, RelocationHolder const& rspec) |
duke@435 | 358 | : _rspec(rspec), |
duke@435 | 359 | _is_lval(false), |
duke@435 | 360 | _target(target) |
duke@435 | 361 | {} |
duke@435 | 362 | |
duke@435 | 363 | AddressLiteral addr() { |
duke@435 | 364 | AddressLiteral ret = *this; |
duke@435 | 365 | ret._is_lval = true; |
duke@435 | 366 | return ret; |
duke@435 | 367 | } |
duke@435 | 368 | |
duke@435 | 369 | |
duke@435 | 370 | private: |
duke@435 | 371 | |
duke@435 | 372 | address target() { return _target; } |
duke@435 | 373 | bool is_lval() { return _is_lval; } |
duke@435 | 374 | |
duke@435 | 375 | relocInfo::relocType reloc() const { return _rspec.type(); } |
duke@435 | 376 | const RelocationHolder& rspec() const { return _rspec; } |
duke@435 | 377 | |
duke@435 | 378 | friend class Assembler; |
duke@435 | 379 | friend class MacroAssembler; |
duke@435 | 380 | friend class Address; |
duke@435 | 381 | friend class LIR_Assembler; |
duke@435 | 382 | }; |
duke@435 | 383 | |
duke@435 | 384 | // Convience classes |
duke@435 | 385 | class RuntimeAddress: public AddressLiteral { |
duke@435 | 386 | |
duke@435 | 387 | public: |
duke@435 | 388 | |
duke@435 | 389 | RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} |
duke@435 | 390 | |
duke@435 | 391 | }; |
duke@435 | 392 | |
duke@435 | 393 | class OopAddress: public AddressLiteral { |
duke@435 | 394 | |
duke@435 | 395 | public: |
duke@435 | 396 | |
duke@435 | 397 | OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} |
duke@435 | 398 | |
duke@435 | 399 | }; |
duke@435 | 400 | |
duke@435 | 401 | class ExternalAddress: public AddressLiteral { |
never@2737 | 402 | private: |
never@2737 | 403 | static relocInfo::relocType reloc_for_target(address target) { |
never@2737 | 404 | // Sometimes ExternalAddress is used for values which aren't |
never@2737 | 405 | // exactly addresses, like the card table base. |
never@2737 | 406 | // external_word_type can't be used for values in the first page |
never@2737 | 407 | // so just skip the reloc in that case. |
never@2737 | 408 | return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
never@2737 | 409 | } |
never@2737 | 410 | |
never@2737 | 411 | public: |
never@2737 | 412 | |
never@2737 | 413 | ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} |
duke@435 | 414 | |
duke@435 | 415 | }; |
duke@435 | 416 | |
duke@435 | 417 | class InternalAddress: public AddressLiteral { |
duke@435 | 418 | |
duke@435 | 419 | public: |
duke@435 | 420 | |
duke@435 | 421 | InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} |
duke@435 | 422 | |
duke@435 | 423 | }; |
duke@435 | 424 | |
duke@435 | 425 | // x86 can do array addressing as a single operation since disp can be an absolute |
duke@435 | 426 | // address amd64 can't. We create a class that expresses the concept but does extra |
duke@435 | 427 | // magic on amd64 to get the final result |
duke@435 | 428 | |
duke@435 | 429 | class ArrayAddress VALUE_OBJ_CLASS_SPEC { |
duke@435 | 430 | private: |
duke@435 | 431 | |
duke@435 | 432 | AddressLiteral _base; |
duke@435 | 433 | Address _index; |
duke@435 | 434 | |
duke@435 | 435 | public: |
duke@435 | 436 | |
duke@435 | 437 | ArrayAddress() {}; |
duke@435 | 438 | ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; |
duke@435 | 439 | AddressLiteral base() { return _base; } |
duke@435 | 440 | Address index() { return _index; } |
duke@435 | 441 | |
duke@435 | 442 | }; |
duke@435 | 443 | |
never@739 | 444 | const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
duke@435 | 445 | |
duke@435 | 446 | // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction |
duke@435 | 447 | // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write |
duke@435 | 448 | // is what you get. The Assembler is generating code into a CodeBuffer. |
duke@435 | 449 | |
duke@435 | 450 | class Assembler : public AbstractAssembler { |
duke@435 | 451 | friend class AbstractAssembler; // for the non-virtual hack |
duke@435 | 452 | friend class LIR_Assembler; // as_Address() |
never@739 | 453 | friend class StubGenerator; |
duke@435 | 454 | |
duke@435 | 455 | public: |
duke@435 | 456 | enum Condition { // The x86 condition codes used for conditional jumps/moves. |
duke@435 | 457 | zero = 0x4, |
duke@435 | 458 | notZero = 0x5, |
duke@435 | 459 | equal = 0x4, |
duke@435 | 460 | notEqual = 0x5, |
duke@435 | 461 | less = 0xc, |
duke@435 | 462 | lessEqual = 0xe, |
duke@435 | 463 | greater = 0xf, |
duke@435 | 464 | greaterEqual = 0xd, |
duke@435 | 465 | below = 0x2, |
duke@435 | 466 | belowEqual = 0x6, |
duke@435 | 467 | above = 0x7, |
duke@435 | 468 | aboveEqual = 0x3, |
duke@435 | 469 | overflow = 0x0, |
duke@435 | 470 | noOverflow = 0x1, |
duke@435 | 471 | carrySet = 0x2, |
duke@435 | 472 | carryClear = 0x3, |
duke@435 | 473 | negative = 0x8, |
duke@435 | 474 | positive = 0x9, |
duke@435 | 475 | parity = 0xa, |
duke@435 | 476 | noParity = 0xb |
duke@435 | 477 | }; |
duke@435 | 478 | |
duke@435 | 479 | enum Prefix { |
duke@435 | 480 | // segment overrides |
duke@435 | 481 | CS_segment = 0x2e, |
duke@435 | 482 | SS_segment = 0x36, |
duke@435 | 483 | DS_segment = 0x3e, |
duke@435 | 484 | ES_segment = 0x26, |
duke@435 | 485 | FS_segment = 0x64, |
duke@435 | 486 | GS_segment = 0x65, |
duke@435 | 487 | |
duke@435 | 488 | REX = 0x40, |
duke@435 | 489 | |
duke@435 | 490 | REX_B = 0x41, |
duke@435 | 491 | REX_X = 0x42, |
duke@435 | 492 | REX_XB = 0x43, |
duke@435 | 493 | REX_R = 0x44, |
duke@435 | 494 | REX_RB = 0x45, |
duke@435 | 495 | REX_RX = 0x46, |
duke@435 | 496 | REX_RXB = 0x47, |
duke@435 | 497 | |
duke@435 | 498 | REX_W = 0x48, |
duke@435 | 499 | |
duke@435 | 500 | REX_WB = 0x49, |
duke@435 | 501 | REX_WX = 0x4A, |
duke@435 | 502 | REX_WXB = 0x4B, |
duke@435 | 503 | REX_WR = 0x4C, |
duke@435 | 504 | REX_WRB = 0x4D, |
duke@435 | 505 | REX_WRX = 0x4E, |
kvn@3388 | 506 | REX_WRXB = 0x4F, |
kvn@3388 | 507 | |
kvn@3388 | 508 | VEX_3bytes = 0xC4, |
kvn@3388 | 509 | VEX_2bytes = 0xC5 |
kvn@3388 | 510 | }; |
kvn@3388 | 511 | |
kvn@3388 | 512 | enum VexPrefix { |
kvn@3388 | 513 | VEX_B = 0x20, |
kvn@3388 | 514 | VEX_X = 0x40, |
kvn@3388 | 515 | VEX_R = 0x80, |
kvn@3388 | 516 | VEX_W = 0x80 |
kvn@3388 | 517 | }; |
kvn@3388 | 518 | |
kvn@3388 | 519 | enum VexSimdPrefix { |
kvn@3388 | 520 | VEX_SIMD_NONE = 0x0, |
kvn@3388 | 521 | VEX_SIMD_66 = 0x1, |
kvn@3388 | 522 | VEX_SIMD_F3 = 0x2, |
kvn@3388 | 523 | VEX_SIMD_F2 = 0x3 |
kvn@3388 | 524 | }; |
kvn@3388 | 525 | |
kvn@3388 | 526 | enum VexOpcode { |
kvn@3388 | 527 | VEX_OPCODE_NONE = 0x0, |
kvn@3388 | 528 | VEX_OPCODE_0F = 0x1, |
kvn@3388 | 529 | VEX_OPCODE_0F_38 = 0x2, |
kvn@3388 | 530 | VEX_OPCODE_0F_3A = 0x3 |
duke@435 | 531 | }; |
duke@435 | 532 | |
duke@435 | 533 | enum WhichOperand { |
duke@435 | 534 | // input to locate_operand, and format code for relocations |
never@739 | 535 | imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
duke@435 | 536 | disp32_operand = 1, // embedded 32-bit displacement or address |
duke@435 | 537 | call32_operand = 2, // embedded 32-bit self-relative displacement |
never@739 | 538 | #ifndef _LP64 |
duke@435 | 539 | _WhichOperand_limit = 3 |
never@739 | 540 | #else |
never@739 | 541 | narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop |
never@739 | 542 | _WhichOperand_limit = 4 |
never@739 | 543 | #endif |
duke@435 | 544 | }; |
duke@435 | 545 | |
never@739 | 546 | |
never@739 | 547 | |
never@739 | 548 | // NOTE: The general philopsophy of the declarations here is that 64bit versions |
never@739 | 549 | // of instructions are freely declared without the need for wrapping them an ifdef. |
never@739 | 550 | // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) |
never@739 | 551 | // In the .cpp file the implementations are wrapped so that they are dropped out |
never@739 | 552 | // of the resulting jvm. This is done mostly to keep the footprint of KERNEL |
never@739 | 553 | // to the size it was prior to merging up the 32bit and 64bit assemblers. |
never@739 | 554 | // |
never@739 | 555 | // This does mean you'll get a linker/runtime error if you use a 64bit only instruction |
never@739 | 556 | // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. |
never@739 | 557 | |
never@739 | 558 | private: |
never@739 | 559 | |
never@739 | 560 | |
never@739 | 561 | // 64bit prefixes |
never@739 | 562 | int prefix_and_encode(int reg_enc, bool byteinst = false); |
never@739 | 563 | int prefixq_and_encode(int reg_enc); |
never@739 | 564 | |
never@739 | 565 | int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); |
never@739 | 566 | int prefixq_and_encode(int dst_enc, int src_enc); |
never@739 | 567 | |
never@739 | 568 | void prefix(Register reg); |
never@739 | 569 | void prefix(Address adr); |
never@739 | 570 | void prefixq(Address adr); |
never@739 | 571 | |
never@739 | 572 | void prefix(Address adr, Register reg, bool byteinst = false); |
kvn@3388 | 573 | void prefix(Address adr, XMMRegister reg); |
never@739 | 574 | void prefixq(Address adr, Register reg); |
kvn@3388 | 575 | void prefixq(Address adr, XMMRegister reg); |
never@739 | 576 | |
never@739 | 577 | void prefetch_prefix(Address src); |
never@739 | 578 | |
kvn@3388 | 579 | void rex_prefix(Address adr, XMMRegister xreg, |
kvn@3388 | 580 | VexSimdPrefix pre, VexOpcode opc, bool rex_w); |
kvn@3388 | 581 | int rex_prefix_and_encode(int dst_enc, int src_enc, |
kvn@3388 | 582 | VexSimdPrefix pre, VexOpcode opc, bool rex_w); |
kvn@3388 | 583 | |
kvn@3388 | 584 | void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, |
kvn@3388 | 585 | int nds_enc, VexSimdPrefix pre, VexOpcode opc, |
kvn@3388 | 586 | bool vector256); |
kvn@3388 | 587 | |
kvn@3388 | 588 | void vex_prefix(Address adr, int nds_enc, int xreg_enc, |
kvn@3388 | 589 | VexSimdPrefix pre, VexOpcode opc, |
kvn@3388 | 590 | bool vex_w, bool vector256); |
kvn@3388 | 591 | |
kvn@3390 | 592 | void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, |
kvn@3390 | 593 | VexSimdPrefix pre, bool vector256 = false) { |
kvn@3390 | 594 | vex_prefix(src, nds->encoding(), dst->encoding(), |
kvn@3390 | 595 | pre, VEX_OPCODE_0F, false, vector256); |
kvn@3390 | 596 | } |
kvn@3390 | 597 | |
kvn@3388 | 598 | int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, |
kvn@3388 | 599 | VexSimdPrefix pre, VexOpcode opc, |
kvn@3388 | 600 | bool vex_w, bool vector256); |
kvn@3388 | 601 | |
kvn@3390 | 602 | int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, |
kvn@3390 | 603 | VexSimdPrefix pre, bool vector256 = false) { |
kvn@3390 | 604 | return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), |
kvn@3390 | 605 | pre, VEX_OPCODE_0F, false, vector256); |
kvn@3390 | 606 | } |
kvn@3388 | 607 | |
kvn@3388 | 608 | void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, |
kvn@3388 | 609 | VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, |
kvn@3388 | 610 | bool rex_w = false, bool vector256 = false); |
kvn@3388 | 611 | |
kvn@3388 | 612 | void simd_prefix(XMMRegister dst, Address src, |
kvn@3388 | 613 | VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
kvn@3388 | 614 | simd_prefix(dst, xnoreg, src, pre, opc); |
kvn@3388 | 615 | } |
kvn@3388 | 616 | void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { |
kvn@3388 | 617 | simd_prefix(src, dst, pre); |
kvn@3388 | 618 | } |
kvn@3388 | 619 | void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, |
kvn@3388 | 620 | VexSimdPrefix pre) { |
kvn@3388 | 621 | bool rex_w = true; |
kvn@3388 | 622 | simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); |
kvn@3388 | 623 | } |
kvn@3388 | 624 | |
kvn@3388 | 625 | |
kvn@3388 | 626 | int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, |
kvn@3388 | 627 | VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, |
kvn@3388 | 628 | bool rex_w = false, bool vector256 = false); |
kvn@3388 | 629 | |
kvn@3388 | 630 | int simd_prefix_and_encode(XMMRegister dst, XMMRegister src, |
kvn@3388 | 631 | VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
kvn@3388 | 632 | return simd_prefix_and_encode(dst, xnoreg, src, pre, opc); |
kvn@3388 | 633 | } |
kvn@3388 | 634 | |
kvn@3388 | 635 | // Move/convert 32-bit integer value. |
kvn@3388 | 636 | int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, |
kvn@3388 | 637 | VexSimdPrefix pre) { |
kvn@3388 | 638 | // It is OK to cast from Register to XMMRegister to pass argument here |
kvn@3388 | 639 | // since only encoding is used in simd_prefix_and_encode() and number of |
kvn@3388 | 640 | // Gen and Xmm registers are the same. |
kvn@3388 | 641 | return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); |
kvn@3388 | 642 | } |
kvn@3388 | 643 | int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { |
kvn@3388 | 644 | return simd_prefix_and_encode(dst, xnoreg, src, pre); |
kvn@3388 | 645 | } |
kvn@3388 | 646 | int simd_prefix_and_encode(Register dst, XMMRegister src, |
kvn@3388 | 647 | VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
kvn@3388 | 648 | return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); |
kvn@3388 | 649 | } |
kvn@3388 | 650 | |
kvn@3388 | 651 | // Move/convert 64-bit integer value. |
kvn@3388 | 652 | int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, |
kvn@3388 | 653 | VexSimdPrefix pre) { |
kvn@3388 | 654 | bool rex_w = true; |
kvn@3388 | 655 | return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); |
kvn@3388 | 656 | } |
kvn@3388 | 657 | int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { |
kvn@3388 | 658 | return simd_prefix_and_encode_q(dst, xnoreg, src, pre); |
kvn@3388 | 659 | } |
kvn@3388 | 660 | int simd_prefix_and_encode_q(Register dst, XMMRegister src, |
kvn@3388 | 661 | VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
kvn@3388 | 662 | bool rex_w = true; |
kvn@3388 | 663 | return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); |
kvn@3388 | 664 | } |
kvn@3388 | 665 | |
never@739 | 666 | // Helper functions for groups of instructions |
never@739 | 667 | void emit_arith_b(int op1, int op2, Register dst, int imm8); |
never@739 | 668 | |
never@739 | 669 | void emit_arith(int op1, int op2, Register dst, int32_t imm32); |
kvn@3574 | 670 | // Force generation of a 4 byte immediate value even if it fits into 8bit |
kvn@3574 | 671 | void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); |
never@739 | 672 | // only 32bit?? |
never@739 | 673 | void emit_arith(int op1, int op2, Register dst, jobject obj); |
never@739 | 674 | void emit_arith(int op1, int op2, Register dst, Register src); |
never@739 | 675 | |
never@739 | 676 | void emit_operand(Register reg, |
never@739 | 677 | Register base, Register index, Address::ScaleFactor scale, |
never@739 | 678 | int disp, |
never@739 | 679 | RelocationHolder const& rspec, |
never@739 | 680 | int rip_relative_correction = 0); |
never@739 | 681 | |
never@739 | 682 | void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); |
never@739 | 683 | |
never@739 | 684 | // operands that only take the original 32bit registers |
never@739 | 685 | void emit_operand32(Register reg, Address adr); |
never@739 | 686 | |
never@739 | 687 | void emit_operand(XMMRegister reg, |
never@739 | 688 | Register base, Register index, Address::ScaleFactor scale, |
never@739 | 689 | int disp, |
never@739 | 690 | RelocationHolder const& rspec); |
never@739 | 691 | |
never@739 | 692 | void emit_operand(XMMRegister reg, Address adr); |
never@739 | 693 | |
never@739 | 694 | void emit_operand(MMXRegister reg, Address adr); |
never@739 | 695 | |
never@739 | 696 | // workaround gcc (3.2.1-7) bug |
never@739 | 697 | void emit_operand(Address adr, MMXRegister reg); |
never@739 | 698 | |
never@739 | 699 | |
never@739 | 700 | // Immediate-to-memory forms |
never@739 | 701 | void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); |
never@739 | 702 | |
never@739 | 703 | void emit_farith(int b1, int b2, int i); |
never@739 | 704 | |
duke@435 | 705 | |
duke@435 | 706 | protected: |
never@739 | 707 | #ifdef ASSERT |
never@739 | 708 | void check_relocation(RelocationHolder const& rspec, int format); |
never@739 | 709 | #endif |
never@739 | 710 | |
never@739 | 711 | inline void emit_long64(jlong x); |
never@739 | 712 | |
never@739 | 713 | void emit_data(jint data, relocInfo::relocType rtype, int format); |
never@739 | 714 | void emit_data(jint data, RelocationHolder const& rspec, int format); |
never@739 | 715 | void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); |
never@739 | 716 | void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); |
never@739 | 717 | |
never@739 | 718 | bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); |
never@739 | 719 | |
never@739 | 720 | // These are all easily abused and hence protected |
never@739 | 721 | |
never@739 | 722 | // 32BIT ONLY SECTION |
never@739 | 723 | #ifndef _LP64 |
never@739 | 724 | // Make these disappear in 64bit mode since they would never be correct |
never@739 | 725 | void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
never@739 | 726 | void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
never@739 | 727 | |
kvn@1077 | 728 | void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
never@739 | 729 | void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
never@739 | 730 | |
never@739 | 731 | void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
never@739 | 732 | #else |
never@739 | 733 | // 64BIT ONLY SECTION |
never@739 | 734 | void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY |
kvn@1077 | 735 | |
kvn@1077 | 736 | void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
kvn@1077 | 737 | void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
kvn@1077 | 738 | |
kvn@1077 | 739 | void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
kvn@1077 | 740 | void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
never@739 | 741 | #endif // _LP64 |
never@739 | 742 | |
never@739 | 743 | // These are unique in that we are ensured by the caller that the 32bit |
never@739 | 744 | // relative in these instructions will always be able to reach the potentially |
never@739 | 745 | // 64bit address described by entry. Since they can take a 64bit address they |
never@739 | 746 | // don't have the 32 suffix like the other instructions in this class. |
never@739 | 747 | |
never@739 | 748 | void call_literal(address entry, RelocationHolder const& rspec); |
never@739 | 749 | void jmp_literal(address entry, RelocationHolder const& rspec); |
never@739 | 750 | |
never@739 | 751 | // Avoid using directly section |
never@739 | 752 | // Instructions in this section are actually usable by anyone without danger |
never@739 | 753 | // of failure but have performance issues that are addressed my enhanced |
never@739 | 754 | // instructions which will do the proper thing base on the particular cpu. |
never@739 | 755 | // We protect them because we don't trust you... |
never@739 | 756 | |
duke@435 | 757 | // Don't use next inc() and dec() methods directly. INC & DEC instructions |
duke@435 | 758 | // could cause a partial flag stall since they don't set CF flag. |
duke@435 | 759 | // Use MacroAssembler::decrement() & MacroAssembler::increment() methods |
duke@435 | 760 | // which call inc() & dec() or add() & sub() in accordance with |
duke@435 | 761 | // the product flag UseIncDec value. |
duke@435 | 762 | |
duke@435 | 763 | void decl(Register dst); |
duke@435 | 764 | void decl(Address dst); |
never@739 | 765 | void decq(Register dst); |
never@739 | 766 | void decq(Address dst); |
duke@435 | 767 | |
duke@435 | 768 | void incl(Register dst); |
duke@435 | 769 | void incl(Address dst); |
never@739 | 770 | void incq(Register dst); |
never@739 | 771 | void incq(Address dst); |
never@739 | 772 | |
never@739 | 773 | // New cpus require use of movsd and movss to avoid partial register stall |
never@739 | 774 | // when loading from memory. But for old Opteron use movlpd instead of movsd. |
never@739 | 775 | // The selection is done in MacroAssembler::movdbl() and movflt(). |
never@739 | 776 | |
never@739 | 777 | // Move Scalar Single-Precision Floating-Point Values |
never@739 | 778 | void movss(XMMRegister dst, Address src); |
never@739 | 779 | void movss(XMMRegister dst, XMMRegister src); |
never@739 | 780 | void movss(Address dst, XMMRegister src); |
never@739 | 781 | |
never@739 | 782 | // Move Scalar Double-Precision Floating-Point Values |
never@739 | 783 | void movsd(XMMRegister dst, Address src); |
never@739 | 784 | void movsd(XMMRegister dst, XMMRegister src); |
never@739 | 785 | void movsd(Address dst, XMMRegister src); |
never@739 | 786 | void movlpd(XMMRegister dst, Address src); |
never@739 | 787 | |
never@739 | 788 | // New cpus require use of movaps and movapd to avoid partial register stall |
never@739 | 789 | // when moving between registers. |
never@739 | 790 | void movaps(XMMRegister dst, XMMRegister src); |
never@739 | 791 | void movapd(XMMRegister dst, XMMRegister src); |
never@739 | 792 | |
never@739 | 793 | // End avoid using directly |
never@739 | 794 | |
never@739 | 795 | |
never@739 | 796 | // Instruction prefixes |
never@739 | 797 | void prefix(Prefix p); |
never@739 | 798 | |
never@739 | 799 | public: |
never@739 | 800 | |
never@739 | 801 | // Creation |
never@739 | 802 | Assembler(CodeBuffer* code) : AbstractAssembler(code) {} |
never@739 | 803 | |
never@739 | 804 | // Decoding |
never@739 | 805 | static address locate_operand(address inst, WhichOperand which); |
never@739 | 806 | static address locate_next_instruction(address inst); |
never@739 | 807 | |
never@739 | 808 | // Utilities |
iveresov@2686 | 809 | static bool is_polling_page_far() NOT_LP64({ return false;}); |
iveresov@2686 | 810 | |
never@739 | 811 | // Generic instructions |
never@739 | 812 | // Does 32bit or 64bit as needed for the platform. In some sense these |
never@739 | 813 | // belong in macro assembler but there is no need for both varieties to exist |
never@739 | 814 | |
never@739 | 815 | void lea(Register dst, Address src); |
never@739 | 816 | |
never@739 | 817 | void mov(Register dst, Register src); |
never@739 | 818 | |
never@739 | 819 | void pusha(); |
never@739 | 820 | void popa(); |
never@739 | 821 | |
never@739 | 822 | void pushf(); |
never@739 | 823 | void popf(); |
never@739 | 824 | |
never@739 | 825 | void push(int32_t imm32); |
never@739 | 826 | |
never@739 | 827 | void push(Register src); |
never@739 | 828 | |
never@739 | 829 | void pop(Register dst); |
never@739 | 830 | |
never@739 | 831 | // These are dummies to prevent surprise implicit conversions to Register |
never@739 | 832 | void push(void* v); |
never@739 | 833 | void pop(void* v); |
never@739 | 834 | |
never@739 | 835 | // These do register sized moves/scans |
never@739 | 836 | void rep_mov(); |
never@739 | 837 | void rep_set(); |
never@739 | 838 | void repne_scan(); |
never@739 | 839 | #ifdef _LP64 |
never@739 | 840 | void repne_scanl(); |
never@739 | 841 | #endif |
never@739 | 842 | |
never@739 | 843 | // Vanilla instructions in lexical order |
never@739 | 844 | |
phh@2423 | 845 | void adcl(Address dst, int32_t imm32); |
phh@2423 | 846 | void adcl(Address dst, Register src); |
never@739 | 847 | void adcl(Register dst, int32_t imm32); |
never@739 | 848 | void adcl(Register dst, Address src); |
never@739 | 849 | void adcl(Register dst, Register src); |
never@739 | 850 | |
never@739 | 851 | void adcq(Register dst, int32_t imm32); |
never@739 | 852 | void adcq(Register dst, Address src); |
never@739 | 853 | void adcq(Register dst, Register src); |
never@739 | 854 | |
never@739 | 855 | void addl(Address dst, int32_t imm32); |
never@739 | 856 | void addl(Address dst, Register src); |
never@739 | 857 | void addl(Register dst, int32_t imm32); |
never@739 | 858 | void addl(Register dst, Address src); |
never@739 | 859 | void addl(Register dst, Register src); |
never@739 | 860 | |
never@739 | 861 | void addq(Address dst, int32_t imm32); |
never@739 | 862 | void addq(Address dst, Register src); |
never@739 | 863 | void addq(Register dst, int32_t imm32); |
never@739 | 864 | void addq(Register dst, Address src); |
never@739 | 865 | void addq(Register dst, Register src); |
never@739 | 866 | |
duke@435 | 867 | void addr_nop_4(); |
duke@435 | 868 | void addr_nop_5(); |
duke@435 | 869 | void addr_nop_7(); |
duke@435 | 870 | void addr_nop_8(); |
duke@435 | 871 | |
never@739 | 872 | // Add Scalar Double-Precision Floating-Point Values |
never@739 | 873 | void addsd(XMMRegister dst, Address src); |
never@739 | 874 | void addsd(XMMRegister dst, XMMRegister src); |
never@739 | 875 | |
never@739 | 876 | // Add Scalar Single-Precision Floating-Point Values |
never@739 | 877 | void addss(XMMRegister dst, Address src); |
never@739 | 878 | void addss(XMMRegister dst, XMMRegister src); |
never@739 | 879 | |
kvn@3388 | 880 | void andl(Address dst, int32_t imm32); |
never@739 | 881 | void andl(Register dst, int32_t imm32); |
never@739 | 882 | void andl(Register dst, Address src); |
never@739 | 883 | void andl(Register dst, Register src); |
never@739 | 884 | |
never@2980 | 885 | void andq(Address dst, int32_t imm32); |
never@739 | 886 | void andq(Register dst, int32_t imm32); |
never@739 | 887 | void andq(Register dst, Address src); |
never@739 | 888 | void andq(Register dst, Register src); |
never@739 | 889 | |
never@739 | 890 | // Bitwise Logical AND of Packed Double-Precision Floating-Point Values |
never@739 | 891 | void andpd(XMMRegister dst, XMMRegister src); |
never@739 | 892 | |
kvn@3388 | 893 | // Bitwise Logical AND of Packed Single-Precision Floating-Point Values |
kvn@3388 | 894 | void andps(XMMRegister dst, XMMRegister src); |
kvn@3388 | 895 | |
twisti@1210 | 896 | void bsfl(Register dst, Register src); |
twisti@1210 | 897 | void bsrl(Register dst, Register src); |
twisti@1210 | 898 | |
twisti@1210 | 899 | #ifdef _LP64 |
twisti@1210 | 900 | void bsfq(Register dst, Register src); |
twisti@1210 | 901 | void bsrq(Register dst, Register src); |
twisti@1210 | 902 | #endif |
twisti@1210 | 903 | |
never@739 | 904 | void bswapl(Register reg); |
never@739 | 905 | |
never@739 | 906 | void bswapq(Register reg); |
never@739 | 907 | |
duke@435 | 908 | void call(Label& L, relocInfo::relocType rtype); |
duke@435 | 909 | void call(Register reg); // push pc; pc <- reg |
duke@435 | 910 | void call(Address adr); // push pc; pc <- adr |
duke@435 | 911 | |
never@739 | 912 | void cdql(); |
never@739 | 913 | |
never@739 | 914 | void cdqq(); |
never@739 | 915 | |
never@739 | 916 | void cld() { emit_byte(0xfc); } |
never@739 | 917 | |
never@739 | 918 | void clflush(Address adr); |
never@739 | 919 | |
never@739 | 920 | void cmovl(Condition cc, Register dst, Register src); |
never@739 | 921 | void cmovl(Condition cc, Register dst, Address src); |
never@739 | 922 | |
never@739 | 923 | void cmovq(Condition cc, Register dst, Register src); |
never@739 | 924 | void cmovq(Condition cc, Register dst, Address src); |
never@739 | 925 | |
never@739 | 926 | |
never@739 | 927 | void cmpb(Address dst, int imm8); |
never@739 | 928 | |
never@739 | 929 | void cmpl(Address dst, int32_t imm32); |
never@739 | 930 | |
never@739 | 931 | void cmpl(Register dst, int32_t imm32); |
never@739 | 932 | void cmpl(Register dst, Register src); |
never@739 | 933 | void cmpl(Register dst, Address src); |
never@739 | 934 | |
never@739 | 935 | void cmpq(Address dst, int32_t imm32); |
never@739 | 936 | void cmpq(Address dst, Register src); |
never@739 | 937 | |
never@739 | 938 | void cmpq(Register dst, int32_t imm32); |
never@739 | 939 | void cmpq(Register dst, Register src); |
never@739 | 940 | void cmpq(Register dst, Address src); |
never@739 | 941 | |
never@739 | 942 | // these are dummies used to catch attempting to convert NULL to Register |
never@739 | 943 | void cmpl(Register dst, void* junk); // dummy |
never@739 | 944 | void cmpq(Register dst, void* junk); // dummy |
never@739 | 945 | |
never@739 | 946 | void cmpw(Address dst, int imm16); |
never@739 | 947 | |
never@739 | 948 | void cmpxchg8 (Address adr); |
never@739 | 949 | |
never@739 | 950 | void cmpxchgl(Register reg, Address adr); |
never@739 | 951 | |
never@739 | 952 | void cmpxchgq(Register reg, Address adr); |
never@739 | 953 | |
never@739 | 954 | // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS |
never@739 | 955 | void comisd(XMMRegister dst, Address src); |
kvn@3388 | 956 | void comisd(XMMRegister dst, XMMRegister src); |
never@739 | 957 | |
never@739 | 958 | // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
never@739 | 959 | void comiss(XMMRegister dst, Address src); |
kvn@3388 | 960 | void comiss(XMMRegister dst, XMMRegister src); |
never@739 | 961 | |
never@739 | 962 | // Identify processor type and features |
never@739 | 963 | void cpuid() { |
never@739 | 964 | emit_byte(0x0F); |
never@739 | 965 | emit_byte(0xA2); |
never@739 | 966 | } |
never@739 | 967 | |
never@739 | 968 | // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value |
never@739 | 969 | void cvtsd2ss(XMMRegister dst, XMMRegister src); |
kvn@3388 | 970 | void cvtsd2ss(XMMRegister dst, Address src); |
never@739 | 971 | |
never@739 | 972 | // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value |
never@739 | 973 | void cvtsi2sdl(XMMRegister dst, Register src); |
kvn@3388 | 974 | void cvtsi2sdl(XMMRegister dst, Address src); |
never@739 | 975 | void cvtsi2sdq(XMMRegister dst, Register src); |
kvn@3388 | 976 | void cvtsi2sdq(XMMRegister dst, Address src); |
never@739 | 977 | |
never@739 | 978 | // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value |
never@739 | 979 | void cvtsi2ssl(XMMRegister dst, Register src); |
kvn@3388 | 980 | void cvtsi2ssl(XMMRegister dst, Address src); |
never@739 | 981 | void cvtsi2ssq(XMMRegister dst, Register src); |
kvn@3388 | 982 | void cvtsi2ssq(XMMRegister dst, Address src); |
never@739 | 983 | |
never@739 | 984 | // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value |
never@739 | 985 | void cvtdq2pd(XMMRegister dst, XMMRegister src); |
never@739 | 986 | |
never@739 | 987 | // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value |
never@739 | 988 | void cvtdq2ps(XMMRegister dst, XMMRegister src); |
never@739 | 989 | |
never@739 | 990 | // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value |
never@739 | 991 | void cvtss2sd(XMMRegister dst, XMMRegister src); |
kvn@3388 | 992 | void cvtss2sd(XMMRegister dst, Address src); |
never@739 | 993 | |
never@739 | 994 | // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer |
never@739 | 995 | void cvttsd2sil(Register dst, Address src); |
never@739 | 996 | void cvttsd2sil(Register dst, XMMRegister src); |
never@739 | 997 | void cvttsd2siq(Register dst, XMMRegister src); |
never@739 | 998 | |
never@739 | 999 | // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer |
never@739 | 1000 | void cvttss2sil(Register dst, XMMRegister src); |
never@739 | 1001 | void cvttss2siq(Register dst, XMMRegister src); |
never@739 | 1002 | |
never@739 | 1003 | // Divide Scalar Double-Precision Floating-Point Values |
never@739 | 1004 | void divsd(XMMRegister dst, Address src); |
never@739 | 1005 | void divsd(XMMRegister dst, XMMRegister src); |
never@739 | 1006 | |
never@739 | 1007 | // Divide Scalar Single-Precision Floating-Point Values |
never@739 | 1008 | void divss(XMMRegister dst, Address src); |
never@739 | 1009 | void divss(XMMRegister dst, XMMRegister src); |
never@739 | 1010 | |
never@739 | 1011 | void emms(); |
never@739 | 1012 | |
never@739 | 1013 | void fabs(); |
never@739 | 1014 | |
never@739 | 1015 | void fadd(int i); |
never@739 | 1016 | |
never@739 | 1017 | void fadd_d(Address src); |
never@739 | 1018 | void fadd_s(Address src); |
never@739 | 1019 | |
never@739 | 1020 | // "Alternate" versions of x87 instructions place result down in FPU |
never@739 | 1021 | // stack instead of on TOS |
never@739 | 1022 | |
never@739 | 1023 | void fadda(int i); // "alternate" fadd |
never@739 | 1024 | void faddp(int i = 1); |
never@739 | 1025 | |
never@739 | 1026 | void fchs(); |
never@739 | 1027 | |
never@739 | 1028 | void fcom(int i); |
never@739 | 1029 | |
never@739 | 1030 | void fcomp(int i = 1); |
never@739 | 1031 | void fcomp_d(Address src); |
never@739 | 1032 | void fcomp_s(Address src); |
never@739 | 1033 | |
never@739 | 1034 | void fcompp(); |
never@739 | 1035 | |
never@739 | 1036 | void fcos(); |
never@739 | 1037 | |
never@739 | 1038 | void fdecstp(); |
never@739 | 1039 | |
never@739 | 1040 | void fdiv(int i); |
never@739 | 1041 | void fdiv_d(Address src); |
never@739 | 1042 | void fdivr_s(Address src); |
never@739 | 1043 | void fdiva(int i); // "alternate" fdiv |
never@739 | 1044 | void fdivp(int i = 1); |
never@739 | 1045 | |
never@739 | 1046 | void fdivr(int i); |
never@739 | 1047 | void fdivr_d(Address src); |
never@739 | 1048 | void fdiv_s(Address src); |
never@739 | 1049 | |
never@739 | 1050 | void fdivra(int i); // "alternate" reversed fdiv |
never@739 | 1051 | |
never@739 | 1052 | void fdivrp(int i = 1); |
never@739 | 1053 | |
never@739 | 1054 | void ffree(int i = 0); |
never@739 | 1055 | |
never@739 | 1056 | void fild_d(Address adr); |
never@739 | 1057 | void fild_s(Address adr); |
never@739 | 1058 | |
never@739 | 1059 | void fincstp(); |
never@739 | 1060 | |
never@739 | 1061 | void finit(); |
never@739 | 1062 | |
never@739 | 1063 | void fist_s (Address adr); |
never@739 | 1064 | void fistp_d(Address adr); |
never@739 | 1065 | void fistp_s(Address adr); |
never@739 | 1066 | |
never@739 | 1067 | void fld1(); |
never@739 | 1068 | |
never@739 | 1069 | void fld_d(Address adr); |
never@739 | 1070 | void fld_s(Address adr); |
never@739 | 1071 | void fld_s(int index); |
never@739 | 1072 | void fld_x(Address adr); // extended-precision (80-bit) format |
never@739 | 1073 | |
never@739 | 1074 | void fldcw(Address src); |
never@739 | 1075 | |
never@739 | 1076 | void fldenv(Address src); |
never@739 | 1077 | |
never@739 | 1078 | void fldlg2(); |
never@739 | 1079 | |
never@739 | 1080 | void fldln2(); |
never@739 | 1081 | |
never@739 | 1082 | void fldz(); |
never@739 | 1083 | |
never@739 | 1084 | void flog(); |
never@739 | 1085 | void flog10(); |
never@739 | 1086 | |
never@739 | 1087 | void fmul(int i); |
never@739 | 1088 | |
never@739 | 1089 | void fmul_d(Address src); |
never@739 | 1090 | void fmul_s(Address src); |
never@739 | 1091 | |
never@739 | 1092 | void fmula(int i); // "alternate" fmul |
never@739 | 1093 | |
never@739 | 1094 | void fmulp(int i = 1); |
never@739 | 1095 | |
never@739 | 1096 | void fnsave(Address dst); |
never@739 | 1097 | |
never@739 | 1098 | void fnstcw(Address src); |
never@739 | 1099 | |
never@739 | 1100 | void fnstsw_ax(); |
never@739 | 1101 | |
never@739 | 1102 | void fprem(); |
never@739 | 1103 | void fprem1(); |
never@739 | 1104 | |
never@739 | 1105 | void frstor(Address src); |
never@739 | 1106 | |
never@739 | 1107 | void fsin(); |
never@739 | 1108 | |
never@739 | 1109 | void fsqrt(); |
never@739 | 1110 | |
never@739 | 1111 | void fst_d(Address adr); |
never@739 | 1112 | void fst_s(Address adr); |
never@739 | 1113 | |
never@739 | 1114 | void fstp_d(Address adr); |
never@739 | 1115 | void fstp_d(int index); |
never@739 | 1116 | void fstp_s(Address adr); |
never@739 | 1117 | void fstp_x(Address adr); // extended-precision (80-bit) format |
never@739 | 1118 | |
never@739 | 1119 | void fsub(int i); |
never@739 | 1120 | void fsub_d(Address src); |
never@739 | 1121 | void fsub_s(Address src); |
never@739 | 1122 | |
never@739 | 1123 | void fsuba(int i); // "alternate" fsub |
never@739 | 1124 | |
never@739 | 1125 | void fsubp(int i = 1); |
never@739 | 1126 | |
never@739 | 1127 | void fsubr(int i); |
never@739 | 1128 | void fsubr_d(Address src); |
never@739 | 1129 | void fsubr_s(Address src); |
never@739 | 1130 | |
never@739 | 1131 | void fsubra(int i); // "alternate" reversed fsub |
never@739 | 1132 | |
never@739 | 1133 | void fsubrp(int i = 1); |
never@739 | 1134 | |
never@739 | 1135 | void ftan(); |
never@739 | 1136 | |
never@739 | 1137 | void ftst(); |
never@739 | 1138 | |
never@739 | 1139 | void fucomi(int i = 1); |
never@739 | 1140 | void fucomip(int i = 1); |
never@739 | 1141 | |
never@739 | 1142 | void fwait(); |
never@739 | 1143 | |
never@739 | 1144 | void fxch(int i = 1); |
never@739 | 1145 | |
never@739 | 1146 | void fxrstor(Address src); |
never@739 | 1147 | |
never@739 | 1148 | void fxsave(Address dst); |
never@739 | 1149 | |
never@739 | 1150 | void fyl2x(); |
never@739 | 1151 | |
never@739 | 1152 | void hlt(); |
never@739 | 1153 | |
never@739 | 1154 | void idivl(Register src); |
kvn@2275 | 1155 | void divl(Register src); // Unsigned division |
never@739 | 1156 | |
never@739 | 1157 | void idivq(Register src); |
never@739 | 1158 | |
never@739 | 1159 | void imull(Register dst, Register src); |
never@739 | 1160 | void imull(Register dst, Register src, int value); |
never@739 | 1161 | |
never@739 | 1162 | void imulq(Register dst, Register src); |
never@739 | 1163 | void imulq(Register dst, Register src, int value); |
never@739 | 1164 | |
duke@435 | 1165 | |
duke@435 | 1166 | // jcc is the generic conditional branch generator to run- |
duke@435 | 1167 | // time routines, jcc is used for branches to labels. jcc |
duke@435 | 1168 | // takes a branch opcode (cc) and a label (L) and generates |
duke@435 | 1169 | // either a backward branch or a forward branch and links it |
duke@435 | 1170 | // to the label fixup chain. Usage: |
duke@435 | 1171 | // |
duke@435 | 1172 | // Label L; // unbound label |
duke@435 | 1173 | // jcc(cc, L); // forward branch to unbound label |
duke@435 | 1174 | // bind(L); // bind label to the current pc |
duke@435 | 1175 | // jcc(cc, L); // backward branch to bound label |
duke@435 | 1176 | // bind(L); // illegal: a label may be bound only once |
duke@435 | 1177 | // |
duke@435 | 1178 | // Note: The same Label can be used for forward and backward branches |
duke@435 | 1179 | // but it may be bound only once. |
duke@435 | 1180 | |
kvn@3049 | 1181 | void jcc(Condition cc, Label& L, bool maybe_short = true); |
duke@435 | 1182 | |
duke@435 | 1183 | // Conditional jump to a 8-bit offset to L. |
duke@435 | 1184 | // WARNING: be very careful using this for forward jumps. If the label is |
duke@435 | 1185 | // not bound within an 8-bit offset of this instruction, a run-time error |
duke@435 | 1186 | // will occur. |
duke@435 | 1187 | void jccb(Condition cc, Label& L); |
duke@435 | 1188 | |
never@739 | 1189 | void jmp(Address entry); // pc <- entry |
never@739 | 1190 | |
never@739 | 1191 | // Label operations & relative jumps (PPUM Appendix D) |
kvn@3049 | 1192 | void jmp(Label& L, bool maybe_short = true); // unconditional jump to L |
never@739 | 1193 | |
never@739 | 1194 | void jmp(Register entry); // pc <- entry |
never@739 | 1195 | |
never@739 | 1196 | // Unconditional 8-bit offset jump to L. |
never@739 | 1197 | // WARNING: be very careful using this for forward jumps. If the label is |
never@739 | 1198 | // not bound within an 8-bit offset of this instruction, a run-time error |
never@739 | 1199 | // will occur. |
never@739 | 1200 | void jmpb(Label& L); |
never@739 | 1201 | |
never@739 | 1202 | void ldmxcsr( Address src ); |
never@739 | 1203 | |
never@739 | 1204 | void leal(Register dst, Address src); |
never@739 | 1205 | |
never@739 | 1206 | void leaq(Register dst, Address src); |
never@739 | 1207 | |
never@739 | 1208 | void lfence() { |
never@739 | 1209 | emit_byte(0x0F); |
never@739 | 1210 | emit_byte(0xAE); |
never@739 | 1211 | emit_byte(0xE8); |
never@739 | 1212 | } |
never@739 | 1213 | |
never@739 | 1214 | void lock(); |
never@739 | 1215 | |
twisti@1210 | 1216 | void lzcntl(Register dst, Register src); |
twisti@1210 | 1217 | |
twisti@1210 | 1218 | #ifdef _LP64 |
twisti@1210 | 1219 | void lzcntq(Register dst, Register src); |
twisti@1210 | 1220 | #endif |
twisti@1210 | 1221 | |
never@739 | 1222 | enum Membar_mask_bits { |
never@739 | 1223 | StoreStore = 1 << 3, |
never@739 | 1224 | LoadStore = 1 << 2, |
never@739 | 1225 | StoreLoad = 1 << 1, |
never@739 | 1226 | LoadLoad = 1 << 0 |
never@739 | 1227 | }; |
never@739 | 1228 | |
never@1106 | 1229 | // Serializes memory and blows flags |
never@739 | 1230 | void membar(Membar_mask_bits order_constraint) { |
never@1106 | 1231 | if (os::is_MP()) { |
never@1106 | 1232 | // We only have to handle StoreLoad |
never@1106 | 1233 | if (order_constraint & StoreLoad) { |
never@1106 | 1234 | // All usable chips support "locked" instructions which suffice |
never@1106 | 1235 | // as barriers, and are much faster than the alternative of |
never@1106 | 1236 | // using cpuid instruction. We use here a locked add [esp],0. |
never@1106 | 1237 | // This is conveniently otherwise a no-op except for blowing |
never@1106 | 1238 | // flags. |
never@1106 | 1239 | // Any change to this code may need to revisit other places in |
never@1106 | 1240 | // the code where this idiom is used, in particular the |
never@1106 | 1241 | // orderAccess code. |
never@1106 | 1242 | lock(); |
never@1106 | 1243 | addl(Address(rsp, 0), 0);// Assert the lock# signal here |
never@1106 | 1244 | } |
never@1106 | 1245 | } |
never@739 | 1246 | } |
never@739 | 1247 | |
never@739 | 1248 | void mfence(); |
never@739 | 1249 | |
never@739 | 1250 | // Moves |
never@739 | 1251 | |
never@739 | 1252 | void mov64(Register dst, int64_t imm64); |
never@739 | 1253 | |
never@739 | 1254 | void movb(Address dst, Register src); |
never@739 | 1255 | void movb(Address dst, int imm8); |
never@739 | 1256 | void movb(Register dst, Address src); |
never@739 | 1257 | |
never@739 | 1258 | void movdl(XMMRegister dst, Register src); |
never@739 | 1259 | void movdl(Register dst, XMMRegister src); |
kvn@2602 | 1260 | void movdl(XMMRegister dst, Address src); |
never@739 | 1261 | |
never@739 | 1262 | // Move Double Quadword |
never@739 | 1263 | void movdq(XMMRegister dst, Register src); |
never@739 | 1264 | void movdq(Register dst, XMMRegister src); |
never@739 | 1265 | |
never@739 | 1266 | // Move Aligned Double Quadword |
never@739 | 1267 | void movdqa(XMMRegister dst, XMMRegister src); |
never@739 | 1268 | |
kvn@840 | 1269 | // Move Unaligned Double Quadword |
kvn@840 | 1270 | void movdqu(Address dst, XMMRegister src); |
kvn@840 | 1271 | void movdqu(XMMRegister dst, Address src); |
kvn@840 | 1272 | void movdqu(XMMRegister dst, XMMRegister src); |
kvn@840 | 1273 | |
never@739 | 1274 | void movl(Register dst, int32_t imm32); |
never@739 | 1275 | void movl(Address dst, int32_t imm32); |
never@739 | 1276 | void movl(Register dst, Register src); |
never@739 | 1277 | void movl(Register dst, Address src); |
never@739 | 1278 | void movl(Address dst, Register src); |
never@739 | 1279 | |
never@739 | 1280 | // These dummies prevent using movl from converting a zero (like NULL) into Register |
never@739 | 1281 | // by giving the compiler two choices it can't resolve |
never@739 | 1282 | |
never@739 | 1283 | void movl(Address dst, void* junk); |
never@739 | 1284 | void movl(Register dst, void* junk); |
never@739 | 1285 | |
never@739 | 1286 | #ifdef _LP64 |
never@739 | 1287 | void movq(Register dst, Register src); |
never@739 | 1288 | void movq(Register dst, Address src); |
phh@2423 | 1289 | void movq(Address dst, Register src); |
never@739 | 1290 | #endif |
never@739 | 1291 | |
never@739 | 1292 | void movq(Address dst, MMXRegister src ); |
never@739 | 1293 | void movq(MMXRegister dst, Address src ); |
never@739 | 1294 | |
never@739 | 1295 | #ifdef _LP64 |
never@739 | 1296 | // These dummies prevent using movq from converting a zero (like NULL) into Register |
never@739 | 1297 | // by giving the compiler two choices it can't resolve |
never@739 | 1298 | |
never@739 | 1299 | void movq(Address dst, void* dummy); |
never@739 | 1300 | void movq(Register dst, void* dummy); |
never@739 | 1301 | #endif |
never@739 | 1302 | |
never@739 | 1303 | // Move Quadword |
never@739 | 1304 | void movq(Address dst, XMMRegister src); |
never@739 | 1305 | void movq(XMMRegister dst, Address src); |
never@739 | 1306 | |
never@739 | 1307 | void movsbl(Register dst, Address src); |
never@739 | 1308 | void movsbl(Register dst, Register src); |
never@739 | 1309 | |
never@739 | 1310 | #ifdef _LP64 |
twisti@1059 | 1311 | void movsbq(Register dst, Address src); |
twisti@1059 | 1312 | void movsbq(Register dst, Register src); |
twisti@1059 | 1313 | |
never@739 | 1314 | // Move signed 32bit immediate to 64bit extending sign |
phh@2423 | 1315 | void movslq(Address dst, int32_t imm64); |
never@739 | 1316 | void movslq(Register dst, int32_t imm64); |
never@739 | 1317 | |
never@739 | 1318 | void movslq(Register dst, Address src); |
never@739 | 1319 | void movslq(Register dst, Register src); |
never@739 | 1320 | void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous |
never@739 | 1321 | #endif |
never@739 | 1322 | |
never@739 | 1323 | void movswl(Register dst, Address src); |
never@739 | 1324 | void movswl(Register dst, Register src); |
never@739 | 1325 | |
twisti@1059 | 1326 | #ifdef _LP64 |
twisti@1059 | 1327 | void movswq(Register dst, Address src); |
twisti@1059 | 1328 | void movswq(Register dst, Register src); |
twisti@1059 | 1329 | #endif |
twisti@1059 | 1330 | |
never@739 | 1331 | void movw(Address dst, int imm16); |
never@739 | 1332 | void movw(Register dst, Address src); |
never@739 | 1333 | void movw(Address dst, Register src); |
never@739 | 1334 | |
never@739 | 1335 | void movzbl(Register dst, Address src); |
never@739 | 1336 | void movzbl(Register dst, Register src); |
never@739 | 1337 | |
twisti@1059 | 1338 | #ifdef _LP64 |
twisti@1059 | 1339 | void movzbq(Register dst, Address src); |
twisti@1059 | 1340 | void movzbq(Register dst, Register src); |
twisti@1059 | 1341 | #endif |
twisti@1059 | 1342 | |
never@739 | 1343 | void movzwl(Register dst, Address src); |
never@739 | 1344 | void movzwl(Register dst, Register src); |
never@739 | 1345 | |
twisti@1059 | 1346 | #ifdef _LP64 |
twisti@1059 | 1347 | void movzwq(Register dst, Address src); |
twisti@1059 | 1348 | void movzwq(Register dst, Register src); |
twisti@1059 | 1349 | #endif |
twisti@1059 | 1350 | |
never@739 | 1351 | void mull(Address src); |
never@739 | 1352 | void mull(Register src); |
never@739 | 1353 | |
never@739 | 1354 | // Multiply Scalar Double-Precision Floating-Point Values |
never@739 | 1355 | void mulsd(XMMRegister dst, Address src); |
never@739 | 1356 | void mulsd(XMMRegister dst, XMMRegister src); |
never@739 | 1357 | |
never@739 | 1358 | // Multiply Scalar Single-Precision Floating-Point Values |
never@739 | 1359 | void mulss(XMMRegister dst, Address src); |
never@739 | 1360 | void mulss(XMMRegister dst, XMMRegister src); |
never@739 | 1361 | |
never@739 | 1362 | void negl(Register dst); |
never@739 | 1363 | |
never@739 | 1364 | #ifdef _LP64 |
never@739 | 1365 | void negq(Register dst); |
never@739 | 1366 | #endif |
never@739 | 1367 | |
never@739 | 1368 | void nop(int i = 1); |
never@739 | 1369 | |
never@739 | 1370 | void notl(Register dst); |
never@739 | 1371 | |
never@739 | 1372 | #ifdef _LP64 |
never@739 | 1373 | void notq(Register dst); |
never@739 | 1374 | #endif |
never@739 | 1375 | |
never@739 | 1376 | void orl(Address dst, int32_t imm32); |
never@739 | 1377 | void orl(Register dst, int32_t imm32); |
never@739 | 1378 | void orl(Register dst, Address src); |
never@739 | 1379 | void orl(Register dst, Register src); |
never@739 | 1380 | |
never@739 | 1381 | void orq(Address dst, int32_t imm32); |
never@739 | 1382 | void orq(Register dst, int32_t imm32); |
never@739 | 1383 | void orq(Register dst, Address src); |
never@739 | 1384 | void orq(Register dst, Register src); |
never@739 | 1385 | |
kvn@3388 | 1386 | // Pack with unsigned saturation |
kvn@3388 | 1387 | void packuswb(XMMRegister dst, XMMRegister src); |
kvn@3388 | 1388 | void packuswb(XMMRegister dst, Address src); |
kvn@3388 | 1389 | |
cfang@1116 | 1390 | // SSE4.2 string instructions |
cfang@1116 | 1391 | void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); |
cfang@1116 | 1392 | void pcmpestri(XMMRegister xmm1, Address src, int imm8); |
cfang@1116 | 1393 | |
kvn@3388 | 1394 | // SSE4.1 packed move |
kvn@3388 | 1395 | void pmovzxbw(XMMRegister dst, XMMRegister src); |
kvn@3388 | 1396 | void pmovzxbw(XMMRegister dst, Address src); |
kvn@3388 | 1397 | |
roland@1495 | 1398 | #ifndef _LP64 // no 32bit push/pop on amd64 |
never@739 | 1399 | void popl(Address dst); |
roland@1495 | 1400 | #endif |
never@739 | 1401 | |
never@739 | 1402 | #ifdef _LP64 |
never@739 | 1403 | void popq(Address dst); |
never@739 | 1404 | #endif |
never@739 | 1405 | |
twisti@1078 | 1406 | void popcntl(Register dst, Address src); |
twisti@1078 | 1407 | void popcntl(Register dst, Register src); |
twisti@1078 | 1408 | |
twisti@1078 | 1409 | #ifdef _LP64 |
twisti@1078 | 1410 | void popcntq(Register dst, Address src); |
twisti@1078 | 1411 | void popcntq(Register dst, Register src); |
twisti@1078 | 1412 | #endif |
twisti@1078 | 1413 | |
never@739 | 1414 | // Prefetches (SSE, SSE2, 3DNOW only) |
never@739 | 1415 | |
never@739 | 1416 | void prefetchnta(Address src); |
never@739 | 1417 | void prefetchr(Address src); |
never@739 | 1418 | void prefetcht0(Address src); |
never@739 | 1419 | void prefetcht1(Address src); |
never@739 | 1420 | void prefetcht2(Address src); |
never@739 | 1421 | void prefetchw(Address src); |
never@739 | 1422 | |
never@2569 | 1423 | // POR - Bitwise logical OR |
never@2569 | 1424 | void por(XMMRegister dst, XMMRegister src); |
kvn@3388 | 1425 | void por(XMMRegister dst, Address src); |
never@2569 | 1426 | |
never@739 | 1427 | // Shuffle Packed Doublewords |
never@739 | 1428 | void pshufd(XMMRegister dst, XMMRegister src, int mode); |
never@739 | 1429 | void pshufd(XMMRegister dst, Address src, int mode); |
never@739 | 1430 | |
never@739 | 1431 | // Shuffle Packed Low Words |
never@739 | 1432 | void pshuflw(XMMRegister dst, XMMRegister src, int mode); |
never@739 | 1433 | void pshuflw(XMMRegister dst, Address src, int mode); |
never@739 | 1434 | |
kvn@2602 | 1435 | // Shift Right by bits Logical Quadword Immediate |
never@739 | 1436 | void psrlq(XMMRegister dst, int shift); |
never@739 | 1437 | |
kvn@2602 | 1438 | // Shift Right by bytes Logical DoubleQuadword Immediate |
kvn@2602 | 1439 | void psrldq(XMMRegister dst, int shift); |
kvn@2602 | 1440 | |
cfang@1116 | 1441 | // Logical Compare Double Quadword |
cfang@1116 | 1442 | void ptest(XMMRegister dst, XMMRegister src); |
cfang@1116 | 1443 | void ptest(XMMRegister dst, Address src); |
cfang@1116 | 1444 | |
never@739 | 1445 | // Interleave Low Bytes |
never@739 | 1446 | void punpcklbw(XMMRegister dst, XMMRegister src); |
kvn@3388 | 1447 | void punpcklbw(XMMRegister dst, Address src); |
kvn@3388 | 1448 | |
kvn@3388 | 1449 | // Interleave Low Doublewords |
kvn@3388 | 1450 | void punpckldq(XMMRegister dst, XMMRegister src); |
kvn@3388 | 1451 | void punpckldq(XMMRegister dst, Address src); |
never@739 | 1452 | |
roland@1495 | 1453 | #ifndef _LP64 // no 32bit push/pop on amd64 |
never@739 | 1454 | void pushl(Address src); |
roland@1495 | 1455 | #endif |
never@739 | 1456 | |
never@739 | 1457 | void pushq(Address src); |
never@739 | 1458 | |
never@739 | 1459 | // Xor Packed Byte Integer Values |
never@739 | 1460 | void pxor(XMMRegister dst, Address src); |
never@739 | 1461 | void pxor(XMMRegister dst, XMMRegister src); |
never@739 | 1462 | |
never@739 | 1463 | void rcll(Register dst, int imm8); |
never@739 | 1464 | |
never@739 | 1465 | void rclq(Register dst, int imm8); |
never@739 | 1466 | |
never@739 | 1467 | void ret(int imm16); |
duke@435 | 1468 | |
duke@435 | 1469 | void sahf(); |
duke@435 | 1470 | |
never@739 | 1471 | void sarl(Register dst, int imm8); |
never@739 | 1472 | void sarl(Register dst); |
never@739 | 1473 | |
never@739 | 1474 | void sarq(Register dst, int imm8); |
never@739 | 1475 | void sarq(Register dst); |
never@739 | 1476 | |
never@739 | 1477 | void sbbl(Address dst, int32_t imm32); |
never@739 | 1478 | void sbbl(Register dst, int32_t imm32); |
never@739 | 1479 | void sbbl(Register dst, Address src); |
never@739 | 1480 | void sbbl(Register dst, Register src); |
never@739 | 1481 | |
never@739 | 1482 | void sbbq(Address dst, int32_t imm32); |
never@739 | 1483 | void sbbq(Register dst, int32_t imm32); |
never@739 | 1484 | void sbbq(Register dst, Address src); |
never@739 | 1485 | void sbbq(Register dst, Register src); |
never@739 | 1486 | |
never@739 | 1487 | void setb(Condition cc, Register dst); |
never@739 | 1488 | |
never@739 | 1489 | void shldl(Register dst, Register src); |
never@739 | 1490 | |
never@739 | 1491 | void shll(Register dst, int imm8); |
never@739 | 1492 | void shll(Register dst); |
never@739 | 1493 | |
never@739 | 1494 | void shlq(Register dst, int imm8); |
never@739 | 1495 | void shlq(Register dst); |
never@739 | 1496 | |
never@739 | 1497 | void shrdl(Register dst, Register src); |
never@739 | 1498 | |
never@739 | 1499 | void shrl(Register dst, int imm8); |
never@739 | 1500 | void shrl(Register dst); |
never@739 | 1501 | |
never@739 | 1502 | void shrq(Register dst, int imm8); |
never@739 | 1503 | void shrq(Register dst); |
never@739 | 1504 | |
never@739 | 1505 | void smovl(); // QQQ generic? |
never@739 | 1506 | |
never@739 | 1507 | // Compute Square Root of Scalar Double-Precision Floating-Point Value |
never@739 | 1508 | void sqrtsd(XMMRegister dst, Address src); |
never@739 | 1509 | void sqrtsd(XMMRegister dst, XMMRegister src); |
never@739 | 1510 | |
twisti@2350 | 1511 | // Compute Square Root of Scalar Single-Precision Floating-Point Value |
twisti@2350 | 1512 | void sqrtss(XMMRegister dst, Address src); |
twisti@2350 | 1513 | void sqrtss(XMMRegister dst, XMMRegister src); |
twisti@2350 | 1514 | |
never@739 | 1515 | void std() { emit_byte(0xfd); } |
never@739 | 1516 | |
never@739 | 1517 | void stmxcsr( Address dst ); |
never@739 | 1518 | |
never@739 | 1519 | void subl(Address dst, int32_t imm32); |
never@739 | 1520 | void subl(Address dst, Register src); |
never@739 | 1521 | void subl(Register dst, int32_t imm32); |
never@739 | 1522 | void subl(Register dst, Address src); |
never@739 | 1523 | void subl(Register dst, Register src); |
never@739 | 1524 | |
never@739 | 1525 | void subq(Address dst, int32_t imm32); |
never@739 | 1526 | void subq(Address dst, Register src); |
never@739 | 1527 | void subq(Register dst, int32_t imm32); |
never@739 | 1528 | void subq(Register dst, Address src); |
never@739 | 1529 | void subq(Register dst, Register src); |
never@739 | 1530 | |
kvn@3574 | 1531 | // Force generation of a 4 byte immediate value even if it fits into 8bit |
kvn@3574 | 1532 | void subl_imm32(Register dst, int32_t imm32); |
kvn@3574 | 1533 | void subq_imm32(Register dst, int32_t imm32); |
never@739 | 1534 | |
never@739 | 1535 | // Subtract Scalar Double-Precision Floating-Point Values |
never@739 | 1536 | void subsd(XMMRegister dst, Address src); |
never@739 | 1537 | void subsd(XMMRegister dst, XMMRegister src); |
never@739 | 1538 | |
never@739 | 1539 | // Subtract Scalar Single-Precision Floating-Point Values |
never@739 | 1540 | void subss(XMMRegister dst, Address src); |
duke@435 | 1541 | void subss(XMMRegister dst, XMMRegister src); |
never@739 | 1542 | |
never@739 | 1543 | void testb(Register dst, int imm8); |
never@739 | 1544 | |
never@739 | 1545 | void testl(Register dst, int32_t imm32); |
never@739 | 1546 | void testl(Register dst, Register src); |
never@739 | 1547 | void testl(Register dst, Address src); |
never@739 | 1548 | |
never@739 | 1549 | void testq(Register dst, int32_t imm32); |
never@739 | 1550 | void testq(Register dst, Register src); |
never@739 | 1551 | |
never@739 | 1552 | |
never@739 | 1553 | // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS |
never@739 | 1554 | void ucomisd(XMMRegister dst, Address src); |
never@739 | 1555 | void ucomisd(XMMRegister dst, XMMRegister src); |
never@739 | 1556 | |
never@739 | 1557 | // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
never@739 | 1558 | void ucomiss(XMMRegister dst, Address src); |
duke@435 | 1559 | void ucomiss(XMMRegister dst, XMMRegister src); |
never@739 | 1560 | |
never@739 | 1561 | void xaddl(Address dst, Register src); |
never@739 | 1562 | |
never@739 | 1563 | void xaddq(Address dst, Register src); |
never@739 | 1564 | |
never@739 | 1565 | void xchgl(Register reg, Address adr); |
never@739 | 1566 | void xchgl(Register dst, Register src); |
never@739 | 1567 | |
never@739 | 1568 | void xchgq(Register reg, Address adr); |
never@739 | 1569 | void xchgq(Register dst, Register src); |
never@739 | 1570 | |
kvn@3388 | 1571 | // Get Value of Extended Control Register |
kvn@3388 | 1572 | void xgetbv() { |
kvn@3388 | 1573 | emit_byte(0x0F); |
kvn@3388 | 1574 | emit_byte(0x01); |
kvn@3388 | 1575 | emit_byte(0xD0); |
kvn@3388 | 1576 | } |
kvn@3388 | 1577 | |
never@739 | 1578 | void xorl(Register dst, int32_t imm32); |
never@739 | 1579 | void xorl(Register dst, Address src); |
never@739 | 1580 | void xorl(Register dst, Register src); |
never@739 | 1581 | |
never@739 | 1582 | void xorq(Register dst, Address src); |
never@739 | 1583 | void xorq(Register dst, Register src); |
never@739 | 1584 | |
never@739 | 1585 | // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values |
kvn@3388 | 1586 | void xorpd(XMMRegister dst, XMMRegister src); |
kvn@3388 | 1587 | |
kvn@3388 | 1588 | // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values |
kvn@3388 | 1589 | void xorps(XMMRegister dst, XMMRegister src); |
kvn@3388 | 1590 | |
kvn@3388 | 1591 | void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 |
kvn@3388 | 1592 | |
kvn@3390 | 1593 | // AVX 3-operands instructions (encoded with VEX prefix) |
kvn@3390 | 1594 | void vaddsd(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1595 | void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
kvn@3390 | 1596 | void vaddss(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1597 | void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
kvn@3390 | 1598 | void vandpd(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1599 | void vandps(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1600 | void vdivsd(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1601 | void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
kvn@3390 | 1602 | void vdivss(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1603 | void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
kvn@3390 | 1604 | void vmulsd(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1605 | void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
kvn@3390 | 1606 | void vmulss(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1607 | void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
kvn@3390 | 1608 | void vsubsd(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1609 | void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
kvn@3390 | 1610 | void vsubss(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1611 | void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
kvn@3390 | 1612 | void vxorpd(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1613 | void vxorps(XMMRegister dst, XMMRegister nds, Address src); |
kvn@3390 | 1614 | |
kvn@3390 | 1615 | |
kvn@3388 | 1616 | protected: |
kvn@3388 | 1617 | // Next instructions require address alignment 16 bytes SSE mode. |
kvn@3388 | 1618 | // They should be called only from corresponding MacroAssembler instructions. |
kvn@3388 | 1619 | void andpd(XMMRegister dst, Address src); |
kvn@3388 | 1620 | void andps(XMMRegister dst, Address src); |
never@739 | 1621 | void xorpd(XMMRegister dst, Address src); |
never@739 | 1622 | void xorps(XMMRegister dst, Address src); |
kvn@3388 | 1623 | |
duke@435 | 1624 | }; |
duke@435 | 1625 | |
duke@435 | 1626 | |
duke@435 | 1627 | // MacroAssembler extends Assembler by frequently used macros. |
duke@435 | 1628 | // |
duke@435 | 1629 | // Instructions for which a 'better' code sequence exists depending |
duke@435 | 1630 | // on arguments should also go in here. |
duke@435 | 1631 | |
duke@435 | 1632 | class MacroAssembler: public Assembler { |
ysr@777 | 1633 | friend class LIR_Assembler; |
ysr@777 | 1634 | friend class Runtime1; // as_Address() |
johnc@2781 | 1635 | |
duke@435 | 1636 | protected: |
duke@435 | 1637 | |
duke@435 | 1638 | Address as_Address(AddressLiteral adr); |
duke@435 | 1639 | Address as_Address(ArrayAddress adr); |
duke@435 | 1640 | |
duke@435 | 1641 | // Support for VM calls |
duke@435 | 1642 | // |
duke@435 | 1643 | // This is the base routine called by the different versions of call_VM_leaf. The interpreter |
duke@435 | 1644 | // may customize this version by overriding it for its purposes (e.g., to save/restore |
duke@435 | 1645 | // additional registers when doing a VM call). |
duke@435 | 1646 | #ifdef CC_INTERP |
duke@435 | 1647 | // c++ interpreter never wants to use interp_masm version of call_VM |
duke@435 | 1648 | #define VIRTUAL |
duke@435 | 1649 | #else |
duke@435 | 1650 | #define VIRTUAL virtual |
duke@435 | 1651 | #endif |
duke@435 | 1652 | |
duke@435 | 1653 | VIRTUAL void call_VM_leaf_base( |
duke@435 | 1654 | address entry_point, // the entry point |
duke@435 | 1655 | int number_of_arguments // the number of arguments to pop after the call |
duke@435 | 1656 | ); |
duke@435 | 1657 | |
duke@435 | 1658 | // This is the base routine called by the different versions of call_VM. The interpreter |
duke@435 | 1659 | // may customize this version by overriding it for its purposes (e.g., to save/restore |
duke@435 | 1660 | // additional registers when doing a VM call). |
duke@435 | 1661 | // |
duke@435 | 1662 | // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base |
duke@435 | 1663 | // returns the register which contains the thread upon return. If a thread register has been |
duke@435 | 1664 | // specified, the return value will correspond to that register. If no last_java_sp is specified |
duke@435 | 1665 | // (noreg) than rsp will be used instead. |
duke@435 | 1666 | VIRTUAL void call_VM_base( // returns the register containing the thread upon return |
duke@435 | 1667 | Register oop_result, // where an oop-result ends up if any; use noreg otherwise |
duke@435 | 1668 | Register java_thread, // the thread if computed before ; use noreg otherwise |
duke@435 | 1669 | Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise |
duke@435 | 1670 | address entry_point, // the entry point |
duke@435 | 1671 | int number_of_arguments, // the number of arguments (w/o thread) to pop after the call |
duke@435 | 1672 | bool check_exceptions // whether to check for pending exceptions after return |
duke@435 | 1673 | ); |
duke@435 | 1674 | |
duke@435 | 1675 | // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. |
duke@435 | 1676 | // The implementation is only non-empty for the InterpreterMacroAssembler, |
duke@435 | 1677 | // as only the interpreter handles PopFrame and ForceEarlyReturn requests. |
duke@435 | 1678 | virtual void check_and_handle_popframe(Register java_thread); |
duke@435 | 1679 | virtual void check_and_handle_earlyret(Register java_thread); |
duke@435 | 1680 | |
duke@435 | 1681 | void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); |
duke@435 | 1682 | |
duke@435 | 1683 | // helpers for FPU flag access |
duke@435 | 1684 | // tmp is a temporary register, if none is available use noreg |
duke@435 | 1685 | void save_rax (Register tmp); |
duke@435 | 1686 | void restore_rax(Register tmp); |
duke@435 | 1687 | |
duke@435 | 1688 | public: |
duke@435 | 1689 | MacroAssembler(CodeBuffer* code) : Assembler(code) {} |
duke@435 | 1690 | |
duke@435 | 1691 | // Support for NULL-checks |
duke@435 | 1692 | // |
duke@435 | 1693 | // Generates code that causes a NULL OS exception if the content of reg is NULL. |
duke@435 | 1694 | // If the accessed location is M[reg + offset] and the offset is known, provide the |
duke@435 | 1695 | // offset. No explicit code generation is needed if the offset is within a certain |
duke@435 | 1696 | // range (0 <= offset <= page_size). |
duke@435 | 1697 | |
duke@435 | 1698 | void null_check(Register reg, int offset = -1); |
kvn@603 | 1699 | static bool needs_explicit_null_check(intptr_t offset); |
duke@435 | 1700 | |
duke@435 | 1701 | // Required platform-specific helpers for Label::patch_instructions. |
duke@435 | 1702 | // They _shadow_ the declarations in AbstractAssembler, which are undefined. |
duke@435 | 1703 | void pd_patch_instruction(address branch, address target); |
duke@435 | 1704 | #ifndef PRODUCT |
duke@435 | 1705 | static void pd_print_patched_instruction(address branch); |
duke@435 | 1706 | #endif |
duke@435 | 1707 | |
duke@435 | 1708 | // The following 4 methods return the offset of the appropriate move instruction |
duke@435 | 1709 | |
jrose@1057 | 1710 | // Support for fast byte/short loading with zero extension (depending on particular CPU) |
duke@435 | 1711 | int load_unsigned_byte(Register dst, Address src); |
jrose@1057 | 1712 | int load_unsigned_short(Register dst, Address src); |
jrose@1057 | 1713 | |
jrose@1057 | 1714 | // Support for fast byte/short loading with sign extension (depending on particular CPU) |
duke@435 | 1715 | int load_signed_byte(Register dst, Address src); |
jrose@1057 | 1716 | int load_signed_short(Register dst, Address src); |
duke@435 | 1717 | |
duke@435 | 1718 | // Support for sign-extension (hi:lo = extend_sign(lo)) |
duke@435 | 1719 | void extend_sign(Register hi, Register lo); |
duke@435 | 1720 | |
twisti@2565 | 1721 | // Load and store values by size and signed-ness |
twisti@2565 | 1722 | void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); |
twisti@2565 | 1723 | void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); |
jrose@1057 | 1724 | |
duke@435 | 1725 | // Support for inc/dec with optimal instruction selection depending on value |
never@739 | 1726 | |
never@739 | 1727 | void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } |
never@739 | 1728 | void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } |
never@739 | 1729 | |
never@739 | 1730 | void decrementl(Address dst, int value = 1); |
never@739 | 1731 | void decrementl(Register reg, int value = 1); |
never@739 | 1732 | |
never@739 | 1733 | void decrementq(Register reg, int value = 1); |
never@739 | 1734 | void decrementq(Address dst, int value = 1); |
never@739 | 1735 | |
never@739 | 1736 | void incrementl(Address dst, int value = 1); |
never@739 | 1737 | void incrementl(Register reg, int value = 1); |
never@739 | 1738 | |
never@739 | 1739 | void incrementq(Register reg, int value = 1); |
never@739 | 1740 | void incrementq(Address dst, int value = 1); |
never@739 | 1741 | |
duke@435 | 1742 | |
duke@435 | 1743 | // Support optimal SSE move instructions. |
duke@435 | 1744 | void movflt(XMMRegister dst, XMMRegister src) { |
duke@435 | 1745 | if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } |
duke@435 | 1746 | else { movss (dst, src); return; } |
duke@435 | 1747 | } |
duke@435 | 1748 | void movflt(XMMRegister dst, Address src) { movss(dst, src); } |
duke@435 | 1749 | void movflt(XMMRegister dst, AddressLiteral src); |
duke@435 | 1750 | void movflt(Address dst, XMMRegister src) { movss(dst, src); } |
duke@435 | 1751 | |
duke@435 | 1752 | void movdbl(XMMRegister dst, XMMRegister src) { |
duke@435 | 1753 | if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } |
duke@435 | 1754 | else { movsd (dst, src); return; } |
duke@435 | 1755 | } |
duke@435 | 1756 | |
duke@435 | 1757 | void movdbl(XMMRegister dst, AddressLiteral src); |
duke@435 | 1758 | |
duke@435 | 1759 | void movdbl(XMMRegister dst, Address src) { |
duke@435 | 1760 | if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } |
duke@435 | 1761 | else { movlpd(dst, src); return; } |
duke@435 | 1762 | } |
duke@435 | 1763 | void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } |
duke@435 | 1764 | |
never@739 | 1765 | void incrementl(AddressLiteral dst); |
never@739 | 1766 | void incrementl(ArrayAddress dst); |
duke@435 | 1767 | |
duke@435 | 1768 | // Alignment |
duke@435 | 1769 | void align(int modulus); |
duke@435 | 1770 | |
kvn@3574 | 1771 | // A 5 byte nop that is safe for patching (see patch_verified_entry) |
kvn@3574 | 1772 | void fat_nop(); |
duke@435 | 1773 | |
duke@435 | 1774 | // Stack frame creation/removal |
duke@435 | 1775 | void enter(); |
duke@435 | 1776 | void leave(); |
duke@435 | 1777 | |
duke@435 | 1778 | // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) |
duke@435 | 1779 | // The pointer will be loaded into the thread register. |
duke@435 | 1780 | void get_thread(Register thread); |
duke@435 | 1781 | |
apetrusenko@797 | 1782 | |
duke@435 | 1783 | // Support for VM calls |
duke@435 | 1784 | // |
duke@435 | 1785 | // It is imperative that all calls into the VM are handled via the call_VM macros. |
duke@435 | 1786 | // They make sure that the stack linkage is setup correctly. call_VM's correspond |
duke@435 | 1787 | // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. |
duke@435 | 1788 | |
never@739 | 1789 | |
never@739 | 1790 | void call_VM(Register oop_result, |
never@739 | 1791 | address entry_point, |
never@739 | 1792 | bool check_exceptions = true); |
never@739 | 1793 | void call_VM(Register oop_result, |
never@739 | 1794 | address entry_point, |
never@739 | 1795 | Register arg_1, |
never@739 | 1796 | bool check_exceptions = true); |
never@739 | 1797 | void call_VM(Register oop_result, |
never@739 | 1798 | address entry_point, |
never@739 | 1799 | Register arg_1, Register arg_2, |
never@739 | 1800 | bool check_exceptions = true); |
never@739 | 1801 | void call_VM(Register oop_result, |
never@739 | 1802 | address entry_point, |
never@739 | 1803 | Register arg_1, Register arg_2, Register arg_3, |
never@739 | 1804 | bool check_exceptions = true); |
never@739 | 1805 | |
never@739 | 1806 | // Overloadings with last_Java_sp |
never@739 | 1807 | void call_VM(Register oop_result, |
never@739 | 1808 | Register last_java_sp, |
never@739 | 1809 | address entry_point, |
never@739 | 1810 | int number_of_arguments = 0, |
never@739 | 1811 | bool check_exceptions = true); |
never@739 | 1812 | void call_VM(Register oop_result, |
never@739 | 1813 | Register last_java_sp, |
never@739 | 1814 | address entry_point, |
never@739 | 1815 | Register arg_1, bool |
never@739 | 1816 | check_exceptions = true); |
never@739 | 1817 | void call_VM(Register oop_result, |
never@739 | 1818 | Register last_java_sp, |
never@739 | 1819 | address entry_point, |
never@739 | 1820 | Register arg_1, Register arg_2, |
never@739 | 1821 | bool check_exceptions = true); |
never@739 | 1822 | void call_VM(Register oop_result, |
never@739 | 1823 | Register last_java_sp, |
never@739 | 1824 | address entry_point, |
never@739 | 1825 | Register arg_1, Register arg_2, Register arg_3, |
never@739 | 1826 | bool check_exceptions = true); |
never@739 | 1827 | |
jrose@2952 | 1828 | // These always tightly bind to MacroAssembler::call_VM_base |
jrose@2952 | 1829 | // bypassing the virtual implementation |
jrose@2952 | 1830 | void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); |
jrose@2952 | 1831 | void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); |
jrose@2952 | 1832 | void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); |
jrose@2952 | 1833 | void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); |
jrose@2952 | 1834 | void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); |
jrose@2952 | 1835 | |
never@739 | 1836 | void call_VM_leaf(address entry_point, |
never@739 | 1837 | int number_of_arguments = 0); |
never@739 | 1838 | void call_VM_leaf(address entry_point, |
never@739 | 1839 | Register arg_1); |
never@739 | 1840 | void call_VM_leaf(address entry_point, |
never@739 | 1841 | Register arg_1, Register arg_2); |
never@739 | 1842 | void call_VM_leaf(address entry_point, |
never@739 | 1843 | Register arg_1, Register arg_2, Register arg_3); |
duke@435 | 1844 | |
never@2868 | 1845 | // These always tightly bind to MacroAssembler::call_VM_leaf_base |
never@2868 | 1846 | // bypassing the virtual implementation |
never@2868 | 1847 | void super_call_VM_leaf(address entry_point); |
never@2868 | 1848 | void super_call_VM_leaf(address entry_point, Register arg_1); |
never@2868 | 1849 | void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); |
never@2868 | 1850 | void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); |
never@2868 | 1851 | void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); |
never@2868 | 1852 | |
duke@435 | 1853 | // last Java Frame (fills frame anchor) |
never@739 | 1854 | void set_last_Java_frame(Register thread, |
never@739 | 1855 | Register last_java_sp, |
never@739 | 1856 | Register last_java_fp, |
never@739 | 1857 | address last_java_pc); |
never@739 | 1858 | |
never@739 | 1859 | // thread in the default location (r15_thread on 64bit) |
never@739 | 1860 | void set_last_Java_frame(Register last_java_sp, |
never@739 | 1861 | Register last_java_fp, |
never@739 | 1862 | address last_java_pc); |
never@739 | 1863 | |
duke@435 | 1864 | void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); |
duke@435 | 1865 | |
never@739 | 1866 | // thread in the default location (r15_thread on 64bit) |
never@739 | 1867 | void reset_last_Java_frame(bool clear_fp, bool clear_pc); |
never@739 | 1868 | |
duke@435 | 1869 | // Stores |
duke@435 | 1870 | void store_check(Register obj); // store check for obj - register is destroyed afterwards |
duke@435 | 1871 | void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) |
duke@435 | 1872 | |
johnc@2781 | 1873 | #ifndef SERIALGC |
johnc@2781 | 1874 | |
apetrusenko@797 | 1875 | void g1_write_barrier_pre(Register obj, |
johnc@2781 | 1876 | Register pre_val, |
apetrusenko@797 | 1877 | Register thread, |
apetrusenko@797 | 1878 | Register tmp, |
johnc@2781 | 1879 | bool tosca_live, |
johnc@2781 | 1880 | bool expand_call); |
johnc@2781 | 1881 | |
apetrusenko@797 | 1882 | void g1_write_barrier_post(Register store_addr, |
apetrusenko@797 | 1883 | Register new_val, |
apetrusenko@797 | 1884 | Register thread, |
apetrusenko@797 | 1885 | Register tmp, |
apetrusenko@797 | 1886 | Register tmp2); |
ysr@777 | 1887 | |
johnc@2781 | 1888 | #endif // SERIALGC |
ysr@777 | 1889 | |
duke@435 | 1890 | // split store_check(Register obj) to enhance instruction interleaving |
duke@435 | 1891 | void store_check_part_1(Register obj); |
duke@435 | 1892 | void store_check_part_2(Register obj); |
duke@435 | 1893 | |
duke@435 | 1894 | // C 'boolean' to Java boolean: x == 0 ? 0 : 1 |
duke@435 | 1895 | void c2bool(Register x); |
duke@435 | 1896 | |
duke@435 | 1897 | // C++ bool manipulation |
duke@435 | 1898 | |
duke@435 | 1899 | void movbool(Register dst, Address src); |
duke@435 | 1900 | void movbool(Address dst, bool boolconst); |
duke@435 | 1901 | void movbool(Address dst, Register src); |
duke@435 | 1902 | void testbool(Register dst); |
duke@435 | 1903 | |
never@739 | 1904 | // oop manipulations |
never@739 | 1905 | void load_klass(Register dst, Register src); |
never@739 | 1906 | void store_klass(Register dst, Register src); |
never@739 | 1907 | |
twisti@2201 | 1908 | void load_heap_oop(Register dst, Address src); |
iveresov@2746 | 1909 | void load_heap_oop_not_null(Register dst, Address src); |
twisti@2201 | 1910 | void store_heap_oop(Address dst, Register src); |
twisti@2201 | 1911 | |
twisti@2201 | 1912 | // Used for storing NULL. All other oop constants should be |
twisti@2201 | 1913 | // stored using routines that take a jobject. |
twisti@2201 | 1914 | void store_heap_oop_null(Address dst); |
twisti@2201 | 1915 | |
never@739 | 1916 | void load_prototype_header(Register dst, Register src); |
never@739 | 1917 | |
never@739 | 1918 | #ifdef _LP64 |
never@739 | 1919 | void store_klass_gap(Register dst, Register src); |
never@739 | 1920 | |
johnc@1482 | 1921 | // This dummy is to prevent a call to store_heap_oop from |
johnc@1482 | 1922 | // converting a zero (like NULL) into a Register by giving |
johnc@1482 | 1923 | // the compiler two choices it can't resolve |
johnc@1482 | 1924 | |
johnc@1482 | 1925 | void store_heap_oop(Address dst, void* dummy); |
johnc@1482 | 1926 | |
never@739 | 1927 | void encode_heap_oop(Register r); |
never@739 | 1928 | void decode_heap_oop(Register r); |
never@739 | 1929 | void encode_heap_oop_not_null(Register r); |
never@739 | 1930 | void decode_heap_oop_not_null(Register r); |
never@739 | 1931 | void encode_heap_oop_not_null(Register dst, Register src); |
never@739 | 1932 | void decode_heap_oop_not_null(Register dst, Register src); |
never@739 | 1933 | |
never@739 | 1934 | void set_narrow_oop(Register dst, jobject obj); |
kvn@1077 | 1935 | void set_narrow_oop(Address dst, jobject obj); |
kvn@1077 | 1936 | void cmp_narrow_oop(Register dst, jobject obj); |
kvn@1077 | 1937 | void cmp_narrow_oop(Address dst, jobject obj); |
never@739 | 1938 | |
never@739 | 1939 | // if heap base register is used - reinit it with the correct value |
never@739 | 1940 | void reinit_heapbase(); |
kvn@2039 | 1941 | |
kvn@2039 | 1942 | DEBUG_ONLY(void verify_heapbase(const char* msg);) |
kvn@2039 | 1943 | |
never@739 | 1944 | #endif // _LP64 |
never@739 | 1945 | |
never@739 | 1946 | // Int division/remainder for Java |
duke@435 | 1947 | // (as idivl, but checks for special case as described in JVM spec.) |
duke@435 | 1948 | // returns idivl instruction offset for implicit exception handling |
duke@435 | 1949 | int corrected_idivl(Register reg); |
duke@435 | 1950 | |
never@739 | 1951 | // Long division/remainder for Java |
never@739 | 1952 | // (as idivq, but checks for special case as described in JVM spec.) |
never@739 | 1953 | // returns idivq instruction offset for implicit exception handling |
never@739 | 1954 | int corrected_idivq(Register reg); |
never@739 | 1955 | |
duke@435 | 1956 | void int3(); |
duke@435 | 1957 | |
never@739 | 1958 | // Long operation macros for a 32bit cpu |
duke@435 | 1959 | // Long negation for Java |
duke@435 | 1960 | void lneg(Register hi, Register lo); |
duke@435 | 1961 | |
duke@435 | 1962 | // Long multiplication for Java |
never@739 | 1963 | // (destroys contents of eax, ebx, ecx and edx) |
duke@435 | 1964 | void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y |
duke@435 | 1965 | |
duke@435 | 1966 | // Long shifts for Java |
duke@435 | 1967 | // (semantics as described in JVM spec.) |
duke@435 | 1968 | void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) |
duke@435 | 1969 | void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) |
duke@435 | 1970 | |
duke@435 | 1971 | // Long compare for Java |
duke@435 | 1972 | // (semantics as described in JVM spec.) |
duke@435 | 1973 | void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) |
duke@435 | 1974 | |
never@739 | 1975 | |
never@739 | 1976 | // misc |
never@739 | 1977 | |
never@739 | 1978 | // Sign extension |
never@739 | 1979 | void sign_extend_short(Register reg); |
never@739 | 1980 | void sign_extend_byte(Register reg); |
never@739 | 1981 | |
never@739 | 1982 | // Division by power of 2, rounding towards 0 |
never@739 | 1983 | void division_with_shift(Register reg, int shift_value); |
never@739 | 1984 | |
duke@435 | 1985 | // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: |
duke@435 | 1986 | // |
duke@435 | 1987 | // CF (corresponds to C0) if x < y |
duke@435 | 1988 | // PF (corresponds to C2) if unordered |
duke@435 | 1989 | // ZF (corresponds to C3) if x = y |
duke@435 | 1990 | // |
duke@435 | 1991 | // The arguments are in reversed order on the stack (i.e., top of stack is first argument). |
duke@435 | 1992 | // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) |
duke@435 | 1993 | void fcmp(Register tmp); |
duke@435 | 1994 | // Variant of the above which allows y to be further down the stack |
duke@435 | 1995 | // and which only pops x and y if specified. If pop_right is |
duke@435 | 1996 | // specified then pop_left must also be specified. |
duke@435 | 1997 | void fcmp(Register tmp, int index, bool pop_left, bool pop_right); |
duke@435 | 1998 | |
duke@435 | 1999 | // Floating-point comparison for Java |
duke@435 | 2000 | // Compares the top-most stack entries on the FPU stack and stores the result in dst. |
duke@435 | 2001 | // The arguments are in reversed order on the stack (i.e., top of stack is first argument). |
duke@435 | 2002 | // (semantics as described in JVM spec.) |
duke@435 | 2003 | void fcmp2int(Register dst, bool unordered_is_less); |
duke@435 | 2004 | // Variant of the above which allows y to be further down the stack |
duke@435 | 2005 | // and which only pops x and y if specified. If pop_right is |
duke@435 | 2006 | // specified then pop_left must also be specified. |
duke@435 | 2007 | void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); |
duke@435 | 2008 | |
duke@435 | 2009 | // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) |
duke@435 | 2010 | // tmp is a temporary register, if none is available use noreg |
duke@435 | 2011 | void fremr(Register tmp); |
duke@435 | 2012 | |
duke@435 | 2013 | |
duke@435 | 2014 | // same as fcmp2int, but using SSE2 |
duke@435 | 2015 | void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); |
duke@435 | 2016 | void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); |
duke@435 | 2017 | |
duke@435 | 2018 | // Inlined sin/cos generator for Java; must not use CPU instruction |
duke@435 | 2019 | // directly on Intel as it does not have high enough precision |
duke@435 | 2020 | // outside of the range [-pi/4, pi/4]. Extra argument indicate the |
duke@435 | 2021 | // number of FPU stack slots in use; all but the topmost will |
duke@435 | 2022 | // require saving if a slow case is necessary. Assumes argument is |
duke@435 | 2023 | // on FP TOS; result is on FP TOS. No cpu registers are changed by |
duke@435 | 2024 | // this code. |
duke@435 | 2025 | void trigfunc(char trig, int num_fpu_regs_in_use = 1); |
duke@435 | 2026 | |
duke@435 | 2027 | // branch to L if FPU flag C2 is set/not set |
duke@435 | 2028 | // tmp is a temporary register, if none is available use noreg |
duke@435 | 2029 | void jC2 (Register tmp, Label& L); |
duke@435 | 2030 | void jnC2(Register tmp, Label& L); |
duke@435 | 2031 | |
duke@435 | 2032 | // Pop ST (ffree & fincstp combined) |
duke@435 | 2033 | void fpop(); |
duke@435 | 2034 | |
duke@435 | 2035 | // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack |
duke@435 | 2036 | void push_fTOS(); |
duke@435 | 2037 | |
duke@435 | 2038 | // pops double TOS element from CPU stack and pushes on FPU stack |
duke@435 | 2039 | void pop_fTOS(); |
duke@435 | 2040 | |
duke@435 | 2041 | void empty_FPU_stack(); |
duke@435 | 2042 | |
duke@435 | 2043 | void push_IU_state(); |
duke@435 | 2044 | void pop_IU_state(); |
duke@435 | 2045 | |
duke@435 | 2046 | void push_FPU_state(); |
duke@435 | 2047 | void pop_FPU_state(); |
duke@435 | 2048 | |
duke@435 | 2049 | void push_CPU_state(); |
duke@435 | 2050 | void pop_CPU_state(); |
duke@435 | 2051 | |
duke@435 | 2052 | // Round up to a power of two |
duke@435 | 2053 | void round_to(Register reg, int modulus); |
duke@435 | 2054 | |
duke@435 | 2055 | // Callee saved registers handling |
duke@435 | 2056 | void push_callee_saved_registers(); |
duke@435 | 2057 | void pop_callee_saved_registers(); |
duke@435 | 2058 | |
duke@435 | 2059 | // allocation |
duke@435 | 2060 | void eden_allocate( |
duke@435 | 2061 | Register obj, // result: pointer to object after successful allocation |
duke@435 | 2062 | Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
duke@435 | 2063 | int con_size_in_bytes, // object size in bytes if known at compile time |
duke@435 | 2064 | Register t1, // temp register |
duke@435 | 2065 | Label& slow_case // continuation point if fast allocation fails |
duke@435 | 2066 | ); |
duke@435 | 2067 | void tlab_allocate( |
duke@435 | 2068 | Register obj, // result: pointer to object after successful allocation |
duke@435 | 2069 | Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
duke@435 | 2070 | int con_size_in_bytes, // object size in bytes if known at compile time |
duke@435 | 2071 | Register t1, // temp register |
duke@435 | 2072 | Register t2, // temp register |
duke@435 | 2073 | Label& slow_case // continuation point if fast allocation fails |
duke@435 | 2074 | ); |
phh@2423 | 2075 | Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address |
phh@2423 | 2076 | void incr_allocated_bytes(Register thread, |
phh@2423 | 2077 | Register var_size_in_bytes, int con_size_in_bytes, |
phh@2423 | 2078 | Register t1 = noreg); |
duke@435 | 2079 | |
jrose@1058 | 2080 | // interface method calling |
jrose@1058 | 2081 | void lookup_interface_method(Register recv_klass, |
jrose@1058 | 2082 | Register intf_klass, |
jrose@1100 | 2083 | RegisterOrConstant itable_index, |
jrose@1058 | 2084 | Register method_result, |
jrose@1058 | 2085 | Register scan_temp, |
jrose@1058 | 2086 | Label& no_such_interface); |
jrose@1058 | 2087 | |
jrose@1079 | 2088 | // Test sub_klass against super_klass, with fast and slow paths. |
jrose@1079 | 2089 | |
jrose@1079 | 2090 | // The fast path produces a tri-state answer: yes / no / maybe-slow. |
jrose@1079 | 2091 | // One of the three labels can be NULL, meaning take the fall-through. |
jrose@1079 | 2092 | // If super_check_offset is -1, the value is loaded up from super_klass. |
jrose@1079 | 2093 | // No registers are killed, except temp_reg. |
jrose@1079 | 2094 | void check_klass_subtype_fast_path(Register sub_klass, |
jrose@1079 | 2095 | Register super_klass, |
jrose@1079 | 2096 | Register temp_reg, |
jrose@1079 | 2097 | Label* L_success, |
jrose@1079 | 2098 | Label* L_failure, |
jrose@1079 | 2099 | Label* L_slow_path, |
jrose@1100 | 2100 | RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); |
jrose@1079 | 2101 | |
jrose@1079 | 2102 | // The rest of the type check; must be wired to a corresponding fast path. |
jrose@1079 | 2103 | // It does not repeat the fast path logic, so don't use it standalone. |
jrose@1079 | 2104 | // The temp_reg and temp2_reg can be noreg, if no temps are available. |
jrose@1079 | 2105 | // Updates the sub's secondary super cache as necessary. |
jrose@1079 | 2106 | // If set_cond_codes, condition codes will be Z on success, NZ on failure. |
jrose@1079 | 2107 | void check_klass_subtype_slow_path(Register sub_klass, |
jrose@1079 | 2108 | Register super_klass, |
jrose@1079 | 2109 | Register temp_reg, |
jrose@1079 | 2110 | Register temp2_reg, |
jrose@1079 | 2111 | Label* L_success, |
jrose@1079 | 2112 | Label* L_failure, |
jrose@1079 | 2113 | bool set_cond_codes = false); |
jrose@1079 | 2114 | |
jrose@1079 | 2115 | // Simplified, combined version, good for typical uses. |
jrose@1079 | 2116 | // Falls through on failure. |
jrose@1079 | 2117 | void check_klass_subtype(Register sub_klass, |
jrose@1079 | 2118 | Register super_klass, |
jrose@1079 | 2119 | Register temp_reg, |
jrose@1079 | 2120 | Label& L_success); |
jrose@1079 | 2121 | |
jrose@1145 | 2122 | // method handles (JSR 292) |
jrose@1145 | 2123 | void check_method_handle_type(Register mtype_reg, Register mh_reg, |
jrose@1145 | 2124 | Register temp_reg, |
jrose@1145 | 2125 | Label& wrong_method_type); |
jrose@1145 | 2126 | void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, |
jrose@1145 | 2127 | Register temp_reg); |
jrose@1145 | 2128 | void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); |
jrose@1145 | 2129 | Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); |
jrose@1145 | 2130 | |
jrose@1145 | 2131 | |
duke@435 | 2132 | //---- |
duke@435 | 2133 | void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 |
duke@435 | 2134 | |
duke@435 | 2135 | // Debugging |
never@739 | 2136 | |
never@739 | 2137 | // only if +VerifyOops |
never@739 | 2138 | void verify_oop(Register reg, const char* s = "broken oop"); |
duke@435 | 2139 | void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
duke@435 | 2140 | |
never@739 | 2141 | // only if +VerifyFPU |
never@739 | 2142 | void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); |
never@739 | 2143 | |
never@739 | 2144 | // prints msg, dumps registers and stops execution |
never@739 | 2145 | void stop(const char* msg); |
never@739 | 2146 | |
never@739 | 2147 | // prints msg and continues |
never@739 | 2148 | void warn(const char* msg); |
never@739 | 2149 | |
never@739 | 2150 | static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); |
never@739 | 2151 | static void debug64(char* msg, int64_t pc, int64_t regs[]); |
never@739 | 2152 | |
duke@435 | 2153 | void os_breakpoint(); |
never@739 | 2154 | |
duke@435 | 2155 | void untested() { stop("untested"); } |
never@739 | 2156 | |
twisti@2201 | 2157 | void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } |
never@739 | 2158 | |
duke@435 | 2159 | void should_not_reach_here() { stop("should not reach here"); } |
never@739 | 2160 | |
duke@435 | 2161 | void print_CPU_state(); |
duke@435 | 2162 | |
duke@435 | 2163 | // Stack overflow checking |
duke@435 | 2164 | void bang_stack_with_offset(int offset) { |
duke@435 | 2165 | // stack grows down, caller passes positive offset |
duke@435 | 2166 | assert(offset > 0, "must bang with negative offset"); |
duke@435 | 2167 | movl(Address(rsp, (-offset)), rax); |
duke@435 | 2168 | } |
duke@435 | 2169 | |
duke@435 | 2170 | // Writes to stack successive pages until offset reached to check for |
duke@435 | 2171 | // stack overflow + shadow pages. Also, clobbers tmp |
duke@435 | 2172 | void bang_stack_size(Register size, Register tmp); |
duke@435 | 2173 | |
jrose@1100 | 2174 | virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, |
jrose@1100 | 2175 | Register tmp, |
jrose@1100 | 2176 | int offset); |
jrose@1057 | 2177 | |
duke@435 | 2178 | // Support for serializing memory accesses between threads |
duke@435 | 2179 | void serialize_memory(Register thread, Register tmp); |
duke@435 | 2180 | |
duke@435 | 2181 | void verify_tlab(); |
duke@435 | 2182 | |
duke@435 | 2183 | // Biased locking support |
duke@435 | 2184 | // lock_reg and obj_reg must be loaded up with the appropriate values. |
duke@435 | 2185 | // swap_reg must be rax, and is killed. |
duke@435 | 2186 | // tmp_reg is optional. If it is supplied (i.e., != noreg) it will |
duke@435 | 2187 | // be killed; if not supplied, push/pop will be used internally to |
duke@435 | 2188 | // allocate a temporary (inefficient, avoid if possible). |
duke@435 | 2189 | // Optional slow case is for implementations (interpreter and C1) which branch to |
duke@435 | 2190 | // slow case directly. Leaves condition codes set for C2's Fast_Lock node. |
duke@435 | 2191 | // Returns offset of first potentially-faulting instruction for null |
duke@435 | 2192 | // check info (currently consumed only by C1). If |
duke@435 | 2193 | // swap_reg_contains_mark is true then returns -1 as it is assumed |
duke@435 | 2194 | // the calling code has already passed any potential faults. |
kvn@855 | 2195 | int biased_locking_enter(Register lock_reg, Register obj_reg, |
kvn@855 | 2196 | Register swap_reg, Register tmp_reg, |
duke@435 | 2197 | bool swap_reg_contains_mark, |
duke@435 | 2198 | Label& done, Label* slow_case = NULL, |
duke@435 | 2199 | BiasedLockingCounters* counters = NULL); |
duke@435 | 2200 | void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); |
duke@435 | 2201 | |
duke@435 | 2202 | |
duke@435 | 2203 | Condition negate_condition(Condition cond); |
duke@435 | 2204 | |
duke@435 | 2205 | // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit |
duke@435 | 2206 | // operands. In general the names are modified to avoid hiding the instruction in Assembler |
duke@435 | 2207 | // so that we don't need to implement all the varieties in the Assembler with trivial wrappers |
duke@435 | 2208 | // here in MacroAssembler. The major exception to this rule is call |
duke@435 | 2209 | |
duke@435 | 2210 | // Arithmetics |
duke@435 | 2211 | |
never@739 | 2212 | |
never@739 | 2213 | void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } |
never@739 | 2214 | void addptr(Address dst, Register src); |
never@739 | 2215 | |
never@739 | 2216 | void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } |
never@739 | 2217 | void addptr(Register dst, int32_t src); |
never@739 | 2218 | void addptr(Register dst, Register src); |
never@2895 | 2219 | void addptr(Register dst, RegisterOrConstant src) { |
never@2895 | 2220 | if (src.is_constant()) addptr(dst, (int) src.as_constant()); |
never@2895 | 2221 | else addptr(dst, src.as_register()); |
never@2895 | 2222 | } |
never@739 | 2223 | |
never@739 | 2224 | void andptr(Register dst, int32_t src); |
never@739 | 2225 | void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } |
never@739 | 2226 | |
never@739 | 2227 | void cmp8(AddressLiteral src1, int imm); |
never@739 | 2228 | |
never@739 | 2229 | // renamed to drag out the casting of address to int32_t/intptr_t |
duke@435 | 2230 | void cmp32(Register src1, int32_t imm); |
duke@435 | 2231 | |
duke@435 | 2232 | void cmp32(AddressLiteral src1, int32_t imm); |
duke@435 | 2233 | // compare reg - mem, or reg - &mem |
duke@435 | 2234 | void cmp32(Register src1, AddressLiteral src2); |
duke@435 | 2235 | |
duke@435 | 2236 | void cmp32(Register src1, Address src2); |
duke@435 | 2237 | |
never@739 | 2238 | #ifndef _LP64 |
never@739 | 2239 | void cmpoop(Address dst, jobject obj); |
never@739 | 2240 | void cmpoop(Register dst, jobject obj); |
never@739 | 2241 | #endif // _LP64 |
never@739 | 2242 | |
duke@435 | 2243 | // NOTE src2 must be the lval. This is NOT an mem-mem compare |
duke@435 | 2244 | void cmpptr(Address src1, AddressLiteral src2); |
duke@435 | 2245 | |
duke@435 | 2246 | void cmpptr(Register src1, AddressLiteral src2); |
duke@435 | 2247 | |
never@739 | 2248 | void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
never@739 | 2249 | void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
never@739 | 2250 | // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
never@739 | 2251 | |
never@739 | 2252 | void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
never@739 | 2253 | void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
never@739 | 2254 | |
never@739 | 2255 | // cmp64 to avoild hiding cmpq |
never@739 | 2256 | void cmp64(Register src1, AddressLiteral src); |
never@739 | 2257 | |
never@739 | 2258 | void cmpxchgptr(Register reg, Address adr); |
never@739 | 2259 | |
never@739 | 2260 | void locked_cmpxchgptr(Register reg, AddressLiteral adr); |
never@739 | 2261 | |
never@739 | 2262 | |
never@739 | 2263 | void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } |
never@739 | 2264 | |
never@739 | 2265 | |
never@739 | 2266 | void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } |
never@739 | 2267 | |
never@739 | 2268 | void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } |
never@739 | 2269 | |
never@739 | 2270 | void shlptr(Register dst, int32_t shift); |
never@739 | 2271 | void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } |
never@739 | 2272 | |
never@739 | 2273 | void shrptr(Register dst, int32_t shift); |
never@739 | 2274 | void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } |
never@739 | 2275 | |
never@739 | 2276 | void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } |
never@739 | 2277 | void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } |
never@739 | 2278 | |
never@739 | 2279 | void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } |
never@739 | 2280 | |
never@739 | 2281 | void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } |
never@739 | 2282 | void subptr(Register dst, int32_t src); |
kvn@3574 | 2283 | // Force generation of a 4 byte immediate value even if it fits into 8bit |
kvn@3574 | 2284 | void subptr_imm32(Register dst, int32_t src); |
never@739 | 2285 | void subptr(Register dst, Register src); |
never@2895 | 2286 | void subptr(Register dst, RegisterOrConstant src) { |
never@2895 | 2287 | if (src.is_constant()) subptr(dst, (int) src.as_constant()); |
never@2895 | 2288 | else subptr(dst, src.as_register()); |
never@2895 | 2289 | } |
never@739 | 2290 | |
never@739 | 2291 | void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } |
never@739 | 2292 | void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } |
never@739 | 2293 | |
never@739 | 2294 | void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } |
never@739 | 2295 | void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } |
never@739 | 2296 | |
never@739 | 2297 | void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } |
never@739 | 2298 | |
never@739 | 2299 | |
duke@435 | 2300 | |
duke@435 | 2301 | // Helper functions for statistics gathering. |
duke@435 | 2302 | // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. |
duke@435 | 2303 | void cond_inc32(Condition cond, AddressLiteral counter_addr); |
duke@435 | 2304 | // Unconditional atomic increment. |
duke@435 | 2305 | void atomic_incl(AddressLiteral counter_addr); |
duke@435 | 2306 | |
duke@435 | 2307 | void lea(Register dst, AddressLiteral adr); |
duke@435 | 2308 | void lea(Address dst, AddressLiteral adr); |
never@739 | 2309 | void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } |
never@739 | 2310 | |
never@739 | 2311 | void leal32(Register dst, Address src) { leal(dst, src); } |
never@739 | 2312 | |
iveresov@2686 | 2313 | // Import other testl() methods from the parent class or else |
iveresov@2686 | 2314 | // they will be hidden by the following overriding declaration. |
iveresov@2686 | 2315 | using Assembler::testl; |
iveresov@2686 | 2316 | void testl(Register dst, AddressLiteral src); |
never@739 | 2317 | |
never@739 | 2318 | void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } |
never@739 | 2319 | void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } |
never@739 | 2320 | void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } |
never@739 | 2321 | |
never@739 | 2322 | void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } |
never@739 | 2323 | void testptr(Register src1, Register src2); |
never@739 | 2324 | |
never@739 | 2325 | void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } |
never@739 | 2326 | void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } |
duke@435 | 2327 | |
duke@435 | 2328 | // Calls |
duke@435 | 2329 | |
duke@435 | 2330 | void call(Label& L, relocInfo::relocType rtype); |
duke@435 | 2331 | void call(Register entry); |
duke@435 | 2332 | |
duke@435 | 2333 | // NOTE: this call tranfers to the effective address of entry NOT |
duke@435 | 2334 | // the address contained by entry. This is because this is more natural |
duke@435 | 2335 | // for jumps/calls. |
duke@435 | 2336 | void call(AddressLiteral entry); |
duke@435 | 2337 | |
duke@435 | 2338 | // Jumps |
duke@435 | 2339 | |
duke@435 | 2340 | // NOTE: these jumps tranfer to the effective address of dst NOT |
duke@435 | 2341 | // the address contained by dst. This is because this is more natural |
duke@435 | 2342 | // for jumps/calls. |
duke@435 | 2343 | void jump(AddressLiteral dst); |
duke@435 | 2344 | void jump_cc(Condition cc, AddressLiteral dst); |
duke@435 | 2345 | |
duke@435 | 2346 | // 32bit can do a case table jump in one instruction but we no longer allow the base |
duke@435 | 2347 | // to be installed in the Address class. This jump will tranfers to the address |
duke@435 | 2348 | // contained in the location described by entry (not the address of entry) |
duke@435 | 2349 | void jump(ArrayAddress entry); |
duke@435 | 2350 | |
duke@435 | 2351 | // Floating |
duke@435 | 2352 | |
duke@435 | 2353 | void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } |
duke@435 | 2354 | void andpd(XMMRegister dst, AddressLiteral src); |
duke@435 | 2355 | |
kvn@3388 | 2356 | void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } |
kvn@3388 | 2357 | void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } |
kvn@3388 | 2358 | void andps(XMMRegister dst, AddressLiteral src); |
kvn@3388 | 2359 | |
kvn@3388 | 2360 | void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } |
duke@435 | 2361 | void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } |
duke@435 | 2362 | void comiss(XMMRegister dst, AddressLiteral src); |
duke@435 | 2363 | |
kvn@3388 | 2364 | void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } |
duke@435 | 2365 | void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } |
duke@435 | 2366 | void comisd(XMMRegister dst, AddressLiteral src); |
duke@435 | 2367 | |
twisti@2350 | 2368 | void fadd_s(Address src) { Assembler::fadd_s(src); } |
twisti@2350 | 2369 | void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } |
twisti@2350 | 2370 | |
duke@435 | 2371 | void fldcw(Address src) { Assembler::fldcw(src); } |
duke@435 | 2372 | void fldcw(AddressLiteral src); |
duke@435 | 2373 | |
duke@435 | 2374 | void fld_s(int index) { Assembler::fld_s(index); } |
duke@435 | 2375 | void fld_s(Address src) { Assembler::fld_s(src); } |
duke@435 | 2376 | void fld_s(AddressLiteral src); |
duke@435 | 2377 | |
duke@435 | 2378 | void fld_d(Address src) { Assembler::fld_d(src); } |
duke@435 | 2379 | void fld_d(AddressLiteral src); |
duke@435 | 2380 | |
duke@435 | 2381 | void fld_x(Address src) { Assembler::fld_x(src); } |
duke@435 | 2382 | void fld_x(AddressLiteral src); |
duke@435 | 2383 | |
twisti@2350 | 2384 | void fmul_s(Address src) { Assembler::fmul_s(src); } |
twisti@2350 | 2385 | void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } |
twisti@2350 | 2386 | |
duke@435 | 2387 | void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } |
duke@435 | 2388 | void ldmxcsr(AddressLiteral src); |
duke@435 | 2389 | |
never@739 | 2390 | private: |
never@739 | 2391 | // these are private because users should be doing movflt/movdbl |
never@739 | 2392 | |
duke@435 | 2393 | void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
duke@435 | 2394 | void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } |
duke@435 | 2395 | void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } |
duke@435 | 2396 | void movss(XMMRegister dst, AddressLiteral src); |
duke@435 | 2397 | |
kvn@3388 | 2398 | void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
never@739 | 2399 | void movlpd(XMMRegister dst, AddressLiteral src); |
never@739 | 2400 | |
never@739 | 2401 | public: |
never@739 | 2402 | |
twisti@2350 | 2403 | void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } |
twisti@2350 | 2404 | void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } |
kvn@3388 | 2405 | void addsd(XMMRegister dst, AddressLiteral src); |
twisti@2350 | 2406 | |
twisti@2350 | 2407 | void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } |
twisti@2350 | 2408 | void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } |
kvn@3388 | 2409 | void addss(XMMRegister dst, AddressLiteral src); |
twisti@2350 | 2410 | |
twisti@2350 | 2411 | void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } |
twisti@2350 | 2412 | void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } |
kvn@3388 | 2413 | void divsd(XMMRegister dst, AddressLiteral src); |
twisti@2350 | 2414 | |
twisti@2350 | 2415 | void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } |
twisti@2350 | 2416 | void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } |
kvn@3388 | 2417 | void divss(XMMRegister dst, AddressLiteral src); |
twisti@2350 | 2418 | |
phh@2423 | 2419 | void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } |
phh@2423 | 2420 | void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } |
phh@2423 | 2421 | void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } |
kvn@3388 | 2422 | void movsd(XMMRegister dst, AddressLiteral src); |
twisti@2350 | 2423 | |
twisti@2350 | 2424 | void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } |
twisti@2350 | 2425 | void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } |
kvn@3388 | 2426 | void mulsd(XMMRegister dst, AddressLiteral src); |
twisti@2350 | 2427 | |
twisti@2350 | 2428 | void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } |
twisti@2350 | 2429 | void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } |
kvn@3388 | 2430 | void mulss(XMMRegister dst, AddressLiteral src); |
twisti@2350 | 2431 | |
twisti@2350 | 2432 | void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } |
twisti@2350 | 2433 | void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } |
kvn@3388 | 2434 | void sqrtsd(XMMRegister dst, AddressLiteral src); |
twisti@2350 | 2435 | |
twisti@2350 | 2436 | void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } |
twisti@2350 | 2437 | void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } |
kvn@3388 | 2438 | void sqrtss(XMMRegister dst, AddressLiteral src); |
twisti@2350 | 2439 | |
twisti@2350 | 2440 | void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } |
twisti@2350 | 2441 | void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } |
kvn@3388 | 2442 | void subsd(XMMRegister dst, AddressLiteral src); |
twisti@2350 | 2443 | |
twisti@2350 | 2444 | void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } |
twisti@2350 | 2445 | void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } |
kvn@3388 | 2446 | void subss(XMMRegister dst, AddressLiteral src); |
duke@435 | 2447 | |
duke@435 | 2448 | void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } |
kvn@3388 | 2449 | void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } |
duke@435 | 2450 | void ucomiss(XMMRegister dst, AddressLiteral src); |
duke@435 | 2451 | |
duke@435 | 2452 | void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } |
kvn@3388 | 2453 | void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } |
duke@435 | 2454 | void ucomisd(XMMRegister dst, AddressLiteral src); |
duke@435 | 2455 | |
duke@435 | 2456 | // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values |
duke@435 | 2457 | void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } |
duke@435 | 2458 | void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } |
duke@435 | 2459 | void xorpd(XMMRegister dst, AddressLiteral src); |
duke@435 | 2460 | |
duke@435 | 2461 | // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values |
duke@435 | 2462 | void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } |
duke@435 | 2463 | void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } |
duke@435 | 2464 | void xorps(XMMRegister dst, AddressLiteral src); |
duke@435 | 2465 | |
kvn@3390 | 2466 | // AVX 3-operands instructions |
kvn@3390 | 2467 | |
kvn@3390 | 2468 | void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); } |
kvn@3390 | 2469 | void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); } |
kvn@3390 | 2470 | void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2471 | |
kvn@3390 | 2472 | void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } |
kvn@3390 | 2473 | void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } |
kvn@3390 | 2474 | void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2475 | |
kvn@3390 | 2476 | void vandpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandpd(dst, nds, src); } |
kvn@3390 | 2477 | void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2478 | |
kvn@3390 | 2479 | void vandps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandps(dst, nds, src); } |
kvn@3390 | 2480 | void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2481 | |
kvn@3390 | 2482 | void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } |
kvn@3390 | 2483 | void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } |
kvn@3390 | 2484 | void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2485 | |
kvn@3390 | 2486 | void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); } |
kvn@3390 | 2487 | void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); } |
kvn@3390 | 2488 | void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2489 | |
kvn@3390 | 2490 | void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); } |
kvn@3390 | 2491 | void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); } |
kvn@3390 | 2492 | void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2493 | |
kvn@3390 | 2494 | void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); } |
kvn@3390 | 2495 | void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); } |
kvn@3390 | 2496 | void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2497 | |
kvn@3390 | 2498 | void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); } |
kvn@3390 | 2499 | void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); } |
kvn@3390 | 2500 | void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2501 | |
kvn@3390 | 2502 | void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); } |
kvn@3390 | 2503 | void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); } |
kvn@3390 | 2504 | void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2505 | |
kvn@3390 | 2506 | void vxorpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorpd(dst, nds, src); } |
kvn@3390 | 2507 | void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2508 | |
kvn@3390 | 2509 | void vxorps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorps(dst, nds, src); } |
kvn@3390 | 2510 | void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
kvn@3390 | 2511 | |
kvn@3390 | 2512 | |
duke@435 | 2513 | // Data |
duke@435 | 2514 | |
twisti@2697 | 2515 | void cmov32( Condition cc, Register dst, Address src); |
twisti@2697 | 2516 | void cmov32( Condition cc, Register dst, Register src); |
twisti@2697 | 2517 | |
twisti@2697 | 2518 | void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } |
twisti@2697 | 2519 | |
twisti@2697 | 2520 | void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
twisti@2697 | 2521 | void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
never@739 | 2522 | |
duke@435 | 2523 | void movoop(Register dst, jobject obj); |
duke@435 | 2524 | void movoop(Address dst, jobject obj); |
duke@435 | 2525 | |
duke@435 | 2526 | void movptr(ArrayAddress dst, Register src); |
duke@435 | 2527 | // can this do an lea? |
duke@435 | 2528 | void movptr(Register dst, ArrayAddress src); |
duke@435 | 2529 | |
never@739 | 2530 | void movptr(Register dst, Address src); |
never@739 | 2531 | |
duke@435 | 2532 | void movptr(Register dst, AddressLiteral src); |
duke@435 | 2533 | |
never@739 | 2534 | void movptr(Register dst, intptr_t src); |
never@739 | 2535 | void movptr(Register dst, Register src); |
never@739 | 2536 | void movptr(Address dst, intptr_t src); |
never@739 | 2537 | |
never@739 | 2538 | void movptr(Address dst, Register src); |
never@739 | 2539 | |
never@2895 | 2540 | void movptr(Register dst, RegisterOrConstant src) { |
never@2895 | 2541 | if (src.is_constant()) movptr(dst, src.as_constant()); |
never@2895 | 2542 | else movptr(dst, src.as_register()); |
never@2895 | 2543 | } |
never@2895 | 2544 | |
never@739 | 2545 | #ifdef _LP64 |
never@739 | 2546 | // Generally the next two are only used for moving NULL |
never@739 | 2547 | // Although there are situations in initializing the mark word where |
never@739 | 2548 | // they could be used. They are dangerous. |
never@739 | 2549 | |
never@739 | 2550 | // They only exist on LP64 so that int32_t and intptr_t are not the same |
never@739 | 2551 | // and we have ambiguous declarations. |
never@739 | 2552 | |
never@739 | 2553 | void movptr(Address dst, int32_t imm32); |
never@739 | 2554 | void movptr(Register dst, int32_t imm32); |
never@739 | 2555 | #endif // _LP64 |
never@739 | 2556 | |
duke@435 | 2557 | // to avoid hiding movl |
duke@435 | 2558 | void mov32(AddressLiteral dst, Register src); |
duke@435 | 2559 | void mov32(Register dst, AddressLiteral src); |
never@739 | 2560 | |
duke@435 | 2561 | // to avoid hiding movb |
duke@435 | 2562 | void movbyte(ArrayAddress dst, int src); |
duke@435 | 2563 | |
duke@435 | 2564 | // Can push value or effective address |
duke@435 | 2565 | void pushptr(AddressLiteral src); |
duke@435 | 2566 | |
never@739 | 2567 | void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } |
never@739 | 2568 | void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } |
never@739 | 2569 | |
never@739 | 2570 | void pushoop(jobject obj); |
never@739 | 2571 | |
never@739 | 2572 | // sign extend as need a l to ptr sized element |
never@739 | 2573 | void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } |
never@739 | 2574 | void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } |
never@739 | 2575 | |
kvn@3574 | 2576 | // C2 compiled method's prolog code. |
kvn@3574 | 2577 | void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b); |
kvn@3574 | 2578 | |
kvn@1421 | 2579 | // IndexOf strings. |
kvn@2602 | 2580 | // Small strings are loaded through stack if they cross page boundary. |
kvn@1421 | 2581 | void string_indexof(Register str1, Register str2, |
kvn@2602 | 2582 | Register cnt1, Register cnt2, |
kvn@2602 | 2583 | int int_cnt2, Register result, |
kvn@1421 | 2584 | XMMRegister vec, Register tmp); |
kvn@1421 | 2585 | |
kvn@2602 | 2586 | // IndexOf for constant substrings with size >= 8 elements |
kvn@2602 | 2587 | // which don't need to be loaded through stack. |
kvn@2602 | 2588 | void string_indexofC8(Register str1, Register str2, |
kvn@2602 | 2589 | Register cnt1, Register cnt2, |
kvn@2602 | 2590 | int int_cnt2, Register result, |
kvn@2602 | 2591 | XMMRegister vec, Register tmp); |
kvn@2602 | 2592 | |
kvn@2602 | 2593 | // Smallest code: we don't need to load through stack, |
kvn@2602 | 2594 | // check string tail. |
kvn@2602 | 2595 | |
kvn@1421 | 2596 | // Compare strings. |
kvn@1421 | 2597 | void string_compare(Register str1, Register str2, |
kvn@1421 | 2598 | Register cnt1, Register cnt2, Register result, |
never@2569 | 2599 | XMMRegister vec1); |
kvn@1421 | 2600 | |
kvn@1421 | 2601 | // Compare char[] arrays. |
kvn@1421 | 2602 | void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
kvn@1421 | 2603 | Register limit, Register result, Register chr, |
kvn@1421 | 2604 | XMMRegister vec1, XMMRegister vec2); |
never@739 | 2605 | |
never@2118 | 2606 | // Fill primitive arrays |
never@2118 | 2607 | void generate_fill(BasicType t, bool aligned, |
never@2118 | 2608 | Register to, Register value, Register count, |
never@2118 | 2609 | Register rtmp, XMMRegister xtmp); |
never@2118 | 2610 | |
duke@435 | 2611 | #undef VIRTUAL |
duke@435 | 2612 | |
duke@435 | 2613 | }; |
duke@435 | 2614 | |
duke@435 | 2615 | /** |
duke@435 | 2616 | * class SkipIfEqual: |
duke@435 | 2617 | * |
duke@435 | 2618 | * Instantiating this class will result in assembly code being output that will |
duke@435 | 2619 | * jump around any code emitted between the creation of the instance and it's |
duke@435 | 2620 | * automatic destruction at the end of a scope block, depending on the value of |
duke@435 | 2621 | * the flag passed to the constructor, which will be checked at run-time. |
duke@435 | 2622 | */ |
duke@435 | 2623 | class SkipIfEqual { |
duke@435 | 2624 | private: |
duke@435 | 2625 | MacroAssembler* _masm; |
duke@435 | 2626 | Label _label; |
duke@435 | 2627 | |
duke@435 | 2628 | public: |
duke@435 | 2629 | SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); |
duke@435 | 2630 | ~SkipIfEqual(); |
duke@435 | 2631 | }; |
duke@435 | 2632 | |
duke@435 | 2633 | #ifdef ASSERT |
duke@435 | 2634 | inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } |
duke@435 | 2635 | #endif |
stefank@2314 | 2636 | |
stefank@2314 | 2637 | #endif // CPU_X86_VM_ASSEMBLER_X86_HPP |