Thu, 29 May 2008 12:04:14 -0700
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
Summary: Generate addresses and implicit null checks with narrow oops to avoid decoding.
Reviewed-by: jrose, never
duke@435 | 1 | /* |
duke@435 | 2 | * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | class BiasedLockingCounters; |
duke@435 | 26 | |
duke@435 | 27 | // Contains all the definitions needed for x86 assembly code generation. |
duke@435 | 28 | |
duke@435 | 29 | // Calling convention |
duke@435 | 30 | class Argument VALUE_OBJ_CLASS_SPEC { |
duke@435 | 31 | public: |
duke@435 | 32 | enum { |
duke@435 | 33 | #ifdef _LP64 |
duke@435 | 34 | #ifdef _WIN64 |
duke@435 | 35 | n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
duke@435 | 36 | n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) |
duke@435 | 37 | #else |
duke@435 | 38 | n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
duke@435 | 39 | n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) |
duke@435 | 40 | #endif // _WIN64 |
duke@435 | 41 | n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... |
duke@435 | 42 | n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... |
duke@435 | 43 | #else |
duke@435 | 44 | n_register_parameters = 0 // 0 registers used to pass arguments |
duke@435 | 45 | #endif // _LP64 |
duke@435 | 46 | }; |
duke@435 | 47 | }; |
duke@435 | 48 | |
duke@435 | 49 | |
duke@435 | 50 | #ifdef _LP64 |
duke@435 | 51 | // Symbolically name the register arguments used by the c calling convention. |
duke@435 | 52 | // Windows is different from linux/solaris. So much for standards... |
duke@435 | 53 | |
duke@435 | 54 | #ifdef _WIN64 |
duke@435 | 55 | |
duke@435 | 56 | REGISTER_DECLARATION(Register, c_rarg0, rcx); |
duke@435 | 57 | REGISTER_DECLARATION(Register, c_rarg1, rdx); |
duke@435 | 58 | REGISTER_DECLARATION(Register, c_rarg2, r8); |
duke@435 | 59 | REGISTER_DECLARATION(Register, c_rarg3, r9); |
duke@435 | 60 | |
duke@435 | 61 | REGISTER_DECLARATION(FloatRegister, c_farg0, xmm0); |
duke@435 | 62 | REGISTER_DECLARATION(FloatRegister, c_farg1, xmm1); |
duke@435 | 63 | REGISTER_DECLARATION(FloatRegister, c_farg2, xmm2); |
duke@435 | 64 | REGISTER_DECLARATION(FloatRegister, c_farg3, xmm3); |
duke@435 | 65 | |
duke@435 | 66 | #else |
duke@435 | 67 | |
duke@435 | 68 | REGISTER_DECLARATION(Register, c_rarg0, rdi); |
duke@435 | 69 | REGISTER_DECLARATION(Register, c_rarg1, rsi); |
duke@435 | 70 | REGISTER_DECLARATION(Register, c_rarg2, rdx); |
duke@435 | 71 | REGISTER_DECLARATION(Register, c_rarg3, rcx); |
duke@435 | 72 | REGISTER_DECLARATION(Register, c_rarg4, r8); |
duke@435 | 73 | REGISTER_DECLARATION(Register, c_rarg5, r9); |
duke@435 | 74 | |
duke@435 | 75 | REGISTER_DECLARATION(FloatRegister, c_farg0, xmm0); |
duke@435 | 76 | REGISTER_DECLARATION(FloatRegister, c_farg1, xmm1); |
duke@435 | 77 | REGISTER_DECLARATION(FloatRegister, c_farg2, xmm2); |
duke@435 | 78 | REGISTER_DECLARATION(FloatRegister, c_farg3, xmm3); |
duke@435 | 79 | REGISTER_DECLARATION(FloatRegister, c_farg4, xmm4); |
duke@435 | 80 | REGISTER_DECLARATION(FloatRegister, c_farg5, xmm5); |
duke@435 | 81 | REGISTER_DECLARATION(FloatRegister, c_farg6, xmm6); |
duke@435 | 82 | REGISTER_DECLARATION(FloatRegister, c_farg7, xmm7); |
duke@435 | 83 | |
duke@435 | 84 | #endif // _WIN64 |
duke@435 | 85 | |
duke@435 | 86 | // Symbolically name the register arguments used by the Java calling convention. |
duke@435 | 87 | // We have control over the convention for java so we can do what we please. |
duke@435 | 88 | // What pleases us is to offset the java calling convention so that when |
duke@435 | 89 | // we call a suitable jni method the arguments are lined up and we don't |
duke@435 | 90 | // have to do little shuffling. A suitable jni method is non-static and a |
duke@435 | 91 | // small number of arguments (two fewer args on windows) |
duke@435 | 92 | // |
duke@435 | 93 | // |-------------------------------------------------------| |
duke@435 | 94 | // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | |
duke@435 | 95 | // |-------------------------------------------------------| |
duke@435 | 96 | // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) |
duke@435 | 97 | // | rdi rsi rdx rcx r8 r9 | solaris/linux |
duke@435 | 98 | // |-------------------------------------------------------| |
duke@435 | 99 | // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | |
duke@435 | 100 | // |-------------------------------------------------------| |
duke@435 | 101 | |
duke@435 | 102 | REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); |
duke@435 | 103 | REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); |
duke@435 | 104 | REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); |
duke@435 | 105 | // Windows runs out of register args here |
duke@435 | 106 | #ifdef _WIN64 |
duke@435 | 107 | REGISTER_DECLARATION(Register, j_rarg3, rdi); |
duke@435 | 108 | REGISTER_DECLARATION(Register, j_rarg4, rsi); |
duke@435 | 109 | #else |
duke@435 | 110 | REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); |
duke@435 | 111 | REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); |
duke@435 | 112 | #endif /* _WIN64 */ |
duke@435 | 113 | REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); |
duke@435 | 114 | |
duke@435 | 115 | REGISTER_DECLARATION(FloatRegister, j_farg0, xmm0); |
duke@435 | 116 | REGISTER_DECLARATION(FloatRegister, j_farg1, xmm1); |
duke@435 | 117 | REGISTER_DECLARATION(FloatRegister, j_farg2, xmm2); |
duke@435 | 118 | REGISTER_DECLARATION(FloatRegister, j_farg3, xmm3); |
duke@435 | 119 | REGISTER_DECLARATION(FloatRegister, j_farg4, xmm4); |
duke@435 | 120 | REGISTER_DECLARATION(FloatRegister, j_farg5, xmm5); |
duke@435 | 121 | REGISTER_DECLARATION(FloatRegister, j_farg6, xmm6); |
duke@435 | 122 | REGISTER_DECLARATION(FloatRegister, j_farg7, xmm7); |
duke@435 | 123 | |
duke@435 | 124 | REGISTER_DECLARATION(Register, rscratch1, r10); // volatile |
duke@435 | 125 | REGISTER_DECLARATION(Register, rscratch2, r11); // volatile |
duke@435 | 126 | |
duke@435 | 127 | REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
duke@435 | 128 | |
duke@435 | 129 | #endif // _LP64 |
duke@435 | 130 | |
duke@435 | 131 | // Address is an abstraction used to represent a memory location |
duke@435 | 132 | // using any of the amd64 addressing modes with one object. |
duke@435 | 133 | // |
duke@435 | 134 | // Note: A register location is represented via a Register, not |
duke@435 | 135 | // via an address for efficiency & simplicity reasons. |
duke@435 | 136 | |
duke@435 | 137 | class ArrayAddress; |
duke@435 | 138 | |
duke@435 | 139 | class Address VALUE_OBJ_CLASS_SPEC { |
duke@435 | 140 | public: |
duke@435 | 141 | enum ScaleFactor { |
duke@435 | 142 | no_scale = -1, |
duke@435 | 143 | times_1 = 0, |
duke@435 | 144 | times_2 = 1, |
duke@435 | 145 | times_4 = 2, |
duke@435 | 146 | times_8 = 3 |
duke@435 | 147 | }; |
duke@435 | 148 | |
duke@435 | 149 | private: |
duke@435 | 150 | Register _base; |
duke@435 | 151 | Register _index; |
duke@435 | 152 | ScaleFactor _scale; |
duke@435 | 153 | int _disp; |
duke@435 | 154 | RelocationHolder _rspec; |
duke@435 | 155 | |
duke@435 | 156 | // Easily misused constructor make them private |
duke@435 | 157 | #ifndef _LP64 |
duke@435 | 158 | Address(address loc, RelocationHolder spec); |
duke@435 | 159 | #endif // _LP64 |
duke@435 | 160 | |
duke@435 | 161 | public: |
duke@435 | 162 | // creation |
duke@435 | 163 | Address() |
duke@435 | 164 | : _base(noreg), |
duke@435 | 165 | _index(noreg), |
duke@435 | 166 | _scale(no_scale), |
duke@435 | 167 | _disp(0) { |
duke@435 | 168 | } |
duke@435 | 169 | |
duke@435 | 170 | // No default displacement otherwise Register can be implicitly |
duke@435 | 171 | // converted to 0(Register) which is quite a different animal. |
duke@435 | 172 | |
duke@435 | 173 | Address(Register base, int disp) |
duke@435 | 174 | : _base(base), |
duke@435 | 175 | _index(noreg), |
duke@435 | 176 | _scale(no_scale), |
duke@435 | 177 | _disp(disp) { |
duke@435 | 178 | } |
duke@435 | 179 | |
duke@435 | 180 | Address(Register base, Register index, ScaleFactor scale, int disp = 0) |
duke@435 | 181 | : _base (base), |
duke@435 | 182 | _index(index), |
duke@435 | 183 | _scale(scale), |
duke@435 | 184 | _disp (disp) { |
duke@435 | 185 | assert(!index->is_valid() == (scale == Address::no_scale), |
duke@435 | 186 | "inconsistent address"); |
duke@435 | 187 | } |
duke@435 | 188 | |
duke@435 | 189 | // The following two overloads are used in connection with the |
duke@435 | 190 | // ByteSize type (see sizes.hpp). They simplify the use of |
duke@435 | 191 | // ByteSize'd arguments in assembly code. Note that their equivalent |
duke@435 | 192 | // for the optimized build are the member functions with int disp |
duke@435 | 193 | // argument since ByteSize is mapped to an int type in that case. |
duke@435 | 194 | // |
duke@435 | 195 | // Note: DO NOT introduce similar overloaded functions for WordSize |
duke@435 | 196 | // arguments as in the optimized mode, both ByteSize and WordSize |
duke@435 | 197 | // are mapped to the same type and thus the compiler cannot make a |
duke@435 | 198 | // distinction anymore (=> compiler errors). |
duke@435 | 199 | |
duke@435 | 200 | #ifdef ASSERT |
duke@435 | 201 | Address(Register base, ByteSize disp) |
duke@435 | 202 | : _base(base), |
duke@435 | 203 | _index(noreg), |
duke@435 | 204 | _scale(no_scale), |
duke@435 | 205 | _disp(in_bytes(disp)) { |
duke@435 | 206 | } |
duke@435 | 207 | |
duke@435 | 208 | Address(Register base, Register index, ScaleFactor scale, ByteSize disp) |
duke@435 | 209 | : _base(base), |
duke@435 | 210 | _index(index), |
duke@435 | 211 | _scale(scale), |
duke@435 | 212 | _disp(in_bytes(disp)) { |
duke@435 | 213 | assert(!index->is_valid() == (scale == Address::no_scale), |
duke@435 | 214 | "inconsistent address"); |
duke@435 | 215 | } |
duke@435 | 216 | #endif // ASSERT |
duke@435 | 217 | |
duke@435 | 218 | // accessors |
duke@435 | 219 | bool uses(Register reg) const { |
duke@435 | 220 | return _base == reg || _index == reg; |
duke@435 | 221 | } |
duke@435 | 222 | |
duke@435 | 223 | // Convert the raw encoding form into the form expected by the constructor for |
duke@435 | 224 | // Address. An index of 4 (rsp) corresponds to having no index, so convert |
duke@435 | 225 | // that to noreg for the Address constructor. |
duke@435 | 226 | static Address make_raw(int base, int index, int scale, int disp); |
duke@435 | 227 | |
duke@435 | 228 | static Address make_array(ArrayAddress); |
duke@435 | 229 | |
duke@435 | 230 | |
duke@435 | 231 | private: |
duke@435 | 232 | bool base_needs_rex() const { |
duke@435 | 233 | return _base != noreg && _base->encoding() >= 8; |
duke@435 | 234 | } |
duke@435 | 235 | |
duke@435 | 236 | bool index_needs_rex() const { |
duke@435 | 237 | return _index != noreg &&_index->encoding() >= 8; |
duke@435 | 238 | } |
duke@435 | 239 | |
duke@435 | 240 | relocInfo::relocType reloc() const { return _rspec.type(); } |
duke@435 | 241 | |
duke@435 | 242 | friend class Assembler; |
duke@435 | 243 | friend class MacroAssembler; |
duke@435 | 244 | friend class LIR_Assembler; // base/index/scale/disp |
duke@435 | 245 | }; |
duke@435 | 246 | |
duke@435 | 247 | // |
duke@435 | 248 | // AddressLiteral has been split out from Address because operands of this type |
duke@435 | 249 | // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out |
duke@435 | 250 | // the few instructions that need to deal with address literals are unique and the |
duke@435 | 251 | // MacroAssembler does not have to implement every instruction in the Assembler |
duke@435 | 252 | // in order to search for address literals that may need special handling depending |
duke@435 | 253 | // on the instruction and the platform. As small step on the way to merging i486/amd64 |
duke@435 | 254 | // directories. |
duke@435 | 255 | // |
duke@435 | 256 | class AddressLiteral VALUE_OBJ_CLASS_SPEC { |
duke@435 | 257 | friend class ArrayAddress; |
duke@435 | 258 | RelocationHolder _rspec; |
duke@435 | 259 | // Typically we use AddressLiterals we want to use their rval |
duke@435 | 260 | // However in some situations we want the lval (effect address) of the item. |
duke@435 | 261 | // We provide a special factory for making those lvals. |
duke@435 | 262 | bool _is_lval; |
duke@435 | 263 | |
duke@435 | 264 | // If the target is far we'll need to load the ea of this to |
duke@435 | 265 | // a register to reach it. Otherwise if near we can do rip |
duke@435 | 266 | // relative addressing. |
duke@435 | 267 | |
duke@435 | 268 | address _target; |
duke@435 | 269 | |
duke@435 | 270 | protected: |
duke@435 | 271 | // creation |
duke@435 | 272 | AddressLiteral() |
duke@435 | 273 | : _is_lval(false), |
duke@435 | 274 | _target(NULL) |
duke@435 | 275 | {} |
duke@435 | 276 | |
duke@435 | 277 | public: |
duke@435 | 278 | |
duke@435 | 279 | |
duke@435 | 280 | AddressLiteral(address target, relocInfo::relocType rtype); |
duke@435 | 281 | |
duke@435 | 282 | AddressLiteral(address target, RelocationHolder const& rspec) |
duke@435 | 283 | : _rspec(rspec), |
duke@435 | 284 | _is_lval(false), |
duke@435 | 285 | _target(target) |
duke@435 | 286 | {} |
duke@435 | 287 | |
duke@435 | 288 | AddressLiteral addr() { |
duke@435 | 289 | AddressLiteral ret = *this; |
duke@435 | 290 | ret._is_lval = true; |
duke@435 | 291 | return ret; |
duke@435 | 292 | } |
duke@435 | 293 | |
duke@435 | 294 | |
duke@435 | 295 | private: |
duke@435 | 296 | |
duke@435 | 297 | address target() { return _target; } |
duke@435 | 298 | bool is_lval() { return _is_lval; } |
duke@435 | 299 | |
duke@435 | 300 | relocInfo::relocType reloc() const { return _rspec.type(); } |
duke@435 | 301 | const RelocationHolder& rspec() const { return _rspec; } |
duke@435 | 302 | |
duke@435 | 303 | friend class Assembler; |
duke@435 | 304 | friend class MacroAssembler; |
duke@435 | 305 | friend class Address; |
duke@435 | 306 | friend class LIR_Assembler; |
duke@435 | 307 | }; |
duke@435 | 308 | |
duke@435 | 309 | // Convience classes |
duke@435 | 310 | class RuntimeAddress: public AddressLiteral { |
duke@435 | 311 | |
duke@435 | 312 | public: |
duke@435 | 313 | |
duke@435 | 314 | RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} |
duke@435 | 315 | |
duke@435 | 316 | }; |
duke@435 | 317 | |
duke@435 | 318 | class OopAddress: public AddressLiteral { |
duke@435 | 319 | |
duke@435 | 320 | public: |
duke@435 | 321 | |
duke@435 | 322 | OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} |
duke@435 | 323 | |
duke@435 | 324 | }; |
duke@435 | 325 | |
duke@435 | 326 | class ExternalAddress: public AddressLiteral { |
duke@435 | 327 | |
duke@435 | 328 | public: |
duke@435 | 329 | |
duke@435 | 330 | ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} |
duke@435 | 331 | |
duke@435 | 332 | }; |
duke@435 | 333 | |
duke@435 | 334 | class InternalAddress: public AddressLiteral { |
duke@435 | 335 | |
duke@435 | 336 | public: |
duke@435 | 337 | |
duke@435 | 338 | InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} |
duke@435 | 339 | |
duke@435 | 340 | }; |
duke@435 | 341 | |
duke@435 | 342 | // x86 can do array addressing as a single operation since disp can be an absolute |
duke@435 | 343 | // address amd64 can't. We create a class that expresses the concept but does extra |
duke@435 | 344 | // magic on amd64 to get the final result |
duke@435 | 345 | |
duke@435 | 346 | class ArrayAddress VALUE_OBJ_CLASS_SPEC { |
duke@435 | 347 | private: |
duke@435 | 348 | |
duke@435 | 349 | AddressLiteral _base; |
duke@435 | 350 | Address _index; |
duke@435 | 351 | |
duke@435 | 352 | public: |
duke@435 | 353 | |
duke@435 | 354 | ArrayAddress() {}; |
duke@435 | 355 | ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; |
duke@435 | 356 | AddressLiteral base() { return _base; } |
duke@435 | 357 | Address index() { return _index; } |
duke@435 | 358 | |
duke@435 | 359 | }; |
duke@435 | 360 | |
duke@435 | 361 | #ifndef _LP64 |
duke@435 | 362 | const int FPUStateSizeInWords = 27; |
duke@435 | 363 | #else |
duke@435 | 364 | const int FPUStateSizeInWords = 512 / wordSize; |
duke@435 | 365 | #endif // _LP64 |
duke@435 | 366 | |
duke@435 | 367 | // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction |
duke@435 | 368 | // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write |
duke@435 | 369 | // is what you get. The Assembler is generating code into a CodeBuffer. |
duke@435 | 370 | |
duke@435 | 371 | class Assembler : public AbstractAssembler { |
duke@435 | 372 | friend class AbstractAssembler; // for the non-virtual hack |
duke@435 | 373 | friend class LIR_Assembler; // as_Address() |
duke@435 | 374 | |
duke@435 | 375 | protected: |
duke@435 | 376 | #ifdef ASSERT |
duke@435 | 377 | void check_relocation(RelocationHolder const& rspec, int format); |
duke@435 | 378 | #endif |
duke@435 | 379 | |
duke@435 | 380 | inline void emit_long64(jlong x); |
duke@435 | 381 | |
duke@435 | 382 | void emit_data(jint data, relocInfo::relocType rtype, int format /* = 0 */); |
duke@435 | 383 | void emit_data(jint data, RelocationHolder const& rspec, int format /* = 0 */); |
duke@435 | 384 | void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); |
duke@435 | 385 | void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); |
duke@435 | 386 | |
duke@435 | 387 | // Helper functions for groups of instructions |
duke@435 | 388 | void emit_arith_b(int op1, int op2, Register dst, int imm8); |
duke@435 | 389 | |
duke@435 | 390 | void emit_arith(int op1, int op2, Register dst, int imm32); |
duke@435 | 391 | // only x86?? |
duke@435 | 392 | void emit_arith(int op1, int op2, Register dst, jobject obj); |
duke@435 | 393 | void emit_arith(int op1, int op2, Register dst, Register src); |
duke@435 | 394 | |
duke@435 | 395 | void emit_operand(Register reg, |
duke@435 | 396 | Register base, Register index, Address::ScaleFactor scale, |
duke@435 | 397 | int disp, |
duke@435 | 398 | RelocationHolder const& rspec); |
duke@435 | 399 | void emit_operand(Register reg, Address adr); |
duke@435 | 400 | |
duke@435 | 401 | // Immediate-to-memory forms |
duke@435 | 402 | void emit_arith_operand(int op1, Register rm, Address adr, int imm32); |
duke@435 | 403 | |
duke@435 | 404 | void emit_farith(int b1, int b2, int i); |
duke@435 | 405 | |
duke@435 | 406 | // macroassembler?? QQQ |
duke@435 | 407 | bool reachable(AddressLiteral adr) { return true; } |
duke@435 | 408 | |
duke@435 | 409 | // These are all easily abused and hence protected |
duke@435 | 410 | |
duke@435 | 411 | // Make these disappear in 64bit mode since they would never be correct |
duke@435 | 412 | #ifndef _LP64 |
duke@435 | 413 | void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); |
duke@435 | 414 | void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); |
duke@435 | 415 | |
duke@435 | 416 | void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); |
duke@435 | 417 | void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); |
duke@435 | 418 | |
duke@435 | 419 | void push_literal32(int32_t imm32, RelocationHolder const& rspec); |
duke@435 | 420 | #endif // _LP64 |
duke@435 | 421 | |
duke@435 | 422 | // These are unique in that we are ensured by the caller that the 32bit |
duke@435 | 423 | // relative in these instructions will always be able to reach the potentially |
duke@435 | 424 | // 64bit address described by entry. Since they can take a 64bit address they |
duke@435 | 425 | // don't have the 32 suffix like the other instructions in this class. |
duke@435 | 426 | |
duke@435 | 427 | void call_literal(address entry, RelocationHolder const& rspec); |
duke@435 | 428 | void jmp_literal(address entry, RelocationHolder const& rspec); |
duke@435 | 429 | |
duke@435 | 430 | |
duke@435 | 431 | public: |
duke@435 | 432 | enum Condition { // The x86 condition codes used for conditional jumps/moves. |
duke@435 | 433 | zero = 0x4, |
duke@435 | 434 | notZero = 0x5, |
duke@435 | 435 | equal = 0x4, |
duke@435 | 436 | notEqual = 0x5, |
duke@435 | 437 | less = 0xc, |
duke@435 | 438 | lessEqual = 0xe, |
duke@435 | 439 | greater = 0xf, |
duke@435 | 440 | greaterEqual = 0xd, |
duke@435 | 441 | below = 0x2, |
duke@435 | 442 | belowEqual = 0x6, |
duke@435 | 443 | above = 0x7, |
duke@435 | 444 | aboveEqual = 0x3, |
duke@435 | 445 | overflow = 0x0, |
duke@435 | 446 | noOverflow = 0x1, |
duke@435 | 447 | carrySet = 0x2, |
duke@435 | 448 | carryClear = 0x3, |
duke@435 | 449 | negative = 0x8, |
duke@435 | 450 | positive = 0x9, |
duke@435 | 451 | parity = 0xa, |
duke@435 | 452 | noParity = 0xb |
duke@435 | 453 | }; |
duke@435 | 454 | |
duke@435 | 455 | enum Prefix { |
duke@435 | 456 | // segment overrides |
duke@435 | 457 | CS_segment = 0x2e, |
duke@435 | 458 | SS_segment = 0x36, |
duke@435 | 459 | DS_segment = 0x3e, |
duke@435 | 460 | ES_segment = 0x26, |
duke@435 | 461 | FS_segment = 0x64, |
duke@435 | 462 | GS_segment = 0x65, |
duke@435 | 463 | |
duke@435 | 464 | REX = 0x40, |
duke@435 | 465 | |
duke@435 | 466 | REX_B = 0x41, |
duke@435 | 467 | REX_X = 0x42, |
duke@435 | 468 | REX_XB = 0x43, |
duke@435 | 469 | REX_R = 0x44, |
duke@435 | 470 | REX_RB = 0x45, |
duke@435 | 471 | REX_RX = 0x46, |
duke@435 | 472 | REX_RXB = 0x47, |
duke@435 | 473 | |
duke@435 | 474 | REX_W = 0x48, |
duke@435 | 475 | |
duke@435 | 476 | REX_WB = 0x49, |
duke@435 | 477 | REX_WX = 0x4A, |
duke@435 | 478 | REX_WXB = 0x4B, |
duke@435 | 479 | REX_WR = 0x4C, |
duke@435 | 480 | REX_WRB = 0x4D, |
duke@435 | 481 | REX_WRX = 0x4E, |
duke@435 | 482 | REX_WRXB = 0x4F |
duke@435 | 483 | }; |
duke@435 | 484 | |
duke@435 | 485 | enum WhichOperand { |
duke@435 | 486 | // input to locate_operand, and format code for relocations |
duke@435 | 487 | imm32_operand = 0, // embedded 32-bit immediate operand |
duke@435 | 488 | disp32_operand = 1, // embedded 32-bit displacement or address |
duke@435 | 489 | call32_operand = 2, // embedded 32-bit self-relative displacement |
duke@435 | 490 | _WhichOperand_limit = 3 |
duke@435 | 491 | }; |
duke@435 | 492 | |
duke@435 | 493 | public: |
duke@435 | 494 | |
duke@435 | 495 | // Creation |
duke@435 | 496 | Assembler(CodeBuffer* code) : AbstractAssembler(code) {} |
duke@435 | 497 | |
duke@435 | 498 | // Decoding |
duke@435 | 499 | static address locate_operand(address inst, WhichOperand which); |
duke@435 | 500 | static address locate_next_instruction(address inst); |
duke@435 | 501 | |
duke@435 | 502 | // Stack |
duke@435 | 503 | void pushad(); |
duke@435 | 504 | void popad(); |
duke@435 | 505 | |
duke@435 | 506 | void pushfd(); |
duke@435 | 507 | void popfd(); |
duke@435 | 508 | |
duke@435 | 509 | void pushl(int imm32); |
duke@435 | 510 | void pushoop(jobject obj); |
duke@435 | 511 | |
duke@435 | 512 | void pushl(Register src); |
duke@435 | 513 | void pushl(Address src); |
duke@435 | 514 | // void pushl(Label& L, relocInfo::relocType rtype); ? needed? |
duke@435 | 515 | |
duke@435 | 516 | // dummy to prevent NULL being converted to Register |
duke@435 | 517 | void pushl(void* dummy); |
duke@435 | 518 | |
duke@435 | 519 | void popl(Register dst); |
duke@435 | 520 | void popl(Address dst); |
duke@435 | 521 | |
duke@435 | 522 | // Instruction prefixes |
duke@435 | 523 | void prefix(Prefix p); |
duke@435 | 524 | |
duke@435 | 525 | // Moves |
duke@435 | 526 | void movb(Register dst, Address src); |
duke@435 | 527 | void movb(Address dst, int imm8); |
duke@435 | 528 | void movb(Address dst, Register src); |
duke@435 | 529 | |
duke@435 | 530 | void movw(Address dst, int imm16); |
duke@435 | 531 | void movw(Register dst, Address src); |
duke@435 | 532 | void movw(Address dst, Register src); |
duke@435 | 533 | |
duke@435 | 534 | // these are dummies used to catch attempting to convert NULL to Register |
duke@435 | 535 | void movl(Register dst, void* junk); |
duke@435 | 536 | void movl(Address dst, void* junk); |
duke@435 | 537 | |
duke@435 | 538 | void movl(Register dst, int imm32); |
duke@435 | 539 | void movl(Address dst, int imm32); |
duke@435 | 540 | void movl(Register dst, Register src); |
duke@435 | 541 | void movl(Register dst, Address src); |
duke@435 | 542 | void movl(Address dst, Register src); |
duke@435 | 543 | |
duke@435 | 544 | void movsxb(Register dst, Address src); |
duke@435 | 545 | void movsxb(Register dst, Register src); |
duke@435 | 546 | |
duke@435 | 547 | void movsxw(Register dst, Address src); |
duke@435 | 548 | void movsxw(Register dst, Register src); |
duke@435 | 549 | |
duke@435 | 550 | void movzxb(Register dst, Address src); |
duke@435 | 551 | void movzxb(Register dst, Register src); |
duke@435 | 552 | |
duke@435 | 553 | void movzxw(Register dst, Address src); |
duke@435 | 554 | void movzxw(Register dst, Register src); |
duke@435 | 555 | |
duke@435 | 556 | // Conditional moves (P6 only) |
duke@435 | 557 | void cmovl(Condition cc, Register dst, Register src); |
duke@435 | 558 | void cmovl(Condition cc, Register dst, Address src); |
duke@435 | 559 | |
duke@435 | 560 | // Prefetches (SSE, SSE2, 3DNOW only) |
duke@435 | 561 | void prefetcht0(Address src); |
duke@435 | 562 | void prefetcht1(Address src); |
duke@435 | 563 | void prefetcht2(Address src); |
duke@435 | 564 | void prefetchnta(Address src); |
duke@435 | 565 | void prefetchw(Address src); |
duke@435 | 566 | void prefetchr(Address src); |
duke@435 | 567 | |
duke@435 | 568 | // Arithmetics |
duke@435 | 569 | void adcl(Register dst, int imm32); |
duke@435 | 570 | void adcl(Register dst, Address src); |
duke@435 | 571 | void adcl(Register dst, Register src); |
duke@435 | 572 | |
duke@435 | 573 | void addl(Address dst, int imm32); |
duke@435 | 574 | void addl(Address dst, Register src); |
duke@435 | 575 | void addl(Register dst, int imm32); |
duke@435 | 576 | void addl(Register dst, Address src); |
duke@435 | 577 | void addl(Register dst, Register src); |
duke@435 | 578 | |
duke@435 | 579 | void andl(Register dst, int imm32); |
duke@435 | 580 | void andl(Register dst, Address src); |
duke@435 | 581 | void andl(Register dst, Register src); |
duke@435 | 582 | |
duke@435 | 583 | void cmpb(Address dst, int imm8); |
duke@435 | 584 | void cmpw(Address dst, int imm16); |
duke@435 | 585 | void cmpl(Address dst, int imm32); |
duke@435 | 586 | void cmpl(Register dst, int imm32); |
duke@435 | 587 | void cmpl(Register dst, Register src); |
duke@435 | 588 | void cmpl(Register dst, Address src); |
duke@435 | 589 | |
duke@435 | 590 | // this is a dummy used to catch attempting to convert NULL to Register |
duke@435 | 591 | void cmpl(Register dst, void* junk); |
duke@435 | 592 | |
duke@435 | 593 | protected: |
duke@435 | 594 | // Don't use next inc() and dec() methods directly. INC & DEC instructions |
duke@435 | 595 | // could cause a partial flag stall since they don't set CF flag. |
duke@435 | 596 | // Use MacroAssembler::decrement() & MacroAssembler::increment() methods |
duke@435 | 597 | // which call inc() & dec() or add() & sub() in accordance with |
duke@435 | 598 | // the product flag UseIncDec value. |
duke@435 | 599 | |
duke@435 | 600 | void decl(Register dst); |
duke@435 | 601 | void decl(Address dst); |
duke@435 | 602 | |
duke@435 | 603 | void incl(Register dst); |
duke@435 | 604 | void incl(Address dst); |
duke@435 | 605 | |
duke@435 | 606 | public: |
duke@435 | 607 | void idivl(Register src); |
duke@435 | 608 | void cdql(); |
duke@435 | 609 | |
duke@435 | 610 | void imull(Register dst, Register src); |
duke@435 | 611 | void imull(Register dst, Register src, int value); |
duke@435 | 612 | |
duke@435 | 613 | void leal(Register dst, Address src); |
duke@435 | 614 | |
duke@435 | 615 | void mull(Address src); |
duke@435 | 616 | void mull(Register src); |
duke@435 | 617 | |
duke@435 | 618 | void negl(Register dst); |
duke@435 | 619 | |
duke@435 | 620 | void notl(Register dst); |
duke@435 | 621 | |
duke@435 | 622 | void orl(Address dst, int imm32); |
duke@435 | 623 | void orl(Register dst, int imm32); |
duke@435 | 624 | void orl(Register dst, Address src); |
duke@435 | 625 | void orl(Register dst, Register src); |
duke@435 | 626 | |
duke@435 | 627 | void rcll(Register dst, int imm8); |
duke@435 | 628 | |
duke@435 | 629 | void sarl(Register dst, int imm8); |
duke@435 | 630 | void sarl(Register dst); |
duke@435 | 631 | |
duke@435 | 632 | void sbbl(Address dst, int imm32); |
duke@435 | 633 | void sbbl(Register dst, int imm32); |
duke@435 | 634 | void sbbl(Register dst, Address src); |
duke@435 | 635 | void sbbl(Register dst, Register src); |
duke@435 | 636 | |
duke@435 | 637 | void shldl(Register dst, Register src); |
duke@435 | 638 | |
duke@435 | 639 | void shll(Register dst, int imm8); |
duke@435 | 640 | void shll(Register dst); |
duke@435 | 641 | |
duke@435 | 642 | void shrdl(Register dst, Register src); |
duke@435 | 643 | |
duke@435 | 644 | void shrl(Register dst, int imm8); |
duke@435 | 645 | void shrl(Register dst); |
duke@435 | 646 | |
duke@435 | 647 | void subl(Address dst, int imm32); |
duke@435 | 648 | void subl(Address dst, Register src); |
duke@435 | 649 | void subl(Register dst, int imm32); |
duke@435 | 650 | void subl(Register dst, Address src); |
duke@435 | 651 | void subl(Register dst, Register src); |
duke@435 | 652 | |
duke@435 | 653 | void testb(Register dst, int imm8); |
duke@435 | 654 | void testl(Register dst, int imm32); |
duke@435 | 655 | void testl(Register dst, Address src); |
duke@435 | 656 | void testl(Register dst, Register src); |
duke@435 | 657 | |
duke@435 | 658 | void xaddl(Address dst, Register src); |
duke@435 | 659 | |
duke@435 | 660 | void xorl(Register dst, int imm32); |
duke@435 | 661 | void xorl(Register dst, Address src); |
duke@435 | 662 | void xorl(Register dst, Register src); |
duke@435 | 663 | |
duke@435 | 664 | // Miscellaneous |
duke@435 | 665 | void bswap(Register reg); |
duke@435 | 666 | void lock(); |
duke@435 | 667 | |
duke@435 | 668 | void xchg (Register reg, Address adr); |
duke@435 | 669 | void xchgl(Register dst, Register src); |
duke@435 | 670 | |
duke@435 | 671 | void cmpxchg (Register reg, Address adr); |
duke@435 | 672 | void cmpxchg8 (Address adr); |
duke@435 | 673 | |
duke@435 | 674 | void nop(int i = 1); |
duke@435 | 675 | void addr_nop_4(); |
duke@435 | 676 | void addr_nop_5(); |
duke@435 | 677 | void addr_nop_7(); |
duke@435 | 678 | void addr_nop_8(); |
duke@435 | 679 | |
duke@435 | 680 | void hlt(); |
duke@435 | 681 | void ret(int imm16); |
duke@435 | 682 | void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 |
duke@435 | 683 | void smovl(); |
duke@435 | 684 | void rep_movl(); |
duke@435 | 685 | void rep_set(); |
duke@435 | 686 | void repne_scan(); |
duke@435 | 687 | void setb(Condition cc, Register dst); |
duke@435 | 688 | void membar(); // Serializing memory-fence |
duke@435 | 689 | void cpuid(); |
duke@435 | 690 | void cld(); |
duke@435 | 691 | void std(); |
duke@435 | 692 | |
duke@435 | 693 | void emit_raw (unsigned char); |
duke@435 | 694 | |
duke@435 | 695 | // Calls |
duke@435 | 696 | void call(Label& L, relocInfo::relocType rtype); |
duke@435 | 697 | void call(Register reg); // push pc; pc <- reg |
duke@435 | 698 | void call(Address adr); // push pc; pc <- adr |
duke@435 | 699 | |
duke@435 | 700 | // Jumps |
duke@435 | 701 | void jmp(Address entry); // pc <- entry |
duke@435 | 702 | void jmp(Register entry); // pc <- entry |
duke@435 | 703 | |
duke@435 | 704 | // Label operations & relative jumps (PPUM Appendix D) |
duke@435 | 705 | void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L |
duke@435 | 706 | |
duke@435 | 707 | // Force an 8-bit jump offset |
duke@435 | 708 | // void jmpb(address entry); |
duke@435 | 709 | |
duke@435 | 710 | // Unconditional 8-bit offset jump to L. |
duke@435 | 711 | // WARNING: be very careful using this for forward jumps. If the label is |
duke@435 | 712 | // not bound within an 8-bit offset of this instruction, a run-time error |
duke@435 | 713 | // will occur. |
duke@435 | 714 | void jmpb(Label& L); |
duke@435 | 715 | |
duke@435 | 716 | // jcc is the generic conditional branch generator to run- |
duke@435 | 717 | // time routines, jcc is used for branches to labels. jcc |
duke@435 | 718 | // takes a branch opcode (cc) and a label (L) and generates |
duke@435 | 719 | // either a backward branch or a forward branch and links it |
duke@435 | 720 | // to the label fixup chain. Usage: |
duke@435 | 721 | // |
duke@435 | 722 | // Label L; // unbound label |
duke@435 | 723 | // jcc(cc, L); // forward branch to unbound label |
duke@435 | 724 | // bind(L); // bind label to the current pc |
duke@435 | 725 | // jcc(cc, L); // backward branch to bound label |
duke@435 | 726 | // bind(L); // illegal: a label may be bound only once |
duke@435 | 727 | // |
duke@435 | 728 | // Note: The same Label can be used for forward and backward branches |
duke@435 | 729 | // but it may be bound only once. |
duke@435 | 730 | |
duke@435 | 731 | void jcc(Condition cc, Label& L, |
duke@435 | 732 | relocInfo::relocType rtype = relocInfo::none); |
duke@435 | 733 | |
duke@435 | 734 | // Conditional jump to a 8-bit offset to L. |
duke@435 | 735 | // WARNING: be very careful using this for forward jumps. If the label is |
duke@435 | 736 | // not bound within an 8-bit offset of this instruction, a run-time error |
duke@435 | 737 | // will occur. |
duke@435 | 738 | void jccb(Condition cc, Label& L); |
duke@435 | 739 | |
duke@435 | 740 | // Floating-point operations |
duke@435 | 741 | void fld1(); |
duke@435 | 742 | void fldz(); |
duke@435 | 743 | |
duke@435 | 744 | void fld_s(Address adr); |
duke@435 | 745 | void fld_s(int index); |
duke@435 | 746 | void fld_d(Address adr); |
duke@435 | 747 | void fld_x(Address adr); // extended-precision (80-bit) format |
duke@435 | 748 | |
duke@435 | 749 | void fst_s(Address adr); |
duke@435 | 750 | void fst_d(Address adr); |
duke@435 | 751 | |
duke@435 | 752 | void fstp_s(Address adr); |
duke@435 | 753 | void fstp_d(Address adr); |
duke@435 | 754 | void fstp_d(int index); |
duke@435 | 755 | void fstp_x(Address adr); // extended-precision (80-bit) format |
duke@435 | 756 | |
duke@435 | 757 | void fild_s(Address adr); |
duke@435 | 758 | void fild_d(Address adr); |
duke@435 | 759 | |
duke@435 | 760 | void fist_s (Address adr); |
duke@435 | 761 | void fistp_s(Address adr); |
duke@435 | 762 | void fistp_d(Address adr); |
duke@435 | 763 | |
duke@435 | 764 | void fabs(); |
duke@435 | 765 | void fchs(); |
duke@435 | 766 | |
duke@435 | 767 | void flog(); |
duke@435 | 768 | void flog10(); |
duke@435 | 769 | |
duke@435 | 770 | void fldln2(); |
duke@435 | 771 | void fyl2x(); |
duke@435 | 772 | void fldlg2(); |
duke@435 | 773 | |
duke@435 | 774 | void fcos(); |
duke@435 | 775 | void fsin(); |
duke@435 | 776 | void ftan(); |
duke@435 | 777 | void fsqrt(); |
duke@435 | 778 | |
duke@435 | 779 | // "Alternate" versions of instructions place result down in FPU |
duke@435 | 780 | // stack instead of on TOS |
duke@435 | 781 | void fadd_s(Address src); |
duke@435 | 782 | void fadd_d(Address src); |
duke@435 | 783 | void fadd(int i); |
duke@435 | 784 | void fadda(int i); // "alternate" fadd |
duke@435 | 785 | |
duke@435 | 786 | void fsub_s(Address src); |
duke@435 | 787 | void fsub_d(Address src); |
duke@435 | 788 | void fsubr_s(Address src); |
duke@435 | 789 | void fsubr_d(Address src); |
duke@435 | 790 | |
duke@435 | 791 | void fmul_s(Address src); |
duke@435 | 792 | void fmul_d(Address src); |
duke@435 | 793 | void fmul(int i); |
duke@435 | 794 | void fmula(int i); // "alternate" fmul |
duke@435 | 795 | |
duke@435 | 796 | void fdiv_s(Address src); |
duke@435 | 797 | void fdiv_d(Address src); |
duke@435 | 798 | void fdivr_s(Address src); |
duke@435 | 799 | void fdivr_d(Address src); |
duke@435 | 800 | |
duke@435 | 801 | void fsub(int i); |
duke@435 | 802 | void fsuba(int i); // "alternate" fsub |
duke@435 | 803 | void fsubr(int i); |
duke@435 | 804 | void fsubra(int i); // "alternate" reversed fsub |
duke@435 | 805 | void fdiv(int i); |
duke@435 | 806 | void fdiva(int i); // "alternate" fdiv |
duke@435 | 807 | void fdivr(int i); |
duke@435 | 808 | void fdivra(int i); // "alternate" reversed fdiv |
duke@435 | 809 | |
duke@435 | 810 | void faddp(int i = 1); |
duke@435 | 811 | void fsubp(int i = 1); |
duke@435 | 812 | void fsubrp(int i = 1); |
duke@435 | 813 | void fmulp(int i = 1); |
duke@435 | 814 | void fdivp(int i = 1); |
duke@435 | 815 | void fdivrp(int i = 1); |
duke@435 | 816 | void fprem(); |
duke@435 | 817 | void fprem1(); |
duke@435 | 818 | |
duke@435 | 819 | void fxch(int i = 1); |
duke@435 | 820 | void fincstp(); |
duke@435 | 821 | void fdecstp(); |
duke@435 | 822 | void ffree(int i = 0); |
duke@435 | 823 | |
duke@435 | 824 | void fcomp_s(Address src); |
duke@435 | 825 | void fcomp_d(Address src); |
duke@435 | 826 | void fcom(int i); |
duke@435 | 827 | void fcomp(int i = 1); |
duke@435 | 828 | void fcompp(); |
duke@435 | 829 | |
duke@435 | 830 | void fucomi(int i = 1); |
duke@435 | 831 | void fucomip(int i = 1); |
duke@435 | 832 | |
duke@435 | 833 | void ftst(); |
duke@435 | 834 | void fnstsw_ax(); |
duke@435 | 835 | void fwait(); |
duke@435 | 836 | void finit(); |
duke@435 | 837 | void fldcw(Address src); |
duke@435 | 838 | void fnstcw(Address src); |
duke@435 | 839 | |
duke@435 | 840 | void fnsave(Address dst); |
duke@435 | 841 | void frstor(Address src); |
duke@435 | 842 | void fldenv(Address src); |
duke@435 | 843 | |
duke@435 | 844 | void sahf(); |
duke@435 | 845 | |
duke@435 | 846 | protected: |
duke@435 | 847 | void emit_sse_operand(XMMRegister reg, Address adr); |
duke@435 | 848 | void emit_sse_operand(Register reg, Address adr); |
duke@435 | 849 | void emit_sse_operand(XMMRegister dst, XMMRegister src); |
duke@435 | 850 | void emit_sse_operand(XMMRegister dst, Register src); |
duke@435 | 851 | void emit_sse_operand(Register dst, XMMRegister src); |
duke@435 | 852 | |
duke@435 | 853 | void emit_operand(MMXRegister reg, Address adr); |
duke@435 | 854 | |
duke@435 | 855 | public: |
duke@435 | 856 | // mmx operations |
duke@435 | 857 | void movq( MMXRegister dst, Address src ); |
duke@435 | 858 | void movq( Address dst, MMXRegister src ); |
duke@435 | 859 | void emms(); |
duke@435 | 860 | |
duke@435 | 861 | // xmm operations |
duke@435 | 862 | void addss(XMMRegister dst, Address src); // Add Scalar Single-Precision Floating-Point Values |
duke@435 | 863 | void addss(XMMRegister dst, XMMRegister src); |
duke@435 | 864 | void addsd(XMMRegister dst, Address src); // Add Scalar Double-Precision Floating-Point Values |
duke@435 | 865 | void addsd(XMMRegister dst, XMMRegister src); |
duke@435 | 866 | |
duke@435 | 867 | void subss(XMMRegister dst, Address src); // Subtract Scalar Single-Precision Floating-Point Values |
duke@435 | 868 | void subss(XMMRegister dst, XMMRegister src); |
duke@435 | 869 | void subsd(XMMRegister dst, Address src); // Subtract Scalar Double-Precision Floating-Point Values |
duke@435 | 870 | void subsd(XMMRegister dst, XMMRegister src); |
duke@435 | 871 | |
duke@435 | 872 | void mulss(XMMRegister dst, Address src); // Multiply Scalar Single-Precision Floating-Point Values |
duke@435 | 873 | void mulss(XMMRegister dst, XMMRegister src); |
duke@435 | 874 | void mulsd(XMMRegister dst, Address src); // Multiply Scalar Double-Precision Floating-Point Values |
duke@435 | 875 | void mulsd(XMMRegister dst, XMMRegister src); |
duke@435 | 876 | |
duke@435 | 877 | void divss(XMMRegister dst, Address src); // Divide Scalar Single-Precision Floating-Point Values |
duke@435 | 878 | void divss(XMMRegister dst, XMMRegister src); |
duke@435 | 879 | void divsd(XMMRegister dst, Address src); // Divide Scalar Double-Precision Floating-Point Values |
duke@435 | 880 | void divsd(XMMRegister dst, XMMRegister src); |
duke@435 | 881 | |
duke@435 | 882 | void sqrtss(XMMRegister dst, Address src); // Compute Square Root of Scalar Single-Precision Floating-Point Value |
duke@435 | 883 | void sqrtss(XMMRegister dst, XMMRegister src); |
duke@435 | 884 | void sqrtsd(XMMRegister dst, Address src); // Compute Square Root of Scalar Double-Precision Floating-Point Value |
duke@435 | 885 | void sqrtsd(XMMRegister dst, XMMRegister src); |
duke@435 | 886 | |
duke@435 | 887 | void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values |
duke@435 | 888 | void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values |
duke@435 | 889 | |
duke@435 | 890 | void comiss(XMMRegister dst, Address src); // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
duke@435 | 891 | void comiss(XMMRegister dst, XMMRegister src); |
duke@435 | 892 | void comisd(XMMRegister dst, Address src); // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS |
duke@435 | 893 | void comisd(XMMRegister dst, XMMRegister src); |
duke@435 | 894 | |
duke@435 | 895 | void ucomiss(XMMRegister dst, Address src); // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
duke@435 | 896 | void ucomiss(XMMRegister dst, XMMRegister src); |
duke@435 | 897 | void ucomisd(XMMRegister dst, Address src); // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS |
duke@435 | 898 | void ucomisd(XMMRegister dst, XMMRegister src); |
duke@435 | 899 | |
duke@435 | 900 | void cvtss2sd(XMMRegister dst, Address src); // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value |
duke@435 | 901 | void cvtss2sd(XMMRegister dst, XMMRegister src); |
duke@435 | 902 | void cvtsd2ss(XMMRegister dst, Address src); // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value |
duke@435 | 903 | void cvtsd2ss(XMMRegister dst, XMMRegister src); |
kvn@506 | 904 | void cvtdq2pd(XMMRegister dst, XMMRegister src); |
kvn@506 | 905 | void cvtdq2ps(XMMRegister dst, XMMRegister src); |
duke@435 | 906 | |
duke@435 | 907 | void cvtsi2ss(XMMRegister dst, Address src); // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value |
duke@435 | 908 | void cvtsi2ss(XMMRegister dst, Register src); |
duke@435 | 909 | void cvtsi2sd(XMMRegister dst, Address src); // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value |
duke@435 | 910 | void cvtsi2sd(XMMRegister dst, Register src); |
duke@435 | 911 | |
duke@435 | 912 | void cvtss2si(Register dst, Address src); // Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer |
duke@435 | 913 | void cvtss2si(Register dst, XMMRegister src); |
duke@435 | 914 | void cvtsd2si(Register dst, Address src); // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer |
duke@435 | 915 | void cvtsd2si(Register dst, XMMRegister src); |
duke@435 | 916 | |
duke@435 | 917 | void cvttss2si(Register dst, Address src); // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer |
duke@435 | 918 | void cvttss2si(Register dst, XMMRegister src); |
duke@435 | 919 | void cvttsd2si(Register dst, Address src); // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer |
duke@435 | 920 | void cvttsd2si(Register dst, XMMRegister src); |
duke@435 | 921 | |
duke@435 | 922 | protected: // Avoid using the next instructions directly. |
duke@435 | 923 | // New cpus require use of movsd and movss to avoid partial register stall |
duke@435 | 924 | // when loading from memory. But for old Opteron use movlpd instead of movsd. |
duke@435 | 925 | // The selection is done in MacroAssembler::movdbl() and movflt(). |
duke@435 | 926 | void movss(XMMRegister dst, Address src); // Move Scalar Single-Precision Floating-Point Values |
duke@435 | 927 | void movss(XMMRegister dst, XMMRegister src); |
duke@435 | 928 | void movss(Address dst, XMMRegister src); |
duke@435 | 929 | void movsd(XMMRegister dst, Address src); // Move Scalar Double-Precision Floating-Point Values |
duke@435 | 930 | void movsd(XMMRegister dst, XMMRegister src); |
duke@435 | 931 | void movsd(Address dst, XMMRegister src); |
duke@435 | 932 | void movlpd(XMMRegister dst, Address src); |
duke@435 | 933 | // New cpus require use of movaps and movapd to avoid partial register stall |
duke@435 | 934 | // when moving between registers. |
duke@435 | 935 | void movaps(XMMRegister dst, XMMRegister src); |
duke@435 | 936 | void movapd(XMMRegister dst, XMMRegister src); |
duke@435 | 937 | public: |
duke@435 | 938 | |
duke@435 | 939 | void andps(XMMRegister dst, Address src); // Bitwise Logical AND of Packed Single-Precision Floating-Point Values |
duke@435 | 940 | void andps(XMMRegister dst, XMMRegister src); |
duke@435 | 941 | void andpd(XMMRegister dst, Address src); // Bitwise Logical AND of Packed Double-Precision Floating-Point Values |
duke@435 | 942 | void andpd(XMMRegister dst, XMMRegister src); |
duke@435 | 943 | |
duke@435 | 944 | void andnps(XMMRegister dst, Address src); // Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values |
duke@435 | 945 | void andnps(XMMRegister dst, XMMRegister src); |
duke@435 | 946 | void andnpd(XMMRegister dst, Address src); // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values |
duke@435 | 947 | void andnpd(XMMRegister dst, XMMRegister src); |
duke@435 | 948 | |
duke@435 | 949 | void orps(XMMRegister dst, Address src); // Bitwise Logical OR of Packed Single-Precision Floating-Point Values |
duke@435 | 950 | void orps(XMMRegister dst, XMMRegister src); |
duke@435 | 951 | void orpd(XMMRegister dst, Address src); // Bitwise Logical OR of Packed Double-Precision Floating-Point Values |
duke@435 | 952 | void orpd(XMMRegister dst, XMMRegister src); |
duke@435 | 953 | |
duke@435 | 954 | void xorps(XMMRegister dst, Address src); // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values |
duke@435 | 955 | void xorps(XMMRegister dst, XMMRegister src); |
duke@435 | 956 | void xorpd(XMMRegister dst, Address src); // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values |
duke@435 | 957 | void xorpd(XMMRegister dst, XMMRegister src); |
duke@435 | 958 | |
duke@435 | 959 | void movq(XMMRegister dst, Address src); // Move Quadword |
duke@435 | 960 | void movq(XMMRegister dst, XMMRegister src); |
duke@435 | 961 | void movq(Address dst, XMMRegister src); |
duke@435 | 962 | |
duke@435 | 963 | void movd(XMMRegister dst, Address src); // Move Doubleword |
duke@435 | 964 | void movd(XMMRegister dst, Register src); |
duke@435 | 965 | void movd(Register dst, XMMRegister src); |
duke@435 | 966 | void movd(Address dst, XMMRegister src); |
duke@435 | 967 | |
duke@435 | 968 | void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword |
duke@435 | 969 | void movdqa(XMMRegister dst, XMMRegister src); |
duke@435 | 970 | void movdqa(Address dst, XMMRegister src); |
duke@435 | 971 | |
duke@435 | 972 | void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords |
duke@435 | 973 | void pshufd(XMMRegister dst, Address src, int mode); |
duke@435 | 974 | void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words |
duke@435 | 975 | void pshuflw(XMMRegister dst, Address src, int mode); |
duke@435 | 976 | |
duke@435 | 977 | void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate |
duke@435 | 978 | |
duke@435 | 979 | void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes |
duke@435 | 980 | void punpcklbw(XMMRegister dst, Address src); |
duke@435 | 981 | |
duke@435 | 982 | void ldmxcsr( Address src ); |
duke@435 | 983 | void stmxcsr( Address dst ); |
duke@435 | 984 | }; |
duke@435 | 985 | |
duke@435 | 986 | |
duke@435 | 987 | // MacroAssembler extends Assembler by frequently used macros. |
duke@435 | 988 | // |
duke@435 | 989 | // Instructions for which a 'better' code sequence exists depending |
duke@435 | 990 | // on arguments should also go in here. |
duke@435 | 991 | |
duke@435 | 992 | class MacroAssembler: public Assembler { |
duke@435 | 993 | friend class LIR_Assembler; |
duke@435 | 994 | protected: |
duke@435 | 995 | |
duke@435 | 996 | Address as_Address(AddressLiteral adr); |
duke@435 | 997 | Address as_Address(ArrayAddress adr); |
duke@435 | 998 | |
duke@435 | 999 | // Support for VM calls |
duke@435 | 1000 | // |
duke@435 | 1001 | // This is the base routine called by the different versions of call_VM_leaf. The interpreter |
duke@435 | 1002 | // may customize this version by overriding it for its purposes (e.g., to save/restore |
duke@435 | 1003 | // additional registers when doing a VM call). |
duke@435 | 1004 | #ifdef CC_INTERP |
duke@435 | 1005 | // c++ interpreter never wants to use interp_masm version of call_VM |
duke@435 | 1006 | #define VIRTUAL |
duke@435 | 1007 | #else |
duke@435 | 1008 | #define VIRTUAL virtual |
duke@435 | 1009 | #endif |
duke@435 | 1010 | |
duke@435 | 1011 | VIRTUAL void call_VM_leaf_base( |
duke@435 | 1012 | address entry_point, // the entry point |
duke@435 | 1013 | int number_of_arguments // the number of arguments to pop after the call |
duke@435 | 1014 | ); |
duke@435 | 1015 | |
duke@435 | 1016 | // This is the base routine called by the different versions of call_VM. The interpreter |
duke@435 | 1017 | // may customize this version by overriding it for its purposes (e.g., to save/restore |
duke@435 | 1018 | // additional registers when doing a VM call). |
duke@435 | 1019 | // |
duke@435 | 1020 | // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base |
duke@435 | 1021 | // returns the register which contains the thread upon return. If a thread register has been |
duke@435 | 1022 | // specified, the return value will correspond to that register. If no last_java_sp is specified |
duke@435 | 1023 | // (noreg) than rsp will be used instead. |
duke@435 | 1024 | VIRTUAL void call_VM_base( // returns the register containing the thread upon return |
duke@435 | 1025 | Register oop_result, // where an oop-result ends up if any; use noreg otherwise |
duke@435 | 1026 | Register java_thread, // the thread if computed before ; use noreg otherwise |
duke@435 | 1027 | Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise |
duke@435 | 1028 | address entry_point, // the entry point |
duke@435 | 1029 | int number_of_arguments, // the number of arguments (w/o thread) to pop after the call |
duke@435 | 1030 | bool check_exceptions // whether to check for pending exceptions after return |
duke@435 | 1031 | ); |
duke@435 | 1032 | |
duke@435 | 1033 | // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. |
duke@435 | 1034 | // The implementation is only non-empty for the InterpreterMacroAssembler, |
duke@435 | 1035 | // as only the interpreter handles PopFrame and ForceEarlyReturn requests. |
duke@435 | 1036 | virtual void check_and_handle_popframe(Register java_thread); |
duke@435 | 1037 | virtual void check_and_handle_earlyret(Register java_thread); |
duke@435 | 1038 | |
duke@435 | 1039 | void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); |
duke@435 | 1040 | |
duke@435 | 1041 | // helpers for FPU flag access |
duke@435 | 1042 | // tmp is a temporary register, if none is available use noreg |
duke@435 | 1043 | void save_rax (Register tmp); |
duke@435 | 1044 | void restore_rax(Register tmp); |
duke@435 | 1045 | |
duke@435 | 1046 | public: |
duke@435 | 1047 | MacroAssembler(CodeBuffer* code) : Assembler(code) {} |
duke@435 | 1048 | |
duke@435 | 1049 | // Support for NULL-checks |
duke@435 | 1050 | // |
duke@435 | 1051 | // Generates code that causes a NULL OS exception if the content of reg is NULL. |
duke@435 | 1052 | // If the accessed location is M[reg + offset] and the offset is known, provide the |
duke@435 | 1053 | // offset. No explicit code generation is needed if the offset is within a certain |
duke@435 | 1054 | // range (0 <= offset <= page_size). |
duke@435 | 1055 | |
duke@435 | 1056 | void null_check(Register reg, int offset = -1); |
kvn@603 | 1057 | static bool needs_explicit_null_check(intptr_t offset); |
duke@435 | 1058 | |
duke@435 | 1059 | // Required platform-specific helpers for Label::patch_instructions. |
duke@435 | 1060 | // They _shadow_ the declarations in AbstractAssembler, which are undefined. |
duke@435 | 1061 | void pd_patch_instruction(address branch, address target); |
duke@435 | 1062 | #ifndef PRODUCT |
duke@435 | 1063 | static void pd_print_patched_instruction(address branch); |
duke@435 | 1064 | #endif |
duke@435 | 1065 | |
duke@435 | 1066 | // The following 4 methods return the offset of the appropriate move instruction |
duke@435 | 1067 | |
duke@435 | 1068 | // Support for fast byte/word loading with zero extension (depending on particular CPU) |
duke@435 | 1069 | int load_unsigned_byte(Register dst, Address src); |
duke@435 | 1070 | int load_unsigned_word(Register dst, Address src); |
duke@435 | 1071 | |
duke@435 | 1072 | // Support for fast byte/word loading with sign extension (depending on particular CPU) |
duke@435 | 1073 | int load_signed_byte(Register dst, Address src); |
duke@435 | 1074 | int load_signed_word(Register dst, Address src); |
duke@435 | 1075 | |
duke@435 | 1076 | // Support for sign-extension (hi:lo = extend_sign(lo)) |
duke@435 | 1077 | void extend_sign(Register hi, Register lo); |
duke@435 | 1078 | |
duke@435 | 1079 | // Support for inc/dec with optimal instruction selection depending on value |
duke@435 | 1080 | void increment(Register reg, int value = 1); |
duke@435 | 1081 | void decrement(Register reg, int value = 1); |
duke@435 | 1082 | void increment(Address dst, int value = 1); |
duke@435 | 1083 | void decrement(Address dst, int value = 1); |
duke@435 | 1084 | |
duke@435 | 1085 | // Support optimal SSE move instructions. |
duke@435 | 1086 | void movflt(XMMRegister dst, XMMRegister src) { |
duke@435 | 1087 | if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } |
duke@435 | 1088 | else { movss (dst, src); return; } |
duke@435 | 1089 | } |
duke@435 | 1090 | void movflt(XMMRegister dst, Address src) { movss(dst, src); } |
duke@435 | 1091 | void movflt(XMMRegister dst, AddressLiteral src); |
duke@435 | 1092 | void movflt(Address dst, XMMRegister src) { movss(dst, src); } |
duke@435 | 1093 | |
duke@435 | 1094 | void movdbl(XMMRegister dst, XMMRegister src) { |
duke@435 | 1095 | if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } |
duke@435 | 1096 | else { movsd (dst, src); return; } |
duke@435 | 1097 | } |
duke@435 | 1098 | |
duke@435 | 1099 | void movdbl(XMMRegister dst, AddressLiteral src); |
duke@435 | 1100 | |
duke@435 | 1101 | void movdbl(XMMRegister dst, Address src) { |
duke@435 | 1102 | if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } |
duke@435 | 1103 | else { movlpd(dst, src); return; } |
duke@435 | 1104 | } |
duke@435 | 1105 | void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } |
duke@435 | 1106 | |
duke@435 | 1107 | void increment(AddressLiteral dst); |
duke@435 | 1108 | void increment(ArrayAddress dst); |
duke@435 | 1109 | |
duke@435 | 1110 | |
duke@435 | 1111 | // Alignment |
duke@435 | 1112 | void align(int modulus); |
duke@435 | 1113 | |
duke@435 | 1114 | // Misc |
duke@435 | 1115 | void fat_nop(); // 5 byte nop |
duke@435 | 1116 | |
duke@435 | 1117 | // Stack frame creation/removal |
duke@435 | 1118 | void enter(); |
duke@435 | 1119 | void leave(); |
duke@435 | 1120 | |
duke@435 | 1121 | // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) |
duke@435 | 1122 | // The pointer will be loaded into the thread register. |
duke@435 | 1123 | void get_thread(Register thread); |
duke@435 | 1124 | |
duke@435 | 1125 | // Support for VM calls |
duke@435 | 1126 | // |
duke@435 | 1127 | // It is imperative that all calls into the VM are handled via the call_VM macros. |
duke@435 | 1128 | // They make sure that the stack linkage is setup correctly. call_VM's correspond |
duke@435 | 1129 | // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. |
duke@435 | 1130 | |
duke@435 | 1131 | void call_VM(Register oop_result, address entry_point, bool check_exceptions = true); |
duke@435 | 1132 | void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); |
duke@435 | 1133 | void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); |
duke@435 | 1134 | void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); |
duke@435 | 1135 | |
duke@435 | 1136 | void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); |
duke@435 | 1137 | void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); |
duke@435 | 1138 | void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); |
duke@435 | 1139 | void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); |
duke@435 | 1140 | |
duke@435 | 1141 | void call_VM_leaf(address entry_point, int number_of_arguments = 0); |
duke@435 | 1142 | void call_VM_leaf(address entry_point, Register arg_1); |
duke@435 | 1143 | void call_VM_leaf(address entry_point, Register arg_1, Register arg_2); |
duke@435 | 1144 | void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); |
duke@435 | 1145 | |
duke@435 | 1146 | // last Java Frame (fills frame anchor) |
duke@435 | 1147 | void set_last_Java_frame(Register thread, Register last_java_sp, Register last_java_fp, address last_java_pc); |
duke@435 | 1148 | void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); |
duke@435 | 1149 | |
duke@435 | 1150 | // Stores |
duke@435 | 1151 | void store_check(Register obj); // store check for obj - register is destroyed afterwards |
duke@435 | 1152 | void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) |
duke@435 | 1153 | |
duke@435 | 1154 | // split store_check(Register obj) to enhance instruction interleaving |
duke@435 | 1155 | void store_check_part_1(Register obj); |
duke@435 | 1156 | void store_check_part_2(Register obj); |
duke@435 | 1157 | |
duke@435 | 1158 | // C 'boolean' to Java boolean: x == 0 ? 0 : 1 |
duke@435 | 1159 | void c2bool(Register x); |
duke@435 | 1160 | |
duke@435 | 1161 | // C++ bool manipulation |
duke@435 | 1162 | |
duke@435 | 1163 | void movbool(Register dst, Address src); |
duke@435 | 1164 | void movbool(Address dst, bool boolconst); |
duke@435 | 1165 | void movbool(Address dst, Register src); |
duke@435 | 1166 | void testbool(Register dst); |
duke@435 | 1167 | |
duke@435 | 1168 | // Int division/reminder for Java |
duke@435 | 1169 | // (as idivl, but checks for special case as described in JVM spec.) |
duke@435 | 1170 | // returns idivl instruction offset for implicit exception handling |
duke@435 | 1171 | int corrected_idivl(Register reg); |
duke@435 | 1172 | |
duke@435 | 1173 | void int3(); |
duke@435 | 1174 | |
duke@435 | 1175 | // Long negation for Java |
duke@435 | 1176 | void lneg(Register hi, Register lo); |
duke@435 | 1177 | |
duke@435 | 1178 | // Long multiplication for Java |
duke@435 | 1179 | // (destroys contents of rax, rbx, rcx and rdx) |
duke@435 | 1180 | void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y |
duke@435 | 1181 | |
duke@435 | 1182 | // Long shifts for Java |
duke@435 | 1183 | // (semantics as described in JVM spec.) |
duke@435 | 1184 | void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) |
duke@435 | 1185 | void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) |
duke@435 | 1186 | |
duke@435 | 1187 | // Long compare for Java |
duke@435 | 1188 | // (semantics as described in JVM spec.) |
duke@435 | 1189 | void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) |
duke@435 | 1190 | |
duke@435 | 1191 | // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: |
duke@435 | 1192 | // |
duke@435 | 1193 | // CF (corresponds to C0) if x < y |
duke@435 | 1194 | // PF (corresponds to C2) if unordered |
duke@435 | 1195 | // ZF (corresponds to C3) if x = y |
duke@435 | 1196 | // |
duke@435 | 1197 | // The arguments are in reversed order on the stack (i.e., top of stack is first argument). |
duke@435 | 1198 | // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) |
duke@435 | 1199 | void fcmp(Register tmp); |
duke@435 | 1200 | // Variant of the above which allows y to be further down the stack |
duke@435 | 1201 | // and which only pops x and y if specified. If pop_right is |
duke@435 | 1202 | // specified then pop_left must also be specified. |
duke@435 | 1203 | void fcmp(Register tmp, int index, bool pop_left, bool pop_right); |
duke@435 | 1204 | |
duke@435 | 1205 | // Floating-point comparison for Java |
duke@435 | 1206 | // Compares the top-most stack entries on the FPU stack and stores the result in dst. |
duke@435 | 1207 | // The arguments are in reversed order on the stack (i.e., top of stack is first argument). |
duke@435 | 1208 | // (semantics as described in JVM spec.) |
duke@435 | 1209 | void fcmp2int(Register dst, bool unordered_is_less); |
duke@435 | 1210 | // Variant of the above which allows y to be further down the stack |
duke@435 | 1211 | // and which only pops x and y if specified. If pop_right is |
duke@435 | 1212 | // specified then pop_left must also be specified. |
duke@435 | 1213 | void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); |
duke@435 | 1214 | |
duke@435 | 1215 | // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) |
duke@435 | 1216 | // tmp is a temporary register, if none is available use noreg |
duke@435 | 1217 | void fremr(Register tmp); |
duke@435 | 1218 | |
duke@435 | 1219 | |
duke@435 | 1220 | // same as fcmp2int, but using SSE2 |
duke@435 | 1221 | void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); |
duke@435 | 1222 | void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); |
duke@435 | 1223 | |
duke@435 | 1224 | // Inlined sin/cos generator for Java; must not use CPU instruction |
duke@435 | 1225 | // directly on Intel as it does not have high enough precision |
duke@435 | 1226 | // outside of the range [-pi/4, pi/4]. Extra argument indicate the |
duke@435 | 1227 | // number of FPU stack slots in use; all but the topmost will |
duke@435 | 1228 | // require saving if a slow case is necessary. Assumes argument is |
duke@435 | 1229 | // on FP TOS; result is on FP TOS. No cpu registers are changed by |
duke@435 | 1230 | // this code. |
duke@435 | 1231 | void trigfunc(char trig, int num_fpu_regs_in_use = 1); |
duke@435 | 1232 | |
duke@435 | 1233 | // branch to L if FPU flag C2 is set/not set |
duke@435 | 1234 | // tmp is a temporary register, if none is available use noreg |
duke@435 | 1235 | void jC2 (Register tmp, Label& L); |
duke@435 | 1236 | void jnC2(Register tmp, Label& L); |
duke@435 | 1237 | |
duke@435 | 1238 | // Pop ST (ffree & fincstp combined) |
duke@435 | 1239 | void fpop(); |
duke@435 | 1240 | |
duke@435 | 1241 | // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack |
duke@435 | 1242 | void push_fTOS(); |
duke@435 | 1243 | |
duke@435 | 1244 | // pops double TOS element from CPU stack and pushes on FPU stack |
duke@435 | 1245 | void pop_fTOS(); |
duke@435 | 1246 | |
duke@435 | 1247 | void empty_FPU_stack(); |
duke@435 | 1248 | |
duke@435 | 1249 | void push_IU_state(); |
duke@435 | 1250 | void pop_IU_state(); |
duke@435 | 1251 | |
duke@435 | 1252 | void push_FPU_state(); |
duke@435 | 1253 | void pop_FPU_state(); |
duke@435 | 1254 | |
duke@435 | 1255 | void push_CPU_state(); |
duke@435 | 1256 | void pop_CPU_state(); |
duke@435 | 1257 | |
duke@435 | 1258 | // Sign extension |
duke@435 | 1259 | void sign_extend_short(Register reg); |
duke@435 | 1260 | void sign_extend_byte(Register reg); |
duke@435 | 1261 | |
duke@435 | 1262 | // Division by power of 2, rounding towards 0 |
duke@435 | 1263 | void division_with_shift(Register reg, int shift_value); |
duke@435 | 1264 | |
duke@435 | 1265 | // Round up to a power of two |
duke@435 | 1266 | void round_to(Register reg, int modulus); |
duke@435 | 1267 | |
duke@435 | 1268 | // Callee saved registers handling |
duke@435 | 1269 | void push_callee_saved_registers(); |
duke@435 | 1270 | void pop_callee_saved_registers(); |
duke@435 | 1271 | |
duke@435 | 1272 | // allocation |
duke@435 | 1273 | void eden_allocate( |
duke@435 | 1274 | Register obj, // result: pointer to object after successful allocation |
duke@435 | 1275 | Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
duke@435 | 1276 | int con_size_in_bytes, // object size in bytes if known at compile time |
duke@435 | 1277 | Register t1, // temp register |
duke@435 | 1278 | Label& slow_case // continuation point if fast allocation fails |
duke@435 | 1279 | ); |
duke@435 | 1280 | void tlab_allocate( |
duke@435 | 1281 | Register obj, // result: pointer to object after successful allocation |
duke@435 | 1282 | Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
duke@435 | 1283 | int con_size_in_bytes, // object size in bytes if known at compile time |
duke@435 | 1284 | Register t1, // temp register |
duke@435 | 1285 | Register t2, // temp register |
duke@435 | 1286 | Label& slow_case // continuation point if fast allocation fails |
duke@435 | 1287 | ); |
duke@435 | 1288 | void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); |
duke@435 | 1289 | |
duke@435 | 1290 | //---- |
duke@435 | 1291 | void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 |
duke@435 | 1292 | |
duke@435 | 1293 | // Debugging |
duke@435 | 1294 | void verify_oop(Register reg, const char* s = "broken oop"); // only if +VerifyOops |
duke@435 | 1295 | void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
duke@435 | 1296 | |
duke@435 | 1297 | void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); // only if +VerifyFPU |
duke@435 | 1298 | void stop(const char* msg); // prints msg, dumps registers and stops execution |
duke@435 | 1299 | void warn(const char* msg); // prints msg and continues |
duke@435 | 1300 | static void debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); |
duke@435 | 1301 | void os_breakpoint(); |
duke@435 | 1302 | void untested() { stop("untested"); } |
duke@435 | 1303 | void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); } |
duke@435 | 1304 | void should_not_reach_here() { stop("should not reach here"); } |
duke@435 | 1305 | void print_CPU_state(); |
duke@435 | 1306 | |
duke@435 | 1307 | // Stack overflow checking |
duke@435 | 1308 | void bang_stack_with_offset(int offset) { |
duke@435 | 1309 | // stack grows down, caller passes positive offset |
duke@435 | 1310 | assert(offset > 0, "must bang with negative offset"); |
duke@435 | 1311 | movl(Address(rsp, (-offset)), rax); |
duke@435 | 1312 | } |
duke@435 | 1313 | |
duke@435 | 1314 | // Writes to stack successive pages until offset reached to check for |
duke@435 | 1315 | // stack overflow + shadow pages. Also, clobbers tmp |
duke@435 | 1316 | void bang_stack_size(Register size, Register tmp); |
duke@435 | 1317 | |
duke@435 | 1318 | // Support for serializing memory accesses between threads |
duke@435 | 1319 | void serialize_memory(Register thread, Register tmp); |
duke@435 | 1320 | |
duke@435 | 1321 | void verify_tlab(); |
duke@435 | 1322 | |
duke@435 | 1323 | // Biased locking support |
duke@435 | 1324 | // lock_reg and obj_reg must be loaded up with the appropriate values. |
duke@435 | 1325 | // swap_reg must be rax, and is killed. |
duke@435 | 1326 | // tmp_reg is optional. If it is supplied (i.e., != noreg) it will |
duke@435 | 1327 | // be killed; if not supplied, push/pop will be used internally to |
duke@435 | 1328 | // allocate a temporary (inefficient, avoid if possible). |
duke@435 | 1329 | // Optional slow case is for implementations (interpreter and C1) which branch to |
duke@435 | 1330 | // slow case directly. Leaves condition codes set for C2's Fast_Lock node. |
duke@435 | 1331 | // Returns offset of first potentially-faulting instruction for null |
duke@435 | 1332 | // check info (currently consumed only by C1). If |
duke@435 | 1333 | // swap_reg_contains_mark is true then returns -1 as it is assumed |
duke@435 | 1334 | // the calling code has already passed any potential faults. |
duke@435 | 1335 | int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg, |
duke@435 | 1336 | bool swap_reg_contains_mark, |
duke@435 | 1337 | Label& done, Label* slow_case = NULL, |
duke@435 | 1338 | BiasedLockingCounters* counters = NULL); |
duke@435 | 1339 | void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); |
duke@435 | 1340 | |
duke@435 | 1341 | |
duke@435 | 1342 | Condition negate_condition(Condition cond); |
duke@435 | 1343 | |
duke@435 | 1344 | // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit |
duke@435 | 1345 | // operands. In general the names are modified to avoid hiding the instruction in Assembler |
duke@435 | 1346 | // so that we don't need to implement all the varieties in the Assembler with trivial wrappers |
duke@435 | 1347 | // here in MacroAssembler. The major exception to this rule is call |
duke@435 | 1348 | |
duke@435 | 1349 | // Arithmetics |
duke@435 | 1350 | |
duke@435 | 1351 | void cmp8(AddressLiteral src1, int8_t imm); |
duke@435 | 1352 | |
duke@435 | 1353 | // QQQ renamed to drag out the casting of address to int32_t/intptr_t |
duke@435 | 1354 | void cmp32(Register src1, int32_t imm); |
duke@435 | 1355 | |
duke@435 | 1356 | void cmp32(AddressLiteral src1, int32_t imm); |
duke@435 | 1357 | // compare reg - mem, or reg - &mem |
duke@435 | 1358 | void cmp32(Register src1, AddressLiteral src2); |
duke@435 | 1359 | |
duke@435 | 1360 | void cmp32(Register src1, Address src2); |
duke@435 | 1361 | |
duke@435 | 1362 | // NOTE src2 must be the lval. This is NOT an mem-mem compare |
duke@435 | 1363 | void cmpptr(Address src1, AddressLiteral src2); |
duke@435 | 1364 | |
duke@435 | 1365 | void cmpptr(Register src1, AddressLiteral src2); |
duke@435 | 1366 | |
duke@435 | 1367 | void cmpoop(Address dst, jobject obj); |
duke@435 | 1368 | void cmpoop(Register dst, jobject obj); |
duke@435 | 1369 | |
duke@435 | 1370 | |
duke@435 | 1371 | void cmpxchgptr(Register reg, AddressLiteral adr); |
duke@435 | 1372 | |
duke@435 | 1373 | // Helper functions for statistics gathering. |
duke@435 | 1374 | // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. |
duke@435 | 1375 | void cond_inc32(Condition cond, AddressLiteral counter_addr); |
duke@435 | 1376 | // Unconditional atomic increment. |
duke@435 | 1377 | void atomic_incl(AddressLiteral counter_addr); |
duke@435 | 1378 | |
duke@435 | 1379 | void lea(Register dst, AddressLiteral adr); |
duke@435 | 1380 | void lea(Address dst, AddressLiteral adr); |
duke@435 | 1381 | |
duke@435 | 1382 | void test32(Register dst, AddressLiteral src); |
duke@435 | 1383 | |
duke@435 | 1384 | // Calls |
duke@435 | 1385 | |
duke@435 | 1386 | void call(Label& L, relocInfo::relocType rtype); |
duke@435 | 1387 | void call(Register entry); |
duke@435 | 1388 | |
duke@435 | 1389 | // NOTE: this call tranfers to the effective address of entry NOT |
duke@435 | 1390 | // the address contained by entry. This is because this is more natural |
duke@435 | 1391 | // for jumps/calls. |
duke@435 | 1392 | void call(AddressLiteral entry); |
duke@435 | 1393 | |
duke@435 | 1394 | // Jumps |
duke@435 | 1395 | |
duke@435 | 1396 | // NOTE: these jumps tranfer to the effective address of dst NOT |
duke@435 | 1397 | // the address contained by dst. This is because this is more natural |
duke@435 | 1398 | // for jumps/calls. |
duke@435 | 1399 | void jump(AddressLiteral dst); |
duke@435 | 1400 | void jump_cc(Condition cc, AddressLiteral dst); |
duke@435 | 1401 | |
duke@435 | 1402 | // 32bit can do a case table jump in one instruction but we no longer allow the base |
duke@435 | 1403 | // to be installed in the Address class. This jump will tranfers to the address |
duke@435 | 1404 | // contained in the location described by entry (not the address of entry) |
duke@435 | 1405 | void jump(ArrayAddress entry); |
duke@435 | 1406 | |
duke@435 | 1407 | // Floating |
duke@435 | 1408 | |
duke@435 | 1409 | void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } |
duke@435 | 1410 | void andpd(XMMRegister dst, AddressLiteral src); |
duke@435 | 1411 | |
duke@435 | 1412 | void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } |
duke@435 | 1413 | void comiss(XMMRegister dst, AddressLiteral src); |
duke@435 | 1414 | |
duke@435 | 1415 | void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } |
duke@435 | 1416 | void comisd(XMMRegister dst, AddressLiteral src); |
duke@435 | 1417 | |
duke@435 | 1418 | void fldcw(Address src) { Assembler::fldcw(src); } |
duke@435 | 1419 | void fldcw(AddressLiteral src); |
duke@435 | 1420 | |
duke@435 | 1421 | void fld_s(int index) { Assembler::fld_s(index); } |
duke@435 | 1422 | void fld_s(Address src) { Assembler::fld_s(src); } |
duke@435 | 1423 | void fld_s(AddressLiteral src); |
duke@435 | 1424 | |
duke@435 | 1425 | void fld_d(Address src) { Assembler::fld_d(src); } |
duke@435 | 1426 | void fld_d(AddressLiteral src); |
duke@435 | 1427 | |
duke@435 | 1428 | void fld_x(Address src) { Assembler::fld_x(src); } |
duke@435 | 1429 | void fld_x(AddressLiteral src); |
duke@435 | 1430 | |
duke@435 | 1431 | void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } |
duke@435 | 1432 | void ldmxcsr(AddressLiteral src); |
duke@435 | 1433 | |
duke@435 | 1434 | void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
duke@435 | 1435 | void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } |
duke@435 | 1436 | void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } |
duke@435 | 1437 | void movss(XMMRegister dst, AddressLiteral src); |
duke@435 | 1438 | |
duke@435 | 1439 | void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } |
duke@435 | 1440 | void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } |
duke@435 | 1441 | void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } |
duke@435 | 1442 | void movsd(XMMRegister dst, AddressLiteral src); |
duke@435 | 1443 | |
duke@435 | 1444 | void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } |
duke@435 | 1445 | void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } |
duke@435 | 1446 | void ucomiss(XMMRegister dst, AddressLiteral src); |
duke@435 | 1447 | |
duke@435 | 1448 | void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } |
duke@435 | 1449 | void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } |
duke@435 | 1450 | void ucomisd(XMMRegister dst, AddressLiteral src); |
duke@435 | 1451 | |
duke@435 | 1452 | // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values |
duke@435 | 1453 | void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } |
duke@435 | 1454 | void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } |
duke@435 | 1455 | void xorpd(XMMRegister dst, AddressLiteral src); |
duke@435 | 1456 | |
duke@435 | 1457 | // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values |
duke@435 | 1458 | void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } |
duke@435 | 1459 | void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } |
duke@435 | 1460 | void xorps(XMMRegister dst, AddressLiteral src); |
duke@435 | 1461 | |
duke@435 | 1462 | // Data |
duke@435 | 1463 | |
duke@435 | 1464 | void movoop(Register dst, jobject obj); |
duke@435 | 1465 | void movoop(Address dst, jobject obj); |
duke@435 | 1466 | |
duke@435 | 1467 | void movptr(ArrayAddress dst, Register src); |
duke@435 | 1468 | // can this do an lea? |
duke@435 | 1469 | void movptr(Register dst, ArrayAddress src); |
duke@435 | 1470 | |
duke@435 | 1471 | void movptr(Register dst, AddressLiteral src); |
duke@435 | 1472 | |
duke@435 | 1473 | // to avoid hiding movl |
duke@435 | 1474 | void mov32(AddressLiteral dst, Register src); |
duke@435 | 1475 | void mov32(Register dst, AddressLiteral src); |
duke@435 | 1476 | // to avoid hiding movb |
duke@435 | 1477 | void movbyte(ArrayAddress dst, int src); |
duke@435 | 1478 | |
duke@435 | 1479 | // Can push value or effective address |
duke@435 | 1480 | void pushptr(AddressLiteral src); |
duke@435 | 1481 | |
duke@435 | 1482 | #undef VIRTUAL |
duke@435 | 1483 | |
duke@435 | 1484 | }; |
duke@435 | 1485 | |
duke@435 | 1486 | /** |
duke@435 | 1487 | * class SkipIfEqual: |
duke@435 | 1488 | * |
duke@435 | 1489 | * Instantiating this class will result in assembly code being output that will |
duke@435 | 1490 | * jump around any code emitted between the creation of the instance and it's |
duke@435 | 1491 | * automatic destruction at the end of a scope block, depending on the value of |
duke@435 | 1492 | * the flag passed to the constructor, which will be checked at run-time. |
duke@435 | 1493 | */ |
duke@435 | 1494 | class SkipIfEqual { |
duke@435 | 1495 | private: |
duke@435 | 1496 | MacroAssembler* _masm; |
duke@435 | 1497 | Label _label; |
duke@435 | 1498 | |
duke@435 | 1499 | public: |
duke@435 | 1500 | SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); |
duke@435 | 1501 | ~SkipIfEqual(); |
duke@435 | 1502 | }; |
duke@435 | 1503 | |
duke@435 | 1504 | #ifdef ASSERT |
duke@435 | 1505 | inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } |
duke@435 | 1506 | #endif |