| Thu, 13 Feb 2020 19:16:02 +0800 |
#11867 Backport of #11497 assert(false) failed: Should Not Reach Here, what is the cpu type? |
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| Thu, 05 Sep 2019 13:07:31 +0800 |
#9372 Refactor VM_Version, removed UseLoongsonISA and Use3A3000, added UseLEXT1, UseLEXT2, UseLEXT3. |
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| Tue, 09 Jul 2019 15:15:56 +0800 |
#9516 [Backport of #9435] Implement BigInteger.montgomeryMultiply intrinsic. |
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| Tue, 28 May 2019 16:35:59 +0800 |
#9224 Backport of #9173 Refactor read_cpu_info and supported 3A4000/3B4000 |
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| Tue, 05 Mar 2019 17:00:17 +0800 |
#8573 Cleanup: x86 registers in comments; comment style; deadcode |
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| Thu, 11 Oct 2018 09:53:13 +0800 |
#7569 update copyright time of files modified in 2017 and 2018 |
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| Tue, 03 Jul 2018 15:57:58 +0800 |
#7215 UseCountLeadingZerosInstruction/UseCountTrailingZerosInstruction renamed UseCountLeadingZerosInstructionMIPS64/UseCountTrailingZerosInstructionMIPS64 |
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| Fri, 15 Jun 2018 17:25:38 +0800 |
#7167 disable UseSHA, UseSHA1Intrinsics, UseSHA256Intrinsics and UseSHA512Intrinsics on MIPS |
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| Tue, 12 Dec 2017 10:30:27 +0800 |
#6345 sync is controled by UseSyncLevel instead of Use3A2000 |
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| Thu, 07 Dec 2017 16:07:58 +0800 |
#6439 3B1500 is not gs464v but gs464. |
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| Tue, 28 Nov 2017 15:50:12 +0800 |
#6408 cpuinfo support 2K1000 and gs264 |
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| Fri, 01 Dec 2017 13:52:28 +0800 |
Tuning G1 for MIPS. |
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| Mon, 23 Oct 2017 17:07:19 +0800 |
[G1] Initial porting of MacroAssembler::g1_write_barrier_{pre/post} |
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| Tue, 10 Oct 2017 10:42:36 +0800 |
#6199 cpuinfo supports 3B2000/3B3000 |
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| Thu, 07 Sep 2017 09:12:16 +0800 |
#5745 [Code Reorganization] code cleanup and code style fix |
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| Wed, 17 May 2017 03:46:25 -0400 |
#5481 Vector optimization was not used by default. |
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| Wed, 29 Mar 2017 09:43:19 +0800 |
#4662 UseG1GC is turned off. |
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| Wed, 29 Mar 2017 09:41:51 +0800 |
#4662 TieredCompilation is turned off. |
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| Sun, 12 Mar 2017 09:04:47 +0800 |
#4670 Detect LoongsonCPUs to adapt different platforms. |
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| Wed, 01 Feb 2017 16:15:19 +0800 |
Set VM prefetch allocation args for Loongson CPUs. |
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| Tue, 17 Jan 2017 19:57:30 -0500 |
ctz/dctz are only supported on 3A2000/3A3000 CPUs (Follows changeset:32b76f240db3). |
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| Tue, 17 Jan 2017 21:53:02 -0500 |
Fix a SIGILL bug introduced by changeset 101daea92bb3. |
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| Thu, 29 Dec 2016 13:40:20 +0800 |
#4814 [C2] initial 64-bit vector support |
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| Fri, 16 Dec 2016 11:39:00 +0800 |
[C2] Added Zeros Count Instructions support in mips_64.ad |
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| Fri, 29 Apr 2016 00:06:10 +0800 |
Added MIPS 64-bit port. |
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