Tue, 17 Jan 2017 19:57:30 -0500
ctz/dctz are only supported on 3A2000/3A3000 CPUs (Follows changeset:32b76f240db3).
src/cpu/mips/vm/globals_mips.hpp | file | annotate | diff | comparison | revisions | |
src/cpu/mips/vm/vm_version_mips.cpp | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/globals_mips.hpp Tue Jan 17 21:53:02 2017 -0500 1.2 +++ b/src/cpu/mips/vm/globals_mips.hpp Tue Jan 17 19:57:30 2017 -0500 1.3 @@ -141,8 +141,7 @@ 1.4 product(bool, Use486InstrsOnly, false, \ 1.5 "Use 80486 Compliant instruction subset") \ 1.6 \ 1.7 - /* Turn on this flag may cause SIGILL on 3B1500 */ \ 1.8 - product(bool, UseCountLeadingZerosInstruction, false, \ 1.9 + product(bool, UseCountLeadingZerosInstruction, true, \ 1.10 "Use count leading zeros instruction") \ 1.11 \ 1.12 /* Use Restricted Transactional Memory for lock eliding */ \
2.1 --- a/src/cpu/mips/vm/vm_version_mips.cpp Tue Jan 17 21:53:02 2017 -0500 2.2 +++ b/src/cpu/mips/vm/vm_version_mips.cpp Tue Jan 17 19:57:30 2017 -0500 2.3 @@ -104,7 +104,7 @@ 2.4 } 2.5 } 2.6 if (UseLoongsonISA) 2.7 - UseCountTrailingZerosInstruction = false; // Turn on this flag may cause SIGILL on 3B1500 2.8 + UseCountTrailingZerosInstruction = false; // 2017.01.22 Now this guy is only supported on 3A2000/3A3000. 2.9 #endif 2.10 UseSSE = 0; // Only on x86 and x64 2.11