src/cpu/mips/vm/vm_version_mips.cpp

Fri, 15 Jun 2018 17:25:38 +0800

author
huangxuguang
date
Fri, 15 Jun 2018 17:25:38 +0800
changeset 9150
f7b3bf895d68
parent 8019
3fb3ceb7398f
child 9155
30adb9fd9663
permissions
-rw-r--r--

#7167 disable UseSHA, UseSHA1Intrinsics, UseSHA256Intrinsics and UseSHA512Intrinsics on MIPS
Reviewed-by: aoqi

aoqi@1 1 /*
aoqi@1 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
aoqi@1 3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
aoqi@1 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@1 5 *
aoqi@1 6 * This code is free software; you can redistribute it and/or modify it
aoqi@1 7 * under the terms of the GNU General Public License version 2 only, as
aoqi@1 8 * published by the Free Software Foundation.
aoqi@1 9 *
aoqi@1 10 * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@1 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@1 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@1 13 * version 2 for more details (a copy is included in the LICENSE file that
aoqi@1 14 * accompanied this code).
aoqi@1 15 *
aoqi@1 16 * You should have received a copy of the GNU General Public License version
aoqi@1 17 * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@1 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@1 19 *
aoqi@1 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@1 21 * or visit www.oracle.com if you need additional information or have any
aoqi@1 22 * questions.
aoqi@1 23 *
aoqi@1 24 */
aoqi@1 25
aoqi@1 26 #include "precompiled.hpp"
aoqi@1 27 #include "asm/macroAssembler.hpp"
aoqi@1 28 #include "asm/macroAssembler.inline.hpp"
aoqi@1 29 #include "memory/resourceArea.hpp"
aoqi@1 30 #include "runtime/java.hpp"
aoqi@1 31 #include "runtime/stubCodeGenerator.hpp"
aoqi@1 32 #include "vm_version_mips.hpp"
aoqi@1 33 #ifdef TARGET_OS_FAMILY_linux
aoqi@1 34 # include "os_linux.inline.hpp"
aoqi@1 35 #endif
aoqi@1 36 #ifdef TARGET_OS_FAMILY_solaris
aoqi@1 37 # include "os_solaris.inline.hpp"
aoqi@1 38 #endif
aoqi@1 39 #ifdef TARGET_OS_FAMILY_windows
aoqi@1 40 # include "os_windows.inline.hpp"
aoqi@1 41 #endif
aoqi@1 42 #ifdef TARGET_OS_FAMILY_bsd
aoqi@1 43 # include "os_bsd.inline.hpp"
aoqi@1 44 #endif
aoqi@1 45 /*
aoqi@1 46 int VM_Version::_cpu;
aoqi@1 47 int VM_Version::_model;
aoqi@1 48 int VM_Version::_stepping;
aoqi@1 49 int VM_Version::_cpuFeatures;
aoqi@1 50 const char* VM_Version::_features_str = "";
aoqi@1 51 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
aoqi@1 52
aoqi@1 53 static BufferBlob* stub_blob;
aoqi@1 54 static const int stub_size = 300;
aoqi@1 55
aoqi@1 56 extern "C" {
aoqi@1 57 typedef void (*getPsrInfo_stub_t)(void*);
aoqi@1 58 }
aoqi@1 59 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
aoqi@1 60 */
aoqi@1 61 int VM_Version::_features = VM_Version::unknown_m;
aoqi@1 62 const char* VM_Version::_features_str = "";
aoqi@1 63 /*
aoqi@1 64 class VM_Version_StubGenerator: public StubCodeGenerator {
aoqi@1 65 public:
aoqi@1 66
aoqi@1 67 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
aoqi@1 68
aoqi@1 69 address generate_getPsrInfo() {
aoqi@1 70 };
aoqi@1 71 };
aoqi@1 72
aoqi@1 73
aoqi@1 74 void VM_Version::get_processor_features() {
aoqi@1 75 }
aoqi@1 76 */
aoqi@1 77 void VM_Version::initialize() {
chenhaoxuan@358 78
fujie@254 79 _features = determine_features();
fujie@254 80 //no need, Abstract_VM_Version already define it as false
fujie@254 81 _supports_cx8 = true;
chenhaoxuan@358 82
chenhaoxuan@358 83 //////////////////////add some other feature here//////////////////
fujie@8014 84
fujie@8014 85 if (UseG1GC && FLAG_IS_DEFAULT(MaxGCPauseMillis)) {
fujie@8014 86 FLAG_SET_CMDLINE(uintx, MaxGCPauseMillis, 650);
fujie@8014 87 }
fujie@8014 88
aoqi@203 89 #ifdef COMPILER2
aoqi@209 90 if (MaxVectorSize > 0) {
aoqi@209 91 if (!is_power_of_2(MaxVectorSize)) {
aoqi@209 92 warning("MaxVectorSize must be a power of 2");
aoqi@209 93 MaxVectorSize = 8;
aoqi@209 94 }
aoqi@209 95 if (MaxVectorSize > 0 && supports_ps()) {
aoqi@209 96 MaxVectorSize = 8;
aoqi@209 97 }
aoqi@209 98 }
aoqi@409 99 /*
aoqi@409 100 *
aoqi@409 101 * 2017/5/17:
aoqi@409 102 * Vector optimization of MIPS works in most cases, but cannot pass hotspot/test/compiler/6340864/TestFloatVect.java.
aoqi@409 103 * Vector optimization was closed by default.
aoqi@409 104 * The reasons:
aoqi@409 105 * 1. The kernel does not have emulation of PS instructions yet, so the emulation of PS instructions must be done in JVM, see JVM_handle_linux_signal.
aoqi@409 106 * 2. It seems the gcc4.4.7 had some bug related to ucontext_t, which is used in signal handler to emulate PS instructions.
aoqi@409 107 */
aoqi@409 108 if (FLAG_IS_DEFAULT(MaxVectorSize)) {
aoqi@409 109 MaxVectorSize = 0;
aoqi@409 110 }
chenhaoxuan@358 111
chenhaoxuan@358 112 if (is_gs464e()) {
chenhaoxuan@358 113 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
chenhaoxuan@358 114 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, 1);
chenhaoxuan@358 115 }
chenhaoxuan@358 116 } else if (UseCountTrailingZerosInstruction) {
chenhaoxuan@358 117 if (!FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction))
chenhaoxuan@358 118 warning("Only 3A2000/3000 CPUs support UseCountTrailingZerosInstruction");
chenhaoxuan@358 119 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, 0);
chenhaoxuan@358 120 }
aoqi@203 121 #endif
aoqi@209 122 UseSSE = 0; // Only on x86 and x64
fujie@254 123
chenhaoxuan@358 124 if (is_loongson()) {
chenhaoxuan@358 125 if (FLAG_IS_DEFAULT(UseLoongsonISA)) {
chenhaoxuan@358 126 FLAG_SET_DEFAULT(UseLoongsonISA, 1);
chenhaoxuan@358 127 }
chenhaoxuan@358 128 } else if (UseLoongsonISA) {
chenhaoxuan@358 129 if (!FLAG_IS_DEFAULT(UseLoongsonISA))
chenhaoxuan@358 130 warning("Only Loongson CPUs support LoongISA");
chenhaoxuan@358 131 FLAG_SET_DEFAULT(UseLoongsonISA, 0);
chenhaoxuan@358 132 }
chenhaoxuan@358 133
chenhaoxuan@358 134 if (is_gs464e()) {
chenhaoxuan@358 135 if (FLAG_IS_DEFAULT(Use3A2000)) {
chenhaoxuan@358 136 FLAG_SET_DEFAULT(Use3A2000, 1);
chenhaoxuan@358 137 }
chenhaoxuan@358 138 } else if (Use3A2000) {
chenhaoxuan@358 139 if (!FLAG_IS_DEFAULT(Use3A2000))
chenhaoxuan@358 140 warning("Only 3A2000/3000 CPUs support this option");
chenhaoxuan@358 141 FLAG_SET_DEFAULT(Use3A2000, 0);
chenhaoxuan@358 142 }
chenhaoxuan@358 143
aoqi@8019 144 if (is_gs464()) {
aoqi@8019 145 if (FLAG_IS_DEFAULT(UseSyncLevel)) {
aoqi@8019 146 FLAG_SET_DEFAULT(UseSyncLevel, 1000);
aoqi@8019 147 }
aoqi@8019 148 }
aoqi@8019 149
aoqi@8019 150 if (is_gs464e()) {
aoqi@8019 151 if (FLAG_IS_DEFAULT(UseSyncLevel)) {
aoqi@8019 152 FLAG_SET_DEFAULT(UseSyncLevel, 2000);
aoqi@8019 153 }
aoqi@8019 154 }
aoqi@8019 155
aoqi@392 156 if (TieredCompilation) {
aoqi@392 157 if (!FLAG_IS_DEFAULT(TieredCompilation))
aoqi@392 158 warning("TieredCompilation not supported");
aoqi@392 159 FLAG_SET_DEFAULT(TieredCompilation, false);
aoqi@392 160 }
aoqi@392 161
chenhaoxuan@358 162 char buf[256];
chenhaoxuan@358 163 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s",
chenhaoxuan@358 164 (has_l2_cache() ? ", has_l2_cache" : ""),
chenhaoxuan@358 165 (has_16k_page() ? ", has_16k_page" : ""),
chenhaoxuan@358 166 (is_loongson() ? ", on_loongson" : ""),
aoqi@8017 167 (is_gs464() ? ", 3A1000/3B1500" : ""),
chenhaoxuan@6897 168 (is_gs464e() ? ", 3A2000/3A3000/3B2000/3B3000" : ""),
aoqi@8016 169 (is_gs264() ? ", 2K1000" : ""),
chenhaoxuan@358 170 (UseLoongsonISA ? ", UseLoongsonISA" : ""),
chenhaoxuan@358 171 (UseCountTrailingZerosInstruction ? ", UseCountTrailingZerosInstruction" : ""),
chenhaoxuan@358 172 (Use3A2000 ? ", Use3A2000" : ""));
chenhaoxuan@358 173
chenhaoxuan@358 174 // buf is started with ", " or is empty
chenhaoxuan@358 175 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
chenhaoxuan@358 176
fujie@254 177 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
fujie@254 178 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
fujie@254 179 }
fujie@254 180
fujie@254 181 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
fujie@254 182 FLAG_SET_DEFAULT(AllocatePrefetchLines, 1);
fujie@254 183 }
fujie@254 184
fujie@254 185 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) {
fujie@254 186 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, 64);
fujie@254 187 }
chenhaoxuan@358 188
fujie@254 189 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
fujie@254 190 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
fujie@254 191 }
fujie@254 192
fujie@254 193 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
fujie@254 194 FLAG_SET_DEFAULT(AllocateInstancePrefetchLines, 1);
fujie@254 195 }
fujie@254 196
huangxuguang@9150 197 if (UseSHA) {
huangxuguang@9150 198 warning("SHA instructions are not available on this CPU");
huangxuguang@9150 199 FLAG_SET_DEFAULT(UseSHA, false);
huangxuguang@9150 200 }
huangxuguang@9150 201
huangxuguang@9150 202 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
huangxuguang@9150 203 warning("SHA intrinsics are not available on this CPU");
huangxuguang@9150 204 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
huangxuguang@9150 205 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
huangxuguang@9150 206 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
huangxuguang@9150 207 }
huangxuguang@9150 208
fujie@254 209 NOT_PRODUCT( if (PrintMiscellaneous && Verbose) print_features(); );
aoqi@1 210 }
aoqi@1 211
aoqi@1 212 void VM_Version::print_features() {
chenhaoxuan@358 213 tty->print_cr("Version:%s", cpu_features());
aoqi@1 214 }
aoqi@1 215
aoqi@1 216 int VM_Version::determine_features() {
chenhaoxuan@358 217 //////////////////////add some other feature here//////////////////
chenhaoxuan@358 218 int features = platform_features(unknown_m);
aoqi@6880 219 //spt_16k_page_m;
chenhaoxuan@358 220 return features;
aoqi@1 221 }
aoqi@1 222
aoqi@1 223 static int saved_features = 0;
aoqi@1 224
aoqi@1 225 void VM_Version::allow_all() {
chenhaoxuan@358 226 saved_features = _features;
chenhaoxuan@358 227 _features = all_features_m;
aoqi@1 228 }
aoqi@1 229
aoqi@1 230 void VM_Version::revert() {
chenhaoxuan@358 231 _features = saved_features;
aoqi@1 232 }

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